// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Author: Developer X <dev@x-wrt.com>
 */

/dts-v1/;
#include "mt7987a.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Tenda BE12 Pro";
	compatible = "tenda,be12-pro", "mediatek,mt7987a", "mediatek,mt7987";

	aliases {
		label-mac-device = &gmac0;
		led-boot = &led_status_green;
		led-failsafe = &led_status_red;
		led-running = &led_status_green;
		led-upgrade = &led_status_red;
	};

	chosen {
		bootargs-override = "console=ttyS0,115200n1 earlycon=uart8250,mmio32,0x11000000 pci=pcie_bus_perf";
	};

	gpio-keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
			debounce-interval = <10>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
			debounce-interval = <10>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led_status_green: status_green {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
		};

		led_status_red: status_red {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	flash@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		mediatek,nmbm;
		mediatek,bmt-max-ratio = <1>;
		mediatek,bmt-max-reserved-blocks = <64>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "Bootloader";
				reg = <0x000000 0x0300000>;
				read-only;
			};

			partition@300000 {
				label = "u-boot-env";
				reg = <0x300000 0x0080000>;
			};

			partition@380000 {
				label = "Factory";
				reg = <0x380000 0x0400000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x1e00>;
					};

					macaddr_factory_4: macaddr@4 {
						compatible = "mac-base";
						reg = <0x4 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@780000 {
				label = "kernel";
				reg = <0x780000 0x0600000>;
			};

			partition@d80000 {
				label = "ubi";
				reg = <0xd80000 0x5a00000>;
			};

			partition@6780000 {
				label = "CFG";
				reg = <0x6780000 0x400000>;
				read-only;
			};

			partition@6b80000 {
				label = "MISC2";
				reg = <0x6b80000 0x400000>;
				read-only;
			};
		};
	};
};

&gmac0 {
	phy-mode = "2500base-x";
	status = "okay";

	nvmem-cells = <&macaddr_factory_4 (-2)>;
	nvmem-cell-names = "mac-address";

	fixed-link {
		speed = <2500>;
		full-duplex;
		pause;
	};
};

&gmac1 {
	phy-mode = "internal";
	phy-handle = <&phy15>;
	status = "okay";

	nvmem-cells = <&macaddr_factory_4 (-2)>;
	nvmem-cell-names = "mac-address";
};

&gmac2 {
	phy-mode = "2500base-x";
	phy-handle = <&phy11>;
	status = "okay";

	nvmem-cells = <&macaddr_factory_4 (-1)>;
	nvmem-cell-names = "mac-address";
};

&mdio {
	phy11: phy@11 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <11>;

		reset-assert-us = <10000>;
		reset-deassert-us = <20000>;
		reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>;
	};

	phy15: phy@15 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <15>;
	};

	mfd@1 {
		compatible = "airoha,an8855-mfd";
		reg = <1>;

		efuse {
			compatible = "airoha,an8855-efuse";
			#nvmem-cell-cells = <0>;

			nvmem-layout {
				compatible = "fixed-layout";
				#address-cells = <1>;
				#size-cells = <1>;

				shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
					reg = <0xc 0x4>;
				};

				shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
					reg = <0x10 0x4>;
				};

				shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
					reg = <0x14 0x4>;
				};

				shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
					reg = <0x18 0x4>;
				};

				shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
					reg = <0x1c 0x4>;
				};

				shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
					reg = <0x20 0x4>;
				};

				shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
					reg = <0x24 0x4>;
				};

				shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
					reg = <0x28 0x4>;
				};

				shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
					reg = <0x2c 0x4>;
				};

				shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
					reg = <0x30 0x4>;
				};

				shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
					reg = <0x34 0x4>;
				};

				shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
					reg = <0x38 0x4>;
				};

				shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
					reg = <0x4c 0x4>;
				};

				shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
					reg = <0x50 0x4>;
				};

				shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
					reg = <0x54 0x4>;
				};

				shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
					reg = <0x58 0x4>;
				};
			};
		};

		ethernet-switch {
			compatible = "airoha,an8855-switch";
			reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
			airoha,ext-surge;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan5";
					phy-mode = "internal";
					phy-handle = <&internal_phy1>;
				};

				port@1 {
					reg = <1>;
					label = "lan4";
					phy-mode = "internal";
					phy-handle = <&internal_phy2>;
				};

				port@2 {
					reg = <2>;
					label = "lan3";
					phy-mode = "internal";
					phy-handle = <&internal_phy3>;
				};

				port@5 {
					reg = <5>;
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};

		mdio {
			compatible = "airoha,an8855-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			internal_phy1: phy@1 {
				reg = <1>;

				nvmem-cells = <&shift_sel_port0_tx_a>,
						<&shift_sel_port0_tx_b>,
						<&shift_sel_port0_tx_c>,
						<&shift_sel_port0_tx_d>;
				nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
			};

			internal_phy2: phy@2 {
				reg = <2>;

				nvmem-cells = <&shift_sel_port1_tx_a>,
						<&shift_sel_port1_tx_b>,
						<&shift_sel_port1_tx_c>,
						<&shift_sel_port1_tx_d>;
				nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
			};

			internal_phy3: phy@3 {
				reg = <3>;

				nvmem-cells = <&shift_sel_port2_tx_a>,
						<&shift_sel_port2_tx_b>,
						<&shift_sel_port2_tx_c>,
						<&shift_sel_port2_tx_d>;
				nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
			};
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		device_type = "pci";
		#address-cells = <3>;
		#size-cells = <2>;

		wifi@0,0 {
			compatible = "mediatek,mt76";
			reg = <0x0000 0 0 0 0>;

			nvmem-cells = <&eeprom_factory_0>;
			nvmem-cell-names = "eeprom";

			#address-cells = <1>;
			#size-cells = <0>;

			ieee80211-freq-limit = <2400000 2500000>,
					       <5170000 5835000>;

			band@0 {
				reg = <0>;
				nvmem-cells = <&macaddr_factory_4 1>;
				nvmem-cell-names = "mac-address";
			};

			band@1 {
				reg = <1>;
				nvmem-cells = <&macaddr_factory_4 3>;
				nvmem-cell-names = "mac-address";
			};
		};
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};
