// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>

#include "mt7986a.dtsi"

/ {
	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "dm-mod.create=\"acer,,,ro,0 1 zero 1 0 0 0\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1";
	};

	memory@40000000 {
		reg = <0 0x40000000 0 0x20000000>;
		device_type = "memory";
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	gpio-keys {
		compatible = "gpio-keys";

		factory {
			label = "factory";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
		};
	};
};

&watchdog {
	status = "okay";
};

&pio {
	mmc0_pins_default: mmc0-pins {
		mux {
			function = "emmc";
			groups = "emmc_51";
		};

		conf-cmd-dat {
			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;	/* pull-up 10K */
		};

		conf-clk {
			pins = "EMMC_CK";
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;	/* pull-down 50K */
		};

		conf-ds {
			pins = "EMMC_DSL";
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;	/* pull-down 50K */
		};

		conf-rst {
			pins = "EMMC_RSTB";
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;	/* pull-up 10K */
		};
	};

	mmc0_pins_uhs: mmc0-uhs-pins {
		mux {
			function = "emmc";
			groups = "emmc_51";
		};

		conf-cmd-dat {
			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;	/* pull-up 10K */
		};

		conf-clk {
			pins = "EMMC_CK";
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;	/* pull-down 50K */
		};

		conf-ds {
			pins = "EMMC_DSL";
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;	/* pull-down 50K */
		};

		conf-rst {
			pins = "EMMC_RSTB";
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;	/* pull-up 10K */
		};
	};

	pcie_pins: pcie-pins {
		mux {
			function = "pcie";
			groups = "pcie_pereset";
		};
	};

	wf_2g_5g_pins: wf_2g_5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};

	wf_dbdc_pins: wf-dbdc-pins {
		mux {
			function = "wifi";
			groups = "wf_dbdc";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
				"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
				"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
				"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
				"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
				"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
				"WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};

	i2c_pins: i2c-pins {
		mux {
			function = "i2c";
			groups = "i2c";
		};
	};
};

&trng {
	status = "okay";
};

&crypto {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins>;
	status = "okay";
};

&mmc0 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <0x08>;
	max-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	hs400-ds-delay = <0x14014>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	non-removable;
	no-sd;
	no-sdio;
	#address-cells = <1>;
	#size-cells = <0>;

	card@0 {
		compatible = "mmc-card";
		reg = <0>;

		block {
			compatible = "block-device";

			partitions {
				block-partition-factory {
					partname = "factory";

					nvmem: nvmem-layout {
						compatible = "fixed-layout";
						#address-cells = <1>;
						#size-cells = <1>;

						eeprom_factory_0: eeprom@0 {
							reg = <0x0 0x1000>;
						};

						precal_factory_1010: precal@1010 {
							reg = <0x1010 0x62810>;
						};
					};
				};
			};
		};
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_pins>;
	status = "okay";

	slot0: pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		#address-cells = <0x03>;
		#size-cells = <0x02>;
	};
};

&pcie_phy {
	status = "okay";
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch: switch@1f {
			compatible = "mediatek,mt7531";
			reg = <31>;
			reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				swport0: port@0 {
					reg = <0>;
					phy-handle = <&swphy0>;
				};

				port@1 {
					reg = <1>;
					label = "lan1";
					phy-handle = <&swphy1>;
				};

				port@2 {
					reg = <2>;
					label = "lan2";
					phy-handle = <&swphy2>;
				};

				port@3 {
					reg = <3>;
					label = "lan3";
					phy-handle = <&swphy3>;
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				swphy0: phy@0 {
					reg = <0>;

					mediatek,led-config = <
						0x21 0x8008 /* BASIC_CTRL */
						0x22 0x0c00 /* ON_DURATION */
						0x23 0x1400 /* BLINK_DURATION */
						0x24 0xc001 /* LED0_ON_CTRL */
						0x25 0x0003 /* LED0_BLINK_CTRL */
						0x26 0xc006 /* LED1_ON_CTRL */
						0x27 0x003c /* LED1_BLINK_CTRL */
					>;
				};

				swphy1: phy@1 {
					reg = <1>;

					mediatek,led-config = <
						0x21 0x8008 /* BASIC_CTRL */
						0x22 0x0c00 /* ON_DURATION */
						0x23 0x1400 /* BLINK_DURATION */
						0x24 0xc001 /* LED0_ON_CTRL */
						0x25 0x0003 /* LED0_BLINK_CTRL */
						0x26 0xc006 /* LED1_ON_CTRL */
						0x27 0x003c /* LED1_BLINK_CTRL */
					>;
				};

				swphy2: phy@2 {
					reg = <2>;

					mediatek,led-config = <
						0x21 0x8008 /* BASIC_CTRL */
						0x22 0x0c00 /* ON_DURATION */
						0x23 0x1400 /* BLINK_DURATION */
						0x24 0xc001 /* LED0_ON_CTRL */
						0x25 0x0003 /* LED0_BLINK_CTRL */
						0x26 0xc006 /* LED1_ON_CTRL */
						0x27 0x003c /* LED1_BLINK_CTRL */
					>;
				};

				swphy3: phy@3 {
					reg = <3>;

					mediatek,led-config = <
						0x21 0x8008 /* BASIC_CTRL */
						0x22 0x0c00 /* ON_DURATION */
						0x23 0x1400 /* BLINK_DURATION */
						0x24 0xc001 /* LED0_ON_CTRL */
						0x25 0x0003 /* LED0_BLINK_CTRL */
						0x26 0xc006 /* LED1_ON_CTRL */
						0x27 0x003c /* LED1_BLINK_CTRL */
					>;
				};
			};
		};
	};
};

&wifi {
	nvmem-cells = <&eeprom_factory_0>, <&precal_factory_1010>;
	nvmem-cell-names = "eeprom", "precal";
	pinctrl-names = "default", "dbdc";
	pinctrl-0 = <&wf_2g_5g_pins>;
	pinctrl-1 = <&wf_dbdc_pins>;
	status = "okay";
};
