From d6f184181b076cbb54f152994f5bc73ce524a67e Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date: Sun, 11 May 2025 18:21:00 -0500
Subject: [PATCH] arm64: dts: qcom: ipq9574: add PCS uniphy nodes

IPQ9574 has three uniphy blocks. IPQ9554 lacks uniphy1. They take
their system and AHB clocks from NSSCC, and also feed NSSCC with
the clocks that are intended for the PHYs. This is not a cirular
dependency. Add nodes for these uniphy blocks, and the clocks they
feed back to the NSSCC node.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 100 ++++++++++++++++++++++++--
 1 file changed, 94 insertions(+), 6 deletions(-)

--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
@@ -1247,12 +1248,12 @@
 				 <&cmn_pll NSS_1200MHZ_CLK>,
 				 <&cmn_pll PPE_353MHZ_CLK>,
 				 <&gcc GPLL0_OUT_AUX>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
+				 <&pcs0 0>,
+				 <&pcs0 1>,
+				 <&pcs1 0>,
+				 <&pcs1 1>,
+				 <&pcs2 0>,
+				 <&pcs2 1>,
 				 <&gcc GCC_NSSCC_CLK>;
 			clock-names = "xo",
 				      "nss_1200",
@@ -1269,6 +1270,93 @@
 			#reset-cells = <1>;
 			#interconnect-cells = <1>;
 		};
+
+		pcs0: ethernet-pcs@7a00000 {
+			compatible = "qcom,ipq9574-pcs";
+			reg = <0x7a00000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
+				 <&gcc GCC_UNIPHY0_AHB_CLK>;
+			clock-names = "sys",
+				      "ahb";
+			resets = <&gcc GCC_UNIPHY0_XPCS_RESET>;
+			#clock-cells = <1>;
+
+			pcs0_ch0: pcs-mii@0 {
+				reg = <0>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+
+			pcs0_ch1: pcs-mii@1 {
+				reg = <1>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+
+			pcs0_ch2: pcs-mii@2 {
+				reg = <2>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+
+			pcs0_ch3: pcs-mii@3 {
+				reg = <3>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+		};
+
+		pcs1: ethernet-pcs@7a10000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,ipq9574-pcs";
+			reg = <0x7a10000 0x10000>;
+			clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
+				 <&gcc GCC_UNIPHY1_AHB_CLK>;
+			clock-names = "sys",
+				      "ahb";
+			resets = <&gcc GCC_UNIPHY1_XPCS_RESET>;
+			#clock-cells = <1>;
+
+			pcs1_ch0: pcs-mii@0 {
+				reg = <0>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+		};
+
+		pcs2: ethernet-pcs@7a20000 {
+			compatible = "qcom,ipq9574-pcs";
+			reg = <0x7a20000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
+				 <&gcc GCC_UNIPHY2_AHB_CLK>;
+			clock-names = "sys",
+				      "ahb";
+			resets = <&gcc GCC_UNIPHY2_XPCS_RESET>;
+			#clock-cells = <1>;
+
+			pcs2_ch0: pcs-mii@0 {
+				reg = <0>;
+				clocks = <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>,
+					 <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>;
+				clock-names = "rx",
+					      "tx";
+			};
+		};
 	};
 
 	thermal-zones {
