// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
/dts-v1/;

#include "rtl930x.dtsi"
#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"

/ {
	compatible = "linksys,lgs328c", "realtek,rtl9301-soc";
	model = "Linksys LGS328C";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
		      <0x20000000 0x10000000>; /* 256 MiB highmem */
	};
};

&i2c_mst1 {
	status = "okay";

	i2c2: i2c@2 {
		reg = <2>;
	};
	i2c3: i2c@3 {
		reg = <3>;
	};
	i2c4: i2c@4 {
		reg = <4>;
	};
	i2c5: i2c@5 {
		reg = <5>;
	};
};

&sfp0 {
	i2c-bus = <&i2c2>;
};

&sfp1 {
	i2c-bus = <&i2c3>;
};

&sfp2 {
	i2c-bus = <&i2c4>;
};

&sfp3 {
	i2c-bus = <&i2c5>;
};

&mdio_aux {
	status = "okay";
	gpio1: expander@0 {
		compatible = "realtek,rtl8231";
		reg = <0>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&gpio1 0 0 37>;

		led-controller {
			compatible = "realtek,rtl8231-leds";
			status = "disabled";
		};
	};
};

&mdio_bus0 {
	PHY_C22(0, 0)
	PHY_C22(1, 1)
	PHY_C22(2, 2)
	PHY_C22(3, 3)
	PHY_C22(4, 4)
	PHY_C22(5, 5)
	PHY_C22(6, 6)
	PHY_C22(7, 7)
};

&mdio_bus1 {
	PHY_C22(8, 8)
	PHY_C22(9, 9)
	PHY_C22(10, 10)
	PHY_C22(11, 11)
	PHY_C22(12, 12)
	PHY_C22(13, 13)
	PHY_C22(14, 14)
	PHY_C22(15, 15)
};

&mdio_bus2 {
	PHY_C22(16, 16)
	PHY_C22(17, 17)
	PHY_C22(18, 18)
	PHY_C22(19, 19)
	PHY_C22(20, 20)
	PHY_C22(21, 21)
	PHY_C22(22, 22)
	PHY_C22(23, 23)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 0, qsgmii)
		SWITCH_PORT_SDS(1, 2, 0, qsgmii)
		SWITCH_PORT_SDS(2, 3, 0, qsgmii)
		SWITCH_PORT_SDS(3, 4, 0, qsgmii)
		SWITCH_PORT_SDS(4, 5, 1, qsgmii)
		SWITCH_PORT_SDS(5, 6, 1, qsgmii)
		SWITCH_PORT_SDS(6, 7, 1, qsgmii)
		SWITCH_PORT_SDS(7, 8, 1, qsgmii)

		SWITCH_PORT_SDS(8, 9, 2, usxgmii)
		SWITCH_PORT_SDS(9, 10, 2, usxgmii)
		SWITCH_PORT_SDS(10, 11, 2, usxgmii)
		SWITCH_PORT_SDS(11, 12, 2, usxgmii)
		SWITCH_PORT_SDS(12, 13, 2, usxgmii)
		SWITCH_PORT_SDS(13, 14, 2, usxgmii)
		SWITCH_PORT_SDS(14, 15, 2, usxgmii)
		SWITCH_PORT_SDS(15, 16, 2, usxgmii)

		SWITCH_PORT_SDS(16, 17, 3, usxgmii)
		SWITCH_PORT_SDS(17, 18, 3, usxgmii)
		SWITCH_PORT_SDS(18, 19, 3, usxgmii)
		SWITCH_PORT_SDS(19, 20, 3, usxgmii)
		SWITCH_PORT_SDS(20, 21, 3, usxgmii)
		SWITCH_PORT_SDS(21, 22, 3, usxgmii)
		SWITCH_PORT_SDS(22, 23, 3, usxgmii)
		SWITCH_PORT_SDS(23, 24, 3, usxgmii)

		SWITCH_PORT_SFP(24, 25, 4, 0, 0)
		SWITCH_PORT_SFP(25, 26, 6, 0, 1)
		SWITCH_PORT_SFP(26, 27, 8, 0, 2)
		SWITCH_PORT_SFP(27, 28, 9, 0, 3)

		port@28 {
			reg = <28>;
			ethernet = <&ethernet0>;
			phy-mode = "internal";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};
