From 96c04debde6e879cf845ebdeedae7bd247e95203 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Thu, 25 Dec 2025 23:10:59 +0000 Subject: [PATCH 01/46] kernel/sunxi: create files for v6.18 (from v6.12) This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Zoltan HERPAI --- target/linux/sunxi/arm926ejs/{config-6.12 => config-6.18} | 0 target/linux/sunxi/{config-6.12 => config-6.18} | 0 target/linux/sunxi/cortexa53/{config-6.12 => config-6.18} | 0 target/linux/sunxi/cortexa7/{config-6.12 => config-6.18} | 0 target/linux/sunxi/cortexa8/{config-6.12 => config-6.18} | 0 .../102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch | 0 .../301-orangepi_pc2_usb_otg_to_host_key_power.patch | 0 ...400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch | 0 .../410-sunxi-add-bananapi-p2-zero.patch | 0 ...430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch | 0 .../431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch | 0 .../442-arm64-dts-orangepi-one-plus-enable-PWM.patch | 0 .../450-arm64-dts-enable-wifi-on-pine64-boards.patch | 0 .../451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch | 0 .../{patches-6.12 => patches-6.18}/460-f1c100s-sram-driver.patch | 0 .../461-f1c100s-watchdog-compat.patch | 0 16 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/sunxi/arm926ejs/{config-6.12 => config-6.18} (100%) rename target/linux/sunxi/{config-6.12 => config-6.18} (100%) rename target/linux/sunxi/cortexa53/{config-6.12 => config-6.18} (100%) rename target/linux/sunxi/cortexa7/{config-6.12 => config-6.18} (100%) rename target/linux/sunxi/cortexa8/{config-6.12 => config-6.18} (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/301-orangepi_pc2_usb_otg_to_host_key_power.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/410-sunxi-add-bananapi-p2-zero.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/442-arm64-dts-orangepi-one-plus-enable-PWM.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/450-arm64-dts-enable-wifi-on-pine64-boards.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/460-f1c100s-sram-driver.patch (100%) rename target/linux/sunxi/{patches-6.12 => patches-6.18}/461-f1c100s-watchdog-compat.patch (100%) diff --git a/target/linux/sunxi/arm926ejs/config-6.12 b/target/linux/sunxi/arm926ejs/config-6.18 similarity index 100% rename from target/linux/sunxi/arm926ejs/config-6.12 rename to target/linux/sunxi/arm926ejs/config-6.18 diff --git a/target/linux/sunxi/config-6.12 b/target/linux/sunxi/config-6.18 similarity index 100% rename from target/linux/sunxi/config-6.12 rename to target/linux/sunxi/config-6.18 diff --git a/target/linux/sunxi/cortexa53/config-6.12 b/target/linux/sunxi/cortexa53/config-6.18 similarity index 100% rename from target/linux/sunxi/cortexa53/config-6.12 rename to target/linux/sunxi/cortexa53/config-6.18 diff --git a/target/linux/sunxi/cortexa7/config-6.12 b/target/linux/sunxi/cortexa7/config-6.18 similarity index 100% rename from target/linux/sunxi/cortexa7/config-6.12 rename to target/linux/sunxi/cortexa7/config-6.18 diff --git a/target/linux/sunxi/cortexa8/config-6.12 b/target/linux/sunxi/cortexa8/config-6.18 similarity index 100% rename from target/linux/sunxi/cortexa8/config-6.12 rename to target/linux/sunxi/cortexa8/config-6.18 diff --git a/target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-6.18/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch rename to target/linux/sunxi/patches-6.18/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch diff --git a/target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch rename to target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch diff --git a/target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-6.18/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch rename to target/linux/sunxi/patches-6.18/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch diff --git a/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch rename to target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch diff --git a/target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-6.18/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch rename to target/linux/sunxi/patches-6.18/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch diff --git a/target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-6.18/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch rename to target/linux/sunxi/patches-6.18/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch diff --git a/target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-6.18/442-arm64-dts-orangepi-one-plus-enable-PWM.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch rename to target/linux/sunxi/patches-6.18/442-arm64-dts-orangepi-one-plus-enable-PWM.patch diff --git a/target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch rename to target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch diff --git a/target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch b/target/linux/sunxi/patches-6.18/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch rename to target/linux/sunxi/patches-6.18/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch diff --git a/target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch b/target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch rename to target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch diff --git a/target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch b/target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch similarity index 100% rename from target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch rename to target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch From 97b33978a83743d2765947e6d735eb065bc083fd Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Thu, 25 Dec 2025 23:11:00 +0000 Subject: [PATCH 02/46] kernel/sunxi: restore files for v6.12 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Zoltan HERPAI --- target/linux/sunxi/arm926ejs/config-6.12 | 56 ++ target/linux/sunxi/config-6.12 | 557 ++++++++++++++++++ target/linux/sunxi/cortexa53/config-6.12 | 138 +++++ target/linux/sunxi/cortexa7/config-6.12 | 44 ++ target/linux/sunxi/cortexa8/config-6.12 | 17 + ...OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch | 30 + ...angepi_pc2_usb_otg_to_host_key_power.patch | 20 + ...a64-sopine-Add-Sopine-flash-partitio.patch | 46 ++ .../410-sunxi-add-bananapi-p2-zero.patch | 292 +++++++++ ...ner-a64-olinuxino-add-status-LED-ali.patch | 32 + ...lwinner-nanopi-r1s-h5-add-status-LED.patch | 35 ++ ...m64-dts-orangepi-one-plus-enable-PWM.patch | 10 + ...m64-dts-enable-wifi-on-pine64-boards.patch | 72 +++ ...csi-video-support-for-nanopi-neo-air.patch | 107 ++++ .../460-f1c100s-sram-driver.patch | 33 ++ .../461-f1c100s-watchdog-compat.patch | 18 + 16 files changed, 1507 insertions(+) create mode 100644 target/linux/sunxi/arm926ejs/config-6.12 create mode 100644 target/linux/sunxi/config-6.12 create mode 100644 target/linux/sunxi/cortexa53/config-6.12 create mode 100644 target/linux/sunxi/cortexa7/config-6.12 create mode 100644 target/linux/sunxi/cortexa8/config-6.12 create mode 100644 target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch create mode 100644 target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch create mode 100644 target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch create mode 100644 target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch create mode 100644 target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch create mode 100644 target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch create mode 100644 target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch create mode 100644 target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch create mode 100644 target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch create mode 100644 target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch create mode 100644 target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch diff --git a/target/linux/sunxi/arm926ejs/config-6.12 b/target/linux/sunxi/arm926ejs/config-6.12 new file mode 100644 index 0000000000..8625b9751b --- /dev/null +++ b/target/linux/sunxi/arm926ejs/config-6.12 @@ -0,0 +1,56 @@ +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +CONFIG_ARCH_NR_GPIO=416 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_MACH_SUNIV=y +# CONFIG_MACH_SUN4I is not set +# CONFIG_MACH_SUN5I is not set +# CONFIG_MACH_SUN6I is not set +# CONFIG_MACH_SUN7I is not set +# CONFIG_MACH_SUN8I is not set +# CONFIG_MACH_SUN9I is not set +CONFIG_MDIO_BUS_MUX=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_NOP_USB_XCEIV=y +# CONFIG_PHY_SUN9I_USB is not set +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNIV_F1C100S=y +CONFIG_PINCTRL_SUNXI=y +CONFIG_SUNIV_F1C100S_CCU=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_SUNXI=y diff --git a/target/linux/sunxi/config-6.12 b/target/linux/sunxi/config-6.12 new file mode 100644 index 0000000000..7ff8f198b9 --- /dev/null +++ b/target/linux/sunxi/config-6.12 @@ -0,0 +1,557 @@ +# CONFIG_AHCI_SUNXI is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_NR_GPIO=416 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI_MC_SMP=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PORT_CTRL=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_AXP20X_POWER=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +CONFIG_BUFFER_HEAD=y +CONFIG_CACHE_L2X0=y +CONFIG_CAN=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_SUNXI=y +CONFIG_CLK_SUNXI_CLOCKS=y +CONFIG_CLK_SUNXI_PRCM_SUN6I=y +CONFIG_CLK_SUNXI_PRCM_SUN8I=y +CONFIG_CLK_SUNXI_PRCM_SUN9I=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE=y +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS=y +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG2=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SUN4I=y +CONFIG_DMA_SUN6I=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DVB_CORE=y +CONFIG_DWMAC_GENERIC=y +# CONFIG_DWMAC_SUN8I is not set +CONFIG_DWMAC_SUNXI=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_CORE=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +CONFIG_FB_LITTLE_ENDIAN=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_SUN6I_P2WI=y +CONFIG_IIO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_AXP20X_PEK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KEYBOARD_SUN4I_LRADC=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_KSM=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_MACH_SUN4I=y +CONFIG_MACH_SUN5I=y +CONFIG_MACH_SUN6I=y +CONFIG_MACH_SUN7I=y +CONFIG_MACH_SUN8I=y +CONFIG_MACH_SUN9I=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_SUN4I=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SUNXI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SUN4I_USB=y +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +CONFIG_PHY_SUN9I_USB=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AXP209 is not set +# CONFIG_PINCTRL_SUN20I_D1 is not set +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SUN4I=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_SUN20I=y +CONFIG_REGULATOR_SY8106A=y +CONFIG_RELAY=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SATA_HOST=y +CONFIG_SATA_PMP=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SDIO_UART=y +CONFIG_SECURITYFS=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SND=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_PCM=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_DMIC is not set +# CONFIG_SND_SUN8I_CODEC is not set +# CONFIG_SND_SUN8I_CODEC_ANALOG is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SUN4I=y +CONFIG_SPI_SUN6I=y +CONFIG_SRCU=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_SUN20I_GPADC is not set +# CONFIG_SUN20I_PPU is not set +CONFIG_SUN4I_A10_CCU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +CONFIG_SUN5I_CCU=y +CONFIG_SUN5I_HSTIMER=y +CONFIG_SUN6I_A31_CCU=y +# CONFIG_SUN6I_RTC_CCU is not set +CONFIG_SUN8I_A23_CCU=y +CONFIG_SUN8I_A33_CCU=y +CONFIG_SUN8I_A83T_CCU=y +CONFIG_SUN8I_DE2_CCU=y +CONFIG_SUN8I_H3_CCU=y +CONFIG_SUN8I_R40_CCU=y +CONFIG_SUN8I_R_CCU=y +CONFIG_SUN8I_THERMAL=y +CONFIG_SUN8I_V3S_CCU=y +CONFIG_SUN9I_A80_CCU=y +CONFIG_SUNXI_CCU=y +CONFIG_SUNXI_MBUS=y +CONFIG_SUNXI_RSB=y +CONFIG_SUNXI_SRAM=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOUCHSCREEN_SUN4I=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_GADGET=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USERIO=y +CONFIG_USE_OF=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VHOST=y +CONFIG_VHOST_IOTLB=y +CONFIG_VHOST_NET=y +CONFIG_VHOST_TASK=y +CONFIG_VIDEO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/sunxi/cortexa53/config-6.12 b/target/linux/sunxi/cortexa53/config-6.12 new file mode 100644 index 0000000000..9c650f1c4d --- /dev/null +++ b/target/linux/sunxi/cortexa53/config-6.12 @@ -0,0 +1,138 @@ +CONFIG_64BIT=y +CONFIG_APERTURE_HELPERS=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DWMAC_SUN8I=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FRAME_POINTER=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_HAS_IOPORT=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IRQ_MSI_LIB=y +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MICREL_PHY=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MOTORCOMM_PHY=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PHY_SUN50I_USB3=y +CONFIG_PINCTRL_SUN50I_A100=y +CONFIG_PINCTRL_SUN50I_A100_R=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_I2C_AND_SPI=y +# CONFIG_SND_SUN50I_CODEC_ANALOG is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SUN50I_A100_CCU=y +CONFIG_SUN50I_A100_R_CCU=y +CONFIG_SUN50I_A64_CCU=y +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUN50I_ERRATUM_UNKNOWN1=y +CONFIG_SUN50I_H616_CCU=y +CONFIG_SUN50I_H6_CCU=y +CONFIG_SUN50I_H6_R_CCU=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN6I_R_INTC=y +CONFIG_SUNXI_NMI_INTC=y +CONFIG_SURFACE_PLATFORMS=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TOOLS_SUPPORT_RELR=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_PHY=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VDSO_GETRANDOM=y +CONFIG_VMAP_STACK=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/sunxi/cortexa7/config-6.12 b/target/linux/sunxi/cortexa7/config-6.12 new file mode 100644 index 0000000000..789a4e6f1b --- /dev/null +++ b/target/linux/sunxi/cortexa7/config-6.12 @@ -0,0 +1,44 @@ +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_B53=y +CONFIG_B53_MDIO_DRIVER=y +CONFIG_CRYPTO_BLAKE2S_ARM=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_DWMAC_SUN8I=y +CONFIG_GRO_CELLS=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +# CONFIG_MACH_SUN4I is not set +# CONFIG_MACH_SUN5I is not set +CONFIG_MDIO_BUS_MUX=y +CONFIG_MICREL_PHY=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_BRCM=y +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM_LEGACY=y +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS=y +CONFIG_NET_DSA_TAG_BRCM_PREPEND=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_PINCTRL_AXP209=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN6I_A31=y +CONFIG_PINCTRL_SUN6I_A31_R=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN8I_V3S=y +CONFIG_PINCTRL_SUN9I_A80=y +CONFIG_PINCTRL_SUN9I_A80_R=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_PHY=y diff --git a/target/linux/sunxi/cortexa8/config-6.12 b/target/linux/sunxi/cortexa8/config-6.12 new file mode 100644 index 0000000000..dbf26947ab --- /dev/null +++ b/target/linux/sunxi/cortexa8/config-6.12 @@ -0,0 +1,17 @@ +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +# CONFIG_ARM_LPAE is not set +CONFIG_CRYPTO_BLAKE2S_ARM=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +# CONFIG_MACH_SUN6I is not set +# CONFIG_MACH_SUN7I is not set +# CONFIG_MACH_SUN8I is not set +# CONFIG_MACH_SUN9I is not set +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PINCTRL_AXP209=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN5I=y +# CONFIG_PHY_SUN9I_USB is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SUN8I_A83T_CCU is not set +# CONFIG_SUN8I_THERMAL is not set diff --git a/target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch new file mode 100644 index 0000000000..30c98aa737 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch @@ -0,0 +1,30 @@ +From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 10 Oct 2021 21:50:17 +0800 +Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5 + +This adds the OF node for the USB3 ethernet adapter on the FriendlyARM +NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration +register to match the blink behavior of the other port on the device. + +Signed-off-by: Chukun Pan +--- + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +@@ -116,6 +116,13 @@ + + &ehci1 { + status = "okay"; ++ ++ usb-eth@1 { ++ compatible = "realtek,rtl8153"; ++ reg = <1>; ++ ++ realtek,led-data = <0x78>; ++ }; + }; + + &ehci2 { diff --git a/target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch new file mode 100644 index 0000000000..eea47737fa --- /dev/null +++ b/target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch @@ -0,0 +1,20 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +@@ -60,7 +60,7 @@ + + key-sw4 { + label = "sw4"; +- linux,code = ; ++ linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; +@@ -221,7 +221,7 @@ + }; + + &usb_otg { +- dr_mode = "otg"; ++ dr_mode = "host"; + status = "okay"; + }; + diff --git a/target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch new file mode 100644 index 0000000000..a8dfcd9dbc --- /dev/null +++ b/target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch @@ -0,0 +1,46 @@ +From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 +From: Oskari Lemmela +Date: Mon, 31 Dec 2018 07:44:49 +0200 +Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. + +First 896kB to u-boot. Enough space for SPL, u-boot and ATF. +Next 128kB to u-boot environment and rest to firmware. + +Firmware partition is compatible FIT image dynamic splitting. + +Signed-off-by: Oskari Lemmela +--- + .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +@@ -58,6 +58,28 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x000000 0x0E0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot-env"; ++ reg = <0x0E0000 0x020000>; ++ }; ++ ++ partition@100000 { ++ compatible = "denx,fit"; ++ label = "firmware"; ++ reg = <0x100000 0xF00000>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch new file mode 100644 index 0000000000..eed2f0feff --- /dev/null +++ b/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch @@ -0,0 +1,292 @@ +--- a/arch/arm/boot/dts/allwinner/Makefile ++++ b/arch/arm/boot/dts/allwinner/Makefile +@@ -220,6 +220,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ ++ sun8i-h2-plus-bananapi-p2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-p2-zero.dts +@@ -0,0 +1,279 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2023 Zoltan HERPAI ++ * ++ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is: ++ * Copyright (C) 2017 Icenowy Zheng ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "Banana Pi BPI-P2-Zero"; ++ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "c"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "bananapi-p2-zero:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ sw4 { ++ label = "power"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ reg_vdd_cpux: vdd-cpux-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ ++ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1100000 0>, <1300000 1>; ++ }; ++ ++ reg_vcc_dram: vcc-dram { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-dram"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ ++ vin-supply = <®_vcc5v0>; ++ }; ++ ++ reg_vcc1v2: vcc1v2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v2"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ ++ vin-supply = <®_vcc5v0>; ++ }; ++ ++ poweroff { ++ compatible = "regulator-poweroff"; ++ cpu-supply = <®_vcc1v2>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ /* ++ * On the production batch of this board the card detect GPIO is ++ * high active (card inserted), although on the early samples it's ++ * low active. ++ */ ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <1500000>; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ vbat-supply = <®_vcc3v3>; ++ vddio-supply = <®_vcc3v3>; ++ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ ++ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ ++ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++ }; ++ ++}; ++ ++&pio { ++ gpio-line-names = ++ /* PA */ ++ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", ++ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", ++ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", ++ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", ++ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", ++ "CON2-P40", "CON2-P38", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PB */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PC */ ++ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", ++ "CON2-P18", "", "", "CON2-P26", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PD */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "CSI-PWR-EN", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PE */ ++ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", ++ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", ++ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", ++ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PF */ ++ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", ++ "SDC0-D2", "SDC0-DET", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ ++ /* PG */ ++ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", ++ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", ++ "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", ++ "BT-RST-N", "AP-WAKE-BT", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&r_pio { ++ gpio-line-names = ++ /* PL */ ++ "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", ++ "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", ++ "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ /* ++ * There're two micro-USB connectors, one is power-only and another is ++ * OTG. The Vbus of these two connectors are connected together, so ++ * the external USB device will be powered just by the power input ++ * from the power-only USB port. ++ */ ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch new file mode 100644 index 0000000000..68ec333e37 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Petr=20=C5=A0tetiar?= +Date: Thu, 26 Mar 2020 10:09:19 +0100 +Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Petr Štetiar + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -15,6 +15,10 @@ + aliases { + ethernet0 = &emac; + serial0 = &uart0; ++ led-boot = &led_user; ++ led-failsafe = &led_user; ++ led-running = &led_user; ++ led-upgrade = &led_user; + }; + + chosen { +@@ -35,7 +39,7 @@ + leds { + compatible = "gpio-leds"; + +- led-0 { ++ led_user: led-0 { + label = "a64-olinuxino:red:user"; + gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + }; diff --git a/target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch new file mode 100644 index 0000000000..8670d06109 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch @@ -0,0 +1,35 @@ +From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 10 Oct 2021 21:50:18 +0800 +Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases + +Use the SYS LED on the casing for showing system status. + +Signed-off-by: Chukun Pan +--- + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +@@ -23,6 +23,11 @@ + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; ++ ++ led-boot = &led_sys; ++ led-failsafe = &led_sys; ++ led-running = &led_sys; ++ led-upgrade = &led_sys; + }; + + chosen { +@@ -38,7 +43,7 @@ + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + +- led-1 { ++ led_sys: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; diff --git a/target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch new file mode 100644 index 0000000000..76a73ee1f0 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts +@@ -41,3 +41,7 @@ + reg = <1>; + }; + }; ++ ++&pwm { ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch new file mode 100644 index 0000000000..3876852c2b --- /dev/null +++ b/target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch @@ -0,0 +1,72 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +@@ -42,6 +42,11 @@ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; + }; + + &ac_power_supply { +@@ -102,6 +107,21 @@ + reg = <1>; + }; + }; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: wifi@1 { ++ reg = <1>; ++ }; ++}; + + &mmc2 { + pinctrl-names = "default"; +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -35,6 +35,11 @@ + }; + }; + }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; + }; + + &codec { +@@ -124,6 +129,21 @@ + status = "okay"; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: wifi@1 { ++ reg = <1>; ++ }; ++}; ++ + &ohci0 { + status = "okay"; + }; diff --git a/target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch b/target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch new file mode 100644 index 0000000000..c17d28c691 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch @@ -0,0 +1,107 @@ +From 4c3a3af679bd59660ac80889b560bddaf475ba81 Mon Sep 17 00:00:00 2001 +From: Michel Promonet +Date: Sun, 21 Jul 2024 19:04:19 +0200 +Subject: [PATCH] sunxi: add csi video support for nanopi-neo-air + +--- + .../dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 85 +++++++++++++++++++ + 1 file changed, 85 insertions(+) + +--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts ++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts +@@ -77,6 +77,39 @@ + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; ++ ++ cam_xclk: cam-xclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "cam-xclk"; ++ }; ++ ++ reg_cam_avdd: cam-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-avdd"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dovdd: cam-dovdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-dovdd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dvdd: cam-dvdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-dvdd"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ + }; + + &mmc0 { +@@ -141,3 +174,55 @@ + /* USB VBUS is always on */ + status = "okay"; + }; ++ ++&csi { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Parallel bus endpoint */ ++ csi_from_ov5640: endpoint { ++ remote-endpoint = <&ov5640_to_csi>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&cam_xclk>; ++ clock-names = "xclk"; ++ ++ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; ++ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; ++ AVDD-supply = <®_cam_avdd>; ++ DOVDD-supply = <®_cam_dovdd>; ++ DVDD-supply = <®_cam_dvdd>; ++ ++ port { ++ ov5640_to_csi: endpoint { ++ remote-endpoint = <&csi_from_ov5640>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++ }; ++}; ++&i2c2_pins { ++ bias-pull-up; ++}; diff --git a/target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch b/target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch new file mode 100644 index 0000000000..4bf090a080 --- /dev/null +++ b/target/linux/sunxi/patches-6.12/460-f1c100s-sram-driver.patch @@ -0,0 +1,33 @@ +Allwinner ARMv5 F1C100s has similar sram controller to sun4i A10 +Add compatible strings for it. + +Signed-off-by: Mesih Kilinc +Acked-by: Maxime Ripard +--- + drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -98,6 +98,10 @@ static const struct of_device_id sunxi_s + .compatible = "allwinner,sun50i-a64-sram-c", + .data = &sun50i_a64_sram_c.data, + }, ++ { ++ .compatible = "allwinner,suniv-f1c100s-sram-d", ++ .data = &sun4i_a10_sram_d.data, ++ }, + {} + }; + +@@ -430,6 +434,10 @@ static const struct of_device_id sunxi_s + .compatible = "allwinner,sun50i-h616-system-control", + .data = &sun50i_h616_sramc_variant, + }, ++ { ++ .compatible = "allwinner,suniv-f1c100s-system-control", ++ .data = &sun4i_a10_sramc_variant, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); diff --git a/target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch b/target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch new file mode 100644 index 0000000000..8baf969a0f --- /dev/null +++ b/target/linux/sunxi/patches-6.12/461-f1c100s-watchdog-compat.patch @@ -0,0 +1,18 @@ +Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31. +Add compatible string for it. + +Signed-off-by: Mesih Kilinc +--- + drivers/watchdog/sunxi_wdt.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/watchdog/sunxi_wdt.c ++++ b/drivers/watchdog/sunxi_wdt.c +@@ -240,6 +240,7 @@ static const struct of_device_id sunxi_w + { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg }, + { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg }, + { .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg }, ++ { .compatible = "allwinner,suniv-f1c100s-wdt", .data = &sun6i_wdt_reg }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids); From 7727944a5c8adb759f4efd0fe6cacad78407322a Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Thu, 5 Feb 2026 15:27:47 +0000 Subject: [PATCH 03/46] sunxi: 6.18: add missing symbols Add sunxi-related missing symbols that were found during 6.18 migration, and reorder configs. Signed-off-by: Zoltan HERPAI --- target/linux/sunxi/arm926ejs/config-6.12 | 16 ++++++++-------- target/linux/sunxi/config-6.18 | 6 ++++++ target/linux/sunxi/cortexa53/config-6.18 | 4 ++++ target/linux/sunxi/cortexa8/config-6.12 | 2 +- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/linux/sunxi/arm926ejs/config-6.12 b/target/linux/sunxi/arm926ejs/config-6.12 index 8625b9751b..771f130cde 100644 --- a/target/linux/sunxi/arm926ejs/config-6.12 +++ b/target/linux/sunxi/arm926ejs/config-6.12 @@ -1,28 +1,28 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y # CONFIG_ARCH_MULTI_V4 is not set # CONFIG_ARCH_MULTI_V4T is not set CONFIG_ARCH_MULTI_V4_V5=y CONFIG_ARCH_MULTI_V5=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_CPU_AUTO=y CONFIG_ARCH_NR_GPIO=416 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HAS_BINFMT_FLAT=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_COMPAT_32BIT_TIME=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_MACH_SUNIV=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_MACH_SUN4I is not set # CONFIG_MACH_SUN5I is not set # CONFIG_MACH_SUN6I is not set # CONFIG_MACH_SUN7I is not set # CONFIG_MACH_SUN8I is not set # CONFIG_MACH_SUN9I is not set +CONFIG_MACH_SUNIV=y CONFIG_MDIO_BUS_MUX=y CONFIG_MTD_SPI_NAND=y CONFIG_MUSB_PIO_ONLY=y @@ -51,6 +51,6 @@ CONFIG_PINCTRL_SUNIV_F1C100S=y CONFIG_PINCTRL_SUNXI=y CONFIG_SUNIV_F1C100S_CCU=y CONFIG_UNWINDER_ARM=y -CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y diff --git a/target/linux/sunxi/config-6.18 b/target/linux/sunxi/config-6.18 index 5362d3e080..9ef0557655 100644 --- a/target/linux/sunxi/config-6.18 +++ b/target/linux/sunxi/config-6.18 @@ -152,6 +152,7 @@ CONFIG_DTC=y CONFIG_DUMMY_CONSOLE=y CONFIG_DVB_CORE=y CONFIG_DWMAC_GENERIC=y +# CONFIG_DWMAC_SUN55I is not set # CONFIG_DWMAC_SUN8I is not set CONFIG_DWMAC_SUNXI=y CONFIG_DYNAMIC_DEBUG=y @@ -348,6 +349,7 @@ CONFIG_OLD_SIGSUSPEND3=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_PAGE_POOL=y CONFIG_PCS_XPCS=y @@ -374,6 +376,8 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_SUN50I_H616 is not set # CONFIG_PINCTRL_SUN50I_H616_R is not set # CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set # CONFIG_PINCTRL_SUN5I is not set # CONFIG_PINCTRL_SUN6I_A31 is not set # CONFIG_PINCTRL_SUN6I_A31_R is not set @@ -476,6 +480,8 @@ CONFIG_STMMAC_PLATFORM=y CONFIG_SUN4I_A10_CCU=y # CONFIG_SUN4I_EMAC is not set CONFIG_SUN4I_TIMER=y +# CONFIG_SUN50I_H6_PRCM_PPU is not set +# CONFIG_SUN55I_PCK600 is not set CONFIG_SUN5I_CCU=y CONFIG_SUN5I_HSTIMER=y CONFIG_SUN6I_A31_CCU=y diff --git a/target/linux/sunxi/cortexa53/config-6.18 b/target/linux/sunxi/cortexa53/config-6.18 index 9c650f1c4d..65ee51de31 100644 --- a/target/linux/sunxi/cortexa53/config-6.18 +++ b/target/linux/sunxi/cortexa53/config-6.18 @@ -22,6 +22,7 @@ CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_GCS=y CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_PA_BITS=48 CONFIG_ARM64_PA_BITS_48=y @@ -119,6 +120,9 @@ CONFIG_SUN50I_ERRATUM_UNKNOWN1=y CONFIG_SUN50I_H616_CCU=y CONFIG_SUN50I_H6_CCU=y CONFIG_SUN50I_H6_R_CCU=y +# CONFIG_SUN55I_A523_CCU is not set +# CONFIG_SUN55I_A523_MCU_CCU is not set +# CONFIG_SUN55I_A523_R_CCU is not set CONFIG_SUN6I_RTC_CCU=y CONFIG_SUN6I_R_INTC=y CONFIG_SUNXI_NMI_INTC=y diff --git a/target/linux/sunxi/cortexa8/config-6.12 b/target/linux/sunxi/cortexa8/config-6.12 index dbf26947ab..715d340640 100644 --- a/target/linux/sunxi/cortexa8/config-6.12 +++ b/target/linux/sunxi/cortexa8/config-6.12 @@ -8,10 +8,10 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y # CONFIG_MACH_SUN8I is not set # CONFIG_MACH_SUN9I is not set CONFIG_PGTABLE_LEVELS=2 +# CONFIG_PHY_SUN9I_USB is not set CONFIG_PINCTRL_AXP209=y CONFIG_PINCTRL_SUN4I_A10=y CONFIG_PINCTRL_SUN5I=y -# CONFIG_PHY_SUN9I_USB is not set # CONFIG_SPI_SUN6I is not set # CONFIG_SUN8I_A83T_CCU is not set # CONFIG_SUN8I_THERMAL is not set From e78de66600577d065cc2662008333fb2306bea99 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Thu, 5 Feb 2026 15:35:54 +0000 Subject: [PATCH 04/46] sunxi: 6.18: refresh patches Refresh patches as required. Signed-off-by: Zoltan HERPAI --- .../301-orangepi_pc2_usb_otg_to_host_key_power.patch | 2 +- .../patches-6.18/410-sunxi-add-bananapi-p2-zero.patch | 2 +- .../450-arm64-dts-enable-wifi-on-pine64-boards.patch | 8 ++++---- .../sunxi/patches-6.18/460-f1c100s-sram-driver.patch | 8 ++++---- .../sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch | 4 ++-- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch index eea47737fa..8eab29848c 100644 --- a/target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch +++ b/target/linux/sunxi/patches-6.18/301-orangepi_pc2_usb_otg_to_host_key_power.patch @@ -9,7 +9,7 @@ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; wakeup-source; }; -@@ -221,7 +221,7 @@ +@@ -222,7 +222,7 @@ }; &usb_otg { diff --git a/target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch index eed2f0feff..e8f31d42ee 100644 --- a/target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch +++ b/target/linux/sunxi/patches-6.18/410-sunxi-add-bananapi-p2-zero.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -220,6 +220,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ +@@ -224,6 +224,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ diff --git a/target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch index 3876852c2b..7b148fc433 100644 --- a/target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch +++ b/target/linux/sunxi/patches-6.18/450-arm64-dts-enable-wifi-on-pine64-boards.patch @@ -32,8 +32,8 @@ + }; +}; - &mmc2 { - pinctrl-names = "default"; + /* On Wifi/BT connector */ + &mmc1 { --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -35,6 +35,11 @@ @@ -48,8 +48,8 @@ }; &codec { -@@ -124,6 +129,21 @@ - status = "okay"; +@@ -135,6 +140,21 @@ + status = "disabled"; }; +&mmc1 { diff --git a/target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch b/target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch index 4bf090a080..38361c7c5c 100644 --- a/target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch +++ b/target/linux/sunxi/patches-6.18/460-f1c100s-sram-driver.patch @@ -9,7 +9,7 @@ Acked-by: Maxime Ripard --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c -@@ -98,6 +98,10 @@ static const struct of_device_id sunxi_s +@@ -99,6 +99,10 @@ static const struct of_device_id sunxi_s .compatible = "allwinner,sun50i-a64-sram-c", .data = &sun50i_a64_sram_c.data, }, @@ -20,9 +20,9 @@ Acked-by: Maxime Ripard {} }; -@@ -430,6 +434,10 @@ static const struct of_device_id sunxi_s - .compatible = "allwinner,sun50i-h616-system-control", - .data = &sun50i_h616_sramc_variant, +@@ -444,6 +448,10 @@ static const struct of_device_id sunxi_s + .compatible = "allwinner,sun55i-a523-system-control", + .data = &sun55i_a523_sramc_variant, }, + { + .compatible = "allwinner,suniv-f1c100s-system-control", diff --git a/target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch b/target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch index 8baf969a0f..4711187d02 100644 --- a/target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch +++ b/target/linux/sunxi/patches-6.18/461-f1c100s-watchdog-compat.patch @@ -8,10 +8,10 @@ Signed-off-by: Mesih Kilinc --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c -@@ -240,6 +240,7 @@ static const struct of_device_id sunxi_w - { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg }, +@@ -251,6 +251,7 @@ static const struct of_device_id sunxi_w { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg }, { .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg }, + { .compatible = "allwinner,sun55i-a523-wdt", .data = &sun55i_wdt_reg }, + { .compatible = "allwinner,suniv-f1c100s-wdt", .data = &sun6i_wdt_reg }, { /* sentinel */ } }; From f56e68791aa6c5a7ef7b8ed85b8621220364fdbe Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Thu, 5 Feb 2026 14:13:00 +0000 Subject: [PATCH 05/46] sunxi: enable 6.18 testing kernel The sunxi target now supports 6.18 kernel as testing. Tested on: - Linksprite pcDuino2 (cortexa8/a10) - Olimex Olinuxino A20 Micro (cortexa7/a20) - OrangePi 2 (cortexa7/h3) - OrangePi Zero2 (cortexa53/h616) Signed-off-by: Zoltan HERPAI --- target/linux/sunxi/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile index a40a495900..f9f362e66a 100644 --- a/target/linux/sunxi/Makefile +++ b/target/linux/sunxi/Makefile @@ -11,6 +11,7 @@ FEATURES:=ext4 display ramdisk rootfs-part rtc squashfs usb usbgadget SUBTARGETS:=cortexa8 cortexa7 cortexa53 arm926ejs KERNEL_PATCHVER:=6.12 +KERNEL_TESTING_PATCHVER:=6.18 KERNELNAME:=zImage dtbs From 32710715799d753c4f32d8767e219706f7e6e8f2 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Fri, 10 Apr 2026 22:02:59 +0200 Subject: [PATCH 06/46] realtek: eth: harden receive path The hardware usually takes care that - a packet is no larger than the available buffer - has at least a FCS checksum of 4 bytes Nevertheless be cautious and improve the existing packet check. Just in case ... Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22884 Signed-off-by: Robert Marko --- .../realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index ccad659d4e..599c5cf29c 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -1022,11 +1022,11 @@ static int rteth_hw_receive(struct net_device *dev, int ring, int budget) packet = &ctrl->rx_data[ring].packet[slot]; len = packet->len; - if (!len) { - netdev_err(dev, "empty packet received\n"); + if (len < ETH_FCS_LEN || len > RING_BUFFER) { + netdev_err(dev, "invalid packet with %d bytes received\n", len); break; } else if (!dsa) { - len -= 4; + len -= ETH_FCS_LEN; } skb = netdev_alloc_skb_ip_align(dev, len); From 90c0a37ddce63a27abbcea7191811ca2194c0a86 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Wed, 22 Apr 2026 08:33:56 +0000 Subject: [PATCH 07/46] realtek: pcs: switch SerDes polarity to {rx,tx}-polarity With the recent backport of the common PHY properties infrastructure (phy-common-props and the phy_get_manual_{rx,tx}_polarity() helpers) to OpenWrt, the generic `{rx,tx}-polarity` device tree properties are now usable for the Realtek PCS driver. Switch the driver and all affected boards from the local vendor-specific `realtek,pnswap-{rx,tx}` booleans to the common properties. Add a `config_polarity` SerDes op (implemented by RTL930x and RTL931x; RTL838x/RTL839x polarity support not yet added) and a generic wrapper that resolves the requested polarity via phy_get_manual_{rx,tx}_polarity() and dispatches to the op. Variants without the op silently accept the default polarity but warn when a non-default polarity is requested, since that cannot be honored. Move the polarity programming out of the variant setup_serdes callbacks into rtpcs_pcs_config, so it runs before setup_serdes. This matches the ordering used by the vendor SDK, which configures polarity first. Update all board DTS files that previously used `realtek,pnswap-{rx,tx}` to the new `{rx,tx}-polarity = ` property, and select PHY_COMMON_PROPS from Kconfig. Each SerDes now retains its DT node for later polarity lookup. Use for_each_child_of_node_scoped for the iterator, and register a devm_add_action_or_reset for each stored reference so it is released on unbind or probe failure. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/23044 Signed-off-by: Robert Marko --- .../realtek/dts/rtl9311_linksys_lgs352c.dts | 10 ++- .../dts/rtl9313_xikestor_sks8300-12x-v1.dts | 25 +++--- .../realtek/dts/rtl9313_zyxel_xs1930-10.dts | 21 ++--- .../realtek/dts/rtl9313_zyxel_xs1930-12f.dts | 21 ++--- .../realtek/dts/rtl9313_zyxel_xs1930-12hp.dts | 25 +++--- .../files-6.18/drivers/net/pcs/pcs-rtl-otto.c | 85 ++++++++++++++----- .../patches-6.18/730-add-pcs-rtl-otto.patch | 3 +- 7 files changed, 120 insertions(+), 70 deletions(-) diff --git a/target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts b/target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts index 7e039e0582..f7e3e21f19 100644 --- a/target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts +++ b/target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts @@ -4,6 +4,8 @@ #include "rtl931x.dtsi" #include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi" +#include + / { compatible = "linksys,lgs352c", "realtek,rtl9311-soc"; model = "Linksys LGS352C"; @@ -238,17 +240,17 @@ }; &serdes8 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes9 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes10 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes11 { - realtek,pnswap-tx; + tx-polarity = ; }; diff --git a/target/linux/realtek/dts/rtl9313_xikestor_sks8300-12x-v1.dts b/target/linux/realtek/dts/rtl9313_xikestor_sks8300-12x-v1.dts index abe2e67297..d3b46c73d8 100644 --- a/target/linux/realtek/dts/rtl9313_xikestor_sks8300-12x-v1.dts +++ b/target/linux/realtek/dts/rtl9313_xikestor_sks8300-12x-v1.dts @@ -5,6 +5,7 @@ #include #include #include +#include / { compatible = "xikestor,sks8300-12x-v1", "realtek,rtl9313-soc"; @@ -488,50 +489,50 @@ }; &serdes2 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes3 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes4 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes5 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes6 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes7 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes8 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes9 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes10 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes11 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes12 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes13 { - realtek,pnswap-tx; + tx-polarity = ; }; diff --git a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-10.dts b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-10.dts index 1f560bd03c..69a4b1e492 100644 --- a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-10.dts +++ b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-10.dts @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "zyxel,xs1930-10", "realtek,rtl9313-soc"; @@ -220,29 +221,29 @@ }; &serdes6 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes7 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes8 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes9 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes12 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes13 { - realtek,pnswap-tx; + tx-polarity = ; }; diff --git a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts index 1c5989f7e8..2a5afafb05 100644 --- a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts +++ b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "zyxel,xs1930-12f", "realtek,rtl9313-soc"; @@ -303,42 +304,42 @@ }; &serdes2 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes3 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes4 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes5 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes6 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes7 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes8 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes9 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes10 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes11 { - realtek,pnswap-tx; + tx-polarity = ; }; diff --git a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12hp.dts b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12hp.dts index 1eab2398ea..5ce41110de 100644 --- a/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12hp.dts +++ b/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12hp.dts @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "zyxel,xs1930-12hp", "realtek,rtl9313-soc"; @@ -266,37 +267,37 @@ }; &serdes6 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes7 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes8 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes9 { - realtek,pnswap-rx; - realtek,pnswap-tx; + rx-polarity = ; + tx-polarity = ; }; &serdes10 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes11 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes12 { - realtek,pnswap-tx; + tx-polarity = ; }; &serdes13 { - realtek,pnswap-tx; + tx-polarity = ; }; diff --git a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c index c8429b4596..2c6fa8bf2c 100644 --- a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c @@ -6,8 +6,9 @@ #include #include #include -#include +#include #include +#include #include #define RTPCS_SDS_CNT 14 @@ -188,6 +189,9 @@ struct rtpcs_sds_ops { int (*reset_cmu)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); /* online reconfiguration of a running SerDes to another PLL */ int (*reconfigure_to_pll)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); + + int (*config_polarity)(struct rtpcs_serdes *sds, unsigned int tx_pol, + unsigned int rx_pol); }; struct rtpcs_sds_reg_field { @@ -205,6 +209,7 @@ struct rtpcs_sds_regs { struct rtpcs_serdes { struct rtpcs_ctrl *ctrl; + struct device_node *of_node; const struct rtpcs_sds_ops *ops; const struct rtpcs_sds_regs *regs; enum rtpcs_sds_type type; @@ -212,9 +217,6 @@ struct rtpcs_serdes { u8 id; u8 num_of_links; bool first_start; - - bool rx_pol_inv; - bool tx_pol_inv; }; struct rtpcs_ctrl { @@ -2768,11 +2770,11 @@ static int rtpcs_930x_sds_10g_idle(struct rtpcs_serdes *sds) return -ETIMEDOUT; } -static int rtpcs_930x_sds_set_polarity(struct rtpcs_serdes *sds, - bool tx_inv, bool rx_inv) +static int rtpcs_930x_sds_config_polarity(struct rtpcs_serdes *sds, unsigned int tx_pol, + unsigned int rx_pol) { - u8 rx_val = rx_inv ? 1 : 0; - u8 tx_val = tx_inv ? 1 : 0; + u8 rx_val = (rx_pol == PHY_POL_INVERT) ? 1 : 0; + u8 tx_val = (tx_pol == PHY_POL_INVERT) ? 1 : 0; u32 val; int ret; @@ -3014,9 +3016,6 @@ static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds, /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */ rtpcs_930x_phy_enable_10g_1g(sds); - /* Set SDS polarity */ - rtpcs_930x_sds_set_polarity(sds, sds->tx_pol_inv, sds->rx_pol_inv); - /* Enable SDS in desired mode */ ret = rtpcs_930x_sds_set_mode(sds, hw_mode); if (ret < 0) @@ -3526,11 +3525,11 @@ static int rtpcs_931x_sds_link_sts_get(struct rtpcs_serdes *sds) return sts1; } -static int rtpcs_931x_sds_set_polarity(struct rtpcs_serdes *sds, - bool tx_inv, bool rx_inv) +static int rtpcs_931x_sds_config_polarity(struct rtpcs_serdes *sds, unsigned int tx_pol, + unsigned int rx_pol) { - u8 rx_val = rx_inv ? 1 : 0; - u8 tx_val = tx_inv ? 1 : 0; + u8 rx_val = (rx_pol == PHY_POL_INVERT) ? 1 : 0; + u8 tx_val = (tx_pol == PHY_POL_INVERT) ? 1 : 0; u32 val; int ret; @@ -3901,8 +3900,6 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds, return ret; } - rtpcs_931x_sds_set_polarity(sds, sds->tx_pol_inv, sds->rx_pol_inv); - rtpcs_931x_sds_power(sds, true); ret = rtpcs_931x_sds_set_mode(sds, hw_mode); @@ -3971,6 +3968,34 @@ static int rtpcs_931x_init(struct rtpcs_ctrl *ctrl) /* Common functions */ +static int rtpcs_sds_config_polarity(struct rtpcs_serdes *sds, phy_interface_t if_mode) +{ + unsigned int rx_pol, tx_pol; + int ret; + + if (!sds->of_node) + return 0; + + ret = phy_get_manual_rx_polarity(of_fwnode_handle(sds->of_node), phy_modes(if_mode), + &rx_pol); + if (ret < 0) + return ret; + + ret = phy_get_manual_tx_polarity(of_fwnode_handle(sds->of_node), phy_modes(if_mode), + &tx_pol); + if (ret < 0) + return ret; + + if (!sds->ops->config_polarity) { + if (tx_pol != PHY_POL_NORMAL || rx_pol != PHY_POL_NORMAL) + dev_warn(sds->ctrl->dev, + "Polarity change requested but not supported\n"); + return 0; + } + + return sds->ops->config_polarity(sds, tx_pol, rx_pol); +} + static void rtpcs_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) { @@ -4067,6 +4092,13 @@ static int rtpcs_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, dev_info(ctrl->dev, "configure SerDes %u for mode %s\n", sds->id, phy_modes(interface)); + ret = rtpcs_sds_config_polarity(sds, interface); + if (ret < 0) { + dev_err(ctrl->dev, "failed to configure polarity of SerDes %u\n", + sds->id); + goto out; + } + ret = ctrl->cfg->setup_serdes(sds, hw_mode); if (ret < 0) goto out; @@ -4179,11 +4211,17 @@ static struct mii_bus *rtpcs_probe_serdes_bus(struct rtpcs_ctrl *ctrl) return bus; } +static void rtpcs_sds_put_of_node(void *data) +{ + struct rtpcs_serdes *sds = data; + + of_node_put(sds->of_node); +} + static int rtpcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; - struct device_node *child; struct rtpcs_serdes *sds; struct rtpcs_ctrl *ctrl; u32 sds_id; @@ -4219,16 +4257,19 @@ static int rtpcs_probe(struct platform_device *pdev) return ret; } - for_each_child_of_node(dev->of_node, child) { + for_each_child_of_node_scoped(dev->of_node, child) { ret = of_property_read_u32(child, "reg", &sds_id); if (ret) return ret; + if (sds_id >= ctrl->cfg->serdes_count) return -EINVAL; sds = &ctrl->serdes[sds_id]; - sds->rx_pol_inv = of_property_read_bool(child, "realtek,pnswap-rx"); - sds->tx_pol_inv = of_property_read_bool(child, "realtek,pnswap-tx"); + sds->of_node = of_node_get(child); + ret = devm_add_action_or_reset(dev, rtpcs_sds_put_of_node, sds); + if (ret) + return ret; } if (ctrl->cfg->init) { @@ -4336,6 +4377,7 @@ static const struct rtpcs_sds_ops rtpcs_930x_sds_ops = { .set_pll_select = rtpcs_930x_sds_set_pll_select, .reset_cmu = rtpcs_930x_sds_reset_cmu, .reconfigure_to_pll = rtpcs_930x_sds_reconfigure_to_pll, + .config_polarity = rtpcs_930x_sds_config_polarity, }; static const struct rtpcs_sds_regs rtpcs_930x_sds_regs = { @@ -4376,6 +4418,7 @@ static const struct rtpcs_sds_ops rtpcs_931x_sds_ops = { .get_pll_select = rtpcs_931x_sds_get_pll_select, .set_pll_select = rtpcs_931x_sds_set_pll_select, .reconfigure_to_pll = rtpcs_931x_sds_reconfigure_to_pll, + .config_polarity = rtpcs_931x_sds_config_polarity, }; static const struct rtpcs_sds_regs rtpcs_931x_sds_regs = { diff --git a/target/linux/realtek/patches-6.18/730-add-pcs-rtl-otto.patch b/target/linux/realtek/patches-6.18/730-add-pcs-rtl-otto.patch index 6fee826884..dc242c495d 100644 --- a/target/linux/realtek/patches-6.18/730-add-pcs-rtl-otto.patch +++ b/target/linux/realtek/patches-6.18/730-add-pcs-rtl-otto.patch @@ -11,13 +11,14 @@ Signed-off-by: Markus Stockhausen --- --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig -@@ -45,6 +45,14 @@ config PCS_MTK_USXGMII +@@ -45,6 +45,15 @@ config PCS_MTK_USXGMII 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same differential pairs via an embedded LynxI PCS. +config PCS_RTL_OTTO + tristate "Realtek Otto SerDes PCS" + depends on MACH_REALTEK_RTL || COMPILE_TEST ++ select PHY_COMMON_PROPS + select PHYLINK + select REGMAP + help From d7512950ba5b0cbebe3826e046f18056bbf53261 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Thu, 23 Apr 2026 11:27:03 +0200 Subject: [PATCH 08/46] util-linux: fix build on Linux v6.18 against musl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Backport an upstream patch to avoid usages of an undefined AT_HANDLE_FID. Closes: https://github.com/openwrt/openwrt/issues/23058 Signed-off-by: Thomas Weißschuh Link: https://github.com/openwrt/openwrt/pull/23059 Signed-off-by: Robert Marko --- ...01-nsenter-Fix-AT_HANDLE_FID-on-musl.patch | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 package/utils/util-linux/patches/0001-nsenter-Fix-AT_HANDLE_FID-on-musl.patch diff --git a/package/utils/util-linux/patches/0001-nsenter-Fix-AT_HANDLE_FID-on-musl.patch b/package/utils/util-linux/patches/0001-nsenter-Fix-AT_HANDLE_FID-on-musl.patch new file mode 100644 index 0000000000..f33ad251f0 --- /dev/null +++ b/package/utils/util-linux/patches/0001-nsenter-Fix-AT_HANDLE_FID-on-musl.patch @@ -0,0 +1,30 @@ +From 5452239f6e69d2d3aaa427d2d2253247cfb7cb7b Mon Sep 17 00:00:00 2001 +From: Aleksi Hannula +Date: Tue, 7 Apr 2026 14:52:16 +0300 +Subject: [PATCH] nsenter: Fix AT_HANDLE_FID on musl +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Aleksi Hannula +--- + sys-utils/nsenter.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/sys-utils/nsenter.c b/sys-utils/nsenter.c +index e10ba9cf90ab..98507958c0f1 100644 +--- a/sys-utils/nsenter.c ++++ b/sys-utils/nsenter.c +@@ -29,6 +29,9 @@ + #ifdef HAVE_LINUX_NSFS_H + # include + #endif ++#ifndef AT_HANDLE_FID ++# define AT_HANDLE_FID 0x200 ++#endif + #ifndef NS_GET_USERNS + # define NS_GET_USERNS _IO(0xb7, 0x1) + #endif +-- +2.53.0 + From 8275b62ecddd2c7e186d97846c9fe79130f52941 Mon Sep 17 00:00:00 2001 From: Carlo Szelinsky Date: Sat, 11 Apr 2026 17:11:25 +0200 Subject: [PATCH 09/46] realtek: rtl930x: add Hasivo S600WP-5GT-2SX-SE This commit adds support for Hasivo S600WP-5GT-2SX-SE switch. Device specification -------------------- SoC Type: Realtek RTL9303 RAM: 128MB DDR3 SDRAM Flash: Fudan FM25Q128A (16 MB) Ethernet: 5x RTL8221B 10/100/1000/2500Mbps PHY (RJ45) 2x SFP+ 10G (I2C/DOM via bit-banged GPIO) LEDs: 1x power green (no control) 1x system green (via RTL9303 GPIO) 3x RJ45 LEDs/port (HC595 shift regs on LED SPI) 1x Green (1G link) 1x Green (10M/100M link) 1x Orange (2.5G link) 2x SFP+ LEDs/port (HC595 shift regs on LED SPI) 1x 10G link 1x 1G link Button: Reset USB ports: None Bootloader: Realtek U-Boot 2011.12 PoE: 1x HS104PTI for 802.3af/at/bt PoE (driver will follow in a separate patch) Installing OpenWrt ------------------ 1. UART RJ45 requires soldering a connector to the empty footprint (RJ1). (Amphenol RJHSEE380 or similar) 2. Connect to UART 38400@8n1, using Cisco Console Rollover cable (RS232) 3. Enter bootloader by pressing esc key during boot 4. Enter password `Hs2021cfgmg` 5. Type `XXXX` to get into U-Boot 6. Increase baudrate: `setenv baudrate 115200` 7. Use serial transfer (Y modem) via minicom: `loady 0x84f00000` Then send the initramfs image via minicom's Y modem upload. 8. `bootm 0x84f00000` Now you should be in OpenWrt, and can use sysupgrade to install. Signed-off-by: Carlo Szelinsky Link: https://github.com/openwrt/openwrt/pull/22310 Signed-off-by: Robert Marko --- .../realtek/base-files/etc/board.d/02_network | 1 + .../dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts | 310 ++++++++++++++++++ target/linux/realtek/image/rtl930x.mk | 9 + 3 files changed, 320 insertions(+) create mode 100644 target/linux/realtek/dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network index df064c4e8e..f6ba62a08c 100644 --- a/target/linux/realtek/base-files/etc/board.d/02_network +++ b/target/linux/realtek/base-files/etc/board.d/02_network @@ -77,6 +77,7 @@ realtek_setup_macs() ;; d-link,dgs-1250-28x|\ hasivo,s1100wp-8gt-se|\ + hasivo,s600wp-5gt-2sx-se|\ hpe,1920-8g|\ hpe,1920-8g-poe-65w|\ hpe,1920-8g-poe-180w|\ diff --git a/target/linux/realtek/dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts b/target/linux/realtek/dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts new file mode 100644 index 0000000000..db999d7b01 --- /dev/null +++ b/target/linux/realtek/dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl930x.dtsi" + +#include +#include +#include + +/ { + compatible = "hasivo,s600wp-5gt-2sx-se"; + model = "Hasivo S600WP-5GT-2SX-SE"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; /* 128 MiB */ + }; + + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + label-mac-device = ðernet0; + }; + + chosen { + stdout-path = "serial0:38400n8"; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>, <&pinmux_enable_led_sync>; + + led_sys: led-0 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + }; + }; + + led_set { + compatible = "realtek,rtl9300-leds"; + + /* Port 25 is unused but present in the HC595 shift + * register chain. Force it into the serial LED stream + * to align all LED positions correctly. + */ + realtek,led-set0-force-port-mask = <(1 << 25)>; + + /* + * RJ45 LED0 (green): 1G/LINK/ACT + * RJ45 LED1 (green): 10M/100M/LINK/ACT + * RJ45 LED2 (orange): 2.5G/LINK/ACT + */ + led_set0 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | + RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>; + + /* + * SFP+ LED0: 10G/LINK/ACT + * SFP+ LED1: 1G/LINK/ACT + * SFP+ LED2: spacer to keep 3 slots per port + */ + led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_NONE)>; + }; + + /* + * TODO: I2C bus to the on-board HS104 PSE controller (PoE). + * Defined here for documentation/future use; currently unused + * because PSE/PoE support for this board is not yet wired up. + */ + i2c_scl23_sda22: i2c-scl23-sda22 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + }; + + i2c_sfp0: i2c-sfp0 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + scl-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <50>; + }; + + i2c_sfp1: i2c-sfp1 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + scl-gpios = <&gpio0 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <50>; + }; + + sfp0: sfp-p26 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp0>; + mod-def0-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2500>; + }; + + sfp1: sfp-p27 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + mod-def0-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + /* + * Stock firmware wires tx-disable to GPIO 12 (FB_TXDIS_1). + * The pin is not claimed by the hardware I2C controller + * (SDA pinmux is in GPIO mode) but still cannot be driven + * HIGH for unknown reasons. Omitted for now. + */ + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "fudan,fm25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* stock is LOADER */ + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x00e0000>; + read-only; + }; + + /* stock is BDINFO */ + partition@e0000 { + label = "u-boot-env"; + reg = <0x00e0000 0x0010000>; + + nvmem-layout { + compatible = "u-boot,env"; + + macaddr_ubootenv_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + serialnumber_ubootenv: serialnumber { + #nvmem-cell-cells = <1>; + }; + pse_bt_port_no_ubootenv: pse_bt_port_no { + #nvmem-cell-cells = <1>; + }; + pse_existed_flag_ubootenv: pse_existed_flag { + #nvmem-cell-cells = <1>; + }; + pse_power_bank_ubootenv: pse_power_bank { + #nvmem-cell-cells = <1>; + }; + }; + }; + + /* stock is SYSINFO */ + partition@f0000 { + label = "u-boot-env2"; + reg = <0x00f0000 0x0010000>; + read-only; + }; + + /* stock is JFFS2_CFG */ + partition@100000 { + label = "jffs"; + reg = <0x0100000 0x0100000>; + }; + + /* stock is JFFS2_LOG */ + partition@200000 { + label = "jffs2"; + reg = <0x0200000 0x0100000>; + }; + + /* stock is RUNTIME */ + partition@300000 { + compatible = "openwrt,uimage", "denx,uimage"; + label = "firmware"; + reg = <0x0300000 0x0c00000>; + }; + + /* stock is OEMINFO */ + partition@f00000 { + label = "oeminfo"; + reg = <0x0f00000 0x0100000>; + read-only; + }; + }; + }; +}; + +ðernet0 { + nvmem-cells = <&macaddr_ubootenv_ethaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&mdio_bus0 { + /* External RTL8221B PHYs */ + PHY_C45(0, 1) + PHY_C45(8, 2) + PHY_C45(16, 3) + PHY_C45(20, 4) +}; + +&mdio_bus1 { + /* External RTL8221B PHY */ + PHY_C45(24, 1) +}; + +&switch0 { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + pcs-handle = <&serdes2>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + led-set = <0>; + }; + + port@8 { + reg = <8>; + label = "lan2"; + pcs-handle = <&serdes3>; + phy-handle = <&phy8>; + phy-mode = "sgmii"; + managed = "in-band-status"; + led-set = <0>; + }; + + port@16 { + reg = <16>; + label = "lan3"; + pcs-handle = <&serdes4>; + phy-handle = <&phy16>; + phy-mode = "sgmii"; + managed = "in-band-status"; + led-set = <0>; + }; + + port@20 { + reg = <20>; + label = "lan4"; + pcs-handle = <&serdes5>; + phy-handle = <&phy20>; + phy-mode = "sgmii"; + managed = "in-band-status"; + led-set = <0>; + }; + + port@24 { + reg = <24>; + label = "lan5"; + pcs-handle = <&serdes6>; + phy-handle = <&phy24>; + phy-mode = "sgmii"; + managed = "in-band-status"; + led-set = <0>; + }; + + SWITCH_PORT_SFP(26, 6, 8, 1, 0) + SWITCH_PORT_SFP(27, 7, 9, 1, 1) + + /* Internal SoC */ + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk index 8731e4ba61..20f96c3ae4 100644 --- a/target/linux/realtek/image/rtl930x.mk +++ b/target/linux/realtek/image/rtl930x.mk @@ -30,6 +30,15 @@ define Device/hasivo_s1100wp-8gt-se endef TARGET_DEVICES += hasivo_s1100wp-8gt-se +define Device/hasivo_s600wp-5gt-2sx-se + SOC := rtl9303 + DEVICE_VENDOR := Hasivo + DEVICE_MODEL := S600WP-5GT-2SX-SE + IMAGE_SIZE := 12288k + $(Device/kernel-lzma) +endef +TARGET_DEVICES += hasivo_s600wp-5gt-2sx-se + define Device/plasmacloud-common SOC := rtl9302 UIMAGE_MAGIC := 0x93000000 From bdd216a4ec6d5a2c04424c1dcbeb4e8736fcdd94 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 17 Apr 2026 14:42:20 +0100 Subject: [PATCH 10/46] mediatek: drop v6.12 and default to v6.18 Switch to kernel v6.18 and drop v6.12. Signed-off-by: Daniel Golle --- target/linux/mediatek/Makefile | 3 +- .../mt7981-rfb-mxl-2p5g-phy-eth1.dtso | 34 - .../mt7981-rfb-mxl-2p5g-phy-swp5.dtso | 35 - .../dts/mediatek/mt7981-rfb-spim-nand.dtso | 76 - .../arm64/boot/dts/mediatek/mt7981-rfb.dts | 189 -- .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 50 - .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 49 - .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 391 --- .../files-6.12/drivers/mfd/airoha-an8855.c | 278 -- .../files-6.12/drivers/net/dsa/an8855.c | 2307 ----------------- .../files-6.12/drivers/net/dsa/an8855.h | 783 ------ .../files-6.12/drivers/net/mdio/mdio-an8855.c | 113 - .../files-6.12/drivers/net/phy/air_an8855.c | 267 -- .../files-6.12/drivers/nvmem/an8855-efuse.c | 63 - .../include/linux/mfd/airoha-an8855-mfd.h | 41 - target/linux/mediatek/filogic/config-6.12 | 534 ---- target/linux/mediatek/mt7622/config-6.12 | 516 ---- target/linux/mediatek/mt7623/config-6.12 | 525 ---- target/linux/mediatek/mt7629/config-6.12 | 367 --- ...tek-add-support-for-MTK_PULL_PD_TYPE.patch | 151 -- ...l-mediatek-add-MT7988-pinctrl-driver.patch | 1610 ------------ ...ediatek-Drop-mtk_pinconf_bias_set_pd.patch | 41 - ...mediatek-mt7988-add-UART-controllers.patch | 71 - ...-dts-mediatek-mt7988-add-efuse-block.patch | 35 - ...-mediatek-mt7988-Add-pinctrl-support.patch | 85 - ...-mediatek-mt7988-Add-reserved-memory.patch | 37 - ...-dts-mediatek-mt7988-Add-mmc-support.patch | 52 - ...64-dts-mediatek-mt7988-Add-lvts-node.patch | 62 - ...dts-mediatek-mt7988-Add-thermal-zone.patch | 39 - ...atek-mt7988-Add-mcu-sys-node-for-cpu.patch | 31 - ...ek-mt7988-Add-CPU-OPP-table-for-cloc.patch | 84 - ...ek-mt7988-Disable-usb-controllers-by.patch | 34 - ...mediatek-mt7988-Add-t-phy-for-ssusb1.patch | 59 - ...4-dts-mediatek-mt7988-Add-pcie-nodes.patch | 176 -- ...ek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch | 211 -- ...iatek-mt7988a-bpi-r4-Enable-watchdog.patch | 25 - ...ek-mt7988a-bpi-r4-Add-fixed-regulato.patch | 48 - ...ek-mt7988a-bpi-r4-Add-thermal-config.patch | 54 - ...ek-mt7988a-bpi-r4-Enable-serial0-deb.patch | 41 - ...ek-mt7988a-bpi-r4-Add-default-UART-s.patch | 29 - ...ek-mt7988a-bpi-r4-Enable-I2C-control.patch | 72 - ...ek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch | 74 - ...ek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch | 41 - ...ek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch | 41 - ...s-mediatek-mt7988a-bpi-r4-Enable-pwm.patch | 40 - ...-mediatek-mt7988a-bpi-r4-Enable-pcie.patch | 83 - ...ek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch | 96 - ...ek-mt7988a-bpi-r4-Add-proc-supply-fo.patch | 80 - ...xsphy-support-type-switch-by-pericfg.patch | 169 -- ...ruct-device-pointer-to-device-contex.patch | 60 - ...13-mmc-mtk-sd-add-support-for-mt7988.patch | 28 - ...ek-mt7986-bpi-r3-Change-fan-PWM-valu.patch | 72 - ...ek-add-thermal-sensor-support-on-mt7.patch | 69 - ...k-enable-ies_present-flag-for-MT798x.patch | 59 - .../100-dts-update-mt7622-rfb1.patch | 130 - .../101-dts-update-mt7629-rfb.patch | 73 - .../103-mt7623-enable-arch-timer.patch | 20 - .../104-mt7622-add-snor-irq.patch | 20 - .../105-dts-mt7622-enable-pstore.patch | 26 - .../106-dts-mt7622-disable_btif.patch | 35 - .../110-dts-fix-bpi2-console.patch | 20 - .../111-dts-fix-bpi64-console.patch | 21 - .../112-dts-fix-bpi64-lan-names.patch | 48 - .../113-dts-fix-bpi64-leds-and-buttons.patch | 61 - .../114-dts-bpi64-disable-rtc.patch | 24 - ...m64-dts-mediatek-fix-t-phy-unit-name.patch | 33 - ...ek-mt7622-readd-syscon-to-pciesys-no.patch | 33 - .../117-complete-mt7981b-dtsi.patch | 657 ----- ...iatek-MT7981-some-register-map-fixes.patch | 76 - .../121-hack-spi-nand-1b-bbm.patch | 31 - .../130-dts-mt7629-add-snand-support.patch | 94 - .../131-dts-mt7622-add-snand-support.patch | 79 - ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 29 - ...s-mt7623-eip97-inside-secure-support.patch | 37 - .../160-dts-mt7623-bpi-r2-earlycon.patch | 22 - ...1-dts-mt7623-bpi-r2-mmc-device-order.patch | 22 - .../162-dts-mt7623-bpi-r2-led-aliases.patch | 38 - ...163-dts-mt7623-bpi-r2-ethernet-alias.patch | 20 - ...ts-mt7623-bpi-r2-rootdisk-for-fitblk.patch | 66 - ...ek-mt7988a-bpi-r4-allow-hw-variants-.patch | 876 ------- ...ek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch | 75 - ...mediatek-mt7988a-bpi-r4-enable-xsphy.patch | 37 - ...-built-in-ethernet-phy-firmware-node.patch | 27 - ...-mediatek-mt7988-add-spi-controllers.patch | 69 - ...ek-mt7988-move-uart0-and-spi1-pins-t.patch | 90 - ...m64-dts-mediatek-mt7988-add-cci-node.patch | 86 - ...ek-mt7988-add-phy-calibration-efuse-.patch | 42 - ...atek-mt7988-add-basic-ethernet-nodes.patch | 213 -- ...-dts-mediatek-mt7988-add-switch-node.patch | 228 -- ...ek-mt7988a-bpi-r4-Add-fan-and-coolin.patch | 59 - ...ek-mt7988a-bpi-r4-configure-spi-node.patch | 55 - ...ek-mt7988a-bpi-r4-add-proc-supply-fo.patch | 28 - ...pi-r4-add-sfp-cages-and-link-to-gmac.patch | 138 - ...pi-r4-configure-switch-phys-and-leds.patch | 113 - ...988a-add-serial1-and-serial2-aliases.patch | 33 - .../186-arm64-dts-mt7988a-complete-dtsi.patch | 235 -- ...4-dts-mediatek-fix-mt7981-spim-clock.patch | 53 - ...ek-add-MT7988A-reference-board-devic.patch | 1293 --------- ...dts-mediatek-mt7988a-complete-bpi-r4.patch | 488 ---- ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 106 - .../193-dts-mt7623-thermal_zone_fix.patch | 48 - .../194-dts-mt7968a-add-ramoops.patch | 27 - ...i-r3-leds-port-names-and-wifi-eeprom.patch | 208 -- ...7986a-bpi-r3-use-all-ubi-nand-layout.patch | 127 - .../198-dts-mt7988a-enable-wed.patch | 177 -- ...ek-mt7986-increase-ATF-reserved-memo.patch | 29 - ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 66 - ...ci-use-devres-for-resource-managemen.patch | 241 -- ...cci-check-cpufreq-availability-early.patch | 53 - ...nfracfg-SPI0-clocks-are-not-critical.patch | 65 - ...k-add-support-for-hw-access-via-SMCC.patch | 212 -- .../330-snand-mtk-bmt-support.patch | 46 - .../331-mt7622-rfb1-enable-bmt.patch | 17 - ...Add-support-for-the-Fidelix-FM35X1GA.patch | 123 - ...freq-mediatek-Add-support-for-MT7988.patch | 45 - ...-mediatek-add-mt7987-pinctrl-support.patch | 793 ------ ...tek-add-mt7987-clock-drivers-support.patch | 1187 --------- ...ypto-add-eip97-inside-secure-support.patch | 39 - ...01-crypto-fix-eip97-cache-incoherent.patch | 38 - .../patches-6.12/410-bt-mtk-serial-fix.patch | 45 - ...-mtd-spinand-fix-support-for-FORESEE.patch | 32 - ...xx-Move-chip_config-to-driver-s-priv.patch | 131 - ...-Add-support-for-dynamic-calibration.patch | 236 -- ...ers-spi-mem-Add-spi-calibration-hook.patch | 41 - ...xx-Add-controller-s-calibration-para.patch | 43 - ...and-Add-calibration-support-for-spin.patch | 81 - ...nor-Add-calibration-support-for-spi-.patch | 57 - ...-nvmem-add-layout-for-Adtran-devices.patch | 192 -- .../500-gsw-rtl8367s-mt7622-support.patch | 36 - ...s-mediatek-add-mt7622-pcie-slot-node.patch | 39 - ...diatek-fix-clearing-interrupt-status.patch | 23 - ...1-pcie-mediatek-gen3-PERST-for-100ms.patch | 29 - ...-Add-2.5Gphy-firmware-dt-bindings-an.patch | 71 - ...-add-driver-for-built-in-2.5G-ethern.patch | 399 --- ...ediatek-add-support-for-coherent-DMA.patch | 91 - .../721-dts-mt7622-mediatek-fix-300mhz.patch | 27 - .../722-remove-300Hz-to-prevent-freeze.patch | 42 - .../734-net-phy-add-Airoha-EN8801SC-PHY.patch | 38 - ...pcs-mtk_usxgmii-add-polarity-control.patch | 65 - .../737-net-dsa-add-Airoha-AN8855.patch | 309 --- ...net-pcs-mtk_lynxi-add-mt7987-support.patch | 36 - ...-mtk-lynxi-add-phya-tx-rx-clock-path.patch | 89 - ...ernet-mtk_eth_soc-add-mt7987-support.patch | 325 --- ...se-hardware-configuration-for-mt7987.patch | 79 - ...ediatek-i2p5g-add-support-for-mt7987.patch | 419 --- .../821-add-pwm-feature-for-mt7987.patch | 44 - ...-lvts_thermal-Add-irq_enable-support.patch | 148 -- ...atek-lvts_thermal-Add-MT7987-support.patch | 106 - ...ort-to-adjust-cpu-volt-by-efuse-cali.patch | 106 - ...u-volt-correction-support-for-mt7988.patch | 45 - ...-efuse-cali-data-for-mt7988-cpu-volt.patch | 48 - ...ufreq-add-support-to-fix-voltage-cpu.patch | 33 - ...freq-mediatek-Add-support-for-MT7987.patch | 34 - .../862-arm64-dts-mt7986-add-afe.patch | 41 - ...63-arm64-dts-mt7986-add-sound-wm8960.patch | 62 - ...-mt7986-add-sound-overlay-for-bpi-r3.patch | 123 - ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 78 - .../901-arm-add-cmdline-override.patch | 68 - .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 45 - .../911-dts-mt7622-bpi-r64-add-rootdisk.patch | 119 - ...-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch | 314 --- ...-msdos-add-OF-node-by-partition-numb.patch | 98 - .../930-spi-mt65xx-enable-sel-clk.patch | 30 - ..._wed-rename-mtk_wed_get_memory_regio.patch | 37 - ...986-move-cpuboot-in-a-dedicated-node.patch | 66 - ..._wed-move-cpuboot-in-a-dedicated-dts.patch | 103 - ...tk_wed-move-ilm-a-dedicated-dts-node.patch | 86 - ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 57 - ...-mt7986-move-ilm-in-a-dedicated-node.patch | 83 - ...-mt7986-move-dlm-in-a-dedicated-node.patch | 81 - .../950-smartrg-i2c-led-driver.patch | 44 - ...i-r3-add-label-to-gmac-for-sfp1-port.patch | 24 - ...960-asus-hack-u-boot-ignore-mtdparts.patch | 47 - .../965-dts-mt7988a-add-trng-support.patch | 30 - ...mediatek-gen3-Add-WIFI-HW-reset-flow.patch | 88 - 175 files changed, 1 insertion(+), 25442 deletions(-) delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts delete mode 100644 target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts delete mode 100644 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mode 100644 target/linux/mediatek/patches-6.12/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch delete mode 100644 target/linux/mediatek/patches-6.12/920-block-partitions-msdos-add-OF-node-by-partition-numb.patch delete mode 100644 target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch delete mode 100644 target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch delete mode 100644 target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch delete mode 100644 target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch delete mode 100644 target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch delete mode 100644 target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch delete mode 100644 target/linux/mediatek/patches-6.12/965-dts-mt7988a-add-trng-support.patch delete mode 100644 target/linux/mediatek/patches-6.12/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index e5bc90f7e5..2515948b68 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -8,8 +8,7 @@ BOARDNAME:=MediaTek ARM SUBTARGETS:=filogic mt7622 mt7623 mt7629 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb -KERNEL_PATCHVER:=6.12 -KERNEL_TESTING_PATCHVER:=6.18 +KERNEL_PATCHVER:=6.18 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso deleted file mode 100644 index 51d5dc661a..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - }; - - fragment@1 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <600>; - reset-post-delay-us = <20000>; - - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso deleted file mode 100644 index 4cc3cf1df6..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&sw_p5>; - __overlay__ { - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <600>; - reset-post-delay-us = <20000>; - - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso deleted file mode 100644 index 7e731cd433..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&chosen>; - rootdisk-spim-nand = <&ubi_rootdisk>; - }; - - fragment@1 { - target = <&spi0>; - __overlay__ { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - spi_nand: spi_nand@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - compatible = "linux,ubi"; - - volumes { - ubi_rootdisk: ubi-volume-fit { - volname = "fit"; - }; - }; - }; - }; - }; - }; - }; - - fragment@2 { - target = <&wifi>; - __overlay__ { - mediatek,mtd-eeprom = <&factory 0x0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts deleted file mode 100644 index 1551577624..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7981b.dtsi" - -/ { - model = "MediaTek MT7981 RFB"; - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - aliases { - serial0 = &uart0; - }; - - chosen: chosen { - stdout-path = "serial0:115200n8"; - bootargs-append = " root=/dev/fit0 rootwait"; - }; - - memory@40000000 { - reg = <0 0x40000000 0 0x20000000>; - device_type = "memory"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&int_gbe_phy>; - }; -}; - -&mdio_bus { - switch: switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&crypto { - status = "okay"; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = ; - bias-pull-up = ; - }; - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = ; - bias-pull-down = ; - }; - }; - -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - sw_p5: port@5 { - reg = <5>; - label = "lan5"; - status = "disabled"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&xhci { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts deleted file mode 100644 index 79a6df7d6b..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snand"; -}; - -&spi0 { - status = "okay"; - - spi_nand: spi_nand@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts deleted file mode 100644 index 009d2e1adf..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snor"; -}; - -&spi0 { - status = "okay"; - - spi_nor: spi_nor@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - factory: partition@50000 { - label = "Factory"; - reg = <0x50000 0x00B0000>; - }; - partition@100000 { - label = "FIP"; - reg = <0x100000 0x0080000>; - }; - partition@180000 { - label = "firmware"; - reg = <0x180000 0xE00000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi deleted file mode 100644 index 1dfb64d456..0000000000 --- a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ /dev/null @@ -1,391 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include -#include -#include "mt7986a.dtsi" - -/ { - model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - reg = <0 0x40000000 0 0x40000000>; - device_type = "memory"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -&mdio { - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - - reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; - reset-deassert-us = <20000>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - - switch: switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = ; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = ; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = ; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = ; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = ; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = ; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; - }; - - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = ; - bias-disable; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = ; - bias-disable; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = ; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = ; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&gmac1 { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy-handle = <&phy6>; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "lan6"; - - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c b/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c deleted file mode 100644 index eeaea348aa..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MFD driver for Airoha AN8855 Switch - */ - -#include -#include -#include -#include -#include -#include - -static const struct mfd_cell an8855_mfd_devs[] = { - { - .name = "an8855-efuse", - .of_compatible = "airoha,an8855-efuse", - }, { - .name = "an8855-switch", - .of_compatible = "airoha,an8855-switch", - }, { - .name = "an8855-mdio", - .of_compatible = "airoha,an8855-mdio", - } -}; - -int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, - u8 page) __must_hold(&priv->bus->mdio_lock) -{ - struct mii_bus *bus = priv->bus; - int ret; - - ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); - if (ret < 0) - dev_err_ratelimited(&bus->dev, - "failed to set an8855 mii page\n"); - - /* Cache current page if next mii read/write is for switch */ - priv->current_page = page; - return ret < 0 ? ret : 0; -} -EXPORT_SYMBOL_GPL(an8855_mii_set_page); - -static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, - u32 *val) __must_hold(&bus->mdio_lock) -{ - int lo, hi, ret; - - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, - AN8855_PBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto err; - - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, - upper_16_bits(reg)); - if (ret < 0) - goto err; - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, - lower_16_bits(reg)); - if (ret < 0) - goto err; - - hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); - if (hi < 0) { - ret = hi; - goto err; - } - lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); - if (lo < 0) { - ret = lo; - goto err; - } - - *val = ((u16)hi << 16) | ((u16)lo & 0xffff); - - return 0; -err: - dev_err_ratelimited(&bus->dev, - "failed to read an8855 register\n"); - return ret; -} - -static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) -{ - struct an8855_mfd_priv *priv = ctx; - struct mii_bus *bus = priv->bus; - u16 addr = priv->switch_addr; - int ret; - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); - if (ret < 0) - goto exit; - - ret = an8855_mii_read32(bus, addr, reg, val); - -exit: - mutex_unlock(&bus->mdio_lock); - - return ret < 0 ? ret : 0; -} - -static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, - u32 val) __must_hold(&bus->mdio_lock) -{ - int ret; - - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, - AN8855_PBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto err; - - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, - upper_16_bits(reg)); - if (ret < 0) - goto err; - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, - lower_16_bits(reg)); - if (ret < 0) - goto err; - - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, - upper_16_bits(val)); - if (ret < 0) - goto err; - ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, - lower_16_bits(val)); - if (ret < 0) - goto err; - - return 0; -err: - dev_err_ratelimited(&bus->dev, - "failed to write an8855 register\n"); - return ret; -} - -static int -an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) -{ - struct an8855_mfd_priv *priv = ctx; - struct mii_bus *bus = priv->bus; - u16 addr = priv->switch_addr; - int ret; - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); - if (ret < 0) - goto exit; - - ret = an8855_mii_write32(bus, addr, reg, val); - -exit: - mutex_unlock(&bus->mdio_lock); - - return ret < 0 ? ret : 0; -} - -static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, - uint32_t write_val) -{ - struct an8855_mfd_priv *priv = ctx; - struct mii_bus *bus = priv->bus; - u16 addr = priv->switch_addr; - u32 val; - int ret; - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); - if (ret < 0) - goto exit; - - ret = an8855_mii_read32(bus, addr, reg, &val); - if (ret < 0) - goto exit; - - val &= ~mask; - val |= write_val; - ret = an8855_mii_write32(bus, addr, reg, val); - -exit: - mutex_unlock(&bus->mdio_lock); - - return ret < 0 ? ret : 0; -} - -static const struct regmap_range an8855_readable_ranges[] = { - regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ - regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ - regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ - regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ - regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ - regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ - regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ - regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ - regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ - regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ - regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ - regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ - regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ - regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ - regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ - regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ - regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ - regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ - regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ - regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ - regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ - regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ - regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ - regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ - regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ - regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ - regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ -}; - -static const struct regmap_access_table an8855_readable_table = { - .yes_ranges = an8855_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges), -}; - -static const struct regmap_config an8855_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0xbfffffff, - .reg_read = an8855_regmap_read, - .reg_write = an8855_regmap_write, - .reg_update_bits = an8855_regmap_update_bits, - .disable_locking = true, - .rd_table = &an8855_readable_table, -}; - -static int an8855_mfd_probe(struct mdio_device *mdiodev) -{ - struct an8855_mfd_priv *priv; - struct regmap *regmap; - - priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->bus = mdiodev->bus; - priv->dev = &mdiodev->dev; - priv->switch_addr = mdiodev->addr; - /* no DMA for mdiobus, mute warning for DMA mask not set */ - priv->dev->dma_mask = &priv->dev->coherent_dma_mask; - - regmap = devm_regmap_init(priv->dev, NULL, priv, - &an8855_regmap_config); - if (IS_ERR(regmap)) - dev_err_probe(priv->dev, PTR_ERR(priv->dev), - "regmap initialization failed\n"); - - dev_set_drvdata(&mdiodev->dev, priv); - - return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs, - ARRAY_SIZE(an8855_mfd_devs), NULL, 0, - NULL); -} - -static const struct of_device_id an8855_mfd_of_match[] = { - { .compatible = "airoha,an8855-mfd" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, an8855_mfd_of_match); - -static struct mdio_driver an8855_mfd_driver = { - .probe = an8855_mfd_probe, - .mdiodrv.driver = { - .name = "an8855", - .of_match_table = an8855_mfd_of_match, - }, -}; -mdio_module_driver(an8855_mfd_driver); - -MODULE_AUTHOR("Christian Marangi "); -MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c deleted file mode 100644 index 47a7d9b625..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c +++ /dev/null @@ -1,2307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Airoha AN8855 DSA Switch driver - * Copyright (C) 2023 Min Yao - * Copyright (C) 2024 Christian Marangi - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "an8855.h" - -static const struct an8855_mib_desc an8855_mib[] = { - MIB_DESC(1, AN8855_PORT_MIB_TX_DROP, "TxDrop"), - MIB_DESC(1, AN8855_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), - MIB_DESC(1, AN8855_PORT_MIB_TX_COLLISION, "TxCollision"), - MIB_DESC(1, AN8855_PORT_MIB_TX_OVERSIZE_DROP, "TxOversizeDrop"), - MIB_DESC(2, AN8855_PORT_MIB_TX_BAD_PKT_BYTES, "TxBadPktBytes"), - MIB_DESC(1, AN8855_PORT_MIB_RX_DROP, "RxDrop"), - MIB_DESC(1, AN8855_PORT_MIB_RX_FILTERING, "RxFiltering"), - MIB_DESC(1, AN8855_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), - MIB_DESC(1, AN8855_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), - MIB_DESC(1, AN8855_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), - MIB_DESC(1, AN8855_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), - MIB_DESC(1, AN8855_PORT_MIB_FLOW_CONTROL_DROP, "FlowControlDrop"), - MIB_DESC(1, AN8855_PORT_MIB_WRED_DROP, "WredDrop"), - MIB_DESC(1, AN8855_PORT_MIB_MIRROR_DROP, "MirrorDrop"), - MIB_DESC(2, AN8855_PORT_MIB_RX_BAD_PKT_BYTES, "RxBadPktBytes"), - MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, "RxsFlowSamplingPktDrop"), - MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, "RxsFlowTotalPktDrop"), - MIB_DESC(1, AN8855_PORT_MIB_PORT_CONTROL_DROP, "PortControlDrop"), -}; - -static int -an8855_mib_init(struct an8855_priv *priv) -{ - int ret; - - ret = regmap_write(priv->regmap, AN8855_MIB_CCR, - AN8855_CCR_MIB_ENABLE); - if (ret) - return ret; - - return regmap_write(priv->regmap, AN8855_MIB_CCR, - AN8855_CCR_MIB_ACTIVATE); -} - -static void an8855_fdb_write(struct an8855_priv *priv, u16 vid, - u8 port_mask, const u8 *mac, - bool add) __must_hold(&priv->reg_mutex) -{ - u32 mac_reg[2] = { }; - u32 reg; - - mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC0, mac[0]); - mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC1, mac[1]); - mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC2, mac[2]); - mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC3, mac[3]); - mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC4, mac[4]); - mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC5, mac[5]); - - regmap_bulk_write(priv->regmap, AN8855_ATA1, mac_reg, - ARRAY_SIZE(mac_reg)); - - reg = AN8855_ATWD_IVL; - if (add) - reg |= AN8855_ATWD_VLD; - reg |= FIELD_PREP(AN8855_ATWD_VID, vid); - reg |= FIELD_PREP(AN8855_ATWD_FID, AN8855_FID_BRIDGED); - regmap_write(priv->regmap, AN8855_ATWD, reg); - regmap_write(priv->regmap, AN8855_ATWD2, - FIELD_PREP(AN8855_ATWD2_PORT, port_mask)); -} - -static void an8855_fdb_read(struct an8855_priv *priv, struct an8855_fdb *fdb) -{ - u32 reg[4]; - - regmap_bulk_read(priv->regmap, AN8855_ATRD0, reg, - ARRAY_SIZE(reg)); - - fdb->live = FIELD_GET(AN8855_ATRD0_LIVE, reg[0]); - fdb->type = FIELD_GET(AN8855_ATRD0_TYPE, reg[0]); - fdb->ivl = FIELD_GET(AN8855_ATRD0_IVL, reg[0]); - fdb->vid = FIELD_GET(AN8855_ATRD0_VID, reg[0]); - fdb->fid = FIELD_GET(AN8855_ATRD0_FID, reg[0]); - fdb->aging = FIELD_GET(AN8855_ATRD1_AGING, reg[1]); - fdb->port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, reg[3]); - fdb->mac[0] = FIELD_GET(AN8855_ATRD2_MAC0, reg[2]); - fdb->mac[1] = FIELD_GET(AN8855_ATRD2_MAC1, reg[2]); - fdb->mac[2] = FIELD_GET(AN8855_ATRD2_MAC2, reg[2]); - fdb->mac[3] = FIELD_GET(AN8855_ATRD2_MAC3, reg[2]); - fdb->mac[4] = FIELD_GET(AN8855_ATRD1_MAC4, reg[1]); - fdb->mac[5] = FIELD_GET(AN8855_ATRD1_MAC5, reg[1]); - fdb->noarp = !!FIELD_GET(AN8855_ATRD0_ARP, reg[0]); -} - -static int an8855_fdb_cmd(struct an8855_priv *priv, u32 cmd, - u32 *rsp) __must_hold(&priv->reg_mutex) -{ - u32 val; - int ret; - - /* Set the command operating upon the MAC address entries */ - val = AN8855_ATC_BUSY | cmd; - ret = regmap_write(priv->regmap, AN8855_ATC, val); - if (ret) - return ret; - - ret = regmap_read_poll_timeout(priv->regmap, AN8855_ATC, val, - !(val & AN8855_ATC_BUSY), 20, 200000); - if (ret) - return ret; - - if (rsp) - *rsp = val; - - return 0; -} - -static void -an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) -{ - struct dsa_port *dp = dsa_to_port(ds, port); - struct an8855_priv *priv = ds->priv; - bool learning = false; - u32 stp_state; - - switch (state) { - case BR_STATE_DISABLED: - stp_state = AN8855_STP_DISABLED; - break; - case BR_STATE_BLOCKING: - stp_state = AN8855_STP_BLOCKING; - break; - case BR_STATE_LISTENING: - stp_state = AN8855_STP_LISTENING; - break; - case BR_STATE_LEARNING: - stp_state = AN8855_STP_LEARNING; - learning = dp->learning; - break; - case BR_STATE_FORWARDING: - learning = dp->learning; - fallthrough; - default: - stp_state = AN8855_STP_FORWARDING; - break; - } - - regmap_update_bits(priv->regmap, AN8855_SSP_P(port), - AN8855_FID_PST_MASK(AN8855_FID_BRIDGED), - AN8855_FID_PST_VAL(AN8855_FID_BRIDGED, stp_state)); - - regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, - learning ? 0 : AN8855_SA_DIS); -} - -static void an8855_port_fast_age(struct dsa_switch *ds, int port) -{ - struct an8855_priv *priv = ds->priv; - int ret; - - /* Set to clean Dynamic entry */ - ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE); - if (ret) - return; - - /* Set Port */ - ret = regmap_write(priv->regmap, AN8855_ATWD2, - FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); - if (ret) - return; - - /* Flush Dynamic entry at port */ - an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_TYPE_PORT) | - AN8855_FDB_FLUSH, NULL); -} - -static int an8855_update_port_member(struct dsa_switch *ds, int port, - const struct net_device *bridge_dev, - bool join) -{ - struct an8855_priv *priv = ds->priv; - bool isolated, other_isolated; - struct dsa_port *dp; - u32 port_mask = 0; - int ret; - - isolated = !!(priv->port_isolated_map & BIT(port)); - - dsa_switch_for_each_user_port(dp, ds) { - if (dp->index == port) - continue; - - if (!dsa_port_offloads_bridge_dev(dp, bridge_dev)) - continue; - - other_isolated = !!(priv->port_isolated_map & BIT(dp->index)); - port_mask |= BIT(dp->index); - /* Add/remove this port to the portvlan mask of the other - * ports in the bridge - */ - if (join && !(isolated && other_isolated)) - ret = regmap_set_bits(priv->regmap, - AN8855_PORTMATRIX_P(dp->index), - FIELD_PREP(AN8855_USER_PORTMATRIX, - BIT(port))); - else - ret = regmap_clear_bits(priv->regmap, - AN8855_PORTMATRIX_P(dp->index), - FIELD_PREP(AN8855_USER_PORTMATRIX, - BIT(port))); - if (ret) - return ret; - } - - /* Add/remove all other ports to this port's portvlan mask */ - return regmap_update_bits(priv->regmap, AN8855_PORTMATRIX_P(port), - AN8855_USER_PORTMATRIX, - join ? port_mask : ~port_mask); -} - -static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port, - struct switchdev_brport_flags flags, - struct netlink_ext_ack *extack) -{ - if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | - BR_BCAST_FLOOD | BR_ISOLATED)) - return -EINVAL; - - return 0; -} - -static int an8855_port_bridge_flags(struct dsa_switch *ds, int port, - struct switchdev_brport_flags flags, - struct netlink_ext_ack *extack) -{ - struct an8855_priv *priv = ds->priv; - int ret; - - if (flags.mask & BR_LEARNING) { - ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, - flags.val & BR_LEARNING ? 0 : AN8855_SA_DIS); - if (ret) - return ret; - } - - if (flags.mask & BR_FLOOD) { - ret = regmap_update_bits(priv->regmap, AN8855_UNUF, BIT(port), - flags.val & BR_FLOOD ? BIT(port) : 0); - if (ret) - return ret; - } - - if (flags.mask & BR_MCAST_FLOOD) { - ret = regmap_update_bits(priv->regmap, AN8855_UNMF, BIT(port), - flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_UNIPMF, BIT(port), - flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); - if (ret) - return ret; - } - - if (flags.mask & BR_BCAST_FLOOD) { - ret = regmap_update_bits(priv->regmap, AN8855_BCF, BIT(port), - flags.val & BR_BCAST_FLOOD ? BIT(port) : 0); - if (ret) - return ret; - } - - if (flags.mask & BR_ISOLATED) { - struct dsa_port *dp = dsa_to_port(ds, port); - struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); - - if (flags.val & BR_ISOLATED) - priv->port_isolated_map |= BIT(port); - else - priv->port_isolated_map &= ~BIT(port); - - ret = an8855_update_port_member(ds, port, bridge_dev, true); - if (ret) - return ret; - } - - return 0; -} - -static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) -{ - struct an8855_priv *priv = ds->priv; - u32 age_count, age_unit, val; - - /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */ - val = msecs / AN8855_L2_AGING_MS_CONSTANT; - /* Derive the count unit */ - age_unit = val / FIELD_MAX(AN8855_AGE_UNIT); - /* Get the count in unit, age_unit is always incremented by 1 internally */ - age_count = val / (age_unit + 1); - - return regmap_update_bits(priv->regmap, AN8855_AAC, - AN8855_AGE_CNT | AN8855_AGE_UNIT, - FIELD_PREP(AN8855_AGE_CNT, age_count) | - FIELD_PREP(AN8855_AGE_UNIT, age_unit)); -} - -static int an8855_port_bridge_join(struct dsa_switch *ds, int port, - struct dsa_bridge bridge, - bool *tx_fwd_offload, - struct netlink_ext_ack *extack) -{ - struct an8855_priv *priv = ds->priv; - int ret; - - ret = an8855_update_port_member(ds, port, bridge.dev, true); - if (ret) - return ret; - - /* Set to fallback mode for independent VLAN learning if in a bridge */ - return regmap_update_bits(priv->regmap, AN8855_PCR_P(port), - AN8855_PORT_VLAN, - FIELD_PREP(AN8855_PORT_VLAN, - AN8855_PORT_FALLBACK_MODE)); -} - -static void an8855_port_bridge_leave(struct dsa_switch *ds, int port, - struct dsa_bridge bridge) -{ - struct an8855_priv *priv = ds->priv; - - an8855_update_port_member(ds, port, bridge.dev, false); - - /* When a port is removed from the bridge, the port would be set up - * back to the default as is at initial boot which is a VLAN-unaware - * port. - */ - regmap_update_bits(priv->regmap, AN8855_PCR_P(port), - AN8855_PORT_VLAN, - FIELD_PREP(AN8855_PORT_VLAN, - AN8855_PORT_MATRIX_MODE)); -} - -static int an8855_port_fdb_add(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid, - struct dsa_db db) -{ - struct an8855_priv *priv = ds->priv; - u8 port_mask = BIT(port); - int ret; - - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid = AN8855_PORT_VID_DEFAULT; - - mutex_lock(&priv->reg_mutex); - an8855_fdb_write(priv, vid, port_mask, addr, true); - ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int an8855_port_fdb_del(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid, - struct dsa_db db) -{ - struct an8855_priv *priv = ds->priv; - u8 port_mask = BIT(port); - int ret; - - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid = AN8855_PORT_VID_DEFAULT; - - mutex_lock(&priv->reg_mutex); - an8855_fdb_write(priv, vid, port_mask, addr, false); - ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int an8855_port_fdb_dump(struct dsa_switch *ds, int port, - dsa_fdb_dump_cb_t *cb, void *data) -{ - struct an8855_priv *priv = ds->priv; - int banks, count = 0; - u32 rsp; - int ret; - int i; - - mutex_lock(&priv->reg_mutex); - - /* Load search port */ - ret = regmap_write(priv->regmap, AN8855_ATWD2, - FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); - if (ret) - goto exit; - ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | - AN8855_FDB_START, &rsp); - if (ret < 0) - goto exit; - - do { - /* From response get the number of banks to read, exit if 0 */ - banks = FIELD_GET(AN8855_ATC_HIT, rsp); - if (!banks) - break; - - /* Each banks have 4 entry */ - for (i = 0; i < 4; i++) { - struct an8855_fdb _fdb = { }; - - count++; - - /* Check if bank is present */ - if (!(banks & BIT(i))) - continue; - - /* Select bank entry index */ - ret = regmap_write(priv->regmap, AN8855_ATRDS, - FIELD_PREP(AN8855_ATRD_SEL, i)); - if (ret) - break; - /* wait 1ms for the bank entry to be filled */ - usleep_range(1000, 1500); - an8855_fdb_read(priv, &_fdb); - - if (!_fdb.live) - continue; - ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data); - if (ret < 0) - break; - } - - /* Stop if reached max FDB number */ - if (count >= AN8855_NUM_FDB_RECORDS) - break; - - /* Read next bank */ - ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | - AN8855_FDB_NEXT, &rsp); - if (ret < 0) - break; - } while (true); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - -static int an8855_vlan_cmd(struct an8855_priv *priv, enum an8855_vlan_cmd cmd, - u16 vid) __must_hold(&priv->reg_mutex) -{ - u32 val; - int ret; - - val = AN8855_VTCR_BUSY | FIELD_PREP(AN8855_VTCR_FUNC, cmd) | - FIELD_PREP(AN8855_VTCR_VID, vid); - ret = regmap_write(priv->regmap, AN8855_VTCR, val); - if (ret) - return ret; - - return regmap_read_poll_timeout(priv->regmap, AN8855_VTCR, val, - !(val & AN8855_VTCR_BUSY), 20, 200000); -} - -static int an8855_vlan_add(struct an8855_priv *priv, u8 port, u16 vid, - bool untagged) __must_hold(&priv->reg_mutex) -{ - u32 port_mask; - u32 val; - int ret; - - /* Fetch entry */ - ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); - if (ret) - return ret; - - ret = regmap_read(priv->regmap, AN8855_VARD0, &val); - if (ret) - return ret; - port_mask = FIELD_GET(AN8855_VA0_PORT, val) | BIT(port); - - /* Validate the entry with independent learning, create egress tag per - * VLAN and joining the port as one of the port members. - */ - val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | - AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | - FIELD_PREP(AN8855_VA0_PORT, port_mask) | - FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED); - ret = regmap_write(priv->regmap, AN8855_VAWD0, val); - if (ret) - return ret; - ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); - if (ret) - return ret; - - /* CPU port is always taken as a tagged port for serving more than one - * VLANs across and also being applied with egress type stack mode for - * that VLAN tags would be appended after hardware special tag used as - * DSA tag. - */ - if (port == AN8855_CPU_PORT) - val = AN8855_VLAN_EGRESS_STACK; - /* Decide whether adding tag or not for those outgoing packets from the - * port inside the VLAN. - */ - else - val = untagged ? AN8855_VLAN_EGRESS_UNTAG : AN8855_VLAN_EGRESS_TAG; - ret = regmap_update_bits(priv->regmap, AN8855_VAWD0, - AN8855_VA0_ETAG_PORT_MASK(port), - AN8855_VA0_ETAG_PORT_VAL(port, val)); - if (ret) - return ret; - - /* Flush result to hardware */ - return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); -} - -static int an8855_vlan_del(struct an8855_priv *priv, u8 port, - u16 vid) __must_hold(&priv->reg_mutex) -{ - u32 port_mask; - u32 val; - int ret; - - /* Fetch entry */ - ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); - if (ret) - return ret; - - ret = regmap_read(priv->regmap, AN8855_VARD0, &val); - if (ret) - return ret; - port_mask = FIELD_GET(AN8855_VA0_PORT, val) & ~BIT(port); - - if (!(val & AN8855_VA0_VLAN_VALID)) { - dev_err(priv->dev, "Cannot be deleted due to invalid entry\n"); - return -EINVAL; - } - - if (port_mask) { - val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | - AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | - FIELD_PREP(AN8855_VA0_PORT, port_mask); - ret = regmap_write(priv->regmap, AN8855_VAWD0, val); - if (ret) - return ret; - } else { - ret = regmap_write(priv->regmap, AN8855_VAWD0, 0); - if (ret) - return ret; - } - ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); - if (ret) - return ret; - - /* Flush result to hardware */ - return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); -} - -static int an8855_port_set_vlan_mode(struct an8855_priv *priv, int port, - enum an8855_port_mode port_mode, - enum an8855_vlan_port_eg_tag eg_tag, - enum an8855_vlan_port_attr vlan_attr, - enum an8855_vlan_port_acc_frm acc_frm) -{ - int ret; - - ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(port), - AN8855_PORT_VLAN, - FIELD_PREP(AN8855_PORT_VLAN, port_mode)); - if (ret) - return ret; - - return regmap_update_bits(priv->regmap, AN8855_PVC_P(port), - AN8855_PVC_EG_TAG | AN8855_VLAN_ATTR | AN8855_ACC_FRM, - FIELD_PREP(AN8855_PVC_EG_TAG, eg_tag) | - FIELD_PREP(AN8855_VLAN_ATTR, vlan_attr) | - FIELD_PREP(AN8855_ACC_FRM, acc_frm)); -} - -static int an8855_port_set_pid(struct an8855_priv *priv, int port, - u16 pid) -{ - int ret; - - ret = regmap_update_bits(priv->regmap, AN8855_PPBV1_P(port), - AN8855_PPBV_G0_PORT_VID, - FIELD_PREP(AN8855_PPBV_G0_PORT_VID, pid)); - if (ret) - return ret; - - return regmap_update_bits(priv->regmap, AN8855_PVID_P(port), - AN8855_G0_PORT_VID, - FIELD_PREP(AN8855_G0_PORT_VID, pid)); -} - -static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port, - bool vlan_filtering, - struct netlink_ext_ack *extack) -{ - struct an8855_priv *priv = ds->priv; - u32 val; - int ret; - - /* The port is being kept as VLAN-unaware port when bridge is - * set up with vlan_filtering not being set, Otherwise, the - * port and the corresponding CPU port is required the setup - * for becoming a VLAN-aware port. - */ - if (vlan_filtering) { - u32 acc_frm; - /* CPU port is set to fallback mode to let untagged - * frames pass through. - */ - ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, - AN8855_PORT_FALLBACK_MODE, - AN8855_VLAN_EG_CONSISTENT, - AN8855_VLAN_USER, - AN8855_VLAN_ACC_ALL); - if (ret) - return ret; - - ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); - if (ret) - return ret; - - /* Only accept tagged frames if PVID is not set */ - if (FIELD_GET(AN8855_G0_PORT_VID, val) != AN8855_PORT_VID_DEFAULT) - acc_frm = AN8855_VLAN_ACC_TAGGED; - else - acc_frm = AN8855_VLAN_ACC_ALL; - - /* Trapped into security mode allows packet forwarding through VLAN - * table lookup. - * Set the port as a user port which is to be able to recognize VID - * from incoming packets before fetching entry within the VLAN table. - */ - ret = an8855_port_set_vlan_mode(priv, port, - AN8855_PORT_SECURITY_MODE, - AN8855_VLAN_EG_DISABLED, - AN8855_VLAN_USER, - acc_frm); - if (ret) - return ret; - } else { - bool disable_cpu_vlan = true; - struct dsa_port *dp; - u32 port_mode; - - /* This is called after .port_bridge_leave when leaving a VLAN-aware - * bridge. Don't set standalone ports to fallback mode. - */ - if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) - port_mode = AN8855_PORT_FALLBACK_MODE; - else - port_mode = AN8855_PORT_MATRIX_MODE; - - /* When a port is removed from the bridge, the port would be set up - * back to the default as is at initial boot which is a VLAN-unaware - * port. - */ - ret = an8855_port_set_vlan_mode(priv, port, port_mode, - AN8855_VLAN_EG_CONSISTENT, - AN8855_VLAN_TRANSPARENT, - AN8855_VLAN_ACC_ALL); - if (ret) - return ret; - - /* Restore default PVID */ - ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); - if (ret) - return ret; - - dsa_switch_for_each_user_port(dp, ds) { - if (dsa_port_is_vlan_filtering(dp)) { - disable_cpu_vlan = false; - break; - } - } - - if (disable_cpu_vlan) { - ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, - AN8855_PORT_MATRIX_MODE, - AN8855_VLAN_EG_CONSISTENT, - AN8855_VLAN_USER, - AN8855_VLAN_ACC_ALL); - if (ret) - return ret; - } - } - - return 0; -} - -static int an8855_port_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan, - struct netlink_ext_ack *extack) -{ - bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; - struct an8855_priv *priv = ds->priv; - u32 val; - int ret; - - mutex_lock(&priv->reg_mutex); - ret = an8855_vlan_add(priv, port, vlan->vid, untagged); - mutex_unlock(&priv->reg_mutex); - if (ret) - return ret; - - if (pvid) { - /* Accept all frames if PVID is set */ - regmap_update_bits(priv->regmap, AN8855_PVC_P(port), AN8855_ACC_FRM, - FIELD_PREP(AN8855_ACC_FRM, AN8855_VLAN_ACC_ALL)); - - /* Only configure PVID if VLAN filtering is enabled */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { - ret = an8855_port_set_pid(priv, port, vlan->vid); - if (ret) - return ret; - } - } else if (vlan->vid) { - ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); - if (ret) - return ret; - - if (FIELD_GET(AN8855_G0_PORT_VID, val) != vlan->vid) - return 0; - - /* This VLAN is overwritten without PVID, so unset it */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { - ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), - AN8855_ACC_FRM, - FIELD_PREP(AN8855_ACC_FRM, - AN8855_VLAN_ACC_TAGGED)); - if (ret) - return ret; - } - - ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); - if (ret) - return ret; - } - - return 0; -} - -static int an8855_port_vlan_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct an8855_priv *priv = ds->priv; - u32 val; - int ret; - - mutex_lock(&priv->reg_mutex); - ret = an8855_vlan_del(priv, port, vlan->vid); - mutex_unlock(&priv->reg_mutex); - if (ret) - return ret; - - ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); - if (ret) - return ret; - - /* PVID is being restored to the default whenever the PVID port - * is being removed from the VLAN. - */ - if (FIELD_GET(AN8855_G0_PORT_VID, val) == vlan->vid) { - /* Only accept tagged frames if the port is VLAN-aware */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { - ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), - AN8855_ACC_FRM, - FIELD_PREP(AN8855_ACC_FRM, - AN8855_VLAN_ACC_TAGGED)); - if (ret) - return ret; - } - - ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); - if (ret) - return ret; - } - - return 0; -} - -static int -an8855_port_mdb_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb, - struct dsa_db db) -{ - struct an8855_priv *priv = ds->priv; - const u8 *addr = mdb->addr; - u16 vid = mdb->vid; - u8 port_mask = 0; - u32 val; - int ret; - - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid = AN8855_PORT_VID_DEFAULT; - - mutex_lock(&priv->reg_mutex); - - an8855_fdb_write(priv, vid, 0, addr, false); - if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { - ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); - if (ret) - goto exit; - - port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); - } - - port_mask |= BIT(port); - an8855_fdb_write(priv, vid, port_mask, addr, true); - ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); - -exit: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -an8855_port_mdb_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb, - struct dsa_db db) -{ - struct an8855_priv *priv = ds->priv; - const u8 *addr = mdb->addr; - u16 vid = mdb->vid; - u8 port_mask = 0; - u32 val; - int ret; - - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid = AN8855_PORT_VID_DEFAULT; - - mutex_lock(&priv->reg_mutex); - - an8855_fdb_write(priv, vid, 0, addr, 0); - if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { - ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); - if (ret) - goto exit; - - port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); - } - - port_mask &= ~BIT(port); - an8855_fdb_write(priv, vid, port_mask, addr, port_mask ? true : false); - ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); - -exit: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -an8855_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) -{ - struct an8855_priv *priv = ds->priv; - int length; - u32 val; - - /* When a new MTU is set, DSA always set the CPU port's MTU to the - * largest MTU of the slave ports. Because the switch only has a global - * RX length register, only allowing CPU port here is enough. - */ - if (!dsa_is_cpu_port(ds, port)) - return 0; - - /* RX length also includes Ethernet header, MTK tag, and FCS length */ - length = new_mtu + ETH_HLEN + MTK_TAG_LEN + ETH_FCS_LEN; - if (length <= 1522) - val = AN8855_MAX_RX_PKT_1518_1522; - else if (length <= 1536) - val = AN8855_MAX_RX_PKT_1536; - else if (length <= 1552) - val = AN8855_MAX_RX_PKT_1552; - else if (length <= 3072) - val = AN8855_MAX_RX_JUMBO_3K; - else if (length <= 4096) - val = AN8855_MAX_RX_JUMBO_4K; - else if (length <= 5120) - val = AN8855_MAX_RX_JUMBO_5K; - else if (length <= 6144) - val = AN8855_MAX_RX_JUMBO_6K; - else if (length <= 7168) - val = AN8855_MAX_RX_JUMBO_7K; - else if (length <= 8192) - val = AN8855_MAX_RX_JUMBO_8K; - else if (length <= 9216) - val = AN8855_MAX_RX_JUMBO_9K; - else if (length <= 12288) - val = AN8855_MAX_RX_JUMBO_12K; - else if (length <= 15360) - val = AN8855_MAX_RX_JUMBO_15K; - else - val = AN8855_MAX_RX_JUMBO_16K; - - /* Enable JUMBO packet */ - if (length > 1552) - val |= AN8855_MAX_RX_PKT_JUMBO; - - return regmap_update_bits(priv->regmap, AN8855_GMACCR, - AN8855_MAX_RX_JUMBO | AN8855_MAX_RX_PKT_LEN, - val); -} - -static int -an8855_port_max_mtu(struct dsa_switch *ds, int port) -{ - return AN8855_MAX_MTU; -} - -static void -an8855_get_strings(struct dsa_switch *ds, int port, u32 stringset, - uint8_t *data) -{ - int i; - - if (stringset != ETH_SS_STATS) - return; - - for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) - ethtool_puts(&data, an8855_mib[i].name); -} - -static void -an8855_read_port_stats(struct an8855_priv *priv, int port, u32 offset, u8 size, - uint64_t *data) -{ - u32 val, reg = AN8855_PORT_MIB_COUNTER(port) + offset; - - regmap_read(priv->regmap, reg, &val); - *data = val; - - if (size == 2) { - regmap_read(priv->regmap, reg + 4, &val); - *data |= (u64)val << 32; - } -} - -static void -an8855_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) -{ - struct an8855_priv *priv = ds->priv; - const struct an8855_mib_desc *mib; - int i; - - for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) { - mib = &an8855_mib[i]; - - an8855_read_port_stats(priv, port, mib->offset, mib->size, - data + i); - } -} - -static int -an8855_get_sset_count(struct dsa_switch *ds, int port, int sset) -{ - if (sset != ETH_SS_STATS) - return 0; - - return ARRAY_SIZE(an8855_mib); -} - -static void -an8855_get_eth_mac_stats(struct dsa_switch *ds, int port, - struct ethtool_eth_mac_stats *mac_stats) -{ - struct an8855_priv *priv = ds->priv; - - /* MIB counter doesn't provide a FramesTransmittedOK but instead - * provide stats for Unicast, Broadcast and Multicast frames separately. - * To simulate a global frame counter, read Unicast and addition Multicast - * and Broadcast later - */ - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_UNICAST, 1, - &mac_stats->FramesTransmittedOK); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_SINGLE_COLLISION, 1, - &mac_stats->SingleCollisionFrames); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 1, - &mac_stats->MultipleCollisionFrames); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNICAST, 1, - &mac_stats->FramesReceivedOK); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BYTES, 2, - &mac_stats->OctetsTransmittedOK); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_ALIGN_ERR, 1, - &mac_stats->AlignmentErrors); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_DEFERRED, 1, - &mac_stats->FramesWithDeferredXmissions); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_LATE_COLLISION, 1, - &mac_stats->LateCollisions); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, - &mac_stats->FramesAbortedDueToXSColls); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BYTES, 2, - &mac_stats->OctetsReceivedOK); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTICAST, 1, - &mac_stats->MulticastFramesXmittedOK); - mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BROADCAST, 1, - &mac_stats->BroadcastFramesXmittedOK); - mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_MULTICAST, 1, - &mac_stats->MulticastFramesReceivedOK); - mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BROADCAST, 1, - &mac_stats->BroadcastFramesReceivedOK); - mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; -} - -static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = { - { 0, 64 }, - { 65, 127 }, - { 128, 255 }, - { 256, 511 }, - { 512, 1023 }, - { 1024, 1518 }, - { 1519, AN8855_MAX_MTU }, - {} -}; - -static void an8855_get_rmon_stats(struct dsa_switch *ds, int port, - struct ethtool_rmon_stats *rmon_stats, - const struct ethtool_rmon_hist_range **ranges) -{ - struct an8855_priv *priv = ds->priv; - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 1, - &rmon_stats->undersize_pkts); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_OVER_SZ_ERR, 1, - &rmon_stats->oversize_pkts); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_FRAG_ERR, 1, - &rmon_stats->fragments); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_JABBER_ERR, 1, - &rmon_stats->jabbers); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_64, 1, - &rmon_stats->hist[0]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, - &rmon_stats->hist[1]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, - &rmon_stats->hist[2]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, - &rmon_stats->hist[3]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, - &rmon_stats->hist[4]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 1, - &rmon_stats->hist[5]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 1, - &rmon_stats->hist[6]); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_64, 1, - &rmon_stats->hist_tx[0]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, - &rmon_stats->hist_tx[1]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, - &rmon_stats->hist_tx[2]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, - &rmon_stats->hist_tx[3]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, - &rmon_stats->hist_tx[4]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 1, - &rmon_stats->hist_tx[5]); - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 1, - &rmon_stats->hist_tx[6]); - - *ranges = an8855_rmon_ranges; -} - -static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port, - struct ethtool_eth_ctrl_stats *ctrl_stats) -{ - struct an8855_priv *priv = ds->priv; - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PAUSE, 1, - &ctrl_stats->MACControlFramesTransmitted); - - an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PAUSE, 1, - &ctrl_stats->MACControlFramesReceived); -} - -static int an8855_port_mirror_add(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror, - bool ingress, - struct netlink_ext_ack *extack) -{ - struct an8855_priv *priv = ds->priv; - int monitor_port; - u32 val; - int ret; - - /* Check for existent entry */ - if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) - return -EEXIST; - - ret = regmap_read(priv->regmap, AN8855_MIR, &val); - if (ret) - return ret; - - /* AN8855 supports 4 monitor port, but only use first group */ - monitor_port = FIELD_GET(AN8855_MIRROR_PORT, val); - if (val & AN8855_MIRROR_EN && monitor_port != mirror->to_local_port) - return -EEXIST; - - val = AN8855_MIRROR_EN; - val |= FIELD_PREP(AN8855_MIRROR_PORT, mirror->to_local_port); - ret = regmap_update_bits(priv->regmap, AN8855_MIR, - AN8855_MIRROR_EN | AN8855_MIRROR_PORT, - val); - if (ret) - return ret; - - ret = regmap_set_bits(priv->regmap, AN8855_PCR_P(port), - ingress ? AN8855_PORT_RX_MIR : AN8855_PORT_TX_MIR); - if (ret) - return ret; - - if (ingress) - priv->mirror_rx |= BIT(port); - else - priv->mirror_tx |= BIT(port); - - return 0; -} - -static void an8855_port_mirror_del(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror) -{ - struct an8855_priv *priv = ds->priv; - - if (mirror->ingress) - priv->mirror_rx &= ~BIT(port); - else - priv->mirror_tx &= ~BIT(port); - - regmap_clear_bits(priv->regmap, AN8855_PCR_P(port), - mirror->ingress ? AN8855_PORT_RX_MIR : - AN8855_PORT_TX_MIR); - - if (!priv->mirror_rx && !priv->mirror_tx) - regmap_clear_bits(priv->regmap, AN8855_MIR, AN8855_MIRROR_EN); -} - -static int an8855_port_set_status(struct an8855_priv *priv, int port, - bool enable) -{ - if (enable) - return regmap_set_bits(priv->regmap, AN8855_PMCR_P(port), - AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); - else - return regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), - AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); -} - -static int an8855_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) -{ - return an8855_port_set_status(ds->priv, port, true); -} - -static void an8855_port_disable(struct dsa_switch *ds, int port) -{ - an8855_port_set_status(ds->priv, port, false); -} - -static u32 en8855_get_phy_flags(struct dsa_switch *ds, int port) -{ - struct an8855_priv *priv = ds->priv; - - /* PHY doesn't need calibration */ - if (!priv->phy_require_calib) - return 0; - - /* Use AN8855_PHY_FLAGS_EN_CALIBRATION to signal - * calibration needed. - */ - return AN8855_PHY_FLAGS_EN_CALIBRATION; -} - -static enum dsa_tag_protocol -an8855_get_tag_protocol(struct dsa_switch *ds, int port, - enum dsa_tag_protocol mp) -{ - return DSA_TAG_PROTO_MTK; -} - -/* Similar to MT7530 also trap link local frame and special frame to CPU */ -static int an8855_trap_special_frames(struct an8855_priv *priv) -{ - int ret; - - /* Trap BPDUs to the CPU port(s) and egress them - * VLAN-untagged. - */ - ret = regmap_update_bits(priv->regmap, AN8855_BPC, - AN8855_BPDU_BPDU_FR | AN8855_BPDU_EG_TAG | - AN8855_BPDU_PORT_FW, - AN8855_BPDU_BPDU_FR | - FIELD_PREP(AN8855_BPDU_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_BPDU_PORT_FW, AN8855_BPDU_CPU_ONLY)); - if (ret) - return ret; - - /* Trap 802.1X PAE frames to the CPU port(s) and egress them - * VLAN-untagged. - */ - ret = regmap_update_bits(priv->regmap, AN8855_PAC, - AN8855_PAE_BPDU_FR | AN8855_PAE_EG_TAG | - AN8855_PAE_PORT_FW, - AN8855_PAE_BPDU_FR | - FIELD_PREP(AN8855_PAE_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_PAE_PORT_FW, AN8855_BPDU_CPU_ONLY)); - if (ret) - return ret; - - /* Trap frames with :01 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, - AN8855_R01_BPDU_FR | AN8855_R01_EG_TAG | - AN8855_R01_PORT_FW, - AN8855_R01_BPDU_FR | - FIELD_PREP(AN8855_R01_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_R01_PORT_FW, AN8855_BPDU_CPU_ONLY)); - if (ret) - return ret; - - /* Trap frames with :02 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, - AN8855_R02_BPDU_FR | AN8855_R02_EG_TAG | - AN8855_R02_PORT_FW, - AN8855_R02_BPDU_FR | - FIELD_PREP(AN8855_R02_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_R02_PORT_FW, AN8855_BPDU_CPU_ONLY)); - if (ret) - return ret; - - /* Trap frames with :03 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, - AN8855_R03_BPDU_FR | AN8855_R03_EG_TAG | - AN8855_R03_PORT_FW, - AN8855_R03_BPDU_FR | - FIELD_PREP(AN8855_R03_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_R03_PORT_FW, AN8855_BPDU_CPU_ONLY)); - if (ret) - return ret; - - /* Trap frames with :0E MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ - return regmap_update_bits(priv->regmap, AN8855_RGAC1, - AN8855_R0E_BPDU_FR | AN8855_R0E_EG_TAG | - AN8855_R0E_PORT_FW, - AN8855_R0E_BPDU_FR | - FIELD_PREP(AN8855_R0E_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | - FIELD_PREP(AN8855_R0E_PORT_FW, AN8855_BPDU_CPU_ONLY)); -} - -static int -an8855_setup_pvid_vlan(struct an8855_priv *priv) -{ - u32 val; - int ret; - - /* Validate the entry with independent learning, keep the original - * ingress tag attribute. - */ - val = AN8855_VA0_IVL_MAC | AN8855_VA0_EG_CON | - FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED) | - AN8855_VA0_PORT | AN8855_VA0_VLAN_VALID; - ret = regmap_write(priv->regmap, AN8855_VAWD0, val); - if (ret) - return ret; - - return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, - AN8855_PORT_VID_DEFAULT); -} - -static int an8855_setup(struct dsa_switch *ds) -{ - struct an8855_priv *priv = ds->priv; - struct dsa_port *dp; - int ret; - - /* Enable and reset MIB counters */ - ret = an8855_mib_init(priv); - if (ret) - return ret; - - dsa_switch_for_each_user_port(dp, ds) { - /* Disable MAC by default on all user ports */ - ret = an8855_port_set_status(priv, dp->index, false); - if (ret) - return ret; - - /* Individual user ports get connected to CPU port only */ - ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index), - FIELD_PREP(AN8855_PORTMATRIX, BIT(AN8855_CPU_PORT))); - if (ret) - return ret; - - /* Disable Broadcast Forward on user ports */ - ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index)); - if (ret) - return ret; - - /* Disable Unknown Unicast Forward on user ports */ - ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index)); - if (ret) - return ret; - - /* Disable Unknown Multicast Forward on user ports */ - ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index)); - if (ret) - return ret; - - ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index)); - if (ret) - return ret; - - /* Set default PVID to on all user ports */ - ret = an8855_port_set_pid(priv, dp->index, AN8855_PORT_VID_DEFAULT); - if (ret) - return ret; - } - - /* Enable Airoha header mode on the cpu port */ - ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT), - AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG); - if (ret) - return ret; - - /* Unknown multicast frame forwarding to the cpu port */ - ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); - if (ret) - return ret; - - /* Set CPU port number */ - ret = regmap_update_bits(priv->regmap, AN8855_MFC, - AN8855_CPU_EN | AN8855_CPU_PORT_IDX, - AN8855_CPU_EN | - FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT)); - if (ret) - return ret; - - /* CPU port gets connected to all user ports of - * the switch. - */ - ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT), - FIELD_PREP(AN8855_PORTMATRIX, dsa_user_ports(ds))); - if (ret) - return ret; - - /* CPU port is set to fallback mode to let untagged - * frames pass through. - */ - ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT), - AN8855_PORT_VLAN, - FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE)); - if (ret) - return ret; - - /* Enable Broadcast Forward on CPU port */ - ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT)); - if (ret) - return ret; - - /* Enable Unknown Unicast Forward on CPU port */ - ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT)); - if (ret) - return ret; - - /* Enable Unknown Multicast Forward on CPU port */ - ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); - if (ret) - return ret; - - ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT)); - if (ret) - return ret; - - /* Setup Trap special frame to CPU rules */ - ret = an8855_trap_special_frames(priv); - if (ret) - return ret; - - dsa_switch_for_each_port(dp, ds) { - /* Disable Learning on all ports. - * Learning on CPU is disabled for fdb isolation and handled by - * assisted_learning_on_cpu_port. - */ - ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index), - AN8855_SA_DIS); - if (ret) - return ret; - - /* Enable consistent egress tag (for VLAN unware VLAN-passtrough) */ - ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index), - AN8855_PVC_EG_TAG, - FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT)); - if (ret) - return ret; - } - - /* Setup VLAN for Default PVID */ - ret = an8855_setup_pvid_vlan(priv); - if (ret) - return ret; - - ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR, - AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP); - if (ret) - return ret; - - /* Release global PHY power down */ - ret = regmap_write(priv->regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); - if (ret) - return ret; - - ds->configure_vlan_while_not_filtering = true; - - /* Flush the FDB table */ - ret = an8855_fdb_cmd(priv, AN8855_FDB_FLUSH, NULL); - if (ret < 0) - return ret; - - /* Set min a max ageing value supported */ - ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT; - ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) * - FIELD_MAX(AN8855_AGE_UNIT) * - AN8855_L2_AGING_MS_CONSTANT; - - /* Enable assisted learning for fdb isolation */ - ds->assisted_learning_on_cpu_port = true; - - return 0; -} - -static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config, - phy_interface_t interface) -{ - struct dsa_port *dp = dsa_phylink_to_port(config); - struct an8855_priv *priv = dp->ds->priv; - - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - return &priv->pcs; - default: - return NULL; - } -} - -static void an8855_phylink_mac_config(struct phylink_config *config, - unsigned int mode, - const struct phylink_link_state *state) -{ - struct dsa_port *dp = dsa_phylink_to_port(config); - struct dsa_switch *ds = dp->ds; - struct an8855_priv *priv; - int port = dp->index; - - priv = ds->priv; - - /* Nothing to configure for internal ports */ - if (port != 5) - return; - - regmap_update_bits(priv->regmap, AN8855_PMCR_P(port), - AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE | - AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN, - FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) | - AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN | - AN8855_PMCR_BACKPR_EN); -} - -static void an8855_phylink_get_caps(struct dsa_switch *ds, int port, - struct phylink_config *config) -{ - switch (port) { - case 0: - case 1: - case 2: - case 3: - case 4: - __set_bit(PHY_INTERFACE_MODE_GMII, - config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); - break; - case 5: - phy_interface_set_rgmii(config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_SGMII, - config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_2500BASEX, - config->supported_interfaces); - break; - } - - config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | - MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD; -} - -static void an8855_phylink_mac_link_down(struct phylink_config *config, - unsigned int mode, - phy_interface_t interface) -{ - struct dsa_port *dp = dsa_phylink_to_port(config); - struct an8855_priv *priv = dp->ds->priv; - - /* With autoneg just disable TX/RX else also force link down */ - if (phylink_autoneg_inband(mode)) { - regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index), - AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); - } else { - regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index), - AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN | - AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK, - AN8855_PMCR_FORCE_MODE); - } -} - -static void an8855_phylink_mac_link_up(struct phylink_config *config, - struct phy_device *phydev, unsigned int mode, - phy_interface_t interface, int speed, - int duplex, bool tx_pause, bool rx_pause) -{ - struct dsa_port *dp = dsa_phylink_to_port(config); - struct an8855_priv *priv = dp->ds->priv; - int port = dp->index; - u32 reg; - - reg = regmap_read(priv->regmap, AN8855_PMCR_P(port), ®); - if (phylink_autoneg_inband(mode)) { - reg &= ~AN8855_PMCR_FORCE_MODE; - } else { - reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK; - - reg &= ~AN8855_PMCR_FORCE_SPEED; - switch (speed) { - case SPEED_10: - reg |= AN8855_PMCR_FORCE_SPEED_10; - break; - case SPEED_100: - reg |= AN8855_PMCR_FORCE_SPEED_100; - break; - case SPEED_1000: - reg |= AN8855_PMCR_FORCE_SPEED_1000; - break; - case SPEED_2500: - reg |= AN8855_PMCR_FORCE_SPEED_2500; - break; - case SPEED_5000: - dev_err(priv->dev, "Missing support for 5G speed. Aborting...\n"); - return; - } - - reg &= ~AN8855_PMCR_FORCE_FDX; - if (duplex == DUPLEX_FULL) - reg |= AN8855_PMCR_FORCE_FDX; - - reg &= ~AN8855_PMCR_RX_FC_EN; - if (rx_pause || dsa_port_is_cpu(dp)) - reg |= AN8855_PMCR_RX_FC_EN; - - reg &= ~AN8855_PMCR_TX_FC_EN; - if (rx_pause || dsa_port_is_cpu(dp)) - reg |= AN8855_PMCR_TX_FC_EN; - - /* Disable any EEE options */ - reg &= ~(AN8855_PMCR_FORCE_EEE5G | AN8855_PMCR_FORCE_EEE2P5G | - AN8855_PMCR_FORCE_EEE1G | AN8855_PMCR_FORCE_EEE100); - } - - reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN; - - regmap_write(priv->regmap, AN8855_PMCR_P(port), reg); -} - -static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs, - phy_interface_t interface) -{ - /* SGMII can be configured to use inband with AN result */ - if (interface == PHY_INTERFACE_MODE_SGMII) - return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; - - /* inband is not supported in 2500-baseX and must be disabled */ - return LINK_INBAND_DISABLE; -} - -static void an8855_pcs_get_state(struct phylink_pcs *pcs, - struct phylink_link_state *state) -{ - struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); - u32 val; - int ret; - - ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val); - if (ret < 0) { - state->link = false; - return; - } - - state->link = !!(val & AN8855_PMSR_LNK); - state->an_complete = state->link; - state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL : - DUPLEX_HALF; - - switch (val & AN8855_PMSR_SPEED) { - case AN8855_PMSR_SPEED_10: - state->speed = SPEED_10; - break; - case AN8855_PMSR_SPEED_100: - state->speed = SPEED_100; - break; - case AN8855_PMSR_SPEED_1000: - state->speed = SPEED_1000; - break; - case AN8855_PMSR_SPEED_2500: - state->speed = SPEED_2500; - break; - case AN8855_PMSR_SPEED_5000: - dev_err(priv->dev, "Missing support for 5G speed. Setting Unknown.\n"); - fallthrough; - default: - state->speed = SPEED_UNKNOWN; - break; - } - - if (val & AN8855_PMSR_RX_FC) - state->pause |= MLO_PAUSE_RX; - if (val & AN8855_PMSR_TX_FC) - state->pause |= MLO_PAUSE_TX; -} - -static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, - phy_interface_t interface, - const unsigned long *advertising, - bool permit_pause_to_mac) -{ - struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); - u32 val; - int ret; - - /* !!! WELCOME TO HELL !!! */ - - /* TX FIR - improve TX EYE */ - ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10, - AN8855_RG_DA_QP_TX_FIR_C2_SEL | - AN8855_RG_DA_QP_TX_FIR_C2_FORCE | - AN8855_RG_DA_QP_TX_FIR_C1_SEL | - AN8855_RG_DA_QP_TX_FIR_C1_FORCE, - AN8855_RG_DA_QP_TX_FIR_C2_SEL | - FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) | - AN8855_RG_DA_QP_TX_FIR_C1_SEL | - FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0)); - if (ret) - return ret; - - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x0; - else - val = 0xd; - ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11, - AN8855_RG_DA_QP_TX_FIR_C0B_SEL | - AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, - AN8855_RG_DA_QP_TX_FIR_C0B_SEL | - FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val)); - if (ret) - return ret; - - /* RX CDR - improve RX Jitter Tolerance */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x5; - else - val = 0x6; - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM, - AN8855_RG_QP_CDR_LPF_KP_GAIN | - AN8855_RG_QP_CDR_LPF_KI_GAIN, - FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) | - FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val)); - if (ret) - return ret; - - /* PLL */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x1; - else - val = 0x0; - ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1, - AN8855_RG_TPHY_SPEED, - FIELD_PREP(AN8855_RG_TPHY_SPEED, val)); - if (ret) - return ret; - - /* PLL - LPF */ - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | - AN8855_RG_DA_QP_PLL_FBKSEL_INTF | - AN8855_RG_DA_QP_PLL_BR_INTF | - AN8855_RG_DA_QP_PLL_BPD_INTF | - AN8855_RG_DA_QP_PLL_BPA_INTF | - AN8855_RG_DA_QP_PLL_BC_INTF, - AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | - FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) | - FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) | - FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) | - FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) | - FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1)); - if (ret) - return ret; - - /* PLL - ICO */ - ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4, - AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF); - if (ret) - return ret; - ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF); - if (ret) - return ret; - - /* PLL - CHP */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x6; - else - val = 0x4; - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_IR_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val)); - if (ret) - return ret; - - /* PLL - PFD */ - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF | - AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF | - AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) | - FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1)); - if (ret) - return ret; - - /* PLL - POSTDIV */ - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF | - AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF | - AN8855_RG_DA_QP_PLL_PCK_SEL_INTF, - AN8855_RG_DA_QP_PLL_PCK_SEL_INTF); - if (ret) - return ret; - - /* PLL - SDM */ - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0)); - if (ret) - return ret; - ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, - AN8855_RG_DA_QP_PLL_SDM_IFM_INTF); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2, - AN8855_RG_NCPO_ANA_MSB, - FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1)); - if (ret) - return ret; - - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x7a000000; - else - val = 0x48000000; - ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2, - FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val)); - if (ret) - return ret; - ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1, - FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val)); - if (ret) - return ret; - - ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5, - AN8855_RG_LCPLL_NCPO_CHG); - if (ret) - return ret; - ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, - AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF); - if (ret) - return ret; - - /* PLL - SS */ - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, - AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0)); - if (ret) - return ret; - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4, - AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0)); - if (ret) - return ret; - ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, - AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, - FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0)); - if (ret) - return ret; - - /* PLL - TDC */ - ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, - AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF); - if (ret) - return ret; - - ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, - AN8855_RG_QP_PLL_SSC_TRI_EN); - if (ret) - return ret; - ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, - AN8855_RG_QP_PLL_SSC_PHASE_INI); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN, - AN8855_RG_QP_SIGDET_HF, - FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2)); - if (ret) - return ret; - - /* TCL Disable (only for Co-SIM) */ - ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0, - AN8855_RG_QP_EQ_RX500M_CK_SEL); - if (ret) - return ret; - - /* TX Init */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x4; - else - val = 0x0; - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE, - AN8855_RG_QP_TX_RESERVE | - AN8855_RG_QP_TX_MODE_16B_EN, - FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val)); - if (ret) - return ret; - - /* RX Control/Init */ - ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE, - AN8855_RG_QP_CDR_PD_10B_EN); - if (ret) - return ret; - - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x1; - else - val = 0x2; - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM, - AN8855_RG_QP_CDR_LPF_RATIO, - FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE, - AN8855_RG_QP_CDR_PR_BUF_IN_SR | - AN8855_RG_QP_CDR_PR_BETA_SEL, - FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) | - FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1)); - if (ret) - return ret; - - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0xf; - else - val = 0xc; - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, - AN8855_RG_QP_CDR_PR_DAC_BAND, - FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, - AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE | - AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, - FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, - AN8855_RG_QP_CDR_PHYCK_SEL | - AN8855_RG_QP_CDR_PHYCK_RSTB | - AN8855_RG_QP_CDR_PHYCK_DIV, - FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) | - FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21)); - if (ret) - return ret; - - ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, - AN8855_RG_QP_CDR_PR_XFICK_EN); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, - AN8855_RG_QP_CDR_PR_KBAND_DIV, - FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26, - AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | - AN8855_RG_LINK_NE_EN | - AN8855_RG_LINK_ERRO_EN, - AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | - AN8855_RG_LINK_ERRO_EN); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0, - AN8855_RG_QP_RX_SAOSC_EN_H_DLY | - AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, - FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) | - FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42, - AN8855_RG_QP_EQ_EN_DLY, - FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2, - AN8855_RG_QP_RX_EQ_EN_H_DLY, - FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9, - AN8855_RG_QP_EQ_LEQOSC_DLYCNT, - FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8, - AN8855_RG_DA_QP_SAOSC_DONE_TIME | - AN8855_RG_DA_QP_LEQOS_EN_TIME, - FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) | - FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff)); - if (ret) - return ret; - - /* Frequency meter */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = 0x10; - else - val = 0x28; - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5, - AN8855_RG_FREDET_CHK_CYCLE, - FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6, - AN8855_RG_FREDET_GOLDEN_CYCLE, - FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64)); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7, - AN8855_RG_FREDET_TOLERATE_CYCLE, - FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710)); - if (ret) - return ret; - - ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0, - AN8855_RG_PHYA_AUTO_INIT); - if (ret) - return ret; - - /* PCS Init */ - if (interface == PHY_INTERFACE_MODE_SGMII && - neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) { - ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0, - AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN); - if (ret) - return ret; - } - - ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1, - AN8855_RG_TBI_10B_MODE); - if (ret) - return ret; - - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { - /* Set AN Ability - Interrupt */ - ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37, - AN8855_RG_FORCE_AN_DONE); - if (ret) - return ret; - - ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13, - AN8855_SGMII_REMOTE_FAULT_DIS | - AN8855_SGMII_IF_MODE, - AN8855_SGMII_REMOTE_FAULT_DIS | - FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb)); - if (ret) - return ret; - } - - /* Rate Adaption - GMII path config. */ - if (interface == PHY_INTERFACE_MODE_2500BASEX) { - ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, - AN8855_RG_P0_DIS_MII_MODE); - if (ret) - return ret; - } else { - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { - ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE, - AN8855_RG_P0_RA_AN_EN); - if (ret) - return ret; - } else { - ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE, - AN8855_RG_FORCE_CUR_SGMII_MODE | - AN8855_RG_FORCE_CUR_SGMII_SEL, - AN8855_RG_FORCE_CUR_SGMII_SEL); - if (ret) - return ret; - - ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, - AN8855_RG_P0_MII_RA_RX_EN | - AN8855_RG_P0_MII_RA_TX_EN | - AN8855_RG_P0_MII_RA_RX_MODE | - AN8855_RG_P0_MII_RA_TX_MODE); - if (ret) - return ret; - } - - ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, - AN8855_RG_P0_MII_MODE); - if (ret) - return ret; - } - - ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0, - AN8855_RG_RATE_ADAPT_RX_BYPASS | - AN8855_RG_RATE_ADAPT_TX_BYPASS | - AN8855_RG_RATE_ADAPT_RX_EN | - AN8855_RG_RATE_ADAPT_TX_EN); - if (ret) - return ret; - - /* Disable AN if not in autoneg */ - ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE, - neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : - 0); - if (ret) - return ret; - - if (interface == PHY_INTERFACE_MODE_SGMII) { - /* Follow SDK init flow with restarting AN after AN enable */ - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { - ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0, - BMCR_ANRESTART); - if (ret) - return ret; - } else { - ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0, - AN8855_RG_FORCE_TXC_SEL); - if (ret) - return ret; - } - } - - /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */ - if (interface == PHY_INTERFACE_MODE_2500BASEX || - neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { - if (interface == PHY_INTERFACE_MODE_2500BASEX) - val = AN8855_RG_LINK_MODE_P0_SPEED_2500; - else - val = AN8855_RG_LINK_MODE_P0_SPEED_1000; - ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0, - AN8855_RG_LINK_MODE_P0 | - AN8855_RG_FORCE_SPD_MODE_P0, - val | AN8855_RG_FORCE_SPD_MODE_P0); - if (ret) - return ret; - } - - /* bypass flow control to MAC */ - ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0, - AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 | - AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 | - AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0); - if (ret) - return ret; - ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2, - AN8855_RG_RXFC_AN_BYPASS_P3 | - AN8855_RG_RXFC_AN_BYPASS_P2 | - AN8855_RG_RXFC_AN_BYPASS_P1 | - AN8855_RG_TXFC_AN_BYPASS_P3 | - AN8855_RG_TXFC_AN_BYPASS_P2 | - AN8855_RG_TXFC_AN_BYPASS_P1 | - AN8855_RG_DPX_AN_BYPASS_P3 | - AN8855_RG_DPX_AN_BYPASS_P2 | - AN8855_RG_DPX_AN_BYPASS_P1 | - AN8855_RG_DPX_AN_BYPASS_P0); - if (ret) - return ret; - - return 0; -} - -static void an8855_pcs_an_restart(struct phylink_pcs *pcs) -{ - return; -} - -static const struct phylink_pcs_ops an8855_pcs_ops = { - .pcs_inband_caps = an8855_pcs_inband_caps, - .pcs_get_state = an8855_pcs_get_state, - .pcs_config = an8855_pcs_config, - .pcs_an_restart = an8855_pcs_an_restart, -}; - -static const struct phylink_mac_ops an8855_phylink_mac_ops = { - .mac_select_pcs = an8855_phylink_mac_select_pcs, - .mac_config = an8855_phylink_mac_config, - .mac_link_down = an8855_phylink_mac_link_down, - .mac_link_up = an8855_phylink_mac_link_up, -}; - -static const struct dsa_switch_ops an8855_switch_ops = { - .get_tag_protocol = an8855_get_tag_protocol, - .setup = an8855_setup, - .get_phy_flags = en8855_get_phy_flags, - .phylink_get_caps = an8855_phylink_get_caps, - .get_strings = an8855_get_strings, - .get_ethtool_stats = an8855_get_ethtool_stats, - .get_sset_count = an8855_get_sset_count, - .get_eth_mac_stats = an8855_get_eth_mac_stats, - .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats, - .get_rmon_stats = an8855_get_rmon_stats, - .port_enable = an8855_port_enable, - .port_disable = an8855_port_disable, - .set_ageing_time = an8855_set_ageing_time, - .port_bridge_join = an8855_port_bridge_join, - .port_bridge_leave = an8855_port_bridge_leave, - .port_fast_age = an8855_port_fast_age, - .port_stp_state_set = an8855_port_stp_state_set, - .port_pre_bridge_flags = an8855_port_pre_bridge_flags, - .port_bridge_flags = an8855_port_bridge_flags, - .port_vlan_filtering = an8855_port_vlan_filtering, - .port_vlan_add = an8855_port_vlan_add, - .port_vlan_del = an8855_port_vlan_del, - .port_fdb_add = an8855_port_fdb_add, - .port_fdb_del = an8855_port_fdb_del, - .port_fdb_dump = an8855_port_fdb_dump, - .port_mdb_add = an8855_port_mdb_add, - .port_mdb_del = an8855_port_mdb_del, - .port_change_mtu = an8855_port_change_mtu, - .port_max_mtu = an8855_port_max_mtu, - .port_mirror_add = an8855_port_mirror_add, - .port_mirror_del = an8855_port_mirror_del, -}; - -static int an8855_read_switch_id(struct an8855_priv *priv) -{ - u32 id; - int ret; - - ret = regmap_read(priv->regmap, AN8855_CREV, &id); - if (ret) - return ret; - - if (id != AN8855_ID) { - dev_err(priv->dev, - "Switch id detected %x but expected %x\n", - id, AN8855_ID); - return -ENODEV; - } - - return 0; -} - -static int an8855_switch_probe(struct platform_device *pdev) -{ - struct an8855_priv *priv; - u32 val; - int ret; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = &pdev->dev; - priv->phy_require_calib = of_property_read_bool(priv->dev->of_node, - "airoha,ext-surge"); - - priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", - GPIOD_OUT_LOW); - if (IS_ERR(priv->reset_gpio)) - return PTR_ERR(priv->reset_gpio); - - /* Get regmap from MFD */ - priv->regmap = dev_get_regmap(priv->dev->parent, NULL); - - if (priv->reset_gpio) { - usleep_range(100000, 150000); - gpiod_set_value_cansleep(priv->reset_gpio, 0); - usleep_range(100000, 150000); - gpiod_set_value_cansleep(priv->reset_gpio, 1); - - /* Poll HWTRAP reg to wait for Switch to fully Init */ - ret = regmap_read_poll_timeout(priv->regmap, AN8855_HWTRAP, val, - val, 20, 200000); - if (ret) - return ret; - } - - ret = an8855_read_switch_id(priv); - if (ret) - return ret; - - priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL); - if (!priv->ds) - return -ENOMEM; - - priv->ds->dev = priv->dev; - priv->ds->num_ports = AN8855_NUM_PORTS; - priv->ds->priv = priv; - priv->ds->ops = &an8855_switch_ops; - devm_mutex_init(priv->dev, &priv->reg_mutex); - priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops; - - priv->pcs.ops = &an8855_pcs_ops; - priv->pcs.neg_mode = true; - priv->pcs.poll = true; - - dev_set_drvdata(priv->dev, priv); - - return dsa_register_switch(priv->ds); -} - -static void an8855_switch_remove(struct platform_device *pdev) -{ - struct an8855_priv *priv = dev_get_drvdata(&pdev->dev); - - if (priv) - dsa_unregister_switch(priv->ds); -} - -static const struct of_device_id an8855_switch_of_match[] = { - { .compatible = "airoha,an8855-switch" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, an8855_switch_of_match); - -static struct platform_driver an8855_switch_driver = { - .probe = an8855_switch_probe, - .remove_new = an8855_switch_remove, - .driver = { - .name = "an8855-switch", - .of_match_table = an8855_switch_of_match, - }, -}; -module_platform_driver(an8855_switch_driver); - -MODULE_AUTHOR("Min Yao "); -MODULE_AUTHOR("Christian Marangi "); -MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h deleted file mode 100644 index 2462b9d337..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h +++ /dev/null @@ -1,783 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2023 Min Yao - * Copyright (C) 2024 Christian Marangi - */ - -#ifndef __AN8855_H -#define __AN8855_H - -#include - -#define AN8855_NUM_PORTS 6 -#define AN8855_CPU_PORT 5 -#define AN8855_NUM_FDB_RECORDS 2048 -#define AN8855_GPHY_SMI_ADDR_DEFAULT 1 -#define AN8855_PORT_VID_DEFAULT 0 - -#define MTK_TAG_LEN 4 -#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN) - -#define AN8855_L2_AGING_MS_CONSTANT 1024 - -#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) - -/* AN8855_SCU 0x10000000 */ -#define AN8855_RG_GPIO_LED_MODE 0x10000054 -#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4))) -#define AN8855_RG_INTB_MODE 0x10000080 -#define AN8855_RG_RGMII_TXCK_C 0x100001d0 - -#define AN8855_PKG_SEL 0x10000094 -#define AN8855_PAG_SEL_AN8855H 0x2 - -/* Register for hw trap status */ -#define AN8855_HWTRAP 0x1000009c - -#define AN8855_RG_GPIO_L_INV 0x10000010 -#define AN8855_RG_GPIO_CTRL 0x1000a300 -#define AN8855_RG_GPIO_DATA 0x1000a304 -#define AN8855_RG_GPIO_OE 0x1000a314 - -#define AN8855_CREV 0x10005000 -#define AN8855_ID 0x8855 - -/* Register for system reset */ -#define AN8855_RST_CTRL 0x100050c0 -#define AN8855_SYS_CTRL_SYS_RST BIT(31) - -#define AN8855_INT_MASK 0x100050f0 -#define AN8855_INT_SYS BIT(15) - -#define AN8855_RG_CLK_CPU_ICG 0x10005034 -#define AN8855_MCU_ENABLE BIT(3) - -#define AN8855_RG_TIMER_CTL 0x1000a100 -#define AN8855_WDOG_ENABLE BIT(25) - -#define AN8855_RG_GDMP_RAM 0x10010000 - -/* Registers to mac forward control for unknown frames */ -#define AN8855_MFC 0x10200010 -#define AN8855_CPU_EN BIT(15) -#define AN8855_CPU_PORT_IDX GENMASK(12, 8) - -#define AN8855_PAC 0x10200024 -#define AN8855_TAG_PAE_MANG_FR BIT(30) -#define AN8855_TAG_PAE_BPDU_FR BIT(28) -#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25) -#define AN8855_TAG_PAE_LKY_VLAN BIT(24) -#define AN8855_TAG_PAE_PRI_HIGH BIT(23) -#define AN8855_TAG_PAE_MIR GENMASK(20, 19) -#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16) -#define AN8855_PAE_MANG_FR BIT(14) -#define AN8855_PAE_BPDU_FR BIT(12) -#define AN8855_PAE_EG_TAG GENMASK(11, 9) -#define AN8855_PAE_LKY_VLAN BIT(8) -#define AN8855_PAE_PRI_HIGH BIT(7) -#define AN8855_PAE_MIR GENMASK(4, 3) -#define AN8855_PAE_PORT_FW GENMASK(2, 0) - -#define AN8855_RGAC1 0x10200028 -#define AN8855_R02_MANG_FR BIT(30) -#define AN8855_R02_BPDU_FR BIT(28) -#define AN8855_R02_EG_TAG GENMASK(27, 25) -#define AN8855_R02_LKY_VLAN BIT(24) -#define AN8855_R02_PRI_HIGH BIT(23) -#define AN8855_R02_MIR GENMASK(20, 19) -#define AN8855_R02_PORT_FW GENMASK(18, 16) -#define AN8855_R01_MANG_FR BIT(14) -#define AN8855_R01_BPDU_FR BIT(12) -#define AN8855_R01_EG_TAG GENMASK(11, 9) -#define AN8855_R01_LKY_VLAN BIT(8) -#define AN8855_R01_PRI_HIGH BIT(7) -#define AN8855_R01_MIR GENMASK(4, 3) -#define AN8855_R01_PORT_FW GENMASK(2, 0) - -#define AN8855_RGAC2 0x1020002c -#define AN8855_R0E_MANG_FR BIT(30) -#define AN8855_R0E_BPDU_FR BIT(28) -#define AN8855_R0E_EG_TAG GENMASK(27, 25) -#define AN8855_R0E_LKY_VLAN BIT(24) -#define AN8855_R0E_PRI_HIGH BIT(23) -#define AN8855_R0E_MIR GENMASK(20, 19) -#define AN8855_R0E_PORT_FW GENMASK(18, 16) -#define AN8855_R03_MANG_FR BIT(14) -#define AN8855_R03_BPDU_FR BIT(12) -#define AN8855_R03_EG_TAG GENMASK(11, 9) -#define AN8855_R03_LKY_VLAN BIT(8) -#define AN8855_R03_PRI_HIGH BIT(7) -#define AN8855_R03_MIR GENMASK(4, 3) -#define AN8855_R03_PORT_FW GENMASK(2, 0) - -#define AN8855_AAC 0x102000a0 -#define AN8855_MAC_AUTO_FLUSH BIT(28) -/* Control Address Table Age time. - * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT - */ -#define AN8855_AGE_CNT GENMASK(20, 12) -/* Value in seconds. Value is always incremented of 1 */ -#define AN8855_AGE_UNIT GENMASK(10, 0) - -/* Registers for ARL Unknown Unicast Forward control */ -#define AN8855_UNUF 0x102000b4 - -/* Registers for ARL Unknown Multicast Forward control */ -#define AN8855_UNMF 0x102000b8 - -/* Registers for ARL Broadcast forward control */ -#define AN8855_BCF 0x102000bc - -/* Registers for port address age disable */ -#define AN8855_AGDIS 0x102000c0 - -/* Registers for mirror port control */ -#define AN8855_MIR 0x102000cc -#define AN8855_MIRROR_EN BIT(7) -#define AN8855_MIRROR_PORT GENMASK(4, 0) - -/* Registers for BPDU and PAE frame control*/ -#define AN8855_BPC 0x102000d0 -#define AN8855_BPDU_MANG_FR BIT(14) -#define AN8855_BPDU_BPDU_FR BIT(12) -#define AN8855_BPDU_EG_TAG GENMASK(11, 9) -#define AN8855_BPDU_LKY_VLAN BIT(8) -#define AN8855_BPDU_PRI_HIGH BIT(7) -#define AN8855_BPDU_MIR GENMASK(4, 3) -#define AN8855_BPDU_PORT_FW GENMASK(2, 0) - -/* Registers for IP Unknown Multicast Forward control */ -#define AN8855_UNIPMF 0x102000dc - -enum an8855_bpdu_port_fw { - AN8855_BPDU_FOLLOW_MFC = 0, - AN8855_BPDU_CPU_EXCLUDE = 4, - AN8855_BPDU_CPU_INCLUDE = 5, - AN8855_BPDU_CPU_ONLY = 6, - AN8855_BPDU_DROP = 7, -}; - -/* Register for address table control */ -#define AN8855_ATC 0x10200300 -#define AN8855_ATC_BUSY BIT(31) -#define AN8855_ATC_HASH GENMASK(24, 16) -#define AN8855_ATC_HIT GENMASK(15, 12) -#define AN8855_ATC_MAT_MASK GENMASK(11, 7) -#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x) -#define AN8855_ATC_SAT GENMASK(5, 4) -#define AN8855_ATC_CMD GENMASK(2, 0) - -enum an8855_fdb_mat_cmds { - AND8855_FDB_MAT_ALL = 0, - AND8855_FDB_MAT_MAC, /* All MAC address */ - AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */ - AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */ - AND8855_FDB_MAT_DIP, /* All DIP/GA address */ - AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */ - AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */ - AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */ - AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */ - AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */ - AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */ - AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */ - AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */ - AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */ - AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */ - AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */ - AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */ - /* All MAC address with MAC type (dynamic or static) with CVID */ - AND8855_FDB_MAT_MAC_TYPE_CVID, - /* All MAC address with MAC type (dynamic or static) with Filter ID */ - AND8855_FDB_MAT_MAC_TYPE_FID, - /* All MAC address with MAC type (dynamic or static) with port */ - AND8855_FDB_MAT_MAC_TYPE_PORT, -}; - -enum an8855_fdb_cmds { - AN8855_FDB_READ = 0, - AN8855_FDB_WRITE = 1, - AN8855_FDB_FLUSH = 2, - AN8855_FDB_START = 4, - AN8855_FDB_NEXT = 5, -}; - -/* Registers for address table access */ -#define AN8855_ATA1 0x10200304 -#define AN8855_ATA1_MAC0 GENMASK(31, 24) -#define AN8855_ATA1_MAC1 GENMASK(23, 16) -#define AN8855_ATA1_MAC2 GENMASK(15, 8) -#define AN8855_ATA1_MAC3 GENMASK(7, 0) -#define AN8855_ATA2 0x10200308 -#define AN8855_ATA2_MAC4 GENMASK(31, 24) -#define AN8855_ATA2_MAC5 GENMASK(23, 16) -#define AN8855_ATA2_UNAUTH BIT(10) -#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */ -#define AN8855_ATA2_AGE GENMASK(8, 0) - -/* Register for address table write data */ -#define AN8855_ATWD 0x10200324 -#define AN8855_ATWD_FID GENMASK(31, 28) -#define AN8855_ATWD_VID GENMASK(27, 16) -#define AN8855_ATWD_IVL BIT(15) -#define AN8855_ATWD_EG_TAG GENMASK(14, 12) -#define AN8855_ATWD_SA_MIR GENMASK(9, 8) -#define AN8855_ATWD_SA_FWD GENMASK(7, 5) -#define AN8855_ATWD_UPRI GENMASK(4, 2) -#define AN8855_ATWD_LEAKY BIT(1) -#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */ -#define AN8855_ATWD2 0x10200328 -#define AN8855_ATWD2_PORT GENMASK(7, 0) - -/* Registers for table search read address */ -#define AN8855_ATRDS 0x10200330 -#define AN8855_ATRD_SEL GENMASK(1, 0) -#define AN8855_ATRD0 0x10200334 -#define AN8855_ATRD0_FID GENMASK(28, 25) -#define AN8855_ATRD0_VID GENMASK(21, 10) -#define AN8855_ATRD0_IVL BIT(9) -#define AN8855_ATRD0_TYPE GENMASK(4, 3) -#define AN8855_ATRD0_ARP GENMASK(2, 1) -#define AN8855_ATRD0_LIVE BIT(0) -#define AN8855_ATRD1 0x10200338 -#define AN8855_ATRD1_MAC4 GENMASK(31, 24) -#define AN8855_ATRD1_MAC5 GENMASK(23, 16) -#define AN8855_ATRD1_AGING GENMASK(11, 3) -#define AN8855_ATRD2 0x1020033c -#define AN8855_ATRD2_MAC0 GENMASK(31, 24) -#define AN8855_ATRD2_MAC1 GENMASK(23, 16) -#define AN8855_ATRD2_MAC2 GENMASK(15, 8) -#define AN8855_ATRD2_MAC3 GENMASK(7, 0) -#define AN8855_ATRD3 0x10200340 -#define AN8855_ATRD3_PORTMASK GENMASK(7, 0) - -enum an8855_fdb_type { - AN8855_MAC_TB_TY_MAC = 0, - AN8855_MAC_TB_TY_DIP = 1, - AN8855_MAC_TB_TY_DIP_SIP = 2, -}; - -/* Register for vlan table control */ -#define AN8855_VTCR 0x10200600 -#define AN8855_VTCR_BUSY BIT(31) -#define AN8855_VTCR_FUNC GENMASK(15, 12) -#define AN8855_VTCR_VID GENMASK(11, 0) - -enum an8855_vlan_cmd { - /* Read/Write the specified VID entry from VAWD register based - * on VID. - */ - AN8855_VTCR_RD_VID = 0, - AN8855_VTCR_WR_VID = 1, -}; - -/* Register for setup vlan write data */ -#define AN8855_VAWD0 0x10200604 -/* VLAN Member Control */ -#define AN8855_VA0_PORT GENMASK(31, 26) -/* Egress Tag Control */ -#define AN8855_VA0_ETAG GENMASK(23, 12) -#define AN8855_VA0_ETAG_PORT GENMASK(13, 12) -#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2) -#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \ - AN8855_VA0_ETAG_PORT_SHIFT(port)) -#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \ - AN8855_VA0_ETAG_PORT_SHIFT(port)) -#define AN8855_VA0_EG_CON BIT(11) -#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */ -#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */ -#define AN8855_VA0_FID GENMASK(4, 1) -#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */ -#define AN8855_VAWD1 0x10200608 -#define AN8855_VA1_PORT_STAG BIT(1) - -enum an8855_fid { - AN8855_FID_STANDALONE = 0, - AN8855_FID_BRIDGED = 1, -}; - -/* Same register field of VAWD0 */ -#define AN8855_VARD0 0x10200618 - -enum an8855_vlan_egress_attr { - AN8855_VLAN_EGRESS_UNTAG = 0, - AN8855_VLAN_EGRESS_TAG = 2, - AN8855_VLAN_EGRESS_STACK = 3, -}; - -/* Register for port STP state control */ -#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200)) -/* Up to 16 FID supported, each with the same mask */ -#define AN8855_FID_PST GENMASK(1, 0) -#define AN8855_FID_PST_SHIFT(fid) (2 * (fid)) -#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \ - AN8855_FID_PST_SHIFT(fid)) -#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \ - AN8855_FID_PST_SHIFT(fid)) - -enum an8855_stp_state { - AN8855_STP_DISABLED = 0, - AN8855_STP_BLOCKING = 1, - AN8855_STP_LISTENING = AN8855_STP_BLOCKING, - AN8855_STP_LEARNING = 2, - AN8855_STP_FORWARDING = 3 -}; - -/* Register for port control */ -#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200)) -#define AN8855_EG_TAG GENMASK(29, 28) -#define AN8855_PORT_PRI GENMASK(26, 24) -#define AN8855_PORT_TX_MIR BIT(20) -#define AN8855_PORT_RX_MIR BIT(16) -#define AN8855_PORT_VLAN GENMASK(1, 0) - -enum an8855_port_mode { - /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ - AN8855_PORT_MATRIX_MODE = 0, - - /* Fallback Mode: Forward received frames with ingress ports that do - * not belong to the VLAN member. Frames whose VID is not listed on - * the VLAN table are forwarded by the PCR_MATRIX members. - */ - AN8855_PORT_FALLBACK_MODE = 1, - - /* Check Mode: Forward received frames whose ingress do not - * belong to the VLAN member. Discard frames if VID ismiddes on the - * VLAN table. - */ - AN8855_PORT_CHECK_MODE = 2, - - /* Security Mode: Discard any frame due to ingress membership - * violation or VID missed on the VLAN table. - */ - AN8855_PORT_SECURITY_MODE = 3, -}; - -/* Register for port security control */ -#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200)) -#define AN8855_SA_DIS BIT(4) - -/* Register for port vlan control */ -#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200)) -#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11) -#define AN8855_PVC_EG_TAG GENMASK(10, 8) -#define AN8855_VLAN_ATTR GENMASK(7, 6) -#define AN8855_PORT_SPEC_TAG BIT(5) -#define AN8855_ACC_FRM GENMASK(1, 0) - -enum an8855_vlan_port_eg_tag { - AN8855_VLAN_EG_DISABLED = 0, - AN8855_VLAN_EG_CONSISTENT = 1, - AN8855_VLAN_EG_UNTAGGED = 4, - AN8855_VLAN_EG_SWAP = 5, - AN8855_VLAN_EG_TAGGED = 6, - AN8855_VLAN_EG_STACK = 7, -}; - -enum an8855_vlan_port_attr { - AN8855_VLAN_USER = 0, - AN8855_VLAN_STACK = 1, - AN8855_VLAN_TRANSPARENT = 3, -}; - -enum an8855_vlan_port_acc_frm { - AN8855_VLAN_ACC_ALL = 0, - AN8855_VLAN_ACC_TAGGED = 1, - AN8855_VLAN_ACC_UNTAGGED = 2, -}; - -#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200)) -#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0) - -#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200)) -#define AN8855_PORTMATRIX GENMASK(5, 0) -/* Port matrix without the CPU port that should never be removed */ -#define AN8855_USER_PORTMATRIX GENMASK(4, 0) - -/* Register for port PVID */ -#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200)) -#define AN8855_G0_PORT_VID GENMASK(11, 0) - -/* Register for port MAC control register */ -#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200)) -#define AN8855_PMCR_FORCE_MODE BIT(31) -#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28) -#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4) -#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3) -#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2) -#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) -#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) -#define AN8855_PMCR_FORCE_FDX BIT(25) -#define AN8855_PMCR_FORCE_LNK BIT(24) -#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20) -#define AN8855_PMCR_EXT_PHY BIT(19) -#define AN8855_PMCR_MAC_MODE BIT(18) -#define AN8855_PMCR_TX_EN BIT(16) -#define AN8855_PMCR_RX_EN BIT(15) -#define AN8855_PMCR_BACKOFF_EN BIT(12) -#define AN8855_PMCR_BACKPR_EN BIT(11) -#define AN8855_PMCR_FORCE_EEE5G BIT(9) -#define AN8855_PMCR_FORCE_EEE2P5G BIT(8) -#define AN8855_PMCR_FORCE_EEE1G BIT(7) -#define AN8855_PMCR_FORCE_EEE100 BIT(6) -#define AN8855_PMCR_TX_FC_EN BIT(5) -#define AN8855_PMCR_RX_FC_EN BIT(4) - -#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200) -#define AN8855_PMSR_SPEED GENMASK(30, 28) -#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4) -#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3) -#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2) -#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1) -#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0) -#define AN8855_PMSR_DPX BIT(25) -#define AN8855_PMSR_LNK BIT(24) -#define AN8855_PMSR_EEE1G BIT(7) -#define AN8855_PMSR_EEE100M BIT(6) -#define AN8855_PMSR_RX_FC BIT(5) -#define AN8855_PMSR_TX_FC BIT(4) - -#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200) -#define AN8855_LPI_MODE_EN BIT(31) -#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16) -#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8) -#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0) -#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200) -#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0) - -#define AN8855_GMACCR 0x10213e00 -#define AN8855_MAX_RX_JUMBO GENMASK(7, 4) -/* 2K for 0x0, 0x1, 0x2 */ -#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0) -#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3) -#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4) -#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5) -#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6) -#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7) -#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8) -#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9) -#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa) -#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb) -#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc) -#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0) -#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0) -#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1) -#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2) -#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3) - -#define AN8855_CKGCR 0x10213e1c -#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14) -#define AN8855_CKG_LNKDN_PORT_STOP BIT(1) -#define AN8855_CKG_LNKDN_GLB_STOP BIT(0) - -/* Register for MIB */ -#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200) -/* Each define is an offset of AN8855_PORT_MIB_COUNTER */ -#define AN8855_PORT_MIB_TX_DROP 0x00 -#define AN8855_PORT_MIB_TX_CRC_ERR 0x04 -#define AN8855_PORT_MIB_TX_UNICAST 0x08 -#define AN8855_PORT_MIB_TX_MULTICAST 0x0c -#define AN8855_PORT_MIB_TX_BROADCAST 0x10 -#define AN8855_PORT_MIB_TX_COLLISION 0x14 -#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18 -#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c -#define AN8855_PORT_MIB_TX_DEFERRED 0x20 -#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24 -#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 -#define AN8855_PORT_MIB_TX_PAUSE 0x2c -#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30 -#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 -#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 -#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3 -#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 -#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44 -#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48 -#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */ -#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54 -#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */ -#define AN8855_PORT_MIB_RX_DROP 0x80 -#define AN8855_PORT_MIB_RX_FILTERING 0x84 -#define AN8855_PORT_MIB_RX_UNICAST 0x88 -#define AN8855_PORT_MIB_RX_MULTICAST 0x8c -#define AN8855_PORT_MIB_RX_BROADCAST 0x90 -#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94 -#define AN8855_PORT_MIB_RX_CRC_ERR 0x98 -#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c -#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0 -#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4 -#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8 -#define AN8855_PORT_MIB_RX_PAUSE 0xac -#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0 -#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4 -#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8 -#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc -#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0 -#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4 -#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8 -#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */ -#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4 -#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8 -#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc -#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0 -#define AN8855_PORT_MIB_WRED_DROP 0xe4 -#define AN8855_PORT_MIB_MIRROR_DROP 0xe8 -#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */ -#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4 -#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8 -#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc -#define AN8855_MIB_CCR 0x10213e30 -#define AN8855_CCR_MIB_ENABLE BIT(31) -#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7) -#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6) -#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5) -#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4) -#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3) -#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2) -#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1) -#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0) -#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \ - AN8855_CCR_RX_OCT_CNT_GOOD | \ - AN8855_CCR_RX_OCT_CNT_BAD | \ - AN8855_CCR_TX_OCT_CNT_GOOD | \ - AN8855_CCR_TX_OCT_CNT_BAD | \ - AN8855_CCR_RX_OCT_CNT_BAD_2 | \ - AN8855_CCR_TX_OCT_CNT_BAD_2) -#define AN8855_MIB_CLR 0x10213e34 -#define AN8855_MIB_PORT6_CLR BIT(6) -#define AN8855_MIB_PORT5_CLR BIT(5) -#define AN8855_MIB_PORT4_CLR BIT(4) -#define AN8855_MIB_PORT3_CLR BIT(3) -#define AN8855_MIB_PORT2_CLR BIT(2) -#define AN8855_MIB_PORT1_CLR BIT(1) -#define AN8855_MIB_PORT0_CLR BIT(0) - -/* HSGMII/SGMII Configuration register */ -/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */ -#define AN8855_SGMII_REG_AN0 0x10220000 -/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */ -/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */ -#define AN8855_SGMII_REG_AN_13 0x10220034 -#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8) -#define AN8855_SGMII_IF_MODE GENMASK(5, 0) -#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060 -#define AN8855_RG_FORCE_AN_DONE BIT(0) - -/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */ -#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00 -#define AN8855_RG_TBI_10B_MODE BIT(30) -#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24 -#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4) -#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0) - -/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */ -#define AN8855_SGMII_STS_CTRL_0 0x10224018 -#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4) -#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3) -#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2) -#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1) -#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0) -#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2) -#define AN8855_MSG_RX_CTRL_0 0x10224100 -#define AN8855_MSG_RX_LIK_STS_0 0x10224514 -#define AN8855_RG_DPX_STS_P3 BIT(24) -#define AN8855_RG_DPX_STS_P2 BIT(16) -#define AN8855_RG_EEE1G_STS_P1 BIT(12) -#define AN8855_RG_DPX_STS_P1 BIT(8) -#define AN8855_RG_TXFC_STS_P0 BIT(2) -#define AN8855_RG_RXFC_STS_P0 BIT(1) -#define AN8855_RG_DPX_STS_P0 BIT(0) -#define AN8855_MSG_RX_LIK_STS_2 0x1022451c -#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11) -#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10) -#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9) -#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7) -#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6) -#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5) -#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3) -#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2) -#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1) -#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0) -#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520 -#define AN8855_RG_FORCE_TXC_SEL BIT(4) - -/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */ -#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8 - -/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */ -#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000 -#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27) -#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26) -#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4) -#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0) -#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100 -#define AN8855_RG_P0_DIS_MII_MODE BIT(31) -#define AN8855_RG_P0_MII_MODE BIT(28) -#define AN8855_RG_P0_MII_RA_RX_EN BIT(3) -#define AN8855_RG_P0_MII_RA_TX_EN BIT(2) -#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1) -#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0) -#define AN8855_MII_RA_AN_ENABLE 0x10226300 -#define AN8855_RG_P0_RA_AN_EN BIT(0) - -/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */ -#define AN8855_QP_CK_RST_CTRL_4 0x1022a310 -#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324 -#define AN8855_RG_SGMII_MODE GENMASK(5, 4) -#define AN8855_RG_SGMII_AN_EN BIT(0) -#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330 -#define AN8855_RG_TPHY_SPEED GENMASK(3, 2) - -/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */ -#define AN8855_USGMII_CTRL_0 0x1022c000 - -/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */ -#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100 -#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12) -#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124 -#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0) - -#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208 -#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16) -#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230 -#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0) -#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c -#define AN8855_RG_LCPLL_NCPO_CHG BIT(24) -#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248 -#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) -#define AN8855_INTF_CTRL_8 0x1022e320 -#define AN8855_INTF_CTRL_9 0x1022e324 -#define AN8855_INTF_CTRL_10 0x1022e328 -#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29) -#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24) -#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21) -#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16) -#define AN8855_INTF_CTRL_11 0x1022e32c -#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6) -#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0) -#define AN8855_PLL_CTRL_0 0x1022e400 -#define AN8855_RG_PHYA_AUTO_INIT BIT(0) -#define AN8855_PLL_CTRL_2 0x1022e408 -#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30) -#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29) -#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28) -#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27) -#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26) -#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24) -#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22) -#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20) -#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16) -#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14) -#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12) -#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8) -#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6) -#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2) -#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0) -#define AN8855_PLL_CTRL_3 0x1022e40c -#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16) -#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0) -#define AN8855_PLL_CTRL_4 0x1022e410 -#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3) -#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2) -#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0) -#define AN8855_PLL_CK_CTRL_0 0x1022e414 -#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9) -#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8) -#define AN8855_RX_DLY_0 0x1022e614 -#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8) -#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0) -#define AN8855_RX_CTRL_2 0x1022e630 -#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16) -#define AN8855_RX_CTRL_5 0x1022e63c -#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10) -#define AN8855_RX_CTRL_6 0x1022e640 -#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0) -#define AN8855_RX_CTRL_7 0x1022e644 -#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0) -#define AN8855_RX_CTRL_8 0x1022e648 -#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16) -#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0) -#define AN8855_RX_CTRL_26 0x1022e690 -#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26) -#define AN8855_RG_LINK_NE_EN BIT(24) -#define AN8855_RG_LINK_ERRO_EN BIT(23) -#define AN8855_RX_CTRL_42 0x1022e6d0 -#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0) - -/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */ -#define AN8855_RG_QP_RX_DAC_EN 0x1022f000 -#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16) -#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004 -#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11) -#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008 -#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24) -#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20) -#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c -#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4) -#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014 -#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29) -#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25) -#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018 -#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24) -#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8) -#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c -#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30) -#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6) -#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0) -#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020 -#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16) -#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13) -#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6) -#define AN8855_RG_QP_TX_MODE 0x1022f028 -#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16) -#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0) -#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c -#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040 -#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4) -#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3) - -/* AN8855_ETHER_SYS_BASE 0x1028c800 */ -#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 -#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848 - -#define MIB_DESC(_s, _o, _n) \ - { \ - .size = (_s), \ - .offset = (_o), \ - .name = (_n), \ - } - -struct an8855_mib_desc { - unsigned int size; - unsigned int offset; - const char *name; -}; - -struct an8855_fdb { - u16 vid; - u8 port_mask; - u16 aging; - u8 mac[6]; - bool noarp; - u8 live; - u8 type; - u8 fid; - u8 ivl; -}; - -struct an8855_priv { - struct device *dev; - struct dsa_switch *ds; - struct regmap *regmap; - struct gpio_desc *reset_gpio; - /* Protect ATU or VLAN table access */ - struct mutex reg_mutex; - - struct phylink_pcs pcs; - - u8 mirror_rx; - u8 mirror_tx; - u8 port_isolated_map; - - bool phy_require_calib; -}; - -#endif /* __AN8855_H */ diff --git a/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c b/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c deleted file mode 100644 index 5feba72c02..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MDIO passthrough driver for Airoha AN8855 Switch - */ - -#include -#include -#include -#include - -static int an855_phy_restore_page(struct an8855_mfd_priv *priv, - int phy) __must_hold(&priv->bus->mdio_lock) -{ - /* Check PHY page only for addr shared with switch */ - if (phy != priv->switch_addr) - return 0; - - /* Don't restore page if it's not set to switch page */ - if (priv->current_page != FIELD_GET(AN8855_PHY_PAGE, - AN8855_PHY_PAGE_EXTENDED_4)) - return 0; - - /* Restore page to 0, PHY might change page right after but that - * will be ignored as it won't be a switch page. - */ - return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD); -} - -static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum) -{ - struct an8855_mfd_priv *priv = bus->priv; - struct mii_bus *real_bus = priv->bus; - int ret; - - mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED); - - ret = an855_phy_restore_page(priv, phy); - if (ret) - goto exit; - - ret = __mdiobus_read(real_bus, phy, regnum); -exit: - mutex_unlock(&real_bus->mdio_lock); - - return ret; -} - -static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val) -{ - struct an8855_mfd_priv *priv = bus->priv; - struct mii_bus *real_bus = priv->bus; - int ret; - - mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED); - - ret = an855_phy_restore_page(priv, phy); - if (ret) - goto exit; - - ret = __mdiobus_write(real_bus, phy, regnum, val); -exit: - mutex_unlock(&real_bus->mdio_lock); - - return ret; -} - -static int an8855_mdio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct an8855_mfd_priv *priv; - struct mii_bus *bus; - int ret; - - /* Get priv of MFD */ - priv = dev_get_drvdata(dev->parent); - - bus = devm_mdiobus_alloc(dev); - if (!bus) - return -ENOMEM; - - bus->priv = priv; - bus->name = KBUILD_MODNAME "-mii"; - snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", - priv->switch_addr); - bus->parent = dev; - bus->read = an8855_phy_read; - bus->write = an8855_phy_write; - - ret = devm_of_mdiobus_register(dev, bus, dev->of_node); - if (ret) - return dev_err_probe(dev, ret, "failed to register MDIO bus\n"); - - return ret; -} - -static const struct of_device_id an8855_mdio_of_match[] = { - { .compatible = "airoha,an8855-mdio", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, an8855_mdio_of_match); - -static struct platform_driver an8855_mdio_driver = { - .probe = an8855_mdio_probe, - .driver = { - .name = "an8855-mdio", - .of_match_table = an8855_mdio_of_match, - }, -}; -module_platform_driver(an8855_mdio_driver); - -MODULE_AUTHOR("Christian Marangi "); -MODULE_DESCRIPTION("Driver for AN8855 MDIO passthrough"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c b/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c deleted file mode 100644 index cf10b7a9a8..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2024 Christian Marangi - */ - -#include -#include -#include -#include - -#define AN8855_PHY_SELECT_PAGE 0x1f -#define AN8855_PHY_PAGE GENMASK(2, 0) -#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) -#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) - -/* MII Registers Page 1 */ -#define AN8855_PHY_EXT_REG_14 0x14 -#define AN8855_PHY_EN_DOWN_SHIFT BIT(4) - -/* R50 Calibration regs in MDIO_MMD_VEND1 */ -#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174 -#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15) -#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8) -#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7) -#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0) -#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175 -#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15) -#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8) -#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7) -#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0) - -#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24) - -/* PHY TX PAIR DELAY SELECT Register */ -#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013 -#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12) -#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8) -#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4) -#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0) -/* PHY ADC Register */ -#define AN8855_PHY_RXADC_CTRL 0x0d8 -#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12) -#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8) -#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4) -#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0) -#define AN8855_PHY_RXADC_REV_0 0x0d9 -#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8) -#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0) -#define AN8855_PHY_RXADC_REV_1 0x0da -#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8) -#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0) - -#define AN8855_PHY_ID 0xc0ff0410 - -#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) - -struct air_an8855_priv { - u8 calibration_data[4]; -}; - -static const u8 dsa_r50ohm_table[] = { - 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, - 127, 127, 127, 127, 127, 127, 127, 126, 122, 117, - 112, 109, 104, 101, 97, 94, 90, 88, 84, 80, - 78, 74, 72, 68, 66, 64, 61, 58, 56, 53, - 51, 48, 47, 44, 42, 40, 38, 36, 34, 32, - 31, 28, 27, 24, 24, 22, 20, 18, 16, 16, - 14, 12, 11, 9 -}; - -static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name, - u8 *dest) -{ - u32 shift_sel, val; - int ret; - int i; - - ret = nvmem_cell_read_u32(dev, calib_name, &val); - if (ret) - return ret; - - shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val); - for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++) - if (dsa_r50ohm_table[i] == shift_sel) - break; - - if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table)) - *dest = dsa_r50ohm_table[25]; - else - *dest = dsa_r50ohm_table[i - 8]; - - return 0; -} - -static int an8855_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - struct device_node *node = dev->of_node; - struct air_an8855_priv *priv; - - /* If we don't have a node, skip calib */ - if (!node) - return 0; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - phydev->priv = priv; - - return 0; -} - -static int an8855_get_downshift(struct phy_device *phydev, u8 *data) -{ - int val; - - val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14); - if (val < 0) - return val; - - *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT : - DOWNSHIFT_DEV_DISABLE; - - return 0; -} - -static int an8855_set_downshift(struct phy_device *phydev, u8 cnt) -{ - u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0; - - return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, - AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT, - ds); -} - -static int an8855_config_init(struct phy_device *phydev) -{ - struct air_an8855_priv *priv = phydev->priv; - struct device *dev = &phydev->mdio.dev; - int ret; - - /* Enable HW auto downshift */ - ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); - if (ret) - return ret; - - /* Apply calibration values, if needed. - * AN8855_PHY_FLAGS_EN_CALIBRATION signal this. - */ - if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) { - u8 *calibration_data = priv->calibration_data; - - ret = en8855_get_r50ohm_val(dev, "tx_a", &calibration_data[0]); - if (ret) - return ret; - - ret = en8855_get_r50ohm_val(dev, "tx_b", &calibration_data[1]); - if (ret) - return ret; - - ret = en8855_get_r50ohm_val(dev, "tx_c", &calibration_data[2]); - if (ret) - return ret; - - ret = en8855_get_r50ohm_val(dev, "tx_d", &calibration_data[3]); - if (ret) - return ret; - - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB, - AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B, - FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) | - FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1])); - if (ret) - return ret; - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD, - AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D, - FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) | - FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3])); - if (ret) - return ret; - } - - /* Apply values to reduce signal noise */ - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE, - FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) | - FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4)); - if (ret) - return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL, - AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A | - AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C); - if (ret) - return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0, - FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1)); - if (ret) - return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1, - FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1)); - if (ret) - return ret; - - return 0; -} - -static int an8855_get_tunable(struct phy_device *phydev, - struct ethtool_tunable *tuna, void *data) -{ - switch (tuna->id) { - case ETHTOOL_PHY_DOWNSHIFT: - return an8855_get_downshift(phydev, data); - default: - return -EOPNOTSUPP; - } -} - -static int an8855_set_tunable(struct phy_device *phydev, - struct ethtool_tunable *tuna, const void *data) -{ - switch (tuna->id) { - case ETHTOOL_PHY_DOWNSHIFT: - return an8855_set_downshift(phydev, *(const u8 *)data); - default: - return -EOPNOTSUPP; - } -} - -static int an8855_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, AN8855_PHY_SELECT_PAGE); -} - -static int an8855_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page); -} - -static struct phy_driver an8855_driver[] = { -{ - PHY_ID_MATCH_EXACT(AN8855_PHY_ID), - .name = "Airoha AN8855 internal PHY", - /* PHY_GBIT_FEATURES */ - .flags = PHY_IS_INTERNAL, - .probe = an8855_probe, - .config_init = an8855_config_init, - .soft_reset = genphy_soft_reset, - .get_tunable = an8855_get_tunable, - .set_tunable = an8855_set_tunable, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = an8855_read_page, - .write_page = an8855_write_page, -}, }; - -module_phy_driver(an8855_driver); - -static const struct mdio_device_id __maybe_unused an8855_tbl[] = { - { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) }, - { } -}; - -MODULE_DEVICE_TABLE(mdio, an8855_tbl); - -MODULE_DESCRIPTION("Airoha AN8855 PHY driver"); -MODULE_AUTHOR("Christian Marangi "); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c b/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c deleted file mode 100644 index 7940453d6e..0000000000 --- a/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Airoha AN8855 Switch EFUSE Driver - */ - -#include -#include -#include -#include -#include - -#define AN8855_EFUSE_CELL 50 - -#define AN8855_EFUSE_DATA0 0x1000a500 -#define AN8855_EFUSE_R50O GENMASK(30, 24) - -static int an8855_efuse_read(void *context, unsigned int offset, - void *val, size_t bytes) -{ - struct regmap *regmap = context; - - return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset, - val, bytes / sizeof(u32)); -} - -static int an8855_efuse_probe(struct platform_device *pdev) -{ - struct nvmem_config an8855_nvmem_config = { - .name = "an8855-efuse", - .size = AN8855_EFUSE_CELL * sizeof(u32), - .stride = sizeof(u32), - .word_size = sizeof(u32), - .reg_read = an8855_efuse_read, - }; - struct device *dev = &pdev->dev; - struct nvmem_device *nvmem; - - /* Assign NVMEM priv to MFD regmap */ - an8855_nvmem_config.priv = dev_get_regmap(dev->parent, NULL); - an8855_nvmem_config.dev = dev; - nvmem = devm_nvmem_register(dev, &an8855_nvmem_config); - - return PTR_ERR_OR_ZERO(nvmem); -} - -static const struct of_device_id an8855_efuse_of_match[] = { - { .compatible = "airoha,an8855-efuse", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, an8855_efuse_of_match); - -static struct platform_driver an8855_efuse_driver = { - .probe = an8855_efuse_probe, - .driver = { - .name = "an8855-efuse", - .of_match_table = an8855_efuse_of_match, - }, -}; -module_platform_driver(an8855_efuse_driver); - -MODULE_AUTHOR("Christian Marangi "); -MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h b/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h deleted file mode 100644 index 56061566a0..0000000000 --- a/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * MFD driver for Airoha AN8855 Switch - */ -#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H -#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H - -#include - -/* MII Registers */ -#define AN8855_PHY_SELECT_PAGE 0x1f -#define AN8855_PHY_PAGE GENMASK(2, 0) -#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) -#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) -#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) - -/* MII Registers Page 4 */ -#define AN8855_PBUS_MODE 0x10 -#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 -#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) -#define AN8855_PBUS_WR_ADDR_HIGH 0x11 -#define AN8855_PBUS_WR_ADDR_LOW 0x12 -#define AN8855_PBUS_WR_DATA_HIGH 0x13 -#define AN8855_PBUS_WR_DATA_LOW 0x14 -#define AN8855_PBUS_RD_ADDR_HIGH 0x15 -#define AN8855_PBUS_RD_ADDR_LOW 0x16 -#define AN8855_PBUS_RD_DATA_HIGH 0x17 -#define AN8855_PBUS_RD_DATA_LOW 0x18 - -struct an8855_mfd_priv { - struct device *dev; - struct mii_bus *bus; - - unsigned int switch_addr; - u16 current_page; -}; - -int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, - u8 page); - -#endif diff --git a/target/linux/mediatek/filogic/config-6.12 b/target/linux/mediatek/filogic/config-6.12 deleted file mode 100644 index d319785ce5..0000000000 --- a/target/linux/mediatek/filogic/config-6.12 +++ /dev/null @@ -1,534 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AIROHA_EN8801SC_PHY=y -CONFIG_AIR_AN8855_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=10 -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PKEY_BITS=3 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_EXECMEM_LATE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PLATFORM_DEVICES=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_52 is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PMUV3=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_NOTIFIERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BUFFER_HEAD=y -CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2712 is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7981=y -CONFIG_COMMON_CLK_MT7981_ETHSYS=y -CONFIG_COMMON_CLK_MT7986=y -CONFIG_COMMON_CLK_MT7986_ETHSYS=y -CONFIG_COMMON_CLK_MT7987=y -CONFIG_COMMON_CLK_MT7988=y -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SM4=y -CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y -CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y -CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DEVFREQ_GOV_PASSIVE=y -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FUNCTION_ALIGNMENT=4 -CONFIG_FUNCTION_ALIGNMENT_4B=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_WATCHDOG=y -CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -# CONFIG_IDPF is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_LIB=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SMARTRG_LED=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LRU_GEN_WALKS_MMU=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_AN8855=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_2P5GE_PHY=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_GE_SOC_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_AIROHA_AN8855=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_MSTC_BOOT=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_NVMEM=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_VIRT_CONCAT=y -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_CPUX_TIMER=y -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_LVTS_THERMAL=y -CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y -CONFIG_MTK_NET_PHYLIB=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_REGULATOR_COUPLER=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SOCINFO is not set -CONFIG_MTK_SOC_THERMAL=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NET_AIROHA is not set -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_AN8855=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_INGRESS=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NET_XGRESS=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_AN8855_EFUSE=y -CONFIG_NVMEM_BLOCK=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_LAYOUT_ADTRAN=y -CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -# CONFIG_PCIE_MEDIATEK is not set -CONFIG_PCIE_MEDIATEK_GEN3=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PCS_MTK_USXGMII=y -CONFIG_PERF_EVENTS=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -CONFIG_PHY_MTK_XFI_TPHY=y -CONFIG_PHY_MTK_XSPHY=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -# CONFIG_PINCTRL_MT7622 is not set -CONFIG_PINCTRL_MT7981=y -CONFIG_PINCTRL_MT7986=y -CONFIG_PINCTRL_MT7987=y -CONFIG_PINCTRL_MT7988=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POLYNOMIAL=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_PHY_HWMON=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_REGULATOR_RT5190A=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_TI_SYSCON=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8261N_PHY=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPI_MTK_SNFI=y -CONFIG_SPLIT_PMD_PTLOCKS=y -CONFIG_SPLIT_PTE_PTLOCKS=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TEST_FPU is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UIMAGE_FIT_BLK=y -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_VDSO_GETRANDOM=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-6.12 b/target/linux/mediatek/mt7622/config-6.12 deleted file mode 100644 index 79b244e0f7..0000000000 --- a/target/linux/mediatek/mt7622/config-6.12 +++ /dev/null @@ -1,516 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -# CONFIG_AIROHA_EN8801SC_PHY is not set -# CONFIG_AIR_AN8855_PHY is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=10 -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PKEY_BITS=3 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_EXECMEM_LATE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PLATFORM_DEVICES=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_52 is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PMUV3=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_NOTIFIERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BUFFER_HEAD=y -CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7987 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SM4=y -CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y -CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y -CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DMADEVICES=y -CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FUNCTION_ALIGNMENT=4 -CONFIG_FUNCTION_ALIGNMENT_4B=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -# CONFIG_IDPF is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INTEL_XWAY_PHY=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_LIB=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LEDS_SMARTRG_LED=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LRU_GEN_WALKS_MMU=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_2P5GE_PHY is not set -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -# CONFIG_MFD_AIROHA_AN8855 is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_NVMEM=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_CPUX_TIMER=y -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_LVTS_THERMAL is not set -CONFIG_MTK_NET_PHYLIB=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_REGULATOR_COUPLER=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SOCINFO is not set -CONFIG_MTK_SOC_THERMAL=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NET_AIROHA is not set -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_INGRESS=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NET_XGRESS=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_BLOCK=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_LAYOUT_ADTRAN=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_EVENTS=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT7981 is not set -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT7987 is not set -# CONFIG_PINCTRL_MT7988 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POLYNOMIAL=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_PHY_HWMON=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TEST_FPU is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UIMAGE_FIT_BLK=y -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_VDSO_GETRANDOM=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.12 b/target/linux/mediatek/mt7623/config-6.12 deleted file mode 100644 index b803887f2d..0000000000 --- a/target/linux/mediatek/mt7623/config-6.12 +++ /dev/null @@ -1,525 +0,0 @@ -# CONFIG_AIO is not set -# CONFIG_AIROHA_EN8801SC_PHY is not set -# CONFIG_AIR_AN8855_PHY is not set -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PAN=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -CONFIG_BUFFER_HEAD=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKSRC_MMIO=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7987 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_GENIV=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_BRIDGE_CONNECTOR=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_DISPLAY_HDMI_HELPER=y -CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y -CONFIG_DRM_DISPLAY_HELPER=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_DMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -# CONFIG_DRM_MEDIATEK_DP is not set -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CORE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_DEVICE=y -CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y -CONFIG_FB_SYSMEM_FOPS=y -CONFIG_FB_SYSMEM_HELPERS=y -CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIXED_PHY=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FREEZER=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GRO_CELLS=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HID_SUPPORT=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CORE_SYNC=y -CONFIG_HOTPLUG_CORE_SYNC_DEAD=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_IOMMUFD is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_QCOM_LPG is not set -# CONFIG_LEDS_SMARTRG_LED is not set -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_MT6359_AUXADC is not set -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMORY=y -# CONFIG_MFD_AIROHA_AN8855 is not set -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_ECC_MEDIATEK is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_ADSP_MBOX is not set -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CPUX_TIMER=y -CONFIG_MTK_CQDMA=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -# CONFIG_MTK_LVTS_THERMAL is not set -CONFIG_MTK_MMSYS=y -CONFIG_MTK_NET_PHYLIB=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_REGULATOR_COUPLER=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SOCINFO is not set -CONFIG_MTK_SOC_THERMAL=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NEON=y -# CONFIG_NET_AIROHA is not set -CONFIG_NET_DEVLINK=y -CONFIG_NET_DEVMEM=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -# CONFIG_NVMEM_LAYOUT_ADTRAN is not set -CONFIG_NVMEM_MTK_EFUSE=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_IOMMU=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -CONFIG_PHY_MTK_HDMI=y -# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set -CONFIG_PHY_MTK_MIPI_DSI=y -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -# CONFIG_PINCTRL_MT6397 is not set -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PRINTK_TIME=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_RAS=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6331 is not set -# CONFIG_REGULATOR_MT6332 is not set -# CONFIG_REGULATOR_MT6357 is not set -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPLIT_PTE_PTLOCKS=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SPMI_MTK_PMIF is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UIMAGE_FIT_BLK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEO=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.12 b/target/linux/mediatek/mt7629/config-6.12 deleted file mode 100644 index 1f49214761..0000000000 --- a/target/linux/mediatek/mt7629/config-6.12 +++ /dev/null @@ -1,367 +0,0 @@ -# CONFIG_AIROHA_EN8801SC_PHY is not set -# CONFIG_AIR_AN8855_PHY is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_DEBUG_WX is not set -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PAN=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7987 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_OPS_HELPERS=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FUNCTION_ALIGNMENT=0 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CORE_SYNC=y -CONFIG_HOTPLUG_CORE_SYNC_DEAD=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -# CONFIG_IDPF is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -# CONFIG_LEDS_SMARTRG_LED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -# CONFIG_MFD_AIROHA_AN8855 is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_CPUX_TIMER=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_NET_PHYLIB=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_BPF_LINK=y -# CONFIG_NET_AIROHA is not set -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_INGRESS=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NET_XGRESS=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -# CONFIG_NVMEM_LAYOUT_ADTRAN is not set -CONFIG_NVMEM_LAYOUT_ASCII_ENV=y -# CONFIG_NVMEM_MTK_EFUSE is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch b/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch deleted file mode 100644 index 2dcdbcffe4..0000000000 --- a/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 17 Dec 2024 09:54:26 +0100 -Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE - -The MediaTek MT7988 SoC got some pins which only got configurable -pull-down but unlike previous designs there is no pull-up option. -Add new type MTK_PULL_PD_TYPE to support configuring such pins. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++--- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + - 2 files changed, 63 insertions(+), 11 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r - */ - static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) -+ u32 pullup, u32 arg, bool pd_only) - { - int err, pu, pd; - -@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st - pu = 0; - pd = 1; - } else { -- err = -EINVAL; -- goto out; -+ return -EINVAL; - } - -- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); -- if (err) -- goto out; -+ if (!pd_only) { -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); -+ if (err) -+ return err; -+ } - -- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+} -+ -+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, pd; -+ -+ if (arg != MTK_DISABLE && arg != MTK_ENABLE) -+ return -EINVAL; -+ -+ if (arg == MTK_DISABLE || pullup) -+ pd = 0; -+ else if (!pullup) -+ pd = 1; -+ -+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); - --out: -- return err; - } - - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, -@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs - return err; - } - -- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable); -+ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false); - } - - int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { -- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false); - if (!err) - return 0; - } -@@ -878,6 +900,29 @@ out: - return err; - } - -+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int err, pd; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; -+ -+ if (pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pd == 1) { -+ *pullup = 0; -+ *enable = MTK_ENABLE; -+ } else -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); - if (!err) ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -24,6 +24,7 @@ - * turned on/off itself. But it can't be selected pull up/down - */ - #define MTK_PULL_RSEL_TYPE BIT(3) -+#define MTK_PULL_PD_TYPE BIT(4) - /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by - * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. - */ diff --git a/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch b/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch deleted file mode 100644 index d94a0ba60b..0000000000 --- a/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch +++ /dev/null @@ -1,1610 +0,0 @@ -From 08bec851118226cc8c4397692542b855de2e0d73 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 17 Dec 2024 09:54:27 +0100 -Subject: [PATCH 2/2] pinctrl: mediatek: add MT7988 pinctrl driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add pinctrl driver for the MediaTek MT7988 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -[correctly initialise for the function_desc structure] -Signed-off-by: Arınç ÜNAL -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/20241217085435.9586-3-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 7 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++++++ - 3 files changed, 1564 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -187,6 +187,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c -@@ -0,0 +1,1556 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7988 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include "pinctrl-moore.h" -+ -+enum mt7988_pinctrl_reg_page { -+ GPIO_BASE, -+ IOCFG_TR_BASE, -+ IOCFG_BR_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { -+ PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { -+ PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { -+ PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { -+ PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { -+ PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), -+ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), -+ PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), -+ PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), -+ PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), -+ PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), -+ PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), -+ PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), -+ PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), -+ PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), -+ PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), -+ PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), -+ PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -+}; -+ -+static const unsigned int mt7988_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ -+ MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ -+ MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ -+ MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ -+ MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ -+ MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ -+ MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ -+ MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ -+ MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7988_pins[] = { -+ MT7988_PIN(0, "UART2_RXD"), -+ MT7988_PIN(1, "UART2_TXD"), -+ MT7988_PIN(2, "UART2_CTS"), -+ MT7988_PIN(3, "UART2_RTS"), -+ MT7988_PIN(4, "GPIO_A"), -+ MT7988_PIN(5, "SMI_0_MDC"), -+ MT7988_PIN(6, "SMI_0_MDIO"), -+ MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), -+ MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), -+ MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), -+ MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), -+ MT7988_PIN(11, "GPIO_P"), -+ MT7988_PIN(12, "WATCHDOG"), -+ MT7988_PIN(13, "GPIO_RESET"), -+ MT7988_PIN(14, "GPIO_WPS"), -+ MT7988_PIN(15, "PMIC_I2C_SCL"), -+ MT7988_PIN(16, "PMIC_I2C_SDA"), -+ MT7988_PIN(17, "I2C_1_SCL"), -+ MT7988_PIN(18, "I2C_1_SDA"), -+ MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), -+ MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), -+ MT7988_PIN(21, "PWMD1"), -+ MT7988_PIN(22, "SPI0_WP"), -+ MT7988_PIN(23, "SPI0_HOLD"), -+ MT7988_PIN(24, "SPI0_CSB"), -+ MT7988_PIN(25, "SPI0_MISO"), -+ MT7988_PIN(26, "SPI0_MOSI"), -+ MT7988_PIN(27, "SPI0_CLK"), -+ MT7988_PIN(28, "SPI1_CSB"), -+ MT7988_PIN(29, "SPI1_MISO"), -+ MT7988_PIN(30, "SPI1_MOSI"), -+ MT7988_PIN(31, "SPI1_CLK"), -+ MT7988_PIN(32, "SPI2_CLK"), -+ MT7988_PIN(33, "SPI2_MOSI"), -+ MT7988_PIN(34, "SPI2_MISO"), -+ MT7988_PIN(35, "SPI2_CSB"), -+ MT7988_PIN(36, "SPI2_HOLD"), -+ MT7988_PIN(37, "SPI2_WP"), -+ MT7988_PIN(38, "EMMC_RSTB"), -+ MT7988_PIN(39, "EMMC_DSL"), -+ MT7988_PIN(40, "EMMC_CK"), -+ MT7988_PIN(41, "EMMC_CMD"), -+ MT7988_PIN(42, "EMMC_DATA_7"), -+ MT7988_PIN(43, "EMMC_DATA_6"), -+ MT7988_PIN(44, "EMMC_DATA_5"), -+ MT7988_PIN(45, "EMMC_DATA_4"), -+ MT7988_PIN(46, "EMMC_DATA_3"), -+ MT7988_PIN(47, "EMMC_DATA_2"), -+ MT7988_PIN(48, "EMMC_DATA_1"), -+ MT7988_PIN(49, "EMMC_DATA_0"), -+ MT7988_PIN(50, "PCM_FS_I2S_LRCK"), -+ MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), -+ MT7988_PIN(52, "PCM_DRX_I2S_DIN"), -+ MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), -+ MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), -+ MT7988_PIN(55, "UART0_RXD"), -+ MT7988_PIN(56, "UART0_TXD"), -+ MT7988_PIN(57, "PWMD0"), -+ MT7988_PIN(58, "JTAG_JTDI"), -+ MT7988_PIN(59, "JTAG_JTDO"), -+ MT7988_PIN(60, "JTAG_JTMS"), -+ MT7988_PIN(61, "JTAG_JTCLK"), -+ MT7988_PIN(62, "JTAG_JTRST_N"), -+ MT7988_PIN(63, "USB_DRV_VBUS_P1"), -+ MT7988_PIN(64, "LED_A"), -+ MT7988_PIN(65, "LED_B"), -+ MT7988_PIN(66, "LED_C"), -+ MT7988_PIN(67, "LED_D"), -+ MT7988_PIN(68, "LED_E"), -+ MT7988_PIN(69, "GPIO_B"), -+ MT7988_PIN(70, "GPIO_C"), -+ MT7988_PIN(71, "I2C_2_SCL"), -+ MT7988_PIN(72, "I2C_2_SDA"), -+ MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), -+ MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), -+ MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), -+ MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), -+ MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), -+ MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), -+ MT7988_PIN(79, "USB_DRV_VBUS_P0"), -+ MT7988_PIN(80, "UART1_RXD"), -+ MT7988_PIN(81, "UART1_TXD"), -+ MT7988_PIN(82, "UART1_CTS"), -+ MT7988_PIN(83, "UART1_RTS"), -+}; -+ -+/* jtag */ -+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -+static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; -+ -+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -+static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -+static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* int_usxgmii */ -+static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; -+static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; -+ -+/* pwm */ -+static const int mt7988_pwm0_pins[] = { 57 }; -+static int mt7988_pwm0_funcs[] = { 1 }; -+ -+static const int mt7988_pwm1_pins[] = { 21 }; -+static int mt7988_pwm1_funcs[] = { 1 }; -+ -+static const int mt7988_pwm2_pins[] = { 80 }; -+static int mt7988_pwm2_funcs[] = { 2 }; -+ -+static const int mt7988_pwm2_0_pins[] = { 58 }; -+static int mt7988_pwm2_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm3_pins[] = { 81 }; -+static int mt7988_pwm3_funcs[] = { 2 }; -+ -+static const int mt7988_pwm3_0_pins[] = { 59 }; -+static int mt7988_pwm3_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm4_pins[] = { 82 }; -+static int mt7988_pwm4_funcs[] = { 2 }; -+ -+static const int mt7988_pwm4_0_pins[] = { 60 }; -+static int mt7988_pwm4_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm5_pins[] = { 83 }; -+static int mt7988_pwm5_funcs[] = { 2 }; -+ -+static const int mt7988_pwm5_0_pins[] = { 61 }; -+static int mt7988_pwm5_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm6_pins[] = { 69 }; -+static int mt7988_pwm6_funcs[] = { 3 }; -+ -+static const int mt7988_pwm6_0_pins[] = { 62 }; -+static int mt7988_pwm6_0_funcs[] = { 5 }; -+ -+static const int mt7988_pwm7_pins[] = { 70 }; -+static int mt7988_pwm7_funcs[] = { 3 }; -+ -+static const int mt7988_pwm7_0_pins[] = { 4 }; -+static int mt7988_pwm7_0_funcs[] = { 3 }; -+ -+/* dfd */ -+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -+static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* i2c */ -+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -+static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -+static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -+static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -+static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_0_pins[] = { 5, 6 }; -+static int mt7988_i2c0_0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -+static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; -+ -+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -+static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -+static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_1_pins[] = { 15, 16 }; -+static int mt7988_i2c0_1_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -+static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -+static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -+static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; -+ -+static const int mt7988_i2c1_0_pins[] = { 17, 18 }; -+static int mt7988_i2c1_0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -+static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -+static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -+static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; -+ -+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -+static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -+static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c1_2_pins[] = { 69, 70 }; -+static int mt7988_i2c1_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c2_0_pins[] = { 69, 70 }; -+static int mt7988_i2c2_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_i2c2_1_pins[] = { 71, 72 }; -+static int mt7988_i2c2_1_funcs[] = { 1, 1 }; -+ -+/* eth */ -+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -+static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -+static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -+static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -+static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; -+ -+/* pcie */ -+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -+static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -+static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -+static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -+static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -+static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; -+ -+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -+static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -+static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -+static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -+static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -+static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -+static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -+static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -+static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -+static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -+static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -+static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -+static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -+static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -+static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -+static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; -+ -+/* pmic */ -+static const int mt7988_pmic_pins[] = { 11 }; -+static int mt7988_pmic_funcs[] = { 1 }; -+ -+/* watchdog */ -+static const int mt7988_watchdog_pins[] = { 12 }; -+static int mt7988_watchdog_funcs[] = { 1 }; -+ -+/* spi */ -+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -+static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; -+ -+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -+static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -+static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -+static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; -+ -+/* flash */ -+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -+static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_emmc_45_pins[] = { -+ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -+}; -+static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -+static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, -+ 44, 45, 46, 47, 48, 49 }; -+static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* uart */ -+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -+static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -+static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -+static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -+static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -+static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -+static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -+static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -+static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -+static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -+static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart0_pins[] = { 55, 56 }; -+static int mt7988_uart0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -+static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -+static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -+static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -+static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -+static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_uart1_2_lite_pins[] = { 80, 81 }; -+static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; -+ -+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -+static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; -+ -+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -+static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -+static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -+static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; -+ -+/* udi */ -+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -+static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* i2s */ -+static const int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -+static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+/* pcm */ -+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -+static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; -+ -+/* led */ -+static const int mt7988_gbe0_led1_pins[] = { 58 }; -+static int mt7988_gbe0_led1_funcs[] = { 6 }; -+static const int mt7988_gbe1_led1_pins[] = { 59 }; -+static int mt7988_gbe1_led1_funcs[] = { 6 }; -+static const int mt7988_gbe2_led1_pins[] = { 60 }; -+static int mt7988_gbe2_led1_funcs[] = { 6 }; -+static const int mt7988_gbe3_led1_pins[] = { 61 }; -+static int mt7988_gbe3_led1_funcs[] = { 6 }; -+ -+static const int mt7988_2p5gbe_led1_pins[] = { 62 }; -+static int mt7988_2p5gbe_led1_funcs[] = { 6 }; -+ -+static const int mt7988_gbe0_led0_pins[] = { 64 }; -+static int mt7988_gbe0_led0_funcs[] = { 1 }; -+static const int mt7988_gbe1_led0_pins[] = { 65 }; -+static int mt7988_gbe1_led0_funcs[] = { 1 }; -+static const int mt7988_gbe2_led0_pins[] = { 66 }; -+static int mt7988_gbe2_led0_funcs[] = { 1 }; -+static const int mt7988_gbe3_led0_pins[] = { 67 }; -+static int mt7988_gbe3_led0_funcs[] = { 1 }; -+ -+static const int mt7988_2p5gbe_led0_pins[] = { 68 }; -+static int mt7988_2p5gbe_led0_funcs[] = { 1 }; -+ -+/* usb */ -+static const int mt7988_drv_vbus_p1_pins[] = { 63 }; -+static int mt7988_drv_vbus_p1_funcs[] = { 1 }; -+ -+static const int mt7988_drv_vbus_pins[] = { 79 }; -+static int mt7988_drv_vbus_funcs[] = { 1 }; -+ -+static const struct group_desc mt7988_groups[] = { -+ /* @GPIO(0,1,2,3): uart2 */ -+ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), -+ /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ -+ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), -+ /* @GPIO(2,3): int_usxgmii */ -+ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), -+ /* @GPIO(0,1,2,3,4): dfd */ -+ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), -+ /* @GPIO(0,1): xfi_phy0_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), -+ /* @GPIO(0,1): xfi_phy1_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), -+ /* @GPIO(3,4): xfi_phy_pll_i2c0 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), -+ /* @GPIO(3,4): xfi_phy_pll_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), -+ /* @GPIO(4): pwm7 */ -+ PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), -+ /* @GPIO(5,6) i2c0_0 */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), -+ /* @GPIO(5,6) i2c1_sfp */ -+ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), -+ /* @GPIO(5,6) xfi_pextp_phy0_i2c */ -+ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), -+ /* @GPIO(5,6) xfi_pextp_phy1_i2c */ -+ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), -+ /* @GPIO(5,6) mdc_mdio0 */ -+ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), -+ /* @GPIO(7): pcie_wake_n0_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), -+ /* @GPIO(8): pcie_clk_req_n0_0 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), -+ /* @GPIO(9): pcie_wake_n3_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), -+ /* @GPIO(10): pcie_clk_req_n3 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), -+ /* @GPIO(10): pcie_clk_req_n0_1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), -+ /* @GPIO(7,8) pcie_p0_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), -+ /* @GPIO(7,8) pcie_p1_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), -+ /* @GPIO(7,8) pcie_p2_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), -+ /* @GPIO(9,10) pcie_p3_phy_i2c */ -+ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), -+ /* @GPIO(9,10) ckm_phy_i2c */ -+ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), -+ /* @GPIO(11): pmic */ -+ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), -+ /* @GPIO(12): watchdog */ -+ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), -+ /* @GPIO(13): pcie_wake_n0_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), -+ /* @GPIO(14): pcie_wake_n3_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), -+ /* @GPIO(15,16) i2c0_1 */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), -+ /* @GPIO(15,16) u30_phy_i2c0 */ -+ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), -+ /* @GPIO(15,16) u32_phy_i2c0 */ -+ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), -+ /* @GPIO(15,16) xfi_phy0_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), -+ /* @GPIO(15,16) xfi_phy1_i2c1 */ -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), -+ /* @GPIO(15,16) xfi_phy_pll_i2c2 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), -+ /* @GPIO(17,18) i2c1_0 */ -+ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), -+ /* @GPIO(17,18) u30_phy_i2c1 */ -+ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), -+ /* @GPIO(17,18) u32_phy_i2c1 */ -+ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), -+ /* @GPIO(17,18) xfi_phy_pll_i2c3 */ -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), -+ /* @GPIO(17,18) sgmii0_i2c */ -+ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), -+ /* @GPIO(17,18) sgmii1_i2c */ -+ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), -+ /* @GPIO(19): pcie_2l_0_pereset */ -+ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), -+ /* @GPIO(20): pcie_1l_1_pereset */ -+ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), -+ /* @GPIO(21): pwm1 */ -+ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), -+ /* @GPIO(22,23) spi0_wp_hold */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), -+ /* @GPIO(24,25,26,27) spi0 */ -+ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), -+ /* @GPIO(28,29,30,31) spi1 */ -+ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), -+ /* @GPIO(32,33,34,35) spi2 */ -+ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), -+ /* @GPIO(36,37) spi2_wp_hold */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), -+ /* @GPIO(22,23,24,25,26,27) snfi */ -+ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), -+ /* @GPIO(22,23) tops_uart0_0 */ -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), -+ /* @GPIO(28,29,30,31) uart2_0 */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), -+ /* @GPIO(32,33,34,35) uart1_0 */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), -+ /* @GPIO(32,33,34,35) uart2_1 */ -+ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), -+ /* @GPIO(28) net_wo0_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ /* @GPIO(29) net_wo1_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ /* @GPIO(30) net_wo2_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ /* @GPIO(28,29) tops_uart1_0 */ -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), -+ /* @GPIO(30,31) tops_uart0_1 */ -+ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), -+ /* @GPIO(36,37) tops_uart1_1 */ -+ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), -+ /* @GPIO(32,33,34,35,36) udi */ -+ PINCTRL_PIN_GROUP("udi", mt7988_udi), -+ /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), -+ /* @GPIO(32,33,34,35,36,37) sdcard */ -+ PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), -+ /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ -+ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), -+ /* @GPIO(28,29) 2p5g_ext_mdio */ -+ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), -+ /* @GPIO(30,31) gbe_ext_mdio */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), -+ /* @GPIO(50,51,52,53,54) i2s */ -+ PINCTRL_PIN_GROUP("i2s", mt7988_i2s), -+ /* @GPIO(50,51,52,53) pcm */ -+ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), -+ /* @GPIO(55,56) uart0 */ -+ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), -+ /* @GPIO(55,56) tops_uart0_2 */ -+ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), -+ /* @GPIO(50,51,52,53) uart2_2 */ -+ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), -+ /* @GPIO(50,51,52,53,54) wo0_jtag */ -+ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), -+ /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ -+ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), -+ /* @GPIO(50,51,52,53,54) wo2_jtag */ -+ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), -+ /* @GPIO(57) pwm0 */ -+ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), -+ /* @GPIO(58) pwm2_0 */ -+ PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), -+ /* @GPIO(59) pwm3_0 */ -+ PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), -+ /* @GPIO(60) pwm4_0 */ -+ PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), -+ /* @GPIO(61) pwm5_0 */ -+ PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), -+ /* @GPIO(58,59,60,61,62) jtag */ -+ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), -+ /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ -+ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), -+ /* @GPIO(58,59,60,61) uart2_3 */ -+ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), -+ /* @GPIO(58,59,60,61) uart1_1 */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), -+ /* @GPIO(58,59,60,61) gbe_led1 */ -+ PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), -+ PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), -+ PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), -+ PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), -+ /* @GPIO(62) pwm6_0 */ -+ PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), -+ /* @GPIO(62) 2p5gbe_led1 */ -+ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), -+ /* @GPIO(64,65,66,67) gbe_led0 */ -+ PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), -+ PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), -+ PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), -+ PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), -+ /* @GPIO(68) 2p5gbe_led0 */ -+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), -+ /* @GPIO(63) drv_vbus_p1 */ -+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), -+ /* @GPIO(63) pcie_clk_req_n2_1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), -+ /* @GPIO(69, 70) mdc_mdio1 */ -+ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), -+ /* @GPIO(69, 70) i2c1_2 */ -+ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), -+ /* @GPIO(69) pwm6 */ -+ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), -+ /* @GPIO(70) pwm7 */ -+ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), -+ /* @GPIO(69,70) i2c2_0 */ -+ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), -+ /* @GPIO(71,72) i2c2_1 */ -+ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), -+ /* @GPIO(73) pcie_2l_1_pereset */ -+ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), -+ /* @GPIO(74) pcie_1l_0_pereset */ -+ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), -+ /* @GPIO(75) pcie_wake_n1_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), -+ /* @GPIO(76) pcie_clk_req_n1 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), -+ /* @GPIO(77) pcie_wake_n2_0 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), -+ /* @GPIO(78) pcie_clk_req_n2_0 */ -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), -+ /* @GPIO(79) drv_vbus */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), -+ /* @GPIO(79) pcie_wake_n2_1 */ -+ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), -+ /* @GPIO(80,81,82,83) uart1_2 */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), -+ /* @GPIO(80,81) uart1_2_lite */ -+ PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), -+ /* @GPIO(80) pwm2 */ -+ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), -+ /* @GPIO(81) pwm3 */ -+ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), -+ /* @GPIO(82) pwm4 */ -+ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), -+ /* @GPIO(83) pwm5 */ -+ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), -+ /* @GPIO(80) net_wo0_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ /* @GPIO(81) net_wo1_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ /* @GPIO(82) net_wo2_uart_txd_0 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ /* @GPIO(80,81) tops_uart1_2 */ -+ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), -+ /* @GPIO(80) net_wo0_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), -+ /* @GPIO(81) net_wo1_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), -+ /* @GPIO(82) net_wo2_uart_txd_1 */ -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char * const mt7988_jtag_groups[] = { -+ "tops_jtag0_0", "wo0_jtag", "wo1_jtag", -+ "wo2_jtag", "jtag", "tops_jtag0_1", -+}; -+static const char * const mt7988_int_usxgmii_groups[] = { -+ "int_usxgmii", -+}; -+static const char * const mt7988_pwm_groups[] = { -+ "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", -+ "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", -+ -+}; -+static const char * const mt7988_dfd_groups[] = { -+ "dfd", -+}; -+static const char * const mt7988_i2c_groups[] = { -+ "xfi_phy0_i2c0", -+ "xfi_phy1_i2c0", -+ "xfi_phy_pll_i2c0", -+ "xfi_phy_pll_i2c1", -+ "i2c0_0", -+ "i2c1_sfp", -+ "xfi_pextp_phy0_i2c", -+ "xfi_pextp_phy1_i2c", -+ "i2c0_1", -+ "u30_phy_i2c0", -+ "u32_phy_i2c0", -+ "xfi_phy0_i2c1", -+ "xfi_phy1_i2c1", -+ "xfi_phy_pll_i2c2", -+ "i2c1_0", -+ "u30_phy_i2c1", -+ "u32_phy_i2c1", -+ "xfi_phy_pll_i2c3", -+ "sgmii0_i2c", -+ "sgmii1_i2c", -+ "i2c1_2", -+ "i2c2_0", -+ "i2c2_1", -+}; -+static const char * const mt7988_ethernet_groups[] = { -+ "mdc_mdio0", -+ "2p5g_ext_mdio", -+ "gbe_ext_mdio", -+ "mdc_mdio1", -+}; -+static const char * const mt7988_pcie_groups[] = { -+ "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", -+ "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", -+ "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", -+ "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", -+ "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", -+ "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", -+ "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", -+ "pcie_clk_req_n0_1" -+}; -+static const char * const mt7988_pmic_groups[] = { -+ "pmic", -+}; -+static const char * const mt7988_wdt_groups[] = { -+ "watchdog", -+}; -+static const char * const mt7988_spi_groups[] = { -+ "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -+}; -+static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", -+ "emmc_51" }; -+static const char * const mt7988_uart_groups[] = { -+ "uart2", -+ "tops_uart0_0", -+ "uart2_0", -+ "uart1_0", -+ "uart2_1", -+ "net_wo0_uart_txd_0", -+ "net_wo1_uart_txd_0", -+ "net_wo2_uart_txd_0", -+ "tops_uart1_0", -+ "ops_uart0_1", -+ "ops_uart1_1", -+ "uart0", -+ "tops_uart0_2", -+ "uart1_1", -+ "uart2_3", -+ "uart1_2", -+ "uart1_2_lite", -+ "tops_uart1_2", -+ "net_wo0_uart_txd_1", -+ "net_wo1_uart_txd_1", -+ "net_wo2_uart_txd_1", -+}; -+static const char * const mt7988_udi_groups[] = { -+ "udi", -+}; -+static const char * const mt7988_audio_groups[] = { -+ "i2s", "pcm", -+}; -+static const char * const mt7988_led_groups[] = { -+ "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", -+ "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", -+ "wf5g_led0", "wf5g_led1", -+}; -+static const char * const mt7988_usb_groups[] = { -+ "drv_vbus", -+ "drv_vbus_p1", -+}; -+ -+static const struct function_desc mt7988_functions[] = { -+ { { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, -+ NULL }, -+ { { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, -+ NULL }, -+ { { "int_usxgmii", mt7988_int_usxgmii_groups, -+ ARRAY_SIZE(mt7988_int_usxgmii_groups) }, -+ NULL }, -+ { { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, NULL }, -+ { { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, NULL }, -+ { { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, NULL }, -+ { { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, -+ NULL }, -+ { { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, -+ NULL }, -+ { { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, -+ NULL }, -+ { { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, -+ NULL }, -+ { { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, NULL }, -+ { { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, -+ NULL }, -+ { { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, -+ NULL }, -+ { { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, NULL }, -+ { { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, NULL }, -+ { { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, NULL }, -+}; -+ -+static const struct mtk_eint_hw mt7988_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7988_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7988_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_tr", "iocfg_br", -+ "iocfg_rb", "iocfg_lb", "iocfg_tl", -+}; -+ -+static const struct mtk_pin_soc mt7988_data = { -+ .reg_cal = mt7988_reg_cals, -+ .pins = mt7988_pins, -+ .npins = ARRAY_SIZE(mt7988_pins), -+ .grps = mt7988_groups, -+ .ngrps = ARRAY_SIZE(mt7988_groups), -+ .funcs = mt7988_functions, -+ .nfuncs = ARRAY_SIZE(mt7988_functions), -+ .eint_hw = &mt7988_eint_hw, -+ .gpio_m = 0, -+ .ies_present = false, -+ .base_names = mt7988_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, -+ .pull_type = mt7988_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7988_pinctrl_of_match[] = { -+ { .compatible = "mediatek,mt7988-pinctrl" }, -+ {} -+}; -+ -+static int mt7988_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -+} -+ -+static struct platform_driver mt7988_pinctrl_driver = { -+ .driver = { -+ .name = "mt7988-pinctrl", -+ .of_match_table = mt7988_pinctrl_of_match, -+ }, -+ .probe = mt7988_pinctrl_probe, -+}; -+ -+static int __init mt7988_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7988_pinctrl_driver); -+} -+arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch b/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch deleted file mode 100644 index e615e39345..0000000000 --- a/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 8 Jan 2025 22:52:44 +0100 -Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() - -This function is unused and causing compile errors, delete it. - -Reported-by: Stephen Rothwell -Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/ -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------ - 1 file changed, 18 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); - } - --static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -- const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) --{ -- int err, pd; -- -- if (arg != MTK_DISABLE && arg != MTK_ENABLE) -- return -EINVAL; -- -- if (arg == MTK_DISABLE || pullup) -- pd = 0; -- else if (!pullup) -- pd = 1; -- -- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -- --} -- - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 pullup, u32 arg) diff --git a/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch b/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch deleted file mode 100644 index 2c0afbe01c..0000000000 --- a/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 5 Jun 2024 10:54:33 +0200 -Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 has three on-SoC UART controllers that support M16C450 and -M16550A modes. - -Signed-off-by: Rafał Miłecki -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com -Signed-off-by: Matthias Brugger -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++- - 1 file changed, 34 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -86,7 +86,7 @@ - #clock-cells = <1>; - }; - -- clock-controller@1001b000 { -+ topckgen: clock-controller@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; -@@ -124,6 +124,39 @@ - status = "disabled"; - }; - -+ serial@11000000 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000000 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART0_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ -+ serial@11000100 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000100 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART1_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ -+ serial@11000200 { -+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; -+ reg = <0 0x11000200 0 0x100>; -+ interrupts = ; -+ interrupt-names = "uart", "wakeup"; -+ clocks = <&topckgen CLK_TOP_UART_SEL>, -+ <&infracfg CLK_INFRA_52M_UART2_CK>; -+ clock-names = "baud", "bus"; -+ status = "disabled"; -+ }; -+ - i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, diff --git a/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch b/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch deleted file mode 100644 index bf4e7a3b63..0000000000 --- a/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 13 Jun 2024 21:59:33 +0200 -Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration -data. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com -Signed-off-by: Matthias Brugger -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -234,6 +234,13 @@ - #clock-cells = <1>; - }; - -+ efuse@11f50000 { -+ compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; -+ reg = <0 0x11f50000 0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ - clock-controller@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch b/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch deleted file mode 100644 index 90ec3186eb..0000000000 --- a/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch +++ /dev/null @@ -1,85 +0,0 @@ -From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 09:54:29 +0100 -Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support - -Add mt7988a pinctrl node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -3,6 +3,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -105,6 +106,59 @@ - #clock-cells = <1>; - }; - -+ pio: pinctrl@1001f000 { -+ compatible = "mediatek,mt7988-pinctrl"; -+ reg = <0 0x1001f000 0 0x1000>, -+ <0 0x11c10000 0 0x1000>, -+ <0 0x11d00000 0 0x1000>, -+ <0 0x11d20000 0 0x1000>, -+ <0 0x11e00000 0 0x1000>, -+ <0 0x11f00000 0 0x1000>, -+ <0 0x1000b000 0 0x1000>; -+ reg-names = "gpio", "iocfg_tr", -+ "iocfg_br", "iocfg_rb", -+ "iocfg_lb", "iocfg_tl", "eint"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&pio 0 0 84>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <2>; -+ -+ pcie0_pins: pcie0-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -+ "pcie_wake_n0_0"; -+ }; -+ }; -+ -+ pcie1_pins: pcie1-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -+ "pcie_wake_n1_0"; -+ }; -+ }; -+ -+ pcie2_pins: pcie2-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -+ "pcie_wake_n2_0"; -+ }; -+ }; -+ -+ pcie3_pins: pcie3-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -+ "pcie_wake_n3_0"; -+ }; -+ }; -+ }; -+ - pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch b/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch deleted file mode 100644 index 043530c994..0000000000 --- a/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:15 +0100 -Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory - -Add memory range handled by ATF to not be touched by linux kernel. -ATF is SoC specific and not board-specific so add it to mt7988.dtsi. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -62,6 +62,18 @@ - method = "smc"; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ -+ secmon@43000000 { -+ reg = <0 0x43000000 0 0x50000>; -+ no-map; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - ranges; diff --git a/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch b/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch deleted file mode 100644 index a52f443d83..0000000000 --- a/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch +++ /dev/null @@ -1,52 +0,0 @@ -From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:16 +0100 -Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support - -Add devicetree node for MMC controller. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -112,7 +112,7 @@ - #reset-cells = <1>; - }; - -- clock-controller@1001e000 { -+ apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; -@@ -293,6 +293,25 @@ - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; - }; - -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7988-mmc"; -+ reg = <0 0x11230000 0 0x1000>, -+ <0 0x11D60000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_MSDC400>, -+ <&infracfg CLK_INFRA_MSDC2_HCK>, -+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, -+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; -+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, -+ <&topckgen CLK_TOP_EMMC_400M_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, -+ <&apmixedsys CLK_APMIXED_MSDCPLL>; -+ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch b/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch deleted file mode 100644 index b878d20f2e..0000000000 --- a/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch +++ /dev/null @@ -1,62 +0,0 @@ -From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:17 +0100 -Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node - -Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -4,6 +4,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -97,6 +98,7 @@ - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; -+ #reset-cells = <1>; - }; - - topckgen: clock-controller@1001b000 { -@@ -265,6 +267,17 @@ - status = "disabled"; - }; - -+ lvts: lvts@1100a000 { -+ compatible = "mediatek,mt7988-lvts-ap"; -+ #thermal-sensor-cells = <1>; -+ reg = <0 0x1100a000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; -+ interrupts = ; -+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; -+ nvmem-cells = <&lvts_calibration>; -+ nvmem-cell-names = "lvts-calib-data-1"; -+ }; -+ - usb@11190000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, -@@ -324,6 +337,10 @@ - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ lvts_calibration: calib@918 { -+ reg = <0x918 0x28>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch b/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch deleted file mode 100644 index e0ff078164..0000000000 --- a/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:18 +0100 -Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone - -Add basic thermal-zone node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -358,6 +358,21 @@ - }; - }; - -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&lvts 0>; -+ trips { -+ cpu_trip_crit: crit { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; diff --git a/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch b/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch deleted file mode 100644 index 551dca3c09..0000000000 --- a/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:20 +0100 -Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu - -In preparation for adding support for CPU DVFS and clock tables for it, -add the MCUSYS clock controller node. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -192,6 +192,12 @@ - status = "disabled"; - }; - -+ mcusys: mcusys@100e0000 { -+ compatible = "mediatek,mt7988-mcusys", "syscon"; -+ reg = <0 0x100e0000 0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ - serial@11000000 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; diff --git a/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch b/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch deleted file mode 100644 index e2bec750e4..0000000000 --- a/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch +++ /dev/null @@ -1,84 +0,0 @@ -From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:21 +0100 -Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for - clock scaling - -Add operating points defining frequency/voltages of cpu cores. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -21,6 +21,10 @@ - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@1 { -@@ -28,6 +32,10 @@ - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@2 { -@@ -35,6 +43,10 @@ - reg = <0x2>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; - }; - - cpu@3 { -@@ -42,6 +54,32 @@ - reg = <0x3>; - device_type = "cpu"; - enable-method = "psci"; -+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cpu", "intermediate"; -+ operating-points-v2 = <&cluster0_opp>; -+ }; -+ -+ cluster0_opp: opp-table-0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1100000000 { -+ opp-hz = /bits/ 64 <1100000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <900000>; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch b/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch deleted file mode 100644 index f65d23bc0a..0000000000 --- a/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:22 +0100 -Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers - by default - -The controllers should be enabled at board level if used. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -334,6 +334,7 @@ - <&infracfg CLK_INFRA_133M_USB_HCK>, - <&infracfg CLK_INFRA_USB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ status = "disabled"; - }; - - usb@11200000 { -@@ -348,6 +349,7 @@ - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ status = "disabled"; - }; - - mmc0: mmc@11230000 { diff --git a/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch b/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch deleted file mode 100644 index c53db06c39..0000000000 --- a/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:23 +0100 -Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1 - -USB controller needs phys for working properly. -On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy. -For now add the t-phy for ssusb1. We can reuse the mt7986 compatible -here. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -349,6 +349,8 @@ - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ phys = <&tphyu2port0 PHY_TYPE_USB2>, -+ <&tphyu3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - -@@ -371,6 +373,29 @@ - status = "disabled"; - }; - -+ t-phy@11c50000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ tphyu2port0: usb-phy@11c50000 { -+ reg = <0 0x11c50000 0 0x700>; -+ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ tphyu3port0: usb-phy@11c50700 { -+ reg = <0 0x11c50700 0 0x900>; -+ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch b/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch deleted file mode 100644 index fe27e5223c..0000000000 --- a/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch +++ /dev/null @@ -1,176 +0,0 @@ -From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:24 +0100 -Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes - -Add pcie controllers for mt7988. Reuse mt7986 compatible. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++ - 1 file changed, 152 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -373,6 +373,158 @@ - status = "disabled"; - }; - -+ pcie@11280000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11280000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <3>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x20000000 0x00 -+ 0x20000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x20200000 0x00 -+ 0x20200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc2 0>, -+ <0 0 0 2 &pcie_intc2 1>, -+ <0 0 0 3 &pcie_intc2 2>, -+ <0 0 0 4 &pcie_intc2 3>; -+ pcie_intc2: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11290000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11290000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <2>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x28000000 0x00 -+ 0x28000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x28200000 0x00 -+ 0x28200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc3 0>, -+ <0 0 0 2 &pcie_intc3 1>, -+ <0 0 0 3 &pcie_intc3 2>, -+ <0 0 0 4 &pcie_intc3 3>; -+ pcie_intc3: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11300000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11300000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <0>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x30000000 0x00 -+ 0x30000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x30200000 0x00 -+ 0x30200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie@11310000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11310000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <1>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0x00 0x38000000 0x00 -+ 0x38000000 0x00 0x00200000>, -+ <0x82000000 0x00 0x38200000 0x00 -+ 0x38200000 0x00 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ - t-phy@11c50000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch b/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch deleted file mode 100644 index 6f0080e6ec..0000000000 --- a/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 09:54:30 +0100 -Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl - subnodes for bpi-r4 - -Add board specific pinctrl configurations on Bananapi R4. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ - 1 file changed, 189 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -9,3 +9,192 @@ - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; - }; -+ -+&pio { -+ mdio0_pins: mdio0-pins { -+ mux { -+ function = "eth"; -+ groups = "mdc_mdio0"; -+ }; -+ -+ conf { -+ pins = "SMI_0_MDC", "SMI_0_MDIO"; -+ drive-strength = <8>; -+ }; -+ }; -+ -+ i2c0_pins: i2c0-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c0_1"; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ i2c1_sfp_pins: i2c1-sfp-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_sfp"; -+ }; -+ }; -+ -+ i2c2_0_pins: i2c2-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_0"; -+ }; -+ }; -+ -+ i2c2_1_pins: i2c2-g1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_1"; -+ }; -+ }; -+ -+ gbe0_led0_pins: gbe0-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led0"; -+ }; -+ }; -+ -+ gbe1_led0_pins: gbe1-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led0"; -+ }; -+ }; -+ -+ gbe2_led0_pins: gbe2-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led0"; -+ }; -+ }; -+ -+ gbe3_led0_pins: gbe3-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led0"; -+ }; -+ }; -+ -+ gbe0_led1_pins: gbe0-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led1"; -+ }; -+ }; -+ -+ gbe1_led1_pins: gbe1-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led1"; -+ }; -+ }; -+ -+ gbe2_led1_pins: gbe2-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led1"; -+ }; -+ }; -+ -+ gbe3_led1_pins: gbe3-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led1"; -+ }; -+ }; -+ -+ i2p5gbe_led0_pins: 2p5gbe-led0-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led0"; -+ }; -+ }; -+ -+ i2p5gbe_led1_pins: 2p5gbe-led1-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led1"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_45: mmc0-emmc-45-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_51: mmc0-emmc-51-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ }; -+ -+ mmc0_pins_sdcard: mmc0-sdcard-pins { -+ mux { -+ function = "flash"; -+ groups = "sdcard"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2"; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch b/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch deleted file mode 100644 index 2ce47ed12a..0000000000 --- a/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:25 +0100 -Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog - -Enable the watchdog on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -198,3 +198,7 @@ - }; - }; - }; -+ -+&watchdog { -+ status = "okay"; -+}; diff --git a/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch b/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch deleted file mode 100644 index fb383d041b..0000000000 --- a/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:26 +0100 -Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed - regulators for 1v8 and 3v3 - -Add regulator nodes used for mmc to Bananapi R4 board. -This board has 1 MMC controller used for SDMMC and eMMC where only one can -be used at one time, selected by hardware switches. SD uses 3v3 for both -supplies and emmc uses both regulators. -So defining both regulators in board dts and referencing them in the dt -overlay. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -8,6 +8,24 @@ - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; - }; - - &pio { diff --git a/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch b/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch deleted file mode 100644 index 3273e7444c..0000000000 --- a/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:28 +0100 -Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal - configuration - -Add additional thermal trips to Bananapi R4 board. -SoC only contains the critical trip. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -28,6 +28,34 @@ - }; - }; - -+&cpu_thermal { -+ trips { -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_med: active-med { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { diff --git a/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch b/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch deleted file mode 100644 index c1d872d1db..0000000000 --- a/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch +++ /dev/null @@ -1,41 +0,0 @@ -From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:29 +0100 -Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0 - debug uart - -Enable the debug uart on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -245,6 +245,10 @@ - }; - }; - -+&serial0 { -+ status = "okay"; -+}; -+ - &watchdog { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -236,7 +236,7 @@ - #clock-cells = <1>; - }; - -- serial@11000000 { -+ serial0: serial@11000000 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch b/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch deleted file mode 100644 index d75b3e57ad..0000000000 --- a/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:30 +0100 -Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART - stdout - -Add chosen node on Bananapi R4 board with stdout and default bootargs. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -9,6 +9,10 @@ - model = "Banana Pi BPI-R4"; - chassis-type = "embedded"; - -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; diff --git a/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch b/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch deleted file mode 100644 index 4f48edd412..0000000000 --- a/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:31 +0100 -Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C - controllers - -Enable the I2C0, I2C2 controllers found on the BananaPi R4 board. -Both controllers are not accessible from user and having fixed spare -devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer -for e.g. SFP cages. -The missing I2C1 is connected to GPIO header which can have either GPIO -mode or I2C mode. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++--- - 2 files changed, 15 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -60,6 +60,18 @@ - }; - }; - -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_1_pins>; -+ status = "okay"; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -269,7 +269,7 @@ - status = "disabled"; - }; - -- i2c@11003000 { -+ i2c0: i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; -@@ -283,7 +283,7 @@ - status = "disabled"; - }; - -- i2c@11004000 { -+ i2c1: i2c@11004000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; -@@ -297,7 +297,7 @@ - status = "disabled"; - }; - -- i2c@11005000 { -+ i2c2: i2c@11005000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; diff --git a/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch b/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch deleted file mode 100644 index 117479b789..0000000000 --- a/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch +++ /dev/null @@ -1,74 +0,0 @@ -From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:32 +0100 -Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C - Mux - -Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom. -Add its node to the right i2c controller. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -2,6 +2,8 @@ - - /dts-v1/; - -+#include -+ - #include "mt7988a.dtsi" - - / { -@@ -70,6 +72,45 @@ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1_pins>; - status = "okay"; -+ -+ pca9545: i2c-mux@70 { -+ compatible = "nxp,pca9545"; -+ reg = <0x70>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ pcf8563: rtc@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c02"; -+ reg = <0x57>; -+ size = <256>; -+ }; -+ -+ }; -+ -+ i2c_sfp1: i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ i2c_sfp2: i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ }; -+ }; - }; - - &pio { diff --git a/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch b/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch deleted file mode 100644 index e16b30ef30..0000000000 --- a/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch +++ /dev/null @@ -1,41 +0,0 @@ -From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:33 +0100 -Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for - ssusb1 - -Bananapi R4 uses t-phy for usb. Enable its node at board level. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -306,6 +306,10 @@ - status = "okay"; - }; - -+&tphy { -+ status = "okay"; -+}; -+ - &watchdog { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -525,7 +525,7 @@ - }; - }; - -- t-phy@11c50000 { -+ tphy: t-phy@11c50000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch b/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch deleted file mode 100644 index d1892c6cc1..0000000000 --- a/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 2b03ef47273db52e0c0010e963c3626e6842204f Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:34 +0100 -Subject: [PATCH 22/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable ssusb1 on - bpi-r4 - -Enable usb on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-21-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -306,6 +306,10 @@ - status = "okay"; - }; - -+&ssusb1 { -+ status = "okay"; -+}; -+ - &tphy { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -337,7 +337,7 @@ - status = "disabled"; - }; - -- usb@11200000 { -+ ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; diff --git a/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch b/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch deleted file mode 100644 index 4e24607e5d..0000000000 --- a/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b074487a4180aeee440b61fc00a865fc2a4bd32a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:35 +0100 -Subject: [PATCH 23/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pwm - -Enable pwm on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-22-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -302,6 +302,10 @@ - }; - }; - -+&pwm { -+ status = "okay"; -+}; -+ - &serial0 { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -211,7 +211,7 @@ - }; - }; - -- pwm@10048000 { -+ pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, diff --git a/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch b/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch deleted file mode 100644 index a25d235630..0000000000 --- a/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 72bc814e8609e8be59dff8bc6e0e185b5005ace8 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 17 Dec 2024 10:12:36 +0100 -Subject: [PATCH 24/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pcie - -Enable the pci controllers on BPI-R4. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241217091238.16032-23-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 20 +++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- - 2 files changed, 24 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -113,6 +113,26 @@ - }; - }; - -+/* mPCIe SIM2 */ -+&pcie0 { -+ status = "okay"; -+}; -+ -+/* mPCIe SIM3 */ -+&pcie1 { -+ status = "okay"; -+}; -+ -+/* M.2 key-B SIM1 */ -+&pcie2 { -+ status = "okay"; -+}; -+ -+/* M.2 key-M SSD */ -+&pcie3 { -+ status = "okay"; -+}; -+ - &pio { - mdio0_pins: mdio0-pins { - mux { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -373,7 +373,7 @@ - status = "disabled"; - }; - -- pcie@11280000 { -+ pcie2: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -411,7 +411,7 @@ - }; - }; - -- pcie@11290000 { -+ pcie3: pcie@11290000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -449,7 +449,7 @@ - }; - }; - -- pcie@11300000 { -+ pcie0: pcie@11300000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; -@@ -487,7 +487,7 @@ - }; - }; - -- pcie@11310000 { -+ pcie1: pcie@11310000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; diff --git a/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch b/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch deleted file mode 100644 index 26a5990b60..0000000000 --- a/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 84087157052afba2f61cea7c99ccabfe9681b643 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 20 Dec 2024 17:38:35 +0100 -Subject: [PATCH 25/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add MediaTek - MT6682A/RT5190A PMIC - -Bananapi R4 Board contains a MT6682A pmic which is compatible to rt5190a. -Add its node to the i2 controller. - -The BananaPi R4 board has a MediaTek MT6682A PMIC, a rebrand of the -Richtek RT5190A chip, connected to the I2C0 bus. - -Add the relevant node and, while at it, also configure the regulators -from this PMIC that are used on this board. - -Only Buck2/Buck3 voltage can be controlled by software. - -BUCK4 input is 5V from BUCK1 output, and the resistor (mapped to RP30/RP31 -on BPI-R4) configures BUCK4 output to 1.8V. -LDO input is 3.3V from 3.3VD, and the resistor (mapped to RP38/RP40 on -BPI-R4) configures LDO output to 1.8V. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241220163838.114786-2-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 50 +++++++++++++++++++ - 1 file changed, 50 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -3,6 +3,7 @@ - /dts-v1/; - - #include -+#include - - #include "mt7988a.dtsi" - -@@ -66,6 +67,55 @@ - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -+ -+ rt5190a_64: rt5190a@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ buck2 { -+ regulator-name = "vcore"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ rt5190_buck3: buck3 { -+ regulator-name = "vproc"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; - }; - - &i2c2 { diff --git a/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch deleted file mode 100644 index c605e90e5d..0000000000 --- a/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch +++ /dev/null @@ -1,80 +0,0 @@ -From c0a17ddd90c2094dfe4610b0d965db8a3b987e32 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 20 Dec 2024 17:38:36 +0100 -Subject: [PATCH 26/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add proc-supply - for cpus - -Add proc-supply property to cpus on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20241220163838.114786-3-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 16 ++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- - 2 files changed, 20 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -35,6 +35,22 @@ - }; - }; - -+&cpu0 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu1 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu2 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu3 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &cpu_thermal { - trips { - cpu_trip_hot: hot { ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -16,7 +16,7 @@ - #address-cells = <1>; - #size-cells = <0>; - -- cpu@0 { -+ cpu0: cpu@0 { - compatible = "arm,cortex-a73"; - reg = <0x0>; - device_type = "cpu"; -@@ -27,7 +27,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@1 { -+ cpu1: cpu@1 { - compatible = "arm,cortex-a73"; - reg = <0x1>; - device_type = "cpu"; -@@ -38,7 +38,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@2 { -+ cpu2: cpu@2 { - compatible = "arm,cortex-a73"; - reg = <0x2>; - device_type = "cpu"; -@@ -49,7 +49,7 @@ - operating-points-v2 = <&cluster0_opp>; - }; - -- cpu@3 { -+ cpu3: cpu@3 { - compatible = "arm,cortex-a73"; - reg = <0x3>; - device_type = "cpu"; diff --git a/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch deleted file mode 100644 index a543ecbaa3..0000000000 --- a/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch +++ /dev/null @@ -1,169 +0,0 @@ -From b7ae3528a588a4006ff9c9cc581efa317df1c1ed Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 22 Apr 2025 15:24:29 +0200 -Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg - -Patch from Sam Shih found in MediaTek SDK -released under GPL. - -Get syscon and use it to set the PHY type. -Extend support to PCIe and SGMII mode in addition to USB2 and USB3. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno ---- - drivers/phy/mediatek/phy-mtk-xsphy.c | 85 +++++++++++++++++++++++++++- - 1 file changed, 84 insertions(+), 1 deletion(-) - ---- a/drivers/phy/mediatek/phy-mtk-xsphy.c -+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c -@@ -11,10 +11,12 @@ - #include - #include - #include -+#include - #include - #include - #include - #include -+#include - - #include "phy-mtk-io.h" - -@@ -81,12 +83,22 @@ - #define XSP_SR_COEF_DIVISOR 1000 - #define XSP_FM_DET_CYCLE_CNT 1024 - -+/* PHY switch between pcie/usb3/sgmii */ -+#define USB_PHY_SWITCH_CTRL 0x0 -+#define RG_PHY_SW_TYPE GENMASK(3, 0) -+#define RG_PHY_SW_PCIE 0x0 -+#define RG_PHY_SW_USB3 0x1 -+#define RG_PHY_SW_SGMII 0x2 -+ - struct xsphy_instance { - struct phy *phy; - void __iomem *port_base; - struct clk *ref_clk; /* reference clock of anolog phy */ - u32 index; - u32 type; -+ struct regmap *type_sw; -+ u32 type_sw_reg; -+ u32 type_sw_index; - /* only for HQA test */ - int efuse_intr; - int efuse_tx_imp; -@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt - inst->efuse_intr, inst->efuse_tx_imp, - inst->efuse_rx_imp); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - return; -@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_ - RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); - } - -+/* type switch for usb3/pcie/sgmii */ -+static int phy_type_syscon_get(struct xsphy_instance *instance, -+ struct device_node *dn) -+{ -+ struct of_phandle_args args; -+ int ret; -+ -+ /* type switch function is optional */ -+ if (!of_property_present(dn, "mediatek,syscon-type")) -+ return 0; -+ -+ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", -+ 2, 0, &args); -+ if (ret) -+ return ret; -+ -+ instance->type_sw_reg = args.args[0]; -+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ -+ instance->type_sw = syscon_node_to_regmap(args.np); -+ of_node_put(args.np); -+ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", -+ instance->type_sw_reg, instance->type_sw_index); -+ -+ return PTR_ERR_OR_ZERO(instance->type_sw); -+} -+ -+static int phy_type_set(struct xsphy_instance *instance) -+{ -+ int type; -+ u32 offset; -+ -+ if (!instance->type_sw) -+ return 0; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB3: -+ type = RG_PHY_SW_USB3; -+ break; -+ case PHY_TYPE_PCIE: -+ type = RG_PHY_SW_PCIE; -+ break; -+ case PHY_TYPE_SGMII: -+ type = RG_PHY_SW_SGMII; -+ break; -+ case PHY_TYPE_USB2: -+ default: -+ return 0; -+ } -+ -+ offset = instance->type_sw_index * BITS_PER_BYTE; -+ regmap_update_bits(instance->type_sw, instance->type_sw_reg, -+ RG_PHY_SW_TYPE << offset, type << offset); -+ -+ return 0; -+} -+ - static int mtk_phy_init(struct phy *phy) - { - struct xsphy_instance *inst = phy_get_drvdata(phy); -@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy) - case PHY_TYPE_USB3: - u3_phy_props_set(xsphy, inst); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do, only used to set type */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - clk_disable_unprepare(inst->ref_clk); -@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct - - inst->type = args->args[0]; - if (!(inst->type == PHY_TYPE_USB2 || -- inst->type == PHY_TYPE_USB3)) { -+ inst->type == PHY_TYPE_USB3 || -+ inst->type == PHY_TYPE_PCIE || -+ inst->type == PHY_TYPE_SGMII)) { - dev_err(dev, "unsupported phy type: %d\n", inst->type); - return ERR_PTR(-EINVAL); - } - - phy_parse_property(xsphy, inst); -+ phy_type_set(inst); - - return inst->phy; - } -@@ -510,6 +589,10 @@ static int mtk_xsphy_probe(struct platfo - dev_err(dev, "failed to get ref_clk(id-%d)\n", port); - return PTR_ERR(inst->ref_clk); - } -+ -+ retval = phy_type_syscon_get(inst, child_np); -+ if (retval) -+ return retval; - } - - provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/target/linux/mediatek/patches-6.12/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch b/target/linux/mediatek/patches-6.12/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch deleted file mode 100644 index 70c771d2df..0000000000 --- a/target/linux/mediatek/patches-6.12/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f9c0c36eefaa8c6ee224634bf9c0b8b4ed87b43a Mon Sep 17 00:00:00 2001 -From: Sakari Ailus -Date: Thu, 10 Apr 2025 18:22:38 +0300 -Subject: [PATCH] hwrng: mtk - Add struct device pointer to device context struct - -Add a struct device pointer field to the device's context struct. This -makes using the unsigned long priv pointer in struct hwrng unnecessary, so -remove that one as well. - -Signed-off-by: Sakari Ailus -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/mtk-rng.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -36,6 +36,7 @@ struct mtk_rng { - void __iomem *base; - struct clk *clk; - struct hwrng rng; -+ struct device *dev; - }; - - static int mtk_rng_init(struct hwrng *rng) -@@ -85,7 +86,7 @@ static int mtk_rng_read(struct hwrng *rn - struct mtk_rng *priv = to_mtk_rng(rng); - int retval = 0; - -- pm_runtime_get_sync((struct device *)priv->rng.priv); -+ pm_runtime_get_sync(priv->dev); - - while (max >= sizeof(u32)) { - if (!mtk_rng_wait_ready(rng, wait)) -@@ -97,8 +98,8 @@ static int mtk_rng_read(struct hwrng *rn - max -= sizeof(u32); - } - -- pm_runtime_mark_last_busy((struct device *)priv->rng.priv); -- pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv); -+ pm_runtime_mark_last_busy(priv->dev); -+ pm_runtime_put_sync_autosuspend(priv->dev); - - return retval || !wait ? retval : -EIO; - } -@@ -112,13 +113,13 @@ static int mtk_rng_probe(struct platform - if (!priv) - return -ENOMEM; - -+ priv->dev = &pdev->dev; - priv->rng.name = pdev->name; - #ifndef CONFIG_PM - priv->rng.init = mtk_rng_init; - priv->rng.cleanup = mtk_rng_cleanup; - #endif - priv->rng.read = mtk_rng_read; -- priv->rng.priv = (unsigned long)&pdev->dev; - priv->rng.quality = 900; - - priv->clk = devm_clk_get(&pdev->dev, "rng"); diff --git a/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch b/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch deleted file mode 100644 index 126ae5f2a3..0000000000 --- a/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch +++ /dev/null @@ -1,28 +0,0 @@ -From de6840095f8ed542308279c4f24fa42ba27c2dd3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sat, 12 Oct 2024 16:38:23 +0200 -Subject: [PATCH] mmc: mtk-sd: add support for mt7988 - -Add support for mmc on MT7988 SoC. - -We can use mt7986 platform data in driver, but mt7988 needs different -clocks so for binding we need own compatible. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Message-ID: <20241012143826.7690-3-linux@fw-web.de> -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -631,6 +631,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, - { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, -+ { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, - { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, - { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.12/061-v6.19-arm64-dts-mediatek-mt7986-bpi-r3-Change-fan-PWM-valu.patch b/target/linux/mediatek/patches-6.12/061-v6.19-arm64-dts-mediatek-mt7986-bpi-r3-Change-fan-PWM-valu.patch deleted file mode 100644 index 4b27031d11..0000000000 --- a/target/linux/mediatek/patches-6.12/061-v6.19-arm64-dts-mediatek-mt7986-bpi-r3-Change-fan-PWM-valu.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 5f271fe1365b63f67fc384ca8d50d473d09de0d1 Mon Sep 17 00:00:00 2001 -From: Mikhail Kshevetskiy -Date: Tue, 3 Dec 2024 07:33:55 +0300 -Subject: [PATCH] arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for - mid speed - -Popular cheap PWM fans for this machine, like the ones coming in -heatsink+fan combos will not work properly at the currently defined -medium speed. Trying different pwm setting using a command - - echo $value > /sys/devices/platform/pwm-fan/hwmon/hwmon1/pwm1 - -I found: - - pwm1 value fan rotation speed cpu temperature notes - ----------------------------------------------------------------- - 0 maximal 31.5 Celsius too noisy - 40 optimal 35.2 Celsius no noise hearable - 95 minimal - above 95 does not rotate 55.5 Celsius - ----------------------------------------------------------------- - -Thus only cpu-active-high and cpu-active-low modes are usable. -I think this is wrong. - -This patch fixes cpu-active-medium settings for bpi-r3 board. - -I know, the patch is not ideal as it can break pwm fan for some users. -Likely this is the only official mt7986-bpi-r3 heatsink+fan solution -available on the market. - -This patch may not be enough. Users may wants to tweak their thermal_zone0 -trip points, thus tuning fan rotation speed depending on cpu temperature. -That can be done on the base of the following example: - - === example ========= - # cpu temperature below 25 Celsius degrees, no rotation - echo 25000 > /sys/class/thermal/thermal_zone0/trip_point_4_temp - # cpu temperature in [25..32] Celsius degrees, normal rotation speed - echo 32000 > /sys/class/thermal/thermal_zone0/trip_point_3_temp - # cpu temperature above 50 Celsius degrees, max rotation speed - echo 50000 > /sys/class/thermal/thermal_zone0/trip_point_2_temp - ===================== - -Signed-off-by: Mikhail Kshevetskiy -Acked-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno - ---- -Changes from v1 to v2: - * improve patch description - -Changes from v2 to v3: - * added question to Frank Wunderlich - -Changes from v3 to v4: - * Acked by Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -42,7 +42,7 @@ - compatible = "pwm-fan"; - #cooling-cells = <2>; - /* cooling level (0, 1, 2) - pwm inverted */ -- cooling-levels = <255 96 0>; -+ cooling-levels = <255 40 0>; - pwms = <&pwm 0 10000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.12/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch b/target/linux/mediatek/patches-6.12/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch deleted file mode 100644 index 444c64dd7c..0000000000 --- a/target/linux/mediatek/patches-6.12/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 0da6f7a0ab5322eb6d091a9c89d799adfeae078d Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sun, 7 Sep 2025 13:15:09 +0200 -Subject: [PATCH] arm64: dts: mediatek: add thermal sensor support on mt7981 - -The temperature sensor in the MT7981 is same as in the MT7986. - -Signed-off-by: Aleksander Jan Bajkowski -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 31 ++++++++++++++++++++++- - 1 file changed, 30 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -@@ -76,7 +76,7 @@ - #reset-cells = <1>; - }; - -- clock-controller@1001e000 { -+ apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7981-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; -@@ -184,6 +184,31 @@ - status = "disabled"; - }; - -+ thermal@1100c800 { -+ compatible = "mediatek,mt7981-thermal", -+ "mediatek,mt7986-thermal"; -+ reg = <0 0x1100c800 0 0x800>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_THERM_CK>, -+ <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "therm", "auxadc"; -+ nvmem-cells = <&thermal_calibration>; -+ nvmem-cell-names = "calibration-data"; -+ #thermal-sensor-cells = <1>; -+ mediatek,auxadc = <&auxadc>; -+ mediatek,apmixedsys = <&apmixedsys>; -+ }; -+ -+ auxadc: adc@1100d000 { -+ compatible = "mediatek,mt7981-auxadc", -+ "mediatek,mt7986-auxadc"; -+ reg = <0 0x1100d000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "main"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, -@@ -211,6 +236,10 @@ - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ thermal_calibration: thermal-calib@274 { -+ reg = <0x274 0xc>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch b/target/linux/mediatek/patches-6.12/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch deleted file mode 100644 index 47263733ac..0000000000 --- a/target/linux/mediatek/patches-6.12/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 6da9f0cc2717158857f8b8b9369523d0d6770c07 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Sat, 17 Jan 2026 11:04:37 +0800 -Subject: [PATCH] pinctrl: mediatek: enable ies_present flag for MT798x - -The MT798x series SoCs have IES regiter definitions. I think we -must enable the ies_present flag to correctly configure the pin -input mode. - -Signed-off-by: Shiji Yang -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 2 +- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 4 ++-- - drivers/pinctrl/mediatek/pinctrl-mt7988.c | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -1019,7 +1019,7 @@ static struct mtk_pin_soc mt7981_data = - .nfuncs = ARRAY_SIZE(mt7981_functions), - .eint_hw = &mt7981_eint_hw, - .gpio_m = 0, -- .ies_present = false, -+ .ies_present = true, - .base_names = mt7981_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -919,7 +919,7 @@ static struct mtk_pin_soc mt7986a_data = - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986a_eint_hw, - .gpio_m = 0, -- .ies_present = false, -+ .ies_present = true, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, -@@ -945,7 +945,7 @@ static struct mtk_pin_soc mt7986b_data = - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986b_eint_hw, - .gpio_m = 0, -- .ies_present = false, -+ .ies_present = true, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c -@@ -1515,7 +1515,7 @@ static const struct mtk_pin_soc mt7988_d - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, -- .ies_present = false, -+ .ies_present = true, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, diff --git a/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index 311e62983f..0000000000 --- a/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,130 +0,0 @@ -From c46ccb69d17e584479df849a107423175a143c83 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 24 Oct 2020 21:15:20 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7622-rfb1: update copyright, fix bootargs and GPIO polarity - -Update the copyright header, add an explicit console= argument to the -chosen/bootargs property, and fix the GPIO polarity flags on the -factory and WPS button keys to use GPIO_ACTIVE_LOW. - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -24,7 +23,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -45,18 +44,18 @@ - key-factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - key-wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - device_type = "memory"; - }; - -@@ -134,9 +133,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- switch@0 { -+ switch@1f { - compatible = "mediatek,mt7531"; -- reg = <0>; -+ reg = <31>; - reset-gpios = <&pio 54 0>; - - ports { -@@ -145,22 +144,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -264,7 +263,22 @@ - status = "okay"; - }; - -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; -+}; -+ - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -541,11 +555,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index 058b7076b3..0000000000 --- a/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,73 +0,0 @@ -From c46ccb69d17e584479df849a107423175a143c83 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 24 Oct 2020 21:15:20 +0200 -Subject: [PATCH] arm: dts: mediatek: mt7629-rfb: add earlycon/console bootargs and MAC address nvmem cells - -Add earlycon= and console= to chosen/bootargs, and wire the two Ethernet -MACs (gmac0, gmac1) to their respective MAC address stored in the factory -partition via nvmem-cells. - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -273,3 +282,19 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ nvmem-layout { -+ compatible = "fixed-layout"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch deleted file mode 100644 index 04df7b927b..0000000000 --- a/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch +++ /dev/null @@ -1,20 +0,0 @@ -From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Fri, 29 Apr 2022 10:40:56 +0800 -Subject: [PATCH] arm: mediatek: select arch timer for mt7623 - -Signed-off-by: Chuanhong Guo ---- - arch/arm/mach-mediatek/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 - config MACH_MT7623 - bool "MediaTek MT7623 SoCs support" - default ARCH_MEDIATEK -+ select HAVE_ARM_ARCH_TIMER - - config MACH_MT7629 - bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch deleted file mode 100644 index 1150758de1..0000000000 --- a/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 99cd44487e2e7205e1521a52faf498dfda6f100c Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sat, 30 Apr 2022 20:24:07 +0800 -Subject: [PATCH] mediatek: mt7622: add irq for spi-nor controller - -Save some CPU from unnecessary polling and make SPI flash reading -a tiny bit faster. - -Signed-off-by: Chuanhong Guo ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -575,6 +575,7 @@ - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; -+ interrupts = ; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index 04aff0d656..0000000000 --- a/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e1adb1fa39dd5ef97280ad1b2bb9e8ff4c43674f Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 7 May 2021 16:53:09 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622: reserve memory for ramoops/pstore - -Reserve 64KiB of memory for crashlogs and enable PSTORE feature in -kernel config for MT7622. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -135,6 +135,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch b/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch deleted file mode 100644 index 9faf83d7ed..0000000000 --- a/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 50416c18dd309fec75b6911221905cd0c0139b25 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 21 Dec 2023 21:20:17 +0100 -Subject: [PATCH] mediatek: disable btif for mt7622 devices - -It breaks built-in SoC WLAN. Can be re-enabled after we've figured out the cause - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -109,10 +109,6 @@ - status = "disabled"; - }; - --&btif { -- status = "okay"; --}; -- - &cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -90,10 +90,6 @@ - status = "disabled"; - }; - --&btif { -- status = "okay"; --}; -- - &cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; diff --git a/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 2b5b8069e2..0000000000 --- a/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 -From: Mark-MC Lee (李明昌) -Date: Mon, 10 Feb 2020 09:33:15 +0100 -Subject: [PATCH] arm: dts: mediatek: mt7623n-bpi-r2: add console= to bootargs - -Add an explicit console=ttyS2,115200n8 argument to the chosen/bootargs -property so that a serial console is available during early boot. - -Signed-off-by: Mark-MC Lee (李明昌) ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch deleted file mode 100644 index 9d0c2d33e2..0000000000 --- a/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 -From: Mark-MC Lee (李明昌) -Date: Mon, 10 Feb 2020 09:33:15 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622-bpi-r64: add console= to bootargs - -Add an explicit console=ttyS0,115200n1 argument to the chosen/bootargs -property so that a serial console is available during early boot. - -Signed-off-by: Mark-MC Lee (李明昌) ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -24,7 +24,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index b94701eaa6..0000000000 --- a/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,48 +0,0 @@ -From dfa0a38d1f4d5bbac768569e3769ae4438a57e73 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 27 Feb 2021 14:17:09 +0000 -Subject: [PATCH] arm64: dts: mediatek: mt7622-bpi-r64: fix LAN port numbering and add ethernet alias - -Renumber the switch LAN port labels from lan0/lan1/lan2 to lan1/lan2/lan3 -to match the silkscreen labelling on the board, and add an ethernet0 alias -pointing to gmac0. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -20,6 +20,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -164,22 +165,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@5 { diff --git a/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index 722c8efbcf..0000000000 --- a/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,61 +0,0 @@ -From dfa0a38d1f4d5bbac768569e3769ae4438a57e73 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 27 Feb 2021 14:17:09 +0000 -Subject: [PATCH] arm64: dts: mediatek: mt7622-bpi-r64: add LED aliases, fix button labels and MMC aliases - -Add led-boot/led-failsafe/led-running/led-upgrade aliases pointing to -the system LEDs, add mmc0/mmc1 aliases for correct MMC device ordering, -rename the factory button to "reset" with KEY_RESTART, and update the -LED gpio-hog and label names to match their physical function. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -21,6 +21,12 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { -@@ -44,8 +50,8 @@ - compatible = "gpio-keys"; - - factory-key { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -59,17 +65,17 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_system_green: led-0 { - label = "bpi-r64:pio:green"; - color = ; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- led-1 { -- label = "bpi-r64:pio:red"; -- color = ; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_blue: led-1 { -+ label = "bpi-r64:pio:blue"; -+ color = ; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; diff --git a/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index caf969d648..0000000000 --- a/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 8dd0215676a304456d25ff3ac4542c7303831a90 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 6 Mar 2021 18:38:30 +0000 -Subject: [PATCH] mediatek: disable RTC on Bananapi R64 - -The in-SoC RTC of the Bananapi R64 is more disruptive than useful -without a battery connected. Disable it to not have Linux use the -RTC provided time 2000-01-01 00:00:00 after power-loss. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -599,6 +599,10 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { - status = "disabled"; - }; diff --git a/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch b/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch deleted file mode 100644 index 1d53cefd7f..0000000000 --- a/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 4c4baed29b168e9bf39545a945a9523ea280cb44 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 1 Feb 2025 04:24:17 +0000 -Subject: [PATCH 1/2] Revert "arm64: dts: mediatek: fix t-phy unit name" - -This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f. ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -908,7 +908,7 @@ - status = "disabled"; - }; - -- sata_phy: t-phy { -+ sata_phy: t-phy@1a243000 { - compatible = "mediatek,mt7622-tphy", - "mediatek,generic-tphy-v1"; - #address-cells = <2>; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -428,7 +428,7 @@ - }; - }; - -- pcie_phy: t-phy { -+ pcie_phy: t-phy@11c00000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - ranges; diff --git a/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch b/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch deleted file mode 100644 index 4ae72fd70a..0000000000 --- a/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 28 Jun 2024 12:55:40 +0200 -Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys - node - -Sata node reference the pciesys with the property mediatek,phy-node -and that is used as a syscon to access the pciesys regs. - -Readd the syscon compatible to pciesys node to restore correct -functionality of the SATA interface. - -Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers") -Reported-by: Frank Wunderlich -Co-developed-by: Frank Wunderlich -Signed-off-by: Frank Wunderlich -Signed-off-by: Christian Marangi -Cc: stable@vger.kernel.org ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -798,7 +798,7 @@ - }; - - pciesys: clock-controller@1a100800 { -- compatible = "mediatek,mt7622-pciesys"; -+ compatible = "mediatek,mt7622-pciesys", "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch b/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch deleted file mode 100644 index 51305b9725..0000000000 --- a/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch +++ /dev/null @@ -1,657 +0,0 @@ -From 3986156b3ba97a9c280f4dfe0efbccf52e1fc488 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 28 Dec 2022 23:44:42 +0000 -Subject: [PATCH] complete mt7981 dts - -working: - * Ethernet (fully working incl. ppe) - * UART - * SPI-NAND flash - * thermal sensors (SoC and mxl-gpy) - * random number generator via SMC - * USB 1.1, 2.0 and 3.0 - * WiFi with MT7976C 2.4G+5G DBDC incl. WED offloading - * PWM - ---- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -@@ -1,7 +1,14 @@ - // SPDX-License-Identifier: GPL-2.0-only OR MIT - - #include -+#include -+#include - #include -+#include -+#include -+#include -+#include -+#include - #include - - / { -@@ -41,6 +48,57 @@ - method = "smc"; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ -+ cooling-levels = <0 128 192 255>; -+ #cooling-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ -+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ -+ secmon_reserved: secmon@43000000 { -+ reg = <0 0x43000000 0 0x30000>; -+ no-map; -+ }; -+ -+ wmcpu_emi: wmcpu-reserved@47c80000 { -+ reg = <0 0x47c80000 0 0x100000>; -+ no-map; -+ }; -+ -+ wo_emi0: wo-emi@47d80000 { -+ reg = <0 0x47d80000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_data: wo-data@47dc0000 { -+ reg = <0 0x47dc0000 0 0x240000>; -+ no-map; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - ranges; -@@ -77,12 +135,12 @@ - }; - - apmixedsys: clock-controller@1001e000 { -- compatible = "mediatek,mt7981-apmixedsys"; -+ compatible = "mediatek,mt7981-apmixedsys", "syscon"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - -- pwm@10048000 { -+ pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, -@@ -94,7 +152,21 @@ - #pwm-cells = <2>; - }; - -- serial@11002000 { -+ crypto: crypto@10320000 { -+ compatible = "inside-secure,safexcel-eip97"; -+ reg = <0 0x10320000 0 0x40000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ clocks = <&topckgen CLK_TOP_EIP97B>; -+ clock-names = "top_eip97_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; -+ }; -+ -+ uart0: serial@11002000 { - compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x100>; - interrupts = ; -@@ -105,7 +177,7 @@ - status = "disabled"; - }; - -- serial@11003000 { -+ uart1: serial@11003000 { - compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x100>; - interrupts = ; -@@ -116,7 +188,7 @@ - status = "disabled"; - }; - -- serial@11004000 { -+ uart2: serial@11004000 { - compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x100>; - interrupts = ; -@@ -127,11 +199,12 @@ - status = "disabled"; - }; - -- i2c@11007000 { -+ i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; -+ clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, -@@ -142,7 +215,7 @@ - status = "disabled"; - }; - -- spi@11009000 { -+ spi2: spi@11009000 { - compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x1000>; - interrupts = ; -@@ -156,7 +229,7 @@ - status = "disabled"; - }; - -- spi@1100a000 { -+ spi0: spi@1100a000 { - compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; -@@ -170,7 +243,7 @@ - status = "disabled"; - }; - -- spi@1100b000 { -+ spi1: spi@1100b000 { - compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; -@@ -184,7 +257,7 @@ - status = "disabled"; - }; - -- thermal@1100c800 { -+ thermal: thermal@1100c800 { - compatible = "mediatek,mt7981-thermal", - "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; -@@ -201,12 +274,48 @@ - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", -- "mediatek,mt7986-auxadc"; -+ "mediatek,mt7986-auxadc", -+ "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; -- clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -- clock-names = "main"; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, -+ <&infracfg CLK_INFRA_ADC_FRC_CK>; -+ clock-names = "main", "32k"; - #io-channel-cells = <1>; -+ }; -+ -+ pcie: pcie@11280000 { -+ compatible = "mediatek,mt7981-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11280000 0 0x4000>; -+ reg-names = "pcie-mac"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 -+ 0x0 0x20000000 0 0x10000000>; - status = "disabled"; -+ -+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>, -+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, -+ <&infracfg CLK_INFRA_IPCIER_CK>, -+ <&infracfg CLK_INFRA_IPCIEB_CK>; -+ -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ pcie_intc: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ }; - }; - - pio: pinctrl@11d00000 { -@@ -229,6 +338,35 @@ - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; -+ -+ mdio_pins: mdc-mdio-pins { -+ mux { -+ function = "eth"; -+ groups = "smi_mdc_mdio"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ wifi_dbdc_pins: wifi-dbdc-pins { -+ mux { -+ function = "eth"; -+ groups = "wf0_mode1"; -+ }; -+ conf { -+ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", -+ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", -+ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", -+ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", -+ "WF_CBA_RESETB", "WF_DIG_RESETB"; -+ drive-strength = ; -+ }; -+ }; - }; - - efuse@11f20000 { -@@ -240,17 +378,293 @@ - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; -+ -+ phy_calibration: phy-calib@8dc { -+ reg = <0x8dc 0x10>; -+ }; -+ -+ comb_rx_imp_p0: usb3-rx-imp@8c8 { -+ reg = <0x8c8 1>; -+ bits = <0 5>; -+ }; -+ -+ comb_tx_imp_p0: usb3-tx-imp@8c8 { -+ reg = <0x8c8 2>; -+ bits = <5 5>; -+ }; -+ -+ comb_intr_p0: usb3-intr@8c9 { -+ reg = <0x8c9 1>; -+ bits = <2 6>; -+ }; - }; - -- clock-controller@15000000 { -+ ethsys: clock-controller@15000000 { - compatible = "mediatek,mt7981-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- wifi@18000000 { -+ wed: wed@15010000 { -+ compatible = "mediatek,mt7981-wed", -+ "mediatek,mt7986-wed", -+ "syscon"; -+ reg = <0 0x15010000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; -+ mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; -+ }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7981-eth"; -+ reg = <0 0x15100000 0 0x80000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <ðsys CLK_ETH_FE_EN>, -+ <ðsys CLK_ETH_GP2_EN>, -+ <ðsys CLK_ETH_GP1_EN>, -+ <ðsys CLK_ETH_WOCPU0_EN>, -+ <&sgmiisys0 CLK_SGM0_TX_EN>, -+ <&sgmiisys0 CLK_SGM0_RX_EN>, -+ <&sgmiisys0 CLK_SGM0_CK0_EN>, -+ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, -+ <&sgmiisys1 CLK_SGM1_TX_EN>, -+ <&sgmiisys1 CLK_SGM1_RX_EN>, -+ <&sgmiisys1 CLK_SGM1_CK1_EN>, -+ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, -+ <&topckgen CLK_TOP_SGM_REG>, -+ <&topckgen CLK_TOP_NETSYS_SEL>, -+ <&topckgen CLK_TOP_NETSYS_500M_SEL>; -+ clock-names = "fe", "gp2", "gp1", "wocpu0", -+ "sgmii_tx250m", "sgmii_rx250m", -+ "sgmii_cdr_ref", "sgmii_cdr_fb", -+ "sgmii2_tx250m", "sgmii2_rx250m", -+ "sgmii2_cdr_ref", "sgmii2_cdr_fb", -+ "sgmii_ck", "netsys0", "netsys1"; -+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, -+ <&topckgen CLK_TOP_SGM_325M_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, -+ <&topckgen CLK_TOP_CB_SGM_325M>; -+ mediatek,ethsys = <ðsys>; -+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; -+ mediatek,infracfg = <&topmisc>; -+ mediatek,wed = <&wed>; -+ mediatek,wed-pcie = <&wed_pcie>; -+ status = "disabled"; -+ -+ mdio_bus: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_gbe_phy: ethernet-phy@0 { -+ reg = <0>; -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ phy-mode = "gmii"; -+ phy-is-integrated; -+ nvmem-cells = <&phy_calibration>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_gbe_phy_led0: int-gbe-phy-led0@0 { -+ reg = <0>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ -+ int_gbe_phy_led1: int-gbe-phy-led1@1 { -+ reg = <1>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ -+ wo_ccif0: syscon@151a5000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; -+ reg = <0 0x10060000 0 0x1000>; -+ mediatek,pnswap; -+ #clock-cells = <1>; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; -+ reg = <0 0x10070000 0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ topmisc: topmisc@11d10000 { -+ compatible = "mediatek,mt7981-topmisc", "syscon"; -+ reg = <0 0x11d10000 0 0x10000>; -+ #clock-cells = <1>; -+ }; -+ -+ snand: snfi@11005000 { -+ compatible = "mediatek,mt7986-snand"; -+ reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, -+ <&infracfg CLK_INFRA_NFI1_CK>, -+ <&infracfg CLK_INFRA_NFI_HCK_CK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, -+ <&topckgen CLK_TOP_NFI1X_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, -+ <&topckgen CLK_TOP_CB_M_D8>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7986-mmc", -+ "mediatek,mt7981-mmc"; -+ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_MSDC_CK>, -+ <&infracfg CLK_INFRA_MSDC_HCK_CK>, -+ <&infracfg CLK_INFRA_MSDC_66M_CK>, -+ <&infracfg CLK_INFRA_MSDC_133M_CK>; -+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, -+ <&topckgen CLK_TOP_EMMC_400M_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, -+ <&topckgen CLK_TOP_CB_NET2_D2>; -+ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; -+ status = "disabled"; -+ }; -+ -+ wed_pcie: wed_pcie@10003000 { -+ compatible = "mediatek,wed_pcie", "syscon"; -+ reg = <0 0x10003000 0 0x10>; -+ }; -+ -+ consys: consys@10000000 { -+ compatible = "mediatek,mt7981-consys"; -+ reg = <0 0x10000000 0 0x8600000>; -+ memory-region = <&wmcpu_emi>; -+ }; -+ -+ xhci: usb@11200000 { -+ compatible = "mediatek,mt7986-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0 0x11200000 0 0x2e00>, -+ <0 0x11203e00 0 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, -+ <&infracfg CLK_INFRA_IUSB_CK>, -+ <&infracfg CLK_INFRA_IUSB_133_CK>, -+ <&infracfg CLK_INFRA_IUSB_66M_CK>, -+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; -+ clock-names = "sys_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck", -+ "xhci_ck"; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>; -+ vusb33-supply = <®_3p3v>; -+ status = "disabled"; -+ }; -+ -+ usb_phy: usb-phy@11e10000 { -+ compatible = "mediatek,mt7981", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0x11e10000 0x1700>; -+ status = "disabled"; -+ -+ u2port0: usb-phy@0 { -+ reg = <0x0 0x700>; -+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u3port0: usb-phy@700 { -+ reg = <0x700 0x900>; -+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ mediatek,syscon-type = <&topmisc 0x218 0>; -+ nvmem-cells = <&comb_intr_p0>, -+ <&comb_rx_imp_p0>, -+ <&comb_tx_imp_p0>; -+ nvmem-cell-names = "intr", "rx_imp", "tx_imp"; -+ status = "okay"; -+ }; -+ }; -+ -+ -+ afe: audio-controller@11210000 { -+ compatible = "mediatek,mt79xx-audio"; -+ reg = <0 0x11210000 0 0x9000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, -+ <&infracfg CLK_INFRA_AUD_26M_CK>, -+ <&infracfg CLK_INFRA_AUD_L_CK>, -+ <&infracfg CLK_INFRA_AUD_AUD_CK>, -+ <&infracfg CLK_INFRA_AUD_EG2_CK>, -+ <&topckgen CLK_TOP_AUD_SEL>; -+ clock-names = "aud_bus_ck", -+ "aud_26m_ck", -+ "aud_l_ck", -+ "aud_aud_ck", -+ "aud_eg2_ck", -+ "aud_sel"; -+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, -+ <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, -+ <&topckgen CLK_TOP_APLL2_D4>, -+ <&topckgen CLK_TOP_CB_APLL2_196M>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ status = "disabled"; -+ }; -+ -+ wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; -+ pinctrl-0 = <&wifi_dbdc_pins>; -+ pinctrl-names = "dbdc"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; -@@ -263,6 +677,67 @@ - clock-names = "mcu", "ap2conn"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; -+ memory-region = <&wmcpu_emi>; -+ status = "disabled"; -+ }; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&thermal 0>; -+ trips { -+ cpu_trip_crit: crit { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_med: active-med { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <60000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ cpu-active-high { -+ /* active: set fan to cooling level 3 */ -+ cooling-device = <&fan 3 3>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ cpu-active-med { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_med>; -+ }; -+ -+ cpu-active-low { -+ /* passive: set fan to cooling level 1 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ }; - }; - }; - -@@ -274,4 +749,8 @@ - , - ; - }; -+ -+ trng { -+ compatible = "mediatek,mt7981-rng"; -+ }; - }; diff --git a/target/linux/mediatek/patches-6.12/119-pinctrl-mediatek-MT7981-some-register-map-fixes.patch b/target/linux/mediatek/patches-6.12/119-pinctrl-mediatek-MT7981-some-register-map-fixes.patch deleted file mode 100644 index fce45298aa..0000000000 --- a/target/linux/mediatek/patches-6.12/119-pinctrl-mediatek-MT7981-some-register-map-fixes.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 2b4d8df6054acb13cae20889c40102c93df2edd6 Mon Sep 17 00:00:00 2001 -From: developer -Date: Tue, 6 Jan 2026 19:52:11 +0800 -Subject: [PATCH] pinctrl: mediatek: MT7981: some register map fixes - -Fix mt7981 pinctrl setting mistake including: -1) Wrong pinctrl bits length -2) Wrong pinctrl register offset - -Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/52579dd19e62df5aff784462e133e14bfe4a7726 -Signed-off-by: Shiji Yang ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -48,7 +48,7 @@ static const struct mtk_pin_field_calc m - - PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), -- PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x20, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), - -@@ -157,7 +157,7 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), -- PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), -@@ -221,8 +221,8 @@ static const struct mtk_pin_field_calc m - - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), - -- PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), -- PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), -@@ -230,9 +230,9 @@ static const struct mtk_pin_field_calc m - - PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), -- PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(11, 11, 5, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), -- PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(13, 13, 5, 0x10, 0x10, 3, 3), - - PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), - -@@ -244,7 +244,7 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), -- PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(23, 23, 2, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), - -@@ -310,7 +310,7 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), -- PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), diff --git a/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch deleted file mode 100644 index 21459e1c17..0000000000 --- a/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 2138956bdc3145fac26d2ba8ac966f31d33cd290 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Thu, 7 Apr 2022 10:05:56 +0800 -Subject: [PATCH] mediatek: spi-nand: check for 1 byte BBM only - -the OOB layout in MTK SNFI uses the 2nd byte, and anything using OOB -will make the block a bad-block in spi-nand driver. -Hack it for now. We need a proper solution upstream. - -Signed-off-by: Chuanhong Guo ---- ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -924,7 +924,7 @@ static int spinand_mtd_write(struct mtd_ - static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) - { - struct spinand_device *spinand = nand_to_spinand(nand); -- u8 marker[2] = { }; -+ u8 marker[1] = { }; - struct nand_page_io_req req = { - .pos = *pos, - .ooblen = sizeof(marker), -@@ -943,7 +943,7 @@ static bool spinand_isbad(struct nand_de - spinand_read_page(spinand, &req); - } - -- if (marker[0] != 0xff || marker[1] != 0xff) -+ if (marker[0] != 0xff) - return true; - - return false; diff --git a/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index c7cd525a5c..0000000000 --- a/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,94 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mediatek/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mediatek/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mediatek/mt7629.dtsi -+++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi -@@ -271,6 +271,27 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts -@@ -255,6 +255,50 @@ - }; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index 5293abc616..0000000000 --- a/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,79 +0,0 @@ -From d3f058db1cb9b2d43764cd0d84fdc2779f0abacf Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 27 Mar 2020 15:34:33 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622-rfb1: add SPI-NAND flash node - -Add a spi-nand child node to the snfi controller with quad-IO bus widths, -an ECC engine reference, and a fixed-partitions layout covering the full -flash address space of the SPI-NAND device populated on the RFB1 board. - -Signed-off-by: John Crispin ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -558,6 +558,65 @@ - status = "disabled"; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index 6c9f5dc01a..0000000000 --- a/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c46ccb69d17e584479df849a107423175a143c83 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 24 Oct 2020 21:15:20 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7622-rfb1: wire EEPROM to wmac from factory partition - -Label the factory partition node so it can be referenced by phandle, and -add a mediatek,mtd-eeprom property to the wmac node pointing at the -factory partition to supply the calibration data at offset 0x0000. - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -599,7 +599,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -660,5 +660,6 @@ - &wmac { - pinctrl-names = "default"; - pinctrl-0 = <&wmac_pins>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 9e96a5a09b..0000000000 --- a/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 127ad76311079a842578e788a8af364f3910c676 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 4 Jun 2020 14:20:34 +0200 -Subject: [PATCH] arm: dts: mediatek: mt7623: switch crypto to inside-secure,safexcel-eip97 - -Switch the DTS compatible string of the crypto engine node from -"mediatek,eip97-crypto" to "inside-secure,safexcel-eip97" to bind to -the upstream Inside Secure SafeXcel driver. Update the interrupt list -to match and add interrupt-names, and remove the now-unused power-domain -and clock-names properties. - -Signed-off-by: John Crispin ---- ---- a/arch/arm/boot/dts/mediatek/mt7623.dtsi -+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi -@@ -995,17 +995,15 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; -+ status = "okay"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 85a8bb9cf3..0000000000 --- a/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 -From: Mark-MC Lee (李明昌) -Date: Mon, 10 Feb 2020 09:33:15 +0100 -Subject: [PATCH] arm: dts: mediatek: mt7623n-bpi-r2: add earlycon= to bootargs - -Add earlycon=uart8250,mmio32,0x11004000 to the chosen/bootargs property -so that kernel messages are available on the serial console before the -full UART driver is initialised. - -Signed-off-by: Mark-MC Lee (李明昌) ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index eb9ba49a5a..0000000000 --- a/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 -From: Mark-MC Lee (李明昌) -Date: Mon, 10 Feb 2020 09:33:15 +0100 -Subject: [PATCH] arm: dts: mediatek: mt7623n-bpi-r2: add mmc device order aliases - -Add mmc0 and mmc1 aliases to fix the MMC controller enumeration order, -ensuring the SD card slot and eMMC are always assigned predictable -device numbers regardless of probe order. - -Signed-off-by: Mark-MC Lee (李明昌) ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index 11cb722151..0000000000 --- a/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 21c7a8593d86175c0764d23e77bb019fd9617f53 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 1 Oct 2021 23:25:48 +0100 -Subject: [PATCH] mediatek: mt7623: bpi-r2: add LED aliases - -Add aliases for LEDs in device tree of the BPi-R2. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index 455f3b0a8d..0000000000 --- a/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 -From: Mark-MC Lee (李明昌) -Date: Mon, 10 Feb 2020 09:33:15 +0100 -Subject: [PATCH] arm: dts: mediatek: mt7623n-bpi-r2: add ethernet0 alias - -Add an ethernet0 alias pointing to gmac0 so that the primary Ethernet -interface is consistently named by the kernel. - -Signed-off-by: Mark-MC Lee (李明昌) ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch deleted file mode 100644 index 91ef678674..0000000000 --- a/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 6368ed1ae5b628898b33273c8950f7b7575e4414 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 24 Feb 2024 03:00:27 +0000 -Subject: [PATCH] mediatek: mt7623: phase out uImage.FIT partition parser - -Use the new fitblk driver on the BananaPi R2 as well as UniElec U7623. -Introduce boot device selection for fitblk's /chosen/rootdisk -handle, similar to how it is already done on MT7622, MT7986 and MT7988. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts -@@ -26,7 +26,9 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; -+ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; -+ rootdisk-emmc = <&emmc_rootdisk>; -+ rootdisk-sd = <&sd_rootdisk>; - }; - - connector { -@@ -338,6 +340,20 @@ - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "msdos-partitions"; -+ emmc_rootdisk: block-partition-fit { -+ partno = <3>; -+ }; -+ }; -+ }; - }; - - &mmc1 { -@@ -351,6 +367,20 @@ - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "msdos-partitions"; -+ sd_rootdisk: block-partition-fit { -+ partno = <3>; -+ }; -+ }; -+ }; - }; - - &mt6323keys { diff --git a/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch b/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch deleted file mode 100644 index 6216f59cfd..0000000000 --- a/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch +++ /dev/null @@ -1,876 +0,0 @@ -From df3c7a5128f88e658bd4519154d5e896519e740a Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:25 +0200 -Subject: [PATCH 27/32] arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants - of bpi-r4 - -Sinovoip has released other variants of Bananapi-R4 board. -The known changes affecting only the LAN SFP+ slot which is replaced -by a 2.5G phy with optional PoE. - -Just move the common parts to a new dtsi and keep differences (only -i2c for lan-sfp) in dts. - -Signed-off-by: Frank Wunderlich -Acked-by: Krzysztof Kozlowski -Reviewed-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/Makefile | 6 + - .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 + - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 400 +----------------- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 399 +++++++++++++++++ - 4 files changed, 421 insertions(+), 395 deletions(-) - create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts - create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi - ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -21,6 +21,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb -@@ -90,3 +93,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pu - # Device tree overlays support - DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ - DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ -+DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ -+DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@ -+DTC_FLAGS_mt8395-radxa-nio-12l := -@ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -@@ -0,0 +1,11 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR MIT -+ -+/dts-v1/; -+ -+#include "mt7988a-bananapi-bpi-r4.dtsi" -+ -+/ { -+ compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a"; -+ model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; -+ chassis-type = "embedded"; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -2,408 +2,18 @@ - - /dts-v1/; - --#include --#include -- --#include "mt7988a.dtsi" -+#include "mt7988a-bananapi-bpi-r4.dtsi" - - / { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -- model = "Banana Pi BPI-R4"; -+ model = "Banana Pi BPI-R4 (2x SFP+)"; - chassis-type = "embedded"; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; - }; - --&cpu0 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu1 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu2 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu3 { -- proc-supply = <&rt5190_buck3>; --}; -- --&cpu_thermal { -- trips { -- cpu_trip_hot: hot { -- temperature = <120000>; -- hysteresis = <2000>; -- type = "hot"; -- }; -- -- cpu_trip_active_high: active-high { -- temperature = <115000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_active_med: active-med { -- temperature = <85000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_active_low: active-low { -- temperature = <40000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- }; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- , ; -- regulator-boot-on; -- regulator-always-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- rt5190_buck3: buck3 { -- regulator-name = "vproc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-allowed-modes = -- , ; -- regulator-boot-on; -- regulator-always-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- }; -- }; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_1_pins>; -- status = "okay"; -- -- pca9545: i2c-mux@70 { -- compatible = "nxp,pca9545"; -- reg = <0x70>; -- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+&pca9545 { -+ i2c_sfp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; -- -- i2c@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- -- pcf8563: rtc@51 { -- compatible = "nxp,pcf8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- }; -- -- eeprom@57 { -- compatible = "atmel,24c02"; -- reg = <0x57>; -- size = <256>; -- }; -- -- }; -- -- i2c_sfp1: i2c@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <1>; -- }; -- -- i2c_sfp2: i2c@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- }; -- }; --}; -- --/* mPCIe SIM2 */ --&pcie0 { -- status = "okay"; --}; -- --/* mPCIe SIM3 */ --&pcie1 { -- status = "okay"; --}; -- --/* M.2 key-B SIM1 */ --&pcie2 { -- status = "okay"; --}; -- --/* M.2 key-M SSD */ --&pcie3 { -- status = "okay"; --}; -- --&pio { -- mdio0_pins: mdio0-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio0"; -- }; -- -- conf { -- pins = "SMI_0_MDC", "SMI_0_MDIO"; -- drive-strength = <8>; -- }; -- }; -- -- i2c0_pins: i2c0-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- i2c1_sfp_pins: i2c1-sfp-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_sfp"; -- }; -- }; -- -- i2c2_0_pins: i2c2-g0-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -+ reg = <2>; - }; -- -- i2c2_1_pins: i2c2-g1-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_1"; -- }; -- }; -- -- gbe0_led0_pins: gbe0-led0-pins { -- mux { -- function = "led"; -- groups = "gbe0_led0"; -- }; -- }; -- -- gbe1_led0_pins: gbe1-led0-pins { -- mux { -- function = "led"; -- groups = "gbe1_led0"; -- }; -- }; -- -- gbe2_led0_pins: gbe2-led0-pins { -- mux { -- function = "led"; -- groups = "gbe2_led0"; -- }; -- }; -- -- gbe3_led0_pins: gbe3-led0-pins { -- mux { -- function = "led"; -- groups = "gbe3_led0"; -- }; -- }; -- -- gbe0_led1_pins: gbe0-led1-pins { -- mux { -- function = "led"; -- groups = "gbe0_led1"; -- }; -- }; -- -- gbe1_led1_pins: gbe1-led1-pins { -- mux { -- function = "led"; -- groups = "gbe1_led1"; -- }; -- }; -- -- gbe2_led1_pins: gbe2-led1-pins { -- mux { -- function = "led"; -- groups = "gbe2_led1"; -- }; -- }; -- -- gbe3_led1_pins: gbe3-led1-pins { -- mux { -- function = "led"; -- groups = "gbe3_led1"; -- }; -- }; -- -- i2p5gbe_led0_pins: 2p5gbe-led0-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led0"; -- }; -- }; -- -- i2p5gbe_led1_pins: 2p5gbe-led1-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led1"; -- }; -- }; -- -- mmc0_pins_emmc_45: mmc0-emmc-45-pins { -- mux { -- function = "flash"; -- groups = "emmc_45"; -- }; -- }; -- -- mmc0_pins_emmc_51: mmc0-emmc-51-pins { -- mux { -- function = "flash"; -- groups = "emmc_51"; -- }; -- }; -- -- mmc0_pins_sdcard: mmc0-sdcard-pins { -- mux { -- function = "flash"; -- groups = "sdcard"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0"; -- }; -- }; -- -- snfi_pins: snfi-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spi0_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0"; -- }; -- }; -- -- spi0_flash_pins: spi0-flash-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spi1_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1"; -- }; -- }; -- -- spi2_pins: spi2-pins { -- mux { -- function = "spi"; -- groups = "spi2"; -- }; -- }; -- -- spi2_flash_pins: spi2-flash-pins { -- mux { -- function = "spi"; -- groups = "spi2", "spi2_wp_hold"; -- }; -- }; --}; -- --&pwm { -- status = "okay"; --}; -- --&serial0 { -- status = "okay"; --}; -- --&ssusb1 { -- status = "okay"; --}; -- --&tphy { -- status = "okay"; --}; -- --&watchdog { -- status = "okay"; - }; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -0,0 +1,399 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR MIT -+ -+/dts-v1/; -+ -+#include -+#include -+ -+#include "mt7988a.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&cpu0 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu1 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu2 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu3 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_med: active-med { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+ -+ rt5190a_64: rt5190a@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ buck2 { -+ regulator-name = "vcore"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ rt5190_buck3: buck3 { -+ regulator-name = "vproc"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-allowed-modes = -+ , ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_1_pins>; -+ status = "okay"; -+ -+ pca9545: i2c-mux@70 { -+ compatible = "nxp,pca9545"; -+ reg = <0x70>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ pcf8563: rtc@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c02"; -+ reg = <0x57>; -+ size = <256>; -+ }; -+ -+ }; -+ -+ i2c_sfp1: i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ }; -+}; -+ -+/* mPCIe SIM2 */ -+&pcie0 { -+ status = "okay"; -+}; -+ -+/* mPCIe SIM3 */ -+&pcie1 { -+ status = "okay"; -+}; -+ -+/* M.2 key-B SIM1 */ -+&pcie2 { -+ status = "okay"; -+}; -+ -+/* M.2 key-M SSD */ -+&pcie3 { -+ status = "okay"; -+}; -+ -+&pio { -+ mdio0_pins: mdio0-pins { -+ mux { -+ function = "eth"; -+ groups = "mdc_mdio0"; -+ }; -+ -+ conf { -+ pins = "SMI_0_MDC", "SMI_0_MDIO"; -+ drive-strength = <8>; -+ }; -+ }; -+ -+ i2c0_pins: i2c0-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c0_1"; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ i2c1_sfp_pins: i2c1-sfp-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_sfp"; -+ }; -+ }; -+ -+ i2c2_0_pins: i2c2-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_0"; -+ }; -+ }; -+ -+ i2c2_1_pins: i2c2-g1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_1"; -+ }; -+ }; -+ -+ gbe0_led0_pins: gbe0-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led0"; -+ }; -+ }; -+ -+ gbe1_led0_pins: gbe1-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led0"; -+ }; -+ }; -+ -+ gbe2_led0_pins: gbe2-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led0"; -+ }; -+ }; -+ -+ gbe3_led0_pins: gbe3-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led0"; -+ }; -+ }; -+ -+ gbe0_led1_pins: gbe0-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led1"; -+ }; -+ }; -+ -+ gbe1_led1_pins: gbe1-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led1"; -+ }; -+ }; -+ -+ gbe2_led1_pins: gbe2-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led1"; -+ }; -+ }; -+ -+ gbe3_led1_pins: gbe3-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led1"; -+ }; -+ }; -+ -+ i2p5gbe_led0_pins: 2p5gbe-led0-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led0"; -+ }; -+ }; -+ -+ i2p5gbe_led1_pins: 2p5gbe-led1-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led1"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_45: mmc0-emmc-45-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_51: mmc0-emmc-51-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ }; -+ -+ mmc0_pins_sdcard: mmc0-sdcard-pins { -+ mux { -+ function = "flash"; -+ groups = "sdcard"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2"; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+}; -+ -+&pwm { -+ status = "okay"; -+}; -+ -+&serial0 { -+ status = "okay"; -+}; -+ -+&ssusb1 { -+ status = "okay"; -+}; -+ -+&tphy { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; diff --git a/target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch b/target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch deleted file mode 100644 index 18f1ddc5bf..0000000000 --- a/target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 2400b24dfecea9a628f63089bf7eeb9a43b91021 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:30 +0200 -Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2 - -First usb and third pcie controller on mt7988 need a xs-phy to work -properly. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -334,6 +334,8 @@ - <&infracfg CLK_INFRA_133M_USB_HCK>, - <&infracfg CLK_INFRA_USB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; -+ phys = <&xphyu2port0 PHY_TYPE_USB2>, -+ <&xphyu3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - -@@ -398,6 +400,9 @@ - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; - -+ phys = <&xphyu3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, -@@ -548,6 +553,37 @@ - }; - }; - -+ -+ topmisc: system-controller@11d10084 { -+ compatible = "mediatek,mt7988-topmisc", -+ "syscon"; -+ reg = <0 0x11d10084 0 0xff80>; -+ }; -+ -+ xs-phy@11e10000 { -+ compatible = "mediatek,mt7988-xsphy", -+ "mediatek,xsphy"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ xphyu2port0: usb-phy@11e10000 { -+ reg = <0 0x11e10000 0 0x400>; -+ clocks = <&infracfg CLK_INFRA_USB_UTMI>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ xphyu3port0: usb-phy@11e13000 { -+ reg = <0 0x11e13400 0 0x500>; -+ clocks = <&infracfg CLK_INFRA_USB_PIPE>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ mediatek,syscon-type = <&topmisc 0x194 0>; -+ }; -+ }; -+ - clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch b/target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch deleted file mode 100644 index d02bca2b4e..0000000000 --- a/target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch +++ /dev/null @@ -1,37 +0,0 @@ -From bb5872c4b6cb0a8687b424b9970b2c3cca2ededd Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 22 Apr 2025 15:24:31 +0200 -Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy - -Enable XS-Phy on Bananapi R4 for pcie2. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250422132438.15735-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -397,3 +397,7 @@ - &watchdog { - status = "okay"; - }; -+ -+&xsphy { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -560,7 +560,7 @@ - reg = <0 0x11d10084 0 0xff80>; - }; - -- xs-phy@11e10000 { -+ xsphy: xs-phy@11e10000 { - compatible = "mediatek,mt7988-xsphy", - "mediatek,xsphy"; - #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch b/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch deleted file mode 100644 index 698f821314..0000000000 --- a/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 6cf55d4520eb4ef3ed2cc3726a765a89b0071d8b Mon Sep 17 00:00:00 2001 -From: Sky Huang -Date: Wed, 19 Feb 2025 16:39:09 +0800 -Subject: [PATCH 30/32] dts: mt7988a: Add built-in ethernet phy firmware node - -Add built-in ethernet phy firmware node in mt7988a.dtsi. - -Signed-off-by: Sky Huang ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -322,6 +322,12 @@ - nvmem-cell-names = "lvts-calib-data-1"; - }; - -+ phyfw: phy-firmware@f000000 { -+ compatible = "mediatek,2p5gphy-fw"; -+ reg = <0 0x0f100000 0 0x20000>, -+ <0 0x0f0f0018 0 0x20>; -+ }; -+ - usb@11190000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, diff --git a/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch deleted file mode 100644 index d634671ab5..0000000000 --- a/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch +++ /dev/null @@ -1,69 +0,0 @@ -From bf7c2ce439ca811dc1697b4bc19ab57bd8f13be3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:35 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add spi controllers - -Add SPI controllers for mt7988. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ - 1 file changed, 45 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -311,6 +311,51 @@ - status = "disabled"; - }; - -+ spi0: spi@11007000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11007000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI0>, -+ <&infracfg CLK_INFRA_66M_SPI0_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@11008000 { -+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; -+ reg = <0 0x11008000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI1>, -+ <&infracfg CLK_INFRA_66M_SPI1_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@11009000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11009000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI2_BCK>, -+ <&infracfg CLK_INFRA_66M_SPI2_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts-ap"; - #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch b/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch deleted file mode 100644 index 54d829c7d9..0000000000 --- a/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch +++ /dev/null @@ -1,90 +0,0 @@ -From b9ebd166b006f77cef4530b4bf4a291a112da4f2 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:36 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc - dtsi - -In order to use uart0 or spi1 there is only 1 possible pin definition -so move them to soc dtsi to reuse them in other boards and avoiding -conflict if defined twice. - -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-7-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ - 2 files changed, 18 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -328,13 +328,6 @@ - }; - }; - -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0"; -- }; -- }; -- - snfi_pins: snfi-pins { - mux { - function = "flash"; -@@ -356,13 +349,6 @@ - }; - }; - -- spi1_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1"; -- }; -- }; -- - spi2_pins: spi2-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -209,6 +209,20 @@ - "pcie_wake_n3_0"; - }; - }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; - }; - - pwm: pwm@10048000 { -@@ -244,6 +258,8 @@ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - -@@ -338,6 +354,8 @@ - "hclk"; - #address-cells = <1>; - #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - diff --git a/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch deleted file mode 100644 index 42a4aed2e2..0000000000 --- a/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0cbdb6d04689f8c05074e348c8e0a42b229ef9a3 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Jul 2025 15:22:03 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add cci node - -Add cci devicetree node for cpu frequency scaling. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250706132213.20412-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -12,6 +12,35 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ cci: cci { -+ compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; -+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cci", "intermediate"; -+ operating-points-v2 = <&cci_opp>; -+ }; -+ -+ cci_opp: opp-table-cci { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ opp-480000000 { -+ opp-hz = /bits/ 64 <480000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-660000000 { -+ opp-hz = /bits/ 64 <660000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1080000000 { -+ opp-hz = /bits/ 64 <1080000000>; -+ opp-microvolt = <900000>; -+ }; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -25,6 +54,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { -@@ -36,6 +66,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { -@@ -47,6 +78,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { -@@ -58,6 +90,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch b/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch deleted file mode 100644 index b657e221f6..0000000000 --- a/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e4950b016c727feb0c39ad12cfcb6182c9ef3814 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:38 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988: add phy calibration efuse - subnodes - -MT7988 contains buildin mt753x switch which needs calibration data from -efuse. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-9-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -702,6 +702,22 @@ - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; -+ -+ phy_calibration_p0: calib@940 { -+ reg = <0x940 0x10>; -+ }; -+ -+ phy_calibration_p1: calib@954 { -+ reg = <0x954 0x10>; -+ }; -+ -+ phy_calibration_p2: calib@968 { -+ reg = <0x968 0x10>; -+ }; -+ -+ phy_calibration_p3: calib@97c { -+ reg = <0x97c 0x10>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch b/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch deleted file mode 100644 index 15c8ad7ea0..0000000000 --- a/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch +++ /dev/null @@ -1,213 +0,0 @@ -From patchwork Sun May 11 14:19:24 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084161 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic - ethernet-nodes -Date: Sun, 11 May 2025 16:19:24 +0200 -Message-ID: <20250511141942.10284-9-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: 5c8e73b6-e2d6-4898-90c0-375604707c20 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add basic ethernet related nodes. - -Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked -later when driver is merged. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++- - 1 file changed, 121 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -686,7 +686,28 @@ - }; - }; - -- clock-controller@11f40000 { -+ xfi_tphy0: phy@11f20000 { -+ compatible = "mediatek,mt7988-xfi-tphy"; -+ reg = <0 0x11f20000 0 0x10000>; -+ resets = <&watchdog 14>; -+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, -+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; -+ clock-names = "xfipll", "topxtal"; -+ mediatek,usxgmii-performance-errata; -+ #phy-cells = <0>; -+ }; -+ -+ xfi_tphy1: phy@11f30000 { -+ compatible = "mediatek,mt7988-xfi-tphy"; -+ reg = <0 0x11f30000 0 0x10000>; -+ resets = <&watchdog 15>; -+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, -+ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; -+ clock-names = "xfipll", "topxtal"; -+ #phy-cells = <0>; -+ }; -+ -+ xfi_pll: clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; - resets = <&watchdog 16>; -@@ -720,19 +741,116 @@ - }; - }; - -- clock-controller@15000000 { -+ ethsys: clock-controller@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- clock-controller@15031000 { -+ ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7988-eth"; -+ reg = <0 0x15100000 0 0x80000>, -+ <0 0x15400000 0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, -+ <ðsys CLK_ETHDMA_FE_EN>, -+ <ðsys CLK_ETHDMA_GP2_EN>, -+ <ðsys CLK_ETHDMA_GP1_EN>, -+ <ðsys CLK_ETHDMA_GP3_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU2_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU1_EN>, -+ <ðwarp CLK_ETHWARP_WOCPU0_EN>, -+ <ðsys CLK_ETHDMA_ESW_EN>, -+ <&topckgen CLK_TOP_ETH_GMII_SEL>, -+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, -+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, -+ <&topckgen CLK_TOP_ETH_SYS_SEL>, -+ <&topckgen CLK_TOP_ETH_XGMII_SEL>, -+ <&topckgen CLK_TOP_ETH_MII_SEL>, -+ <&topckgen CLK_TOP_NETSYS_SEL>, -+ <&topckgen CLK_TOP_NETSYS_500M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, -+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, -+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>, -+ <ðsys CLK_ETHDMA_XGP1_EN>, -+ <ðsys CLK_ETHDMA_XGP2_EN>, -+ <ðsys CLK_ETHDMA_XGP3_EN>; -+ clock-names = "crypto", "fe", "gp2", "gp1", -+ "gp3", -+ "ethwarp_wocpu2", "ethwarp_wocpu1", -+ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", -+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", -+ "top_eth_sys_sel", "top_eth_xgmii_sel", -+ "top_eth_mii_sel", "top_netsys_sel", -+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel", -+ "top_netsys_sync_250m_sel", -+ "top_netsys_ppefb_250m_sel", -+ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; -+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, -+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>, -+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, -+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, -+ <&topckgen CLK_TOP_SGM_0_SEL>, -+ <&topckgen CLK_TOP_SGM_1_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, -+ <&topckgen CLK_TOP_NET1PLL_D4>, -+ <&topckgen CLK_TOP_NET1PLL_D8_D4>, -+ <&topckgen CLK_TOP_NET1PLL_D8_D4>, -+ <&apmixedsys CLK_APMIXED_SGMPLL>, -+ <&apmixedsys CLK_APMIXED_SGMPLL>; -+ mediatek,ethsys = <ðsys>; -+ mediatek,infracfg = <&topmisc>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "internal"; -+ -+ fixed-link { -+ speed = <10000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ status = "disabled"; -+ }; -+ -+ gmac2: mac@2 { -+ compatible = "mediatek,eth-mac"; -+ reg = <2>; -+ status = "disabled"; -+ }; -+ -+ mdio_bus: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* internal 2.5G PHY */ -+ int_2p5g_phy: ethernet-phy@f { -+ reg = <15>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ phy-mode = "internal"; -+ }; -+ }; -+ }; - }; - - thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch b/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch deleted file mode 100644 index de43734c26..0000000000 --- a/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch +++ /dev/null @@ -1,228 +0,0 @@ -From patchwork Sun May 11 14:19:25 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084123 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node -Date: Sun, 11 May 2025 16:19:25 +0200 -Message-ID: <20250511141942.10284-10-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: a24ecea1-b7fd-4cb4-a93d-b29036e2e6ac -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add mt7988 builtin mt753x switch nodes. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++ - 1 file changed, 166 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7988a"; -@@ -748,6 +749,159 @@ - #reset-cells = <1>; - }; - -+ switch: switch@15020000 { -+ compatible = "mediatek,mt7988-switch"; -+ reg = <0 0x15020000 0 0x8000>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_port0: port@0 { -+ reg = <0>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy0>; -+ }; -+ -+ gsw_port1: port@1 { -+ reg = <1>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy1>; -+ }; -+ -+ gsw_port2: port@2 { -+ reg = <2>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy2>; -+ }; -+ -+ gsw_port3: port@3 { -+ reg = <3>; -+ phy-mode = "internal"; -+ phy-handle = <&gsw_phy3>; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ ethernet = <&gmac0>; -+ phy-mode = "internal"; -+ -+ fixed-link { -+ speed = <10000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mediatek,pio = <&pio>; -+ -+ gsw_phy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ interrupts = <0>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p0>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy0_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy0_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupts = <1>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p1>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy1_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy1_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <2>; -+ interrupts = <2>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p2>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy2_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy2_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ gsw_phy3: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ interrupts = <3>; -+ phy-mode = "internal"; -+ nvmem-cells = <&phy_calibration_p3>; -+ nvmem-cell-names = "phy-cal-data"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gsw_phy3_led0: led@0 { -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ gsw_phy3_led1: led@1 { -+ reg = <1>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch b/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch deleted file mode 100644 index 9b616cebd1..0000000000 --- a/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 0f63e96e2ab422d1d35def1da75d3df299bf503e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:41 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps - -Add Fan and cooling maps for Bananapi-R4 board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -12,6 +12,15 @@ - stdout-path = "serial0:115200n8"; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ -+ cooling-levels = <0 80 128 255>; -+ #cooling-cells = <2>; -+ pwms = <&pwm 0 50000>; -+ status = "okay"; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; -@@ -73,6 +82,26 @@ - type = "active"; - }; - }; -+ -+ cooling-maps { -+ map-cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 3 3>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ map-cpu-active-med { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_med>; -+ }; -+ -+ map-cpu-active-low { -+ /* active: set fan to cooling level 0 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ }; - }; - - &i2c0 { diff --git a/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch b/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch deleted file mode 100644 index cffc02226b..0000000000 --- a/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6b7642e9d095d33d8034b8b396a2de9e5ecb25a7 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 16 May 2025 20:01:42 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes - -Configure and enable SPI nodes on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20250516180147.10416-13-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -401,6 +401,38 @@ - status = "okay"; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ -+ spi_nand: flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&spi1 { -+ status = "okay"; -+}; -+ -+&spi_nand { -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x200000>; -+ read-only; -+ }; -+ }; -+}; -+ - &ssusb1 { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch deleted file mode 100644 index 68858e76b0..0000000000 --- a/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b5a4ad957114b59a74b3e3f598ae0785dd86cd32 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Jul 2025 15:22:06 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci - -CCI requires proc-supply. Add it on board level. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20250706132213.20412-12-linux@fw-web.de -Signed-off-by: AngeloGioacchino Del Regno ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -40,6 +40,10 @@ - }; - }; - -+&cci { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &cpu0 { - proc-supply = <&rt5190_buck3>; - }; diff --git a/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch b/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch deleted file mode 100644 index 9861dc0f5b..0000000000 --- a/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch +++ /dev/null @@ -1,138 +0,0 @@ -From patchwork Sun May 11 14:26:53 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084128 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages - and link to gmac -Date: Sun, 11 May 2025 16:26:53 +0200 -Message-ID: <20250511142655.11007-4-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> -References: <20250511142655.11007-1-frank-w@public-files.de> -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the -wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP -variant. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 18 ++++++++++++++++++ - 3 files changed, 47 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -@@ -9,3 +9,14 @@ - model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; - chassis-type = "embedded"; - }; -+ -+&gmac1 { -+ phy-mode = "internal"; -+ phy-connection-type = "internal"; -+ phy = <&int_2p5g_phy>; -+}; -+ -+&int_2p5g_phy { -+ pinctrl-names = "i2p5gbe-led"; -+ pinctrl-0 = <&i2p5gbe_led0_pins>; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -8,6 +8,24 @@ - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - model = "Banana Pi BPI-R4 (2x SFP+)"; - chassis-type = "embedded"; -+ -+ /* SFP2 cage (LAN) */ -+ sfp2: sfp2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ }; -+}; -+ -+&gmac1 { -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; - }; - - &pca9545 { ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -38,6 +38,18 @@ - regulator-boot-on; - regulator-always-on; - }; -+ -+ /* SFP1 cage (WAN) */ -+ sfp1: sfp1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ }; - }; - - &cci { -@@ -108,6 +120,12 @@ - }; - }; - -+&gmac2 { -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch b/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch deleted file mode 100644 index 0bdc6c9a15..0000000000 --- a/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch +++ /dev/null @@ -1,113 +0,0 @@ -From patchwork Sun May 11 14:26:54 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084132 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 14/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure - switch phys and leds -Date: Sun, 11 May 2025 16:26:54 +0200 -Message-ID: <20250511142655.11007-5-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> -References: <20250511142655.11007-1-frank-w@public-files.de> -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -Assign pinctrl to switch phys and leds. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 40 +++++++++++++++++++ - 1 file changed, 40 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -126,6 +126,54 @@ - phy-mode = "usxgmii"; - }; - -+&gsw_phy0 { -+ pinctrl-names = "gbe-led"; -+ label = "wan"; -+ pinctrl-0 = <&gbe0_led0_pins>; -+}; -+ -+&gsw_phy0_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_WAN; -+ color = ; -+}; -+ -+&gsw_phy1 { -+ pinctrl-names = "gbe-led"; -+ label = "lan1"; -+ pinctrl-0 = <&gbe1_led0_pins>; -+}; -+ -+&gsw_phy1_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_phy2 { -+ pinctrl-names = "gbe-led"; -+ label = "lan2"; -+ pinctrl-0 = <&gbe2_led0_pins>; -+}; -+ -+&gsw_phy2_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_phy3 { -+ pinctrl-names = "gbe-led"; -+ label = "lan3"; -+ pinctrl-0 = <&gbe3_led0_pins>; -+}; -+ -+&gsw_phy3_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch b/target/linux/mediatek/patches-6.12/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch deleted file mode 100644 index efa2121812..0000000000 --- a/target/linux/mediatek/patches-6.12/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 109a9c8409f85d777f8ffa3fe145498a1fec0f1e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 8 May 2025 04:03:58 +0100 -Subject: [PATCH] arm64: dts: mt7988a: add serial1 and serial2 aliases - -Add aliases serial1 and serial2, so boards can make use of the -auxilary UARTs of the MediaTek MT7988 SoC. - -Signed-off-by: Daniel Golle ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -297,7 +297,7 @@ - status = "disabled"; - }; - -- serial@11000100 { -+ serial1: serial@11000100 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000100 0 0x100>; - interrupts = ; -@@ -308,7 +308,7 @@ - status = "disabled"; - }; - -- serial@11000200 { -+ serial2: serial@11000200 { - compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; - reg = <0 0x11000200 0 0x100>; - interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch b/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch deleted file mode 100644 index b7c609f0f5..0000000000 --- a/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch +++ /dev/null @@ -1,235 +0,0 @@ -From: Daniel Golle -Date: Thu, 26 Jun 2025 00:54:32 +0100 -Subject: [PATCH] arm64: dts: mt7988a: complete dtsi - -Work-in-progress patch to complete mt7988a.dtsi ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -193,7 +193,7 @@ - }; - - pio: pinctrl@1001f000 { -- compatible = "mediatek,mt7988-pinctrl"; -+ compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, -@@ -212,6 +212,13 @@ - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; -@@ -278,6 +285,60 @@ - status = "disabled"; - }; - -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7988-sgmiisys", -+ "mediatek,mt7988-sgmiisys0", -+ "syscon", -+ "simple-mfd"; -+ reg = <0 0x10060000 0 0x1000>; -+ resets = <&watchdog 1>; -+ #clock-cells = <1>; -+ -+ sgmiipcs0: pcs { -+ compatible = "mediatek,mt7988-sgmii"; -+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>, -+ <&sgmiisys0 CLK_SGM0_TX_EN>, -+ <&sgmiisys0 CLK_SGM0_RX_EN>; -+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; -+ #pcs-cells = <0>; -+ }; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7988-sgmiisys", -+ "mediatek,mt7988-sgmiisys1", -+ "syscon", -+ "simple-mfd"; -+ reg = <0 0x10070000 0 0x1000>; -+ resets = <&watchdog 2>; -+ #clock-cells = <1>; -+ -+ sgmiipcs1: pcs { -+ compatible = "mediatek,mt7988-sgmii"; -+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>, -+ <&sgmiisys1 CLK_SGM1_TX_EN>, -+ <&sgmiisys1 CLK_SGM1_RX_EN>; -+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; -+ #pcs-cells = <0>; -+ }; -+ }; -+ -+ usxgmiisys0: pcs@10080000 { -+ compatible = "mediatek,mt7988-usxgmiisys"; -+ reg = <0 0x10080000 0 0x1000>; -+ resets = <&watchdog 12>; -+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; -+ #pcs-cells = <0>; -+ }; -+ -+ usxgmiisys1: pcs@10081000 { -+ compatible = "mediatek,mt7988-usxgmiisys"; -+ reg = <0 0x10081000 0 0x1000>; -+ resets = <&watchdog 13>; -+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; -+ #pcs-cells = <0>; -+ }; -+ - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; -@@ -319,6 +380,32 @@ - status = "disabled"; - }; - -+ snand: spi@11001000 { -+ compatible = "mediatek,mt7986-snand"; -+ reg = <0 0x11001000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_SPINFI>, -+ <&infracfg CLK_INFRA_NFI>, -+ <&infracfg CLK_INFRA_66M_NFI_HCK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ nand-ecc-engine = <&bch>; -+ mediatek,quad-spi; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&snfi_pins>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@11002000 { -+ compatible = "mediatek,mt7686-ecc"; -+ reg = <0 0x11002000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_NFI>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, -@@ -425,7 +512,7 @@ - <0 0x0f0f0018 0 0x20>; - }; - -- usb@11190000 { -+ ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; -@@ -459,6 +546,35 @@ - status = "disabled"; - }; - -+ afe: audio-controller@11210000 { -+ compatible = "mediatek,mt79xx-audio"; -+ reg = <0 0x11210000 0 0x9000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, -+ <&infracfg CLK_INFRA_AUD_26M>, -+ <&infracfg CLK_INFRA_AUD_L>, -+ <&infracfg CLK_INFRA_AUD_AUD>, -+ <&infracfg CLK_INFRA_AUD_EG2>, -+ <&topckgen CLK_TOP_AUD_SEL>, -+ <&topckgen CLK_TOP_AUD_I2S_M>; -+ clock-names = "aud_bus_ck", -+ "aud_26m_ck", -+ "aud_l_ck", -+ "aud_aud_ck", -+ "aud_eg2_ck", -+ "aud_sel", -+ "aud_i2s_m"; -+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, -+ <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>, -+ <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ status = "disabled"; -+ }; -+ - mmc0: mmc@11230000 { - compatible = "mediatek,mt7988-mmc"; - reg = <0 0x11230000 0 0x1000>, -@@ -721,6 +837,10 @@ - #address-cells = <1>; - #size-cells = <1>; - -+ cpufreq_calibration: calib@278 { -+ reg = <0x278 0x1>; -+ }; -+ - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; -@@ -984,12 +1104,16 @@ - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; -+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; -+ phys = <&xfi_tphy1>; - status = "disabled"; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; -+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; -+ phys = <&xfi_tphy0>; - status = "disabled"; - }; - -@@ -1002,9 +1126,37 @@ - reg = <15>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2p5gbe_led0: i2p5gbe-led0@0 { -+ reg = <0>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ -+ i2p5gbe_led1: i2p5gbe-led1@1 { -+ reg = <1>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ }; - }; - }; - }; -+ -+ crypto: crypto@15600000 { -+ compatible = "inside-secure,safexcel-eip197b"; -+ reg = <0 0x15600000 0 0x180000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ status = "okay"; -+ }; - }; - - thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch b/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch deleted file mode 100644 index 9e89a192d1..0000000000 --- a/target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0c74ae06ed6b6c9627712a74ecee4e61bbd4092d Mon Sep 17 00:00:00 2001 -From: developer -Date: Mon, 19 Jan 2026 21:42:29 +0800 -Subject: [PATCH] arm64: dts: mediatek: fix mt7981 spim clock - -1) Add spi0/1/2 clock parent setting -2) Fix spi1 clock_sel to CLK_TOP_SPIM_MST_SEL - -Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/836034ca0baad57e4c287a62ccc5677c60be0e18 -Signed-off-by: Shiji Yang ---- - arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi -@@ -223,6 +223,10 @@ - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; -+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_SPI2_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; -@@ -237,6 +241,10 @@ - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; -+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_SPI0_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; -@@ -248,9 +256,13 @@ - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, -- <&topckgen CLK_TOP_SPI_SEL>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; -+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_SPI1_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch deleted file mode 100644 index 0e0236c5fc..0000000000 --- a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch +++ /dev/null @@ -1,1293 +0,0 @@ -From bb72bb160130c35fa4b7dedd0f881085f0af1313 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 22 Feb 2023 19:15:49 +0000 -Subject: [PATCH 31/32] dts: arm64: mediatek: add MT7988A reference board - device tree - -Complete device tree include for the MediaTek MT7988A SoC and make use -of it by adding the device tree of the MediaTek MT7988A Reference Board -as well as overlays for various options regarding the connected -network interfaces and storage devices present. - -Available options for GMAC1 (eth0): - * internal 4-port 1GE switch - -Available options for GMAC2 (eth1): - * internal 2.5G PHY - * external MaxLinear 2.5G PHY - * external Aquantia AQR113C PHY - * SFP+ cage - -Available options for GMAC3 (eth2): - * external MaxLinear 2.5G PHY - * external Aquantia AQR113C PHY - * SFP+ cage - -Available storage options: - * eMMC - * SNFI (ECC-less SPI-NAND with BCH done in SoC) - * SPI-NAND (with ECC done by the flash die) - * SPI-NOR - * SD card - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -24,6 +24,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-aqr.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-i2p5g-phy.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-mxl.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-sfp.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-aqr.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-mxl.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-sfp.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-sd.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-snfi-nand.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nand.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nor.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso -@@ -0,0 +1,62 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&mmc0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_emmc_51>; -+ pinctrl-1 = <&mmc0_pins_emmc_51>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x12814>; -+ vqmmc-supply = <®_1p8v>; -+ vmmc-supply = <®_3p3v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ -+ emmc_root: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-emmc = <&emmc_root>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso -@@ -0,0 +1,41 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&mdio_bus>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* external Aquantia AQR113C */ -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <100000>; -+ reset-deassert-us = <221000>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gmac1>; -+ __overlay__ { -+ phy-mode = "usxgmii"; -+ phy-connection-type = "usxgmii"; -+ phy = <&phy0>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&gmac1>; -+ __overlay__ { -+ phy-mode = "internal"; -+ phy-connection-type = "internal"; -+ phy = <&int_2p5g_phy>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&int_2p5g_phy>; -+ __overlay__ { -+ pinctrl-names = "i2p5gbe-led"; -+ pinctrl-0 = <&i2p5gbe_led0_pins>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&mdio_bus>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* external Maxlinear GPY211C */ -+ phy13: ethernet-phy@13 { -+ reg = <13>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ phy-mode = "2500base-x"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gmac1>; -+ __overlay__ { -+ phy-mode = "2500base-x"; -+ phy-connection-type = "2500base-x"; -+ phy = <&phy13>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&i2c2>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/"; -+ __overlay__ { -+ sfp_esp1: sfp@1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c2>; -+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; -+ los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; -+ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; -+ maximum-power-milliwatt = <3000>; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&gmac1>; -+ __overlay__ { -+ phy-mode = "10gbase-r"; -+ managed = "in-band-status"; -+ sfp = <&sfp_esp1>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso -@@ -0,0 +1,41 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&mdio_bus>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* external Aquantia AQR113C */ -+ phy8: ethernet-phy@8 { -+ reg = <8>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <100000>; -+ reset-deassert-us = <221000>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gmac2>; -+ __overlay__ { -+ phy-mode = "usxgmii"; -+ phy-connection-type = "usxgmii"; -+ phy = <&phy8>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&mdio_bus>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* external Maxlinear GPY211C */ -+ phy5: ethernet-phy@5 { -+ reg = <5>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ phy-mode = "2500base-x"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gmac2>; -+ __overlay__ { -+ phy-mode = "2500base-x"; -+ phy-connection-type = "2500base-x"; -+ phy = <&phy5>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&i2c1>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/"; -+ __overlay__ { -+ sfp_esp0: sfp@0 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c1>; -+ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; -+ los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; -+ tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; -+ maximum-power-milliwatt = <3000>; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&gmac2>; -+ __overlay__ { -+ phy-mode = "10gbase-r"; -+ managed = "in-band-status"; -+ sfp = <&sfp_esp0>; -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target-path = <&mmc0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_sdcard>; -+ pinctrl-1 = <&mmc0_pins_sdcard>; -+ cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ no-mmc; -+ status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ -+ sd_root: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-sd = <&sd_root>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso -@@ -0,0 +1,85 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&snand>; -+ __overlay__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00000 0x0200000>; -+ read-only; -+ }; -+ -+ ubi_part: partition@200000 { -+ label = "ubi"; -+ reg = <0x0200000 0x7e00000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ ubi-volume-ubootenv { -+ volname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ ubi-volume-ubootenv2 { -+ volname = "ubootenv2"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ snfi_root: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&bch>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target-path = "/chosen"; -+ __overlay__ { -+ /* -+ * U-Boot currently cannot detect diffrentiate between -+ * SD and SNFI boot media and always uses rootdisk-sd in -+ * both cases -+ */ -+ rootdisk-sd = <&snfi_root>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso -@@ -0,0 +1,87 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&ubi_part>; -+ -+ __overlay__ { -+ volumes { -+ ubi_factory: ubi-volume-factory { -+ volname = "factory"; -+ -+ nvmem-layout { -+ compatible = "fixed-layout"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ eeprom_wmac: eeprom@0 { -+ reg = <0x0 0x1e00>; -+ }; -+ -+ gmac2_mac: eeprom@fffee { -+ reg = <0xfffee 0x6>; -+ }; -+ -+ gmac1_mac: eeprom@ffff4 { -+ reg = <0xffff4 0x6>; -+ }; -+ -+ gmac0_mac: eeprom@ffffa { -+ reg = <0xffffa 0x6>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&pcie0>; -+ __overlay__ { -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ wifi@0,0 { -+ compatible = "mediatek,mt76"; -+ reg = <0x0000 0 0 0 0>; -+ nvmem-cell-names = "eeprom"; -+ nvmem-cells = <&eeprom_wmac>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&gmac0>; -+ __overlay__ { -+ nvmem-cell-names = "mac-address"; -+ nvmem-cells = <&gmac0_mac>; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&gmac1>; -+ __overlay__ { -+ nvmem-cell-names = "mac-address"; -+ nvmem-cells = <&gmac1_mac>; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&gmac2>; -+ __overlay__ { -+ nvmem-cell-names = "mac-address"; -+ nvmem-cells = <&gmac2_mac>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00000 0x0200000>; -+ read-only; -+ }; -+ -+ ubi_part: partition@200000 { -+ label = "ubi"; -+ reg = <0x0200000 0x7e00000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ ubi-volume-ubootenv { -+ volname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ ubi-volume-ubootenv2 { -+ volname = "ubootenv2"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ ubi_root: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-spim-nand = <&ubi_root>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&spi2>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_flash_pins>; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-cal-enable; -+ spi-cal-mode = "read-data"; -+ spi-cal-datalen = <7>; -+ spi-cal-data = /bits/ 8 < -+ 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ -+ spi-cal-addrlen = <1>; -+ spi-cal-addr = /bits/ 32 <0x0>; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x0 0x40000>; -+ }; -+ partition@40000 { -+ label = "u-boot-env"; -+ reg = <0x40000 0x10000>; -+ }; -+ partition@50000 { -+ label = "Factory"; -+ reg = <0x50000 0x200000>; -+ }; -+ partition@250000 { -+ label = "FIP"; -+ reg = <0x250000 0x80000>; -+ }; -+ nor_root: partition@2D0000 { -+ label = "firmware"; -+ reg = <0x2d0000 0x1d30000>; -+ compatible = "denx,fit"; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-nor = <&nor_root>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts -@@ -0,0 +1,471 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+ -+#include "mt7988a.dtsi" -+ -+/ { -+ model = "MediaTek MT7988A Reference Board"; -+ compatible = "mediatek,mt7988a-rfb", -+ "mediatek,mt7988a"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n1 \ -+ earlycon=uart8250,mmio32,0x11000000 \ -+ pci=pcie_bus_perf"; -+ }; -+ -+ memory@40000000 { -+ reg = <0 0x40000000 0 0x40000000>; -+ device_type = "memory"; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+ð { -+ pinctrl-0 = <&mdio0_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&gmac0 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu1 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu2 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cpu3 { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+&cci { -+ proc-supply = <&rt5190_buck3>; -+}; -+ -+ð { -+ status = "okay"; -+}; -+ -+&switch { -+ status = "okay"; -+}; -+ -+&gsw_phy0 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe0_led0_pins>; -+}; -+ -+&gsw_phy0_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_port0 { -+ label = "lan0"; -+}; -+ -+&gsw_phy1 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe1_led0_pins>; -+}; -+ -+&gsw_phy1_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_port1 { -+ label = "lan1"; -+}; -+ -+&gsw_phy2 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe2_led0_pins>; -+}; -+ -+&gsw_phy2_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_port2 { -+ label = "lan2"; -+}; -+ -+&gsw_phy3 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe3_led0_pins>; -+}; -+ -+&gsw_phy3_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_port3 { -+ label = "lan3"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+ -+ rt5190a_64: rt5190a@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = -+ ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ buck2 { -+ regulator-name = "vcore"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ rt5190_buck3: buck3 { -+ regulator-name = "vproc"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-allowed-modes = -+ ; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2 { -+ status = "disabled"; -+}; -+ -+&pcie3 { -+ status = "okay"; -+}; -+ -+&pio { -+ mdio0_pins: mdio0-pins { -+ mux { -+ function = "eth"; -+ groups = "mdc_mdio0"; -+ }; -+ -+ conf { -+ groups = "mdc_mdio0"; -+ drive-strength = ; -+ }; -+ }; -+ -+ gbe0_led0_pins: gbe0-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led0"; -+ }; -+ }; -+ -+ gbe1_led0_pins: gbe1-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led0"; -+ }; -+ }; -+ -+ gbe2_led0_pins: gbe2-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led0"; -+ }; -+ }; -+ -+ gbe3_led0_pins: gbe3-led0-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led0"; -+ }; -+ }; -+ -+ gbe0_led1_pins: gbe0-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe0_led1"; -+ }; -+ }; -+ -+ gbe1_led1_pins: gbe1-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe1_led1"; -+ }; -+ }; -+ -+ gbe2_led1_pins: gbe2-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe2_led1"; -+ }; -+ }; -+ -+ gbe3_led1_pins: gbe3-led1-pins { -+ mux { -+ function = "led"; -+ groups = "gbe3_led1"; -+ }; -+ }; -+ -+ i2c0_pins: i2c0-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c0_1"; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ i2c1_sfp_pins: i2c1-sfp-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_sfp"; -+ }; -+ }; -+ -+ i2c2_0_pins: i2c2-g0-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_0"; -+ }; -+ }; -+ -+ i2c2_1_pins: i2c2-g1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c2_1"; -+ }; -+ }; -+ -+ i2p5gbe_led0_pins: 2p5gbe-led0-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led0"; -+ }; -+ }; -+ -+ i2p5gbe_led1_pins: 2p5gbe-led1-pins { -+ mux { -+ function = "led"; -+ groups = "2p5gbe_led1"; -+ }; -+ }; -+ -+ mmc0_pins_emmc_51: mmc0-emmc-51-pins { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ }; -+ -+ mmc0_pins_sdcard: mmc0-sdcard-pins { -+ mux { -+ function = "flash"; -+ groups = "sdcard"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2"; -+ }; -+ }; -+ -+ spi2_flash_pins: spi2-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; -+ -+ uart1_0_pins: uart1-0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_0"; -+ }; -+ }; -+ -+ uart1_1_pins: uart1-1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_1"; -+ }; -+ }; -+ -+ uart1_2_pins: uart1-2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_2"; -+ }; -+ }; -+ -+ uart1_2_lite_pins: uart1-2-lite-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_2_lite"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2"; -+ }; -+ }; -+ -+ uart2_0_pins: uart2-0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_0"; -+ }; -+ }; -+ -+ uart2_1_pins: uart2-1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_1"; -+ }; -+ }; -+ -+ uart2_2_pins: uart2-2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_2"; -+ }; -+ }; -+ -+ uart2_3_pins: uart2-3-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_3"; -+ }; -+ }; -+}; -+ -+&ssusb0 { -+ status = "okay"; -+}; -+ -+&ssusb1 { -+ status = "okay"; -+}; -+ -+&tphy { -+ status = "okay"; -+}; -+ -+&serial0 { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+&xsphy { -+ status = "okay"; -+}; diff --git a/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch b/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch deleted file mode 100644 index 8eccb6f8f1..0000000000 --- a/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch +++ /dev/null @@ -1,488 +0,0 @@ -From f7fb27b62f0ef45f94f4ec33c608bfad1c7691b3 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 26 Jul 2023 14:56:28 +0100 -Subject: [PATCH 32/32] WIP: add BPi-R4 - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts -@@ -20,3 +20,16 @@ - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - }; -+ -+&gmac1 { -+ phy-mode = "internal"; -+ phy-connection-type = "internal"; -+ phy = <&int_2p5g_phy>; -+ openwrt,netdev-name = "lan4"; -+ status = "okay"; -+}; -+ -+&int_2p5g_phy { -+ pinctrl-names = "i2p5gbe-led"; -+ pinctrl-0 = <&i2p5gbe_led0_pins>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso -@@ -0,0 +1,56 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+}; -+ -+&{/soc/mmc@11230000} { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_emmc_51>; -+ pinctrl-1 = <&mmc0_pins_emmc_51>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x12814>; -+ vqmmc-supply = <®_1p8v>; -+ vmmc-supply = <®_3p3v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ -+ emmc_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+}; -+ -+&{/chosen} { -+ rootdisk-emmc = <&emmc_rootfs>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 -+ * Author: Daniel Golle -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+ -+ fragment@0 { -+ target = <&pcf8563>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ * Author: Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+}; -+ -+&{/soc/mmc@11230000} { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_sdcard>; -+ pinctrl-1 = <&mmc0_pins_sdcard>; -+ cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ no-mmc; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ -+ sd_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+}; -+ -+&{/chosen} { -+ rootdisk-sd = <&sd_rootfs>; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts -@@ -35,3 +35,11 @@ - reg = <2>; - }; - }; -+ -+&gmac1 { -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; -+ openwrt,netdev-name = "sfp-lan"; -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -3,6 +3,8 @@ - /dts-v1/; - - #include -+#include -+#include - #include - - #include "mt7988a.dtsi" -@@ -10,6 +12,8 @@ - / { - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "console=ttyS0,115200n1 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; -+ rootdisk-spim-nand = <&ubi_rootfs>; - }; - - fan: pwm-fan { -@@ -50,6 +54,142 @@ - rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; -+ -+ aliases { -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ ethernet2 = &gmac2; -+ serial0 = &serial0; -+ led-boot = &led_green; -+ led-failsafe = &led_green; -+ led-running = &led_green; -+ led-upgrade = &led_green; -+ }; -+ -+ memory@40000000 { -+ reg = <0x00 0x40000000 0x00 0x10000000>; -+ device_type = "memory"; -+ }; -+ -+ /* SFP1 cage (WAN) */ -+ sfp1: sfp1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&pio 14 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ led_green: led-green { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ led_blue: led-blue { -+ function = LED_FUNCTION_WPS; -+ color = ; -+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+}; -+ -+ð { -+ status = "okay"; -+}; -+ -+&gmac0 { -+ status = "okay"; -+}; -+ -+&gmac2 { -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ phy-mode = "usxgmii"; -+ openwrt,netdev-name = "sfp-wan"; -+ status = "okay"; -+}; -+ -+&switch { -+ status = "okay"; -+}; -+ -+&gsw_phy0 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe0_led0_pins>; -+}; -+ -+&gsw_port0 { -+ label = "wan"; -+}; -+ -+&gsw_phy0_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_WAN; -+ color = ; -+}; -+ -+&gsw_phy1 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe1_led0_pins>; -+}; -+ -+&gsw_port1 { -+ label = "lan1"; -+}; -+ -+&gsw_phy1_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_phy2 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe2_led0_pins>; -+}; -+ -+&gsw_port2 { -+ label = "lan2"; -+}; -+ -+&gsw_phy2_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; -+}; -+ -+&gsw_phy3 { -+ pinctrl-names = "gbe-led"; -+ pinctrl-0 = <&gbe3_led0_pins>; -+}; -+ -+&gsw_port3 { -+ label = "lan3"; -+}; -+ -+&gsw_phy3_led0 { -+ status = "okay"; -+ function = LED_FUNCTION_LAN; -+ color = ; - }; - - &cci { -@@ -174,6 +314,10 @@ - color = ; - }; - -+&cci { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -@@ -265,6 +409,14 @@ - #size-cells = <0>; - reg = <1>; - }; -+ -+ i2c_wifi: i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ -+ status = "disabled"; -+ }; - }; - }; - -@@ -364,34 +516,6 @@ - }; - }; - -- gbe0_led1_pins: gbe0-led1-pins { -- mux { -- function = "led"; -- groups = "gbe0_led1"; -- }; -- }; -- -- gbe1_led1_pins: gbe1-led1-pins { -- mux { -- function = "led"; -- groups = "gbe1_led1"; -- }; -- }; -- -- gbe2_led1_pins: gbe2-led1-pins { -- mux { -- function = "led"; -- groups = "gbe2_led1"; -- }; -- }; -- -- gbe3_led1_pins: gbe3-led1-pins { -- mux { -- function = "led"; -- groups = "gbe3_led1"; -- }; -- }; -- - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; -@@ -399,13 +523,6 @@ - }; - }; - -- i2p5gbe_led1_pins: 2p5gbe-led1-pins { -- mux { -- function = "led"; -- groups = "2p5gbe_led1"; -- }; -- }; -- - mmc0_pins_emmc_45: mmc0-emmc-45-pins { - mux { - function = "flash"; -@@ -427,40 +544,12 @@ - }; - }; - -- snfi_pins: snfi-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spi0_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0"; -- }; -- }; -- - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; -- -- spi2_pins: spi2-pins { -- mux { -- function = "spi"; -- groups = "spi2"; -- }; -- }; -- -- spi2_flash_pins: spi2-flash-pins { -- mux { -- function = "spi"; -- groups = "spi2", "spi2_wp_hold"; -- }; -- }; - }; - - &pwm { -@@ -500,6 +589,32 @@ - reg = <0x0 0x200000>; - read-only; - }; -+ -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x200000 0x7e00000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ ubi-volume-ubootenv { -+ volname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool-layout"; -+ }; -+ }; -+ -+ ubi-volume-ubootenv2 { -+ volname = "ubootenv2"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool-layout"; -+ }; -+ }; -+ -+ ubi_rootfs: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch deleted file mode 100644 index bf6823147e..0000000000 --- a/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ /dev/null @@ -1,106 +0,0 @@ -From patchwork Tue Apr 26 19:51:36 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 12827872 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF - for ; 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Tue, 26 Apr 2022 19:51:57 +0000 -Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 -Received: from local - by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) - (Exim 4.94.2) (envelope-from ) - id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 -Date: Tue, 26 Apr 2022 20:51:36 +0100 -From: Daniel Golle -To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, - linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org -Cc: Rob Herring , - Krzysztof Kozlowski , - Matthias Brugger -Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C -X-CRM114-Status: GOOD ( 12.45 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -With the current range specified for the CPU interface there is an -error message at boot: - -GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set - -Setting irqchip.gicv2_force_probe=1 in bootargs results in: - -GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB -GIC: Adjusting CPU interface base to 0x000000001032f000 -GIC: Using split EOI/Deactivate mode - -Using the adjusted CPU interface base and 8K size results in only the -final line remaining and fully working system as well as /proc/interrupts -showing additional IPI3,4,5,6: - -IPI3: 0 0 CPU stop (for crash dump) interrupts -IPI4: 0 0 Timer broadcast interrupts -IPI5: 0 0 IRQ work interrupts -IPI6: 0 0 CPU wake-up interrupts - -Signed-off-by: Daniel Golle ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -345,7 +345,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, -- <0 0x10320000 0 0x1000>, -+ <0 0x1032f000 0 0x2000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; diff --git a/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch deleted file mode 100644 index da9ba5f305..0000000000 --- a/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 -From: Bruno Umuarama -Date: Thu, 13 Oct 2022 21:18:21 +0000 -Subject: [PATCH] mediatek: mt7623: fix thermal zone -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Raising the temperatures for passive and active trips. @VA1DER -proposed at issue 9396 to remove passive trip. This commit relates to -his suggestion. - -Without this patch. the CPU will be throttled all the way down to 98MHz -if the temperature rises even a degree above the trip point, and it was -further discovered that if the internal temperature of the device is -above the first trip point temperature when it boots then it will start -in a throttled state and even -$ echo disabled > /sys/class/thermal/thermal_zone0/mode -will have no effect. - -The patch increases the passive trip point and active cooling map. The -throttling temperature will then be at 77°C and 82°C, which is still a -low enough temperature for ARM devices to not be in the real danger -zone, and gives some operational headroom. - -Signed-off-by: Bruno Umuarama ---- - arch/arm/boot/dts/mediatek/mt7623.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/mediatek/mt7623.dtsi -+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi -@@ -160,13 +160,13 @@ - - trips { - cpu_passive: cpu-passive { -- temperature = <57000>; -+ temperature = <77000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { -- temperature = <67000>; -+ temperature = <82000>; - hysteresis = <2000>; - type = "active"; - }; diff --git a/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch deleted file mode 100644 index 680c90a0f2..0000000000 --- a/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch +++ /dev/null @@ -1,27 +0,0 @@ -From e1adb1fa39dd5ef97280ad1b2bb9e8ff4c43674f Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 7 May 2021 16:53:09 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7986a: reserve memory for ramoops/pstore - -Reserve 64 KiB of memory at 0x42ff0000 in the MT7986a DTSI for the -ramoops/pstore driver so that kernel crash logs survive a reboot. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -68,6 +68,14 @@ - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch deleted file mode 100644 index 2554f88317..0000000000 --- a/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 7a0ec001ff79b12beefb8f3773820bfedebbb340 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 4 Jun 2023 15:56:15 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7986a-bpi-r3: fix LED/LAN port naming and wire WiFi EEPROM - -Add led-boot/led-failsafe/led-running/led-upgrade aliases pointing to -the green and blue system LEDs, renumber the switch LAN port labels from -lan0/lan1/lan2 to lan1/lan2/lan3 to match the board silkscreen, and wire -the built-in WiFi EEPROM from the factory partition. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -23,6 +23,10 @@ - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; -+ led-boot = &green_led; -+ led-failsafe = &green_led; -+ led-running = &green_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -418,27 +422,27 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port5: port@5 { - reg = <5>; -- label = "lan4"; -+ label = "sfp2"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; -@@ -489,9 +493,137 @@ - - &wifi { - status = "okay"; -- pinctrl-names = "default", "dbdc"; -+ pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 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0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - - led { - led-active-low; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -55,6 +55,7 @@ - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; -+ compatible = "denx,fit"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch deleted file mode 100644 index f2d1967934..0000000000 --- a/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 61137a88952e125c574aa35209fd581591d8796a Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 18 Jan 2024 22:15:35 +0000 -Subject: [PATCH] arm64: dts: mediatek: mt7986a-bpi-r3: add fitblk rootdisk for eMMC and NAND overlays - -Add GPT block partition and mmc-card nodes to the eMMC dtso overlay so -that fitblk can find the production partition via /chosen/rootdisk-emmc, -and update the NAND dtso overlay to wire up the UBI volume used as the -root filesystem via /chosen/rootdisk-nand. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -@@ -21,5 +21,24 @@ - non-removable; - no-sd; - no-sdio; -+ #address-cells = <1>; -+ #size-cells = <0>; - status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ emmc_rootdisk: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+}; -+ -+&{/chosen} { -+ rootdisk-emmc = <&emmc_rootdisk>; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -29,25 +29,24 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x100000>; -- read-only; -+ reg = <0x0 0x200000>; - }; - -- partition@100000 { -- label = "reserved"; -- reg = <0x100000 0x280000>; -- }; -- -- partition@380000 { -- label = "fip"; -- reg = <0x380000 0x200000>; -- read-only; -- }; -- -- partition@580000 { -+ partition@200000 { - label = "ubi"; -- reg = <0x580000 0x7a80000>; -+ reg = <0x200000 0x7e00000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ nand_rootdisk: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; - }; - }; - }; - }; -+ -+&{/chosen} { -+ rootdisk-spim-nand = <&nand_rootdisk>; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -52,7 +52,7 @@ - reg = <0x180000 0xa80000>; - }; - -- partition@c00000 { -+ nor_rootdisk: partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - compatible = "denx,fit"; -@@ -60,3 +60,7 @@ - }; - }; - }; -+ -+&{/chosen} { -+ rootdisk-nor = <&nor_rootdisk>; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -@@ -15,5 +15,24 @@ - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; -+ #address-cells = <1>; -+ #size-cells = <0>; - status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ partitions { -+ compatible = "gpt-partitions"; -+ -+ sd_rootdisk: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+}; -+ -+&{/chosen} { -+ rootdisk-sd = <&sd_rootdisk>; - }; diff --git a/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch b/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch deleted file mode 100644 index 45ae596256..0000000000 --- a/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch +++ /dev/null @@ -1,177 +0,0 @@ -From 4dd35ca6747a57261f3b10982a4a8cc765d6549f Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Thu, 17 Jul 2025 18:45:48 +0200 -Subject: [PATCH] target: mediatek: Enable WED for MT7988 devices running 6.12.x kernels - -Add WED related nodes to the device tree of the MT7988 SoC family. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -145,6 +145,32 @@ - reg = <0 0x43000000 0 0x50000>; - no-map; - }; -+ -+ wmcpu_emi: wmcpu-reserved@47cc0000 { -+ reg = <0 0x47cc0000 0 0x00100000>; -+ no-map; -+ }; -+ -+ wo_emi0: wo-emi@4f600000 { -+ reg = <0 0x4f600000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_emi1: wo-emi@4f640000 { -+ reg = <0 0x4f640000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_emi2: wo-emi@4f680000 { -+ reg = <0 0x4f680000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_data: wo-data@4f700000 { -+ reg = <0 0x4f700000 0 0x800000>; -+ no-map; -+ shared = <1>; -+ }; - }; - - soc { -@@ -867,6 +893,50 @@ - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ -+ wed0: wed@15010000 { -+ compatible = "mediatek,mt7988-wed", -+ "syscon"; -+ reg = <0 0x15010000 0 0x2000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; -+ mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot0>; -+ }; -+ -+ wed1: wed@15012000 { -+ compatible = "mediatek,mt7988-wed", -+ "syscon"; -+ reg = <0 0x15012000 0 0x2000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; -+ mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot1>; -+ }; -+ -+ wed2: wed@15014000 { -+ compatible = "mediatek,mt7988-wed", -+ "syscon"; -+ reg = <0 0x15014000 0 0x2000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ memory-region = <&wo_emi2>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; -+ mediatek,wo-ccif = <&wo_ccif2>; -+ mediatek,wo-ilm = <&wo_ilm2>; -+ mediatek,wo-dlm = <&wo_dlm2>; -+ mediatek,wo-cpuboot = <&wo_cpuboot2>; - }; - - switch: switch@15020000 { -@@ -1086,6 +1156,7 @@ - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,infracfg = <&topmisc>; -+ mediatek,wed = <&wed0>, <&wed1>, <&wed2>; - #address-cells = <1>; - #size-cells = <0>; - -@@ -1147,6 +1218,72 @@ - }; - }; - -+ wo_ccif0: syscon@151a5000 { -+ compatible = "mediatek,mt7988-wo-ccif", "syscon"; -+ reg = <0 0x151a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ccif1: syscon@152a5000 { -+ compatible = "mediatek,mt7988-wo-ccif", "syscon"; -+ reg = <0 0x152a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ccif2: syscon@153a5000 { -+ compatible = "mediatek,mt7988-wo-ccif", "syscon"; -+ reg = <0 0x153a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7988-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@152e0000 { -+ compatible = "mediatek,mt7988-wo-ilm", "syscon"; -+ reg = <0 0x152e0000 0 0x8000>; -+ }; -+ -+ wo_ilm2: syscon@153e0000 { -+ compatible = "mediatek,mt7988-wo-ilm", "syscon"; -+ reg = <0 0x153e0000 0 0x8000>; -+ }; -+ -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7988-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@152e8000 { -+ compatible = "mediatek,mt7988-wo-dlm", "syscon"; -+ reg = <0 0x152e8000 0 0x2000>; -+ }; -+ -+ wo_dlm2: syscon@153e8000 { -+ compatible = "mediatek,mt7988-wo-dlm", "syscon"; -+ reg = <0 0x153e8000 0 0x2000>; -+ }; -+ -+ wo_cpuboot0: syscon@15194000 { -+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ -+ wo_cpuboot1: syscon@15294000 { -+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; -+ reg = <0 0x15294000 0 0x1000>; -+ }; -+ -+ wo_cpuboot2: syscon@15394000 { -+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon"; -+ reg = <0 0x15394000 0 0x1000>; -+ }; -+ - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; diff --git a/target/linux/mediatek/patches-6.12/199-arm64-dts-mediatek-mt7986-increase-ATF-reserved-memo.patch b/target/linux/mediatek/patches-6.12/199-arm64-dts-mediatek-mt7986-increase-ATF-reserved-memo.patch deleted file mode 100644 index 8cef5ba442..0000000000 --- a/target/linux/mediatek/patches-6.12/199-arm64-dts-mediatek-mt7986-increase-ATF-reserved-memo.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 236317dd4e55512933dcdaec3d0b4a0824f5e5bd Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Sun, 10 Aug 2025 18:11:01 +0800 -Subject: [PATCH] arm64: dts: mediatek: mt7986: increase ATF reserved memory to - 256 kiB - -The latest Mediatek open-source Trusted Firmware-A project has -reserved 256 KiB for BL2 and BL31. It is better to increase the -reserved memory region in the Linux kernel to protect the data. - -Signed-off-by: Shiji Yang ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -76,9 +76,9 @@ - record-size = <0x1000>; - }; - -- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ -+ /* 256 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */ - secmon_reserved: secmon@43000000 { -- reg = <0 0x43000000 0 0x30000>; -+ reg = <0 0x43000000 0 0x40000>; - no-map; - }; - diff --git a/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 5c482f6358..0000000000 --- a/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -18,6 +18,8 @@ - #include - #include - #include -+#include -+#include - - #include "phy-mtk-io.h" - -@@ -271,6 +273,9 @@ - - #define USER_BUF_LEN(count) min_t(size_t, 8, (count)) - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -339,6 +344,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -973,6 +979,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | -@@ -1621,6 +1631,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } - -+ if (of_property_present(np, "mediatek,phy-switch")) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node_scoped(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-6.12/210-PM-devfreq-mtk-cci-use-devres-for-resource-managemen.patch b/target/linux/mediatek/patches-6.12/210-PM-devfreq-mtk-cci-use-devres-for-resource-managemen.patch deleted file mode 100644 index 1777c72142..0000000000 --- a/target/linux/mediatek/patches-6.12/210-PM-devfreq-mtk-cci-use-devres-for-resource-managemen.patch +++ /dev/null @@ -1,241 +0,0 @@ -From b61fcc3c7f95734e14741d8787fc9eb69b8437d4 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 11 Apr 2026 22:47:15 +0100 -Subject: [PATCH 1/2] PM / devfreq: mtk-cci: use devres for resource management - in probe - -Convert mtk_ccifreq_probe() to use devm-managed resource cleanup -instead of manual goto-based error handling. - -This pattern (devm_add_action_or_reset with a regulator disable -callback) is well-established in the kernel, used by drivers such as -ads7846, max6639 and others. - -Signed-off-by: Daniel Golle ---- - drivers/devfreq/mtk-cci-devfreq.c | 150 +++++++++++++++--------------- - 1 file changed, 73 insertions(+), 77 deletions(-) - ---- a/drivers/devfreq/mtk-cci-devfreq.c -+++ b/drivers/devfreq/mtk-cci-devfreq.c -@@ -246,6 +246,21 @@ static struct devfreq_dev_profile mtk_cc - .target = mtk_ccifreq_target, - }; - -+static void mtk_ccifreq_regulator_disable(void *data) -+{ -+ regulator_disable(data); -+} -+ -+static void mtk_ccifreq_clk_disable_unprepare(void *data) -+{ -+ clk_disable_unprepare(data); -+} -+ -+static void mtk_ccifreq_opp_of_remove_table(void *data) -+{ -+ dev_pm_opp_of_remove_table(data); -+} -+ - static int mtk_ccifreq_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -266,44 +281,47 @@ static int mtk_ccifreq_probe(struct plat - platform_set_drvdata(pdev, drv); - - drv->cci_clk = devm_clk_get(dev, "cci"); -- if (IS_ERR(drv->cci_clk)) { -- ret = PTR_ERR(drv->cci_clk); -- return dev_err_probe(dev, ret, "failed to get cci clk\n"); -- } -+ if (IS_ERR(drv->cci_clk)) -+ return dev_err_probe(dev, PTR_ERR(drv->cci_clk), -+ "failed to get cci clk\n"); - - drv->inter_clk = devm_clk_get(dev, "intermediate"); -- if (IS_ERR(drv->inter_clk)) { -- ret = PTR_ERR(drv->inter_clk); -- return dev_err_probe(dev, ret, -+ if (IS_ERR(drv->inter_clk)) -+ return dev_err_probe(dev, PTR_ERR(drv->inter_clk), - "failed to get intermediate clk\n"); -- } - - drv->proc_reg = devm_regulator_get_optional(dev, "proc"); -- if (IS_ERR(drv->proc_reg)) { -- ret = PTR_ERR(drv->proc_reg); -- return dev_err_probe(dev, ret, -+ if (IS_ERR(drv->proc_reg)) -+ return dev_err_probe(dev, PTR_ERR(drv->proc_reg), - "failed to get proc regulator\n"); -- } - - ret = regulator_enable(drv->proc_reg); -- if (ret) { -- dev_err(dev, "failed to enable proc regulator\n"); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to enable proc regulator\n"); -+ -+ ret = devm_add_action_or_reset(dev, mtk_ccifreq_regulator_disable, -+ drv->proc_reg); -+ if (ret) - return ret; -- } - - drv->sram_reg = devm_regulator_get_optional(dev, "sram"); - if (IS_ERR(drv->sram_reg)) { -- ret = PTR_ERR(drv->sram_reg); -- if (ret == -EPROBE_DEFER) -- goto out_free_resources; -+ if (PTR_ERR(drv->sram_reg) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; - - drv->sram_reg = NULL; - } else { - ret = regulator_enable(drv->sram_reg); -- if (ret) { -- dev_err(dev, "failed to enable sram regulator\n"); -- goto out_free_resources; -- } -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to enable sram regulator\n"); -+ -+ ret = devm_add_action_or_reset(dev, -+ mtk_ccifreq_regulator_disable, -+ drv->sram_reg); -+ if (ret) -+ return ret; - } - - /* -@@ -317,31 +335,36 @@ static int mtk_ccifreq_probe(struct plat - - ret = clk_prepare_enable(drv->cci_clk); - if (ret) -- goto out_free_resources; -+ return ret; -+ -+ ret = devm_add_action_or_reset(dev, mtk_ccifreq_clk_disable_unprepare, -+ drv->cci_clk); -+ if (ret) -+ return ret; - - ret = dev_pm_opp_of_add_table(dev); -- if (ret) { -- dev_err(dev, "failed to add opp table: %d\n", ret); -- goto out_disable_cci_clk; -- } -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to add opp table\n"); -+ -+ ret = devm_add_action_or_reset(dev, mtk_ccifreq_opp_of_remove_table, -+ dev); -+ if (ret) -+ return ret; - - rate = clk_get_rate(drv->inter_clk); - opp = dev_pm_opp_find_freq_ceil(dev, &rate); -- if (IS_ERR(opp)) { -- ret = PTR_ERR(opp); -- dev_err(dev, "failed to get intermediate opp: %d\n", ret); -- goto out_remove_opp_table; -- } -+ if (IS_ERR(opp)) -+ return dev_err_probe(dev, PTR_ERR(opp), -+ "failed to get intermediate opp\n"); -+ - drv->inter_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - - rate = U32_MAX; - opp = dev_pm_opp_find_freq_floor(drv->dev, &rate); -- if (IS_ERR(opp)) { -- dev_err(dev, "failed to get opp\n"); -- ret = PTR_ERR(opp); -- goto out_remove_opp_table; -- } -+ if (IS_ERR(opp)) -+ return dev_err_probe(dev, PTR_ERR(opp), -+ "failed to get opp\n"); - - opp_volt = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); -@@ -349,63 +372,36 @@ static int mtk_ccifreq_probe(struct plat - if (ret) { - dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n", - opp_volt); -- goto out_remove_opp_table; -+ return ret; - } - - passive_data = devm_kzalloc(dev, sizeof(*passive_data), GFP_KERNEL); -- if (!passive_data) { -- ret = -ENOMEM; -- goto out_remove_opp_table; -- } -+ if (!passive_data) -+ return -ENOMEM; - - passive_data->parent_type = CPUFREQ_PARENT_DEV; - drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile, - DEVFREQ_GOV_PASSIVE, - passive_data); -- if (IS_ERR(drv->devfreq)) { -- ret = -EPROBE_DEFER; -- dev_err(dev, "failed to add devfreq device: %ld\n", -- PTR_ERR(drv->devfreq)); -- goto out_remove_opp_table; -- } -+ if (IS_ERR(drv->devfreq)) -+ return dev_err_probe(dev, -EPROBE_DEFER, -+ "failed to add devfreq device: %ld\n", -+ PTR_ERR(drv->devfreq)); - - drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier; - ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb); -- if (ret) { -- dev_err(dev, "failed to register opp notifier: %d\n", ret); -- goto out_remove_opp_table; -- } -- return 0; -- --out_remove_opp_table: -- dev_pm_opp_of_remove_table(dev); -- --out_disable_cci_clk: -- clk_disable_unprepare(drv->cci_clk); -- --out_free_resources: -- if (regulator_is_enabled(drv->proc_reg)) -- regulator_disable(drv->proc_reg); -- if (!IS_ERR_OR_NULL(drv->sram_reg) && -- regulator_is_enabled(drv->sram_reg)) -- regulator_disable(drv->sram_reg); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to register opp notifier\n"); - -- return ret; -+ return 0; - } - - static void mtk_ccifreq_remove(struct platform_device *pdev) - { -- struct device *dev = &pdev->dev; -- struct mtk_ccifreq_drv *drv; -- -- drv = platform_get_drvdata(pdev); -+ struct mtk_ccifreq_drv *drv = platform_get_drvdata(pdev); - -- dev_pm_opp_unregister_notifier(dev, &drv->opp_nb); -- dev_pm_opp_of_remove_table(dev); -- clk_disable_unprepare(drv->cci_clk); -- regulator_disable(drv->proc_reg); -- if (drv->sram_reg) -- regulator_disable(drv->sram_reg); -+ dev_pm_opp_unregister_notifier(&pdev->dev, &drv->opp_nb); - } - - static const struct mtk_ccifreq_platform_data mt8183_platform_data = { diff --git a/target/linux/mediatek/patches-6.12/211-PM-devfreq-mtk-cci-check-cpufreq-availability-early.patch b/target/linux/mediatek/patches-6.12/211-PM-devfreq-mtk-cci-check-cpufreq-availability-early.patch deleted file mode 100644 index d18e2264e2..0000000000 --- a/target/linux/mediatek/patches-6.12/211-PM-devfreq-mtk-cci-check-cpufreq-availability-early.patch +++ /dev/null @@ -1,53 +0,0 @@ -From b19968e432fe2ebe3af4bc9190923edb70b6aeee Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 13 Apr 2026 15:22:05 +0100 -Subject: [PATCH 2/2] PM / devfreq: mtk-cci: check cpufreq availability early - -Check spufreq availablility early at probe so -EPROBE_DEFER is emitted -before touching any regulators. - -Signed-off-by: Daniel Golle ---- - drivers/devfreq/mtk-cci-devfreq.c | 18 +++++++++++++++++- - 1 file changed, 17 insertions(+), 1 deletion(-) - ---- a/drivers/devfreq/mtk-cci-devfreq.c -+++ b/drivers/devfreq/mtk-cci-devfreq.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -263,13 +264,28 @@ static void mtk_ccifreq_opp_of_remove_ta - - static int mtk_ccifreq_probe(struct platform_device *pdev) - { -+ struct devfreq_passive_data *passive_data; - struct device *dev = &pdev->dev; -+ struct cpufreq_policy *policy; - struct mtk_ccifreq_drv *drv; -- struct devfreq_passive_data *passive_data; - struct dev_pm_opp *opp; - unsigned long rate, opp_volt; - int ret; - -+ /* -+ * Check if cpufreq is available before touching any regulators. -+ * The passive devfreq governor needs cpufreq as its parent and -+ * will return -EPROBE_DEFER if it is not yet registered. If we -+ * enable the proc regulator (CPU core power) before this check, -+ * the subsequent probe failure causes devres to disable that -+ * regulator, potentially cutting CPU core voltage and hanging -+ * the system. -+ */ -+ policy = cpufreq_cpu_get(0); -+ if (!policy) -+ return -EPROBE_DEFER; -+ cpufreq_cpu_put(policy); -+ - drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); - if (!drv) - return -ENOMEM; diff --git a/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch b/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch deleted file mode 100644 index ed3471933c..0000000000 --- a/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch +++ /dev/null @@ -1,65 +0,0 @@ -From patchwork Fri Nov 1 03:19:39 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 13858671 -Return-Path: - -Date: Fri, 1 Nov 2024 03:19:39 +0000 -From: Daniel Golle -To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe - =?iso-8859-1?q?Kleine-K=F6nig?= , - Sam Shih , Frank Wunderlich , - Daniel Golle , - AngeloGioacchino Del Regno , - Matthias Brugger , Stephen Boyd , - Michael Turquette -Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -SPI0 clocks have wrongly been marked as critical while, probably due -to the SPI driver not requesting them. This can (and should) be addressed -in device tree instead. -Remove CLK_IS_CRITICAL flag from clocks related to SPI0. - -Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC") -Signed-off-by: Daniel Golle ---- - drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[ - GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, - CLK_IS_CRITICAL), -- GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, -- CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12), - GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), - GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), -- GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, -- CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15), - GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), - GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), - GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), diff --git a/target/linux/mediatek/patches-6.12/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch b/target/linux/mediatek/patches-6.12/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch deleted file mode 100644 index 9bd9d0ab31..0000000000 --- a/target/linux/mediatek/patches-6.12/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch +++ /dev/null @@ -1,212 +0,0 @@ -From d211e2184d820207d14f5e8f84938c639875bf0d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 3 Mar 2026 23:45:46 +0000 -Subject: [PATCH] hwrng: mtk - add support for hw access via SMCC - -Newer versions of ARM TrustedFirmware-A on MediaTek's ARMv8 SoCs no longer -allow accessing the TRNG from outside of the trusted firmware. -Instead, a vendor-defined custom Secure Monitor Call can be used to -acquire random bytes. -Add support for newer SoCs (MT7981, MT7987, MT7988). On MT7986 the best bet -is to test if firmware blocks direct access to the hwrng and if so, expect -the SMCC interface to be usable. - -Signed-off-by: Daniel Golle ---- - drivers/char/hw_random/mtk-rng.c | 128 ++++++++++++++++++++++++++----- - 1 file changed, 107 insertions(+), 21 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -3,6 +3,7 @@ - * Driver for Mediatek Hardware Random Number Generator - * - * Copyright (C) 2017 Sean Wang -+ * Copyright (C) 2026 Daniel Golle - */ - #define MTK_RNG_DEV KBUILD_MODNAME - -@@ -17,6 +18,8 @@ - #include - #include - #include -+#include -+#include - - /* Runtime PM autosuspend timeout: */ - #define RNG_AUTOSUSPEND_TIMEOUT 100 -@@ -30,6 +33,11 @@ - - #define RNG_DATA 0x08 - -+/* Driver feature flags */ -+#define MTK_RNG_SMC BIT(0) -+ -+#define MTK_SIP_KERNEL_GET_RND MTK_SIP_SMC_CMD(0x550) -+ - #define to_mtk_rng(p) container_of(p, struct mtk_rng, rng) - - struct mtk_rng { -@@ -37,6 +45,7 @@ struct mtk_rng { - struct clk *clk; - struct hwrng rng; - struct device *dev; -+ unsigned long flags; - }; - - static int mtk_rng_init(struct hwrng *rng) -@@ -104,6 +113,56 @@ static int mtk_rng_read(struct hwrng *rn - return retval || !wait ? retval : -EIO; - } - -+static int mtk_rng_read_smc(struct hwrng *rng, void *buf, size_t max, -+ bool wait) -+{ -+ struct arm_smccc_res res; -+ int retval = 0; -+ -+ while (max >= sizeof(u32)) { -+ arm_smccc_smc(MTK_SIP_KERNEL_GET_RND, 0, 0, 0, 0, 0, 0, 0, -+ &res); -+ if (res.a0) -+ break; -+ -+ *(u32 *)buf = res.a1; -+ retval += sizeof(u32); -+ buf += sizeof(u32); -+ max -= sizeof(u32); -+ } -+ -+ return retval || !wait ? retval : -EIO; -+} -+ -+static bool mtk_rng_hw_accessible(struct mtk_rng *priv) -+{ -+ u32 val; -+ int err; -+ -+ err = clk_prepare_enable(priv->clk); -+ if (err) -+ return false; -+ -+ val = readl(priv->base + RNG_CTRL); -+ val |= RNG_EN; -+ writel(val, priv->base + RNG_CTRL); -+ -+ val = readl(priv->base + RNG_CTRL); -+ -+ if (val & RNG_EN) { -+ /* HW is accessible, clean up: disable RNG and clock */ -+ writel(val & ~RNG_EN, priv->base + RNG_CTRL); -+ clk_disable_unprepare(priv->clk); -+ return true; -+ } -+ -+ /* -+ * If TF-A blocks direct access, the register reads back as 0. -+ * Leave the clock enabled as TF-A's SMC handler needs it. -+ */ -+ return false; -+} -+ - static int mtk_rng_probe(struct platform_device *pdev) - { - int ret; -@@ -115,23 +174,42 @@ static int mtk_rng_probe(struct platform - - priv->dev = &pdev->dev; - priv->rng.name = pdev->name; --#ifndef CONFIG_PM -- priv->rng.init = mtk_rng_init; -- priv->rng.cleanup = mtk_rng_cleanup; --#endif -- priv->rng.read = mtk_rng_read; - priv->rng.quality = 900; -+ priv->flags = (unsigned long)device_get_match_data(&pdev->dev); - -- priv->clk = devm_clk_get(&pdev->dev, "rng"); -- if (IS_ERR(priv->clk)) { -- ret = PTR_ERR(priv->clk); -- dev_err(&pdev->dev, "no clock for device: %d\n", ret); -- return ret; -+ if (!(priv->flags & MTK_RNG_SMC)) { -+ priv->clk = devm_clk_get(&pdev->dev, "rng"); -+ if (IS_ERR(priv->clk)) { -+ ret = PTR_ERR(priv->clk); -+ dev_err(&pdev->dev, "no clock for device: %d\n", ret); -+ return ret; -+ } -+ -+ priv->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(priv->base)) -+ return PTR_ERR(priv->base); -+ -+ if (IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) && -+ of_device_is_compatible(pdev->dev.of_node, -+ "mediatek,mt7986-rng") && -+ !mtk_rng_hw_accessible(priv)) { -+ priv->flags |= MTK_RNG_SMC; -+ dev_info(&pdev->dev, -+ "HW RNG not MMIO accessible, using SMC\n"); -+ } - } - -- priv->base = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(priv->base)) -- return PTR_ERR(priv->base); -+ if (priv->flags & MTK_RNG_SMC) { -+ if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)) -+ return -ENODEV; -+ priv->rng.read = mtk_rng_read_smc; -+ } else { -+#ifndef CONFIG_PM -+ priv->rng.init = mtk_rng_init; -+ priv->rng.cleanup = mtk_rng_cleanup; -+#endif -+ priv->rng.read = mtk_rng_read; -+ } - - ret = devm_hwrng_register(&pdev->dev, &priv->rng); - if (ret) { -@@ -140,12 +218,15 @@ static int mtk_rng_probe(struct platform - return ret; - } - -- dev_set_drvdata(&pdev->dev, priv); -- pm_runtime_set_autosuspend_delay(&pdev->dev, RNG_AUTOSUSPEND_TIMEOUT); -- pm_runtime_use_autosuspend(&pdev->dev); -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -+ if (!(priv->flags & MTK_RNG_SMC)) { -+ dev_set_drvdata(&pdev->dev, priv); -+ pm_runtime_set_autosuspend_delay(&pdev->dev, -+ RNG_AUTOSUSPEND_TIMEOUT); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ ret = devm_pm_runtime_enable(&pdev->dev); -+ if (ret) -+ return ret; -+ } - - dev_info(&pdev->dev, "registered RNG driver\n"); - -@@ -182,8 +263,12 @@ static const struct dev_pm_ops mtk_rng_p - #endif /* CONFIG_PM */ - - static const struct of_device_id mtk_rng_match[] = { -- { .compatible = "mediatek,mt7986-rng" }, - { .compatible = "mediatek,mt7623-rng" }, -+ { .compatible = "mediatek,mt7622-rng" }, -+ { .compatible = "mediatek,mt7981-rng", .data = (void *)MTK_RNG_SMC }, -+ { .compatible = "mediatek,mt7986-rng" }, -+ { .compatible = "mediatek,mt7987-rng", .data = (void *)MTK_RNG_SMC }, -+ { .compatible = "mediatek,mt7988-rng", .data = (void *)MTK_RNG_SMC }, - {}, - }; - MODULE_DEVICE_TABLE(of, mtk_rng_match); -@@ -201,4 +286,5 @@ module_platform_driver(mtk_rng_driver); - - MODULE_DESCRIPTION("Mediatek Random Number Generator Driver"); - MODULE_AUTHOR("Sean Wang "); -+MODULE_AUTHOR("Daniel Golle "); - MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch deleted file mode 100644 index 28e63ebeee..0000000000 --- a/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 68d5efaa10cf0689521fe05e386e3a1e11d8cb29 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Thu, 7 Apr 2022 10:16:47 +0800 -Subject: [PATCH] mtd: spinand: attach/detach MTK BMT on probe/remove - -Call mtk_bmt_attach() after the MTD device is registered in -spinand_probe() and mtk_bmt_detach() before it is unregistered in -spinand_remove() to enable the MediaTek bad block management table for -SPI-NAND devices. - -Signed-off-by: Chuanhong Guo ---- ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) - { -@@ -1604,6 +1605,7 @@ static int spinand_probe(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_attach(mtd); - ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto err_spinand_cleanup; -@@ -1611,6 +1613,7 @@ static int spinand_probe(struct spi_mem - return 0; - - err_spinand_cleanup: -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return ret; -@@ -1629,6 +1632,7 @@ static int spinand_remove(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return 0; diff --git a/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index d1bc35f1f2..0000000000 --- a/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,17 +0,0 @@ -From f9a28d216d65b55e1139e2c73d016c5e77d7fe0b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 4 Dec 2021 22:46:00 +0100 -Subject: [PATCH] mediatek: enable bmt on mt7622-rfb1 - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -572,6 +572,7 @@ - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - nand-ecc-engine = <&snfi>; -+ mediatek,bmt-v2; - - partitions { - compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index 05a02bde22..0000000000 --- a/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,4 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fmsh.o foresee.o gigadevice.o -+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o fmsh.o foresee.o gigadevice.o - spinand-objs += macronix.o micron.o paragon.o skyhigh.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1189,6 +1189,7 @@ static const struct spinand_manufacturer - &esmt_c8_spinand_manufacturer, - &etron_spinand_manufacturer, - &fmsh_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &foresee_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -266,6 +266,7 @@ extern const struct spinand_manufacturer - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; - extern const struct spinand_manufacturer etron_spinand_manufacturer; - extern const struct spinand_manufacturer fmsh_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer foresee_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch deleted file mode 100644 index c52ed76e92..0000000000 --- a/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ /dev/null @@ -1,45 +0,0 @@ -From patchwork Fri Apr 19 16:59:07 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 13636668 -Return-Path: - -Date: Fri, 19 Apr 2024 17:59:07 +0100 -From: Daniel Golle -To: "Rafael J. Wysocki" , - Viresh Kumar , - Matthias Brugger , - AngeloGioacchino Del Regno , - linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org -Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A -Message-ID: - -Content-Disposition: inline -List-Id: - -From: Sam Shih - -This add cpufreq support for mediatek MT7988A SoC. - -The platform data of MT7988A is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Sam Shih ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -744,6 +744,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, - { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, -+ { .compatible = "mediatek,mt7988d", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.12/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch b/target/linux/mediatek/patches-6.12/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch deleted file mode 100644 index 061a14c5f6..0000000000 --- a/target/linux/mediatek/patches-6.12/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch +++ /dev/null @@ -1,793 +0,0 @@ -From e37d53fb387eb788dff33cdc4c1009543e2ccd5f Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Mon, 20 Jan 2025 19:49:34 +0800 -Subject: [PATCH 1/2] pinctrl: mediatek: add mt7987 pinctrl support - -Signed-off-by: Daniel Golle ---- - drivers/pinctrl/mediatek/Kconfig | 6 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7987.c | 752 ++++++++++++++++++++++ - 3 files changed, 759 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7987.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -187,6 +187,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7987 -+ bool "Mediatek MT7987 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7988 - bool "Mediatek MT7988 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o - obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c -@@ -0,0 +1,751 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7987 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Tim.Kuo -+ */ -+ -+#include "pinctrl-moore.h" -+ -+enum MT7987_PINCTRL_REG_PAGE { -+ GPIO_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_RT1_BASE, -+ IOCFG_RT2_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+#define MT7987_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = { -+ PIN_FIELD(0, 49, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = { -+ PIN_FIELD(0, 49, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_di_range[] = { -+ PIN_FIELD(0, 49, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_do_range[] = { -+ PIN_FIELD(0, 49, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = { -+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = { -+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3), -+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3), -+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3), -+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3), -+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3), -+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3), -+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3), -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1), -+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), -+}; -+ -+static const unsigned int mt7987_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ -+ MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ -+ MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ -+ MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7987_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7987_pins[] = { -+ MT7987_PIN(0, "GPIO_WPS"), -+ MT7987_PIN(1, "GPIO_RESET"), -+ MT7987_PIN(2, "SYS_WATCHDOG"), -+ MT7987_PIN(3, "JTAG_JTDO"), -+ MT7987_PIN(4, "JTAG_JTDI"), -+ MT7987_PIN(5, "JTAG_JTMS"), -+ MT7987_PIN(6, "JTAG_JTCLK"), -+ MT7987_PIN(7, "JTAG_JTRST_N"), -+ MT7987_PIN(8, "PCM_DTX_I2S_DOUT"), -+ MT7987_PIN(9, "PCM_DRX_I2S_DIN"), -+ MT7987_PIN(10, "PCM_CLK_I2S_BCLK"), -+ MT7987_PIN(11, "PCM_FS_I2S_LRCK"), -+ MT7987_PIN(12, "PCM_MCK_I2S_MCLK"), -+ MT7987_PIN(13, "PWM0"), -+ MT7987_PIN(14, "USB_VBUS"), -+ MT7987_PIN(15, "SPI0_CLK"), -+ MT7987_PIN(16, "SPI0_MOSI"), -+ MT7987_PIN(17, "SPI0_MISO"), -+ MT7987_PIN(18, "SPI0_CS"), -+ MT7987_PIN(19, "SPI0_HOLD"), -+ MT7987_PIN(20, "SPI0_WP"), -+ MT7987_PIN(21, "SPI1_CLK"), -+ MT7987_PIN(22, "SPI1_MOSI"), -+ MT7987_PIN(23, "SPI1_MISO"), -+ MT7987_PIN(24, "SPI1_CS"), -+ MT7987_PIN(25, "SPI2_CLK"), -+ MT7987_PIN(26, "SPI2_MOSI"), -+ MT7987_PIN(27, "SPI2_MISO"), -+ MT7987_PIN(28, "SPI2_CS"), -+ MT7987_PIN(29, "SPI2_HOLD"), -+ MT7987_PIN(30, "SPI2_WP"), -+ MT7987_PIN(31, "UART0_RXD"), -+ MT7987_PIN(32, "UART0_TXD"), -+ MT7987_PIN(33, "PCIE_PERESET_N_0"), -+ MT7987_PIN(34, "PCIE_CLK_REQ_0"), -+ MT7987_PIN(35, "PCIE_WAKE_N_0"), -+ MT7987_PIN(36, "PCIE_PERESET_N_1"), -+ MT7987_PIN(37, "PCIE_CLK_REQ_1"), -+ MT7987_PIN(38, "PCIE_WAKE_N_1"), -+ MT7987_PIN(39, "SMI_MDC"), -+ MT7987_PIN(40, "SMI_MDIO"), -+ MT7987_PIN(41, "GBE_INT"), -+ MT7987_PIN(42, "GBE_RESET"), -+ MT7987_PIN(43, "I2C_SCLK"), -+ MT7987_PIN(44, "I2C_SDATA"), -+ MT7987_PIN(45, "2P5G_LED0"), -+ MT7987_PIN(46, "UART1_RXD"), -+ MT7987_PIN(47, "UART1_TXD"), -+ MT7987_PIN(48, "UART1_CTS"), -+ MT7987_PIN(49, "UART1_RTS"), -+}; -+ -+/* watchdog */ -+static int mt7987_watchdog_pins[] = {2}; -+static int mt7987_watchdog_funcs[] = {1}; -+ -+/* jtag */ -+static int mt7987_jtag_pins[] = {3, 4, 5, 6, 7}; -+static int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1}; -+ -+/* i2s */ -+static int mt7987_i2s_pins[] = { 8, 9, 10, 11, 12 }; -+static int mt7987_i2s_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+/* pcm */ -+static int mt7987_pcm_pins[] = { 8, 9, 10, 11 }; -+static int mt7987_pcm_funcs[] = { 1, 1, 1, 1 }; -+ -+/* uart */ -+static int mt7987_uart0_pins[] = {31, 32}; -+static int mt7987_uart0_funcs[] = {1, 1}; -+ -+static int mt7987_uart1_0_pins[] = {3, 4, 5, 6}; -+static int mt7987_uart1_0_funcs[] = {3, 3, 3, 3}; -+ -+static int mt7987_uart1_0_lite_pins[] = {3, 4}; -+static int mt7987_uart1_0_lite_funcs[] = {3, 3}; -+ -+static int mt7987_uart1_1_pins[] = {21, 22, 23, 24}; -+static int mt7987_uart1_1_funcs[] = {3, 3, 3, 3}; -+ -+static int mt7987_uart1_2_pins[] = {46, 47, 48, 49}; -+static int mt7987_uart1_2_funcs[] = {1, 1, 1, 1}; -+ -+static int mt7987_uart2_0_pins[] = {8, 9, 10, 11}; -+static int mt7987_uart2_0_funcs[] = {2, 2, 2, 2}; -+ -+static int mt7987_uart2_1_pins[] = {25, 26, 27, 28}; -+static int mt7987_uart2_1_funcs[] = {2, 2, 2, 2}; -+ -+/* pwm */ -+static int mt7987_pwm0_pins[] = {13}; -+static int mt7987_pwm0_funcs[] = {1}; -+ -+static int mt7987_pwm1_0_pins[] = {7}; -+static int mt7987_pwm1_0_funcs[] = {3}; -+ -+static int mt7987_pwm1_1_pins[] = {43}; -+static int mt7987_pwm1_1_funcs[] = {2}; -+ -+static int mt7987_pwm2_0_pins[] = {12}; -+static int mt7987_pwm2_0_funcs[] = {2}; -+ -+static int mt7987_pwm2_1_pins[] = {44}; -+static int mt7987_pwm2_1_funcs[] = {2}; -+ -+/* vbus */ -+static int mt7987_drv_vbus_p1_pins[] = {14}; -+static int mt7987_drv_vbus_p1_funcs[] = {1}; -+ -+static int mt7987_drv_vbus_pins[] = {48}; -+static int mt7987_drv_vbus_funcs[] = {3}; -+ -+/* 2p5gbe_led */ -+static int mt7987_2p5gbe_led0_pins[] = {45}; -+static int mt7987_2p5gbe_led0_funcs[] = {1}; -+ -+static int mt7987_2p5gbe_led1_0_pins[] = {13}; -+static int mt7987_2p5gbe_led1_0_funcs[] = {2}; -+ -+static int mt7987_2p5gbe_led1_1_pins[] = {49}; -+static int mt7987_2p5gbe_led1_1_funcs[] = {3}; -+ -+/* mdc, mdio */ -+static int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24}; -+static int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4}; -+ -+static int mt7987_mdc_mdio_pins[] = {39, 40}; -+static int mt7987_mdc_mdio_funcs[] = {1, 1}; -+ -+/* spi */ -+static int mt7987_spi0_pins[] = {15, 16, 17, 18}; -+static int mt7987_spi0_funcs[] = {1, 1, 1, 1}; -+ -+static int mt7987_spi0_wp_hold_pins[] = {19, 20}; -+static int mt7987_spi0_wp_hold_funcs[] = {1, 1}; -+ -+static int mt7987_spi1_pins[] = {21, 22, 23, 24}; -+static int mt7987_spi1_funcs[] = {1, 1, 1, 1}; -+ -+static int mt7987_spi1_1_pins[] = {46, 47, 48, 49}; -+static int mt7987_spi1_1_funcs[] = {2, 2, 2, 2}; -+ -+static int mt7987_spi2_pins[] = {25, 26, 27, 28}; -+static int mt7987_spi2_funcs[] = {1, 1, 1, 1}; -+ -+static int mt7987_spi2_wp_hold_pins[] = {29, 30}; -+static int mt7987_spi2_wp_hold_funcs[] = {1, 1}; -+ -+/* emmc */ -+static int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; -+static int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; -+ -+/* sd */ -+static int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24}; -+static int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2}; -+ -+/* i2c */ -+static int mt7987_i2c0_0_pins[] = {29, 30}; -+static int mt7987_i2c0_0_funcs[] = {2, 2}; -+ -+static int mt7987_i2c0_1_pins[] = {39, 40}; -+static int mt7987_i2c0_1_funcs[] = {2, 2}; -+ -+static int mt7987_i2c0_2_pins[] = {43, 44}; -+static int mt7987_i2c0_2_funcs[] = {1, 1}; -+ -+/* pcie */ -+static int mt7987_pcie0_pereset_pins[] = {33}; -+static int mt7987_pcie0_pereset_funcs[] = {1}; -+ -+static int mt7987_pcie0_clkreq_pins[] = {34}; -+static int mt7987_pcie0_clkreq_funcs[] = {1}; -+ -+static int mt7987_pcie0_wake_pins[] = {35}; -+static int mt7987_pcie0_wake_funcs[] = {1}; -+ -+static int mt7987_pcie1_pereset_pins[] = {36}; -+static int mt7987_pcie1_pereset_funcs[] = {1}; -+ -+static int mt7987_pcie1_clkreq_pins[] = {37}; -+static int mt7987_pcie1_clkreq_funcs[] = {1}; -+ -+static int mt7987_pcie1_wake_pins[] = {38}; -+static int mt7987_pcie1_wake_funcs[] = {1}; -+ -+static int mt7987_pcie_phy_i2c_pins[] = {43, 44}; -+static int mt7987_pcie_phy_i2c_funcs[] = {3, 3}; -+ -+static const struct group_desc mt7987_groups[] = { -+ PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog), -+ PINCTRL_PIN_GROUP("jtag", mt7987_jtag), -+ PINCTRL_PIN_GROUP("i2s", mt7987_i2s), -+ PINCTRL_PIN_GROUP("pcm", mt7987_pcm), -+ PINCTRL_PIN_GROUP("uart0", mt7987_uart0), -+ PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0), -+ PINCTRL_PIN_GROUP("uart1_0_lite", mt7987_uart1_0_lite), -+ PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1), -+ PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2), -+ PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0), -+ PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1), -+ PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0), -+ PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0), -+ PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1), -+ PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0), -+ PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1), -+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1), -+ PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus), -+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0), -+ PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0), -+ PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1), -+ PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio), -+ PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio), -+ PINCTRL_PIN_GROUP("spi0", mt7987_spi0), -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold), -+ PINCTRL_PIN_GROUP("spi1", mt7987_spi1), -+ PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1), -+ PINCTRL_PIN_GROUP("spi2", mt7987_spi2), -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold), -+ PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45), -+ PINCTRL_PIN_GROUP("sd", mt7987_sd), -+ PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0), -+ PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1), -+ PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2), -+ PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset), -+ PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq), -+ PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake), -+ PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset), -+ PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq), -+ PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake), -+ PINCTRL_PIN_GROUP("pcie1_pcie_phy_i2c", mt7987_pcie_phy_i2c), -+}; -+ -+static const char *const mt7987_audio_groups[] = {"i2s", "pcm",}; -+static const char *const mt7987_wdt_groups[] = {"watchdog",}; -+static const char *const mt7987_jtag_groups[] = {"jtag",}; -+static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", -+ "uart1_0_lite", "uart1_1", -+ "uart1_2", "uart2_0", -+ "uart2_1",}; -+static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0", -+ "pwm2_1",}; -+static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",}; -+static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0", -+ "2p5gbe_led1_1",}; -+static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",}; -+static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1", -+ "spi1_1", "spi2", "spi2_wp_hold",}; -+static const char *const mt7987_flash_groups[] = {"emmc_45", "sd",}; -+static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",}; -+static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset", -+ "pcie0_clkreq", "pcie0_wake", -+ "pcie1_pereset", "pcie1_clkreq", -+ "pcie1_wake",}; -+ -+ -+static const struct function_desc mt7987_functions[] = { -+ { {"audio", mt7987_audio_groups, ARRAY_SIZE(mt7987_audio_groups)}, NULL }, -+ { {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, NULL }, -+ { {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, NULL }, -+ { {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, NULL }, -+ { {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, NULL }, -+ { {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, NULL }, -+ { {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, NULL }, -+ { {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, NULL }, -+ { {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, NULL }, -+ { {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, NULL }, -+ { {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, NULL }, -+ { {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, NULL }, -+}; -+ -+static const struct mtk_eint_hw mt7987_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7987_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7987_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl", -+}; -+ -+static struct mtk_pin_soc mt7987_data = { -+ .reg_cal = mt7987_reg_cals, -+ .pins = mt7987_pins, -+ .npins = ARRAY_SIZE(mt7987_pins), -+ .grps = mt7987_groups, -+ .ngrps = ARRAY_SIZE(mt7987_groups), -+ .funcs = mt7987_functions, -+ .nfuncs = ARRAY_SIZE(mt7987_functions), -+ .eint_hw = &mt7987_eint_hw, -+ .gpio_m = 0, -+ .ies_present = true, -+ .base_names = mt7987_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, -+ .pull_type = mt7987_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7987_pinctrl_of_match[] = { -+ { -+ .compatible = "mediatek,mt7987-pinctrl", -+ }, -+ {} -+}; -+ -+static int mt7987_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7987_data); -+} -+ -+static struct platform_driver mt7987_pinctrl_driver = { -+ .driver = { -+ .name = "mt7987-pinctrl", -+ .of_match_table = mt7987_pinctrl_of_match, -+ }, -+ .probe = mt7987_pinctrl_probe, -+}; -+ -+static int __init mt7987_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7987_pinctrl_driver); -+} -+arch_initcall(mt7987_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch b/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch deleted file mode 100644 index 249e239086..0000000000 --- a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch +++ /dev/null @@ -1,1187 +0,0 @@ -From 08b3847982f4c470ff1ac0761bed0d8d83f1fd49 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Mon, 20 Jan 2025 19:50:03 +0800 -Subject: [PATCH 2/2] clk: mediatek: add mt7987 clock drivers support - -Signed-off-by: Daniel Golle ---- - drivers/clk/mediatek/Kconfig | 9 + - drivers/clk/mediatek/Makefile | 5 + - drivers/clk/mediatek/clk-mt7987-apmixed.c | 116 +++++++ - drivers/clk/mediatek/clk-mt7987-eth.c | 94 +++++ - drivers/clk/mediatek/clk-mt7987-infracfg.c | 328 ++++++++++++++++++ - drivers/clk/mediatek/clk-mt7987-mcusys.c | 47 +++ - drivers/clk/mediatek/clk-mt7987-topckgen.c | 311 +++++++++++++++++ - .../dt-bindings/clock/mediatek,mt7987-clk.h | 206 +++++++++++ - .../reset/mediatek,mt7987-resets.h | 10 + - 9 files changed, 1126 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7987-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7987-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7987-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7987-mcusys.c - create mode 100644 drivers/clk/mediatek/clk-mt7987-topckgen.c - create mode 100644 include/dt-bindings/clock/mediatek,mt7987-clk.h - create mode 100644 include/dt-bindings/reset/mediatek,mt7987-resets.h - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7987 -+ tristate "Clock driver for MediaTek MT7987" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7987 basic clocks and clocks -+ required for various periperals found on this SoC. -+ - config COMMON_CLK_MT7988 - tristate "Clock driver for MediaTek MT7988" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-mcusys.o -+obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7987-apmixed.c -@@ -0,0 +1,116 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+#include -+ -+#define MT7987_PLL_FMAX (2500UL * MHZ) -+#define MT7987_PCW_CHG_SHIFT 2 -+ -+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ -+ _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ -+ _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _div_table, \ -+ _parent_name) \ -+ { \ -+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, .flags = _flags, \ -+ .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7987_PLL_FMAX, \ -+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, .tuner_en_reg = _tuner_en_reg, \ -+ .tuner_en_bit = _tuner_en_bit, .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, .pcw_chg_reg = _pcw_chg_reg, \ -+ .pcw_chg_bit = MT7987_PCW_CHG_SHIFT, \ -+ .div_table = _div_table, .parent_name = _parent_name, \ -+ } -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ -+ _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ -+ _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _parent_name) \ -+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ -+ _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ -+ _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL, \ -+ _parent_name) -+ -+static const struct mtk_pll_div_table mt7987_arm_ll_div[] = { -+ { .div = 0, .freq = 2000000000 }, -+ { .div = 1, .freq = 1500000000 }, -+ { .div = 2, .freq = 750000000 }, -+ { .div = 3, .freq = 375000000 }, -+ {} /* sentinel */ -+}; -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, -+ 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114, "clkxtal"), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, -+ 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134, "clkxtal"), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, -+ HAVE_RST_BAR | PLL_AO, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, -+ 0x0144, "clkxtal"), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, -+ HAVE_RST_BAR | PLL_AO, 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, -+ 0x0154, "clkxtal"), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, -+ 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164, "clkxtal"), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, -+ 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174, "clkxtal"), -+ PLL_B(CLK_APMIXED_ARM_LL, "arm_ll", 0x0104, 0x0110, 0x00000001, -+ PLL_AO, 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104, -+ mt7987_arm_ll_div, "clkxtal"), -+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0124, 0x0130, 0x00000001, 0, 0, -+ 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124, "clkxtal"), -+}; -+ -+static const struct of_device_id of_match_clk_mt7987_apmixed[] = { -+ { .compatible = "mediatek,mt7987-apmixedsys" }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7987_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ if (r) -+ goto free_apmixed_data; -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) -+ goto unregister_plls; -+ -+ return r; -+ -+unregister_plls: -+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7987_apmixed_drv = { -+ .probe = clk_mt7987_apmixed_probe, -+ .driver = { -+ .name = "mt7987-apmixedsys", -+ .of_match_table = of_match_clk_mt7987_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7987_apmixed_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7987-eth.c -@@ -0,0 +1,94 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include -+ -+static const struct mtk_gate_regs ethdma_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETHDMA(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = ðdma_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate ethdma_clks[] = { -+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), -+ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "netsys_500m_sel", 7), -+ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "netsys_500m_sel", 8), -+ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "netsys_500m_sel", 10), -+}; -+ -+static const struct mtk_clk_desc ethdma_desc = { -+ .clks = ethdma_clks, -+ .num_clks = ARRAY_SIZE(ethdma_clks), -+}; -+ -+static const struct mtk_gate_regs sgmii_cg_regs = { -+ .set_ofs = 0xe4, -+ .clr_ofs = 0xe4, -+ .sta_ofs = 0xe4, -+}; -+ -+#define GATE_SGMII(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &sgmii_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] = { -+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "clkxtal", 2), -+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "clkxtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_gate sgmii1_clks[] = { -+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "clkxtal", 2), -+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "clkxtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct of_device_id of_match_clk_mt7987_eth[] = { -+ { .compatible = "mediatek,mt7987-ethsys", .data = ðdma_desc }, -+ { .compatible = "mediatek,mt7987-sgmiisys0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7987-sgmiisys1", .data = &sgmii1_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7987_eth); -+ -+static struct platform_driver clk_mt7987_eth_drv = { -+ .driver = { -+ .name = "clk-mt7987-eth", -+ .of_match_table = of_match_clk_mt7987_eth, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7987_eth_drv); -+ -+MODULE_DESCRIPTION("MediaTek MT7987 Ethernet clocks driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7987-infracfg.c -@@ -0,0 +1,325 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-mux.h" -+#include "clk-gate.h" -+#include -+#include -+ -+#define MT7987_INFRA_RST0_SET_OFFSET 0x70 -+#define MT7987_INFRA_RST1_SET_OFFSET 0x80 -+ -+static DEFINE_SPINLOCK(mt7987_clk_lock); -+ -+static const char *const infra_mux_uart0_parents[] = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart1_parents[] = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart2_parents[] = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_spi0_parents[] = { -+ "i2c_sel", -+ "spi_sel" -+}; -+ -+static const char *const infra_mux_spi1_parents[] = { -+ "i2c_sel", -+ "spim_mst_sel" -+}; -+ -+static const char *const infra_mux_spi2_bck_parents[] = { -+ "i2c_sel", -+ "spi_sel" -+}; -+ -+static const char *const infra_pwm_bck_parents[] = { "cb_rtc_32p7k", -+ "csw_infra_f26m_sel", -+ "sysaxi_sel", "pwm_sel" }; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] = { -+ "cb_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", -+ "pextp_tl_ck_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] = { -+ "cb_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", -+ "pextp_tl_ck_p1_sel" -+}; -+ -+static struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", -+ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, -+ 0, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", -+ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, -+ 1, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", -+ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, -+ 2, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", -+ infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, -+ 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", -+ infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, -+ 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_BCK_SEL, -+ "infra_mux_spi2_bck_sel", -+ infra_mux_spi2_bck_parents, 0x0018, 0x0010, -+ 0x0014, 6, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", -+ infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, -+ 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, -+ "infra_pcie_gfmux_tl_ck_o_p0_sel", -+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, -+ 0x0020, 0x0024, 0, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, -+ "infra_pcie_gfmux_tl_ck_o_p1_sel", -+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, -+ 0x0020, 0x0024, 2, 2, -1, -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x10, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x18, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra3_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra0_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra1_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra2_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA3(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra3_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = _regs, .shift = _shift, .flags = CLK_IS_CRITICAL, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+static const struct mtk_gate infra_clks[] __initconst = { -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", -+ "sysaxi_sel", 0), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", -+ "sysaxi_sel", 1), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", -+ "infra_pwm_bck_sel", 2), -+ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", -+ "sysaxi_sel", 12), -+ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", -+ "sysaxi_sel", 13), -+ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", -+ "csw_infra_f26m_sel", 14), -+ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), -+ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), -+ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), -+ GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", -+ "csw_infra_f26m_sel", 19), -+ GATE_CRITICAL(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", -+ "sysaxi_sel", &infra1_cg_regs, 20), -+ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", -+ "sysaxi_sel", 21), -+ GATE_INFRA1(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src", -+ "emmc_200m_sel", 28), -+ GATE_CRITICAL(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", -+ "sysaxi_sel", &infra1_cg_regs, 29), -+ GATE_CRITICAL(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", -+ "csw_infra_f26m_sel", &infra1_cg_regs, 30), -+ GATE_CRITICAL(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", "sysaxi_sel", -+ &infra1_cg_regs, 31), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", -+ "csw_infra_f26m_sel", 0), -+ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), -+ GATE_INFRA2(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", -+ "sysaxi_sel", 3), -+ GATE_INFRA2(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", -+ "sysaxi_sel", 4), -+ GATE_INFRA2(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", -+ "sysaxi_sel", 5), -+ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", -+ "infra_mux_uart0_sel", 3), -+ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", -+ "infra_mux_uart1_sel", 4), -+ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", -+ "infra_mux_uart2_sel", 5), -+ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi_sel", 9), -+ GATE_CRITICAL(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", -+ "sysaxi_sel", &infra2_cg_regs, 11), -+ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", -+ "infra_mux_spi0_sel", 12), -+ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", -+ "infra_mux_spi1_sel", 13), -+ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", -+ "infra_mux_spi2_bck_sel", 14), -+ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", -+ "sysaxi_sel", 15), -+ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", -+ "sysaxi_sel", 16), -+ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", -+ "sysaxi_sel", 17), -+ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", -+ "sysaxi_sel", 18), -+ GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "cb_rtc_32k", -+ &infra2_cg_regs, 19), -+ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", -+ "csw_infra_f26m_sel", 20), -+ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", -+ 21), -+ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", -+ 22), -+ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", -+ 23), -+ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", -+ "sysaxi_sel", 24), -+ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", -+ "sysaxi_sel", 25), -+ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", -+ "sysaxi_sel", 26), -+ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi_sel", 27), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, -+ "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, -+ "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), -+ /* INFRA3 */ -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", -+ 0), -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", -+ "sysaxi_sel", 1), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", -+ 2), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", -+ "sysaxi_sel", 3), -+ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", -+ "usb_sys_p1_sel", 5), -+ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "cb_cksq_40m", 7), -+ GATE_CRITICAL(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", -+ "cksq_40m_d2", &infra3_cg_regs, 9), -+ GATE_CRITICAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", -+ "usb_phy_sel", &infra3_cg_regs, 11), -+ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", -+ "clkxtal", 13), -+ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", -+ "usb_xhci_p1_sel", 15), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", -+ "infra_pcie_gfmux_tl_ck_o_p0_sel", 20), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", -+ "infra_pcie_gfmux_tl_ck_o_p1_sel", 21), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "clkxtal", -+ 24), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "clkxtal", -+ 25), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", -+ "sysaxi_sel", 28), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", -+ "sysaxi_sel", 29), -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, -+ "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, -+ "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), -+}; -+ -+static u16 infra_rst_ofs[] = { -+ MT7987_INFRA_RST0_SET_OFFSET, -+ MT7987_INFRA_RST1_SET_OFFSET, -+}; -+ -+static u16 infra_idx_map[] = { -+ [MT7987_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, -+ [MT7987_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, -+}; -+ -+static struct mtk_clk_rst_desc infra_rst_desc = { -+ .version = MTK_RST_SET_CLR, -+ .rst_bank_ofs = infra_rst_ofs, -+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), -+ .rst_idx_map = infra_idx_map, -+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), -+}; -+ -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clk_lock = &mt7987_clk_lock, -+ .rst_desc = &infra_rst_desc, -+}; -+ -+static const struct of_device_id of_match_clk_mt7987_infracfg[] = { -+ { .compatible = "mediatek,mt7987-infracfg", .data = &infra_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7987_infracfg); -+ -+static struct platform_driver clk_mt7987_infracfg_drv = { -+ .driver = { -+ .name = "clk-mt7987-infracfg", -+ .of_match_table = of_match_clk_mt7987_infracfg, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7987_infracfg_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7987-mcusys.c -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7987_clk_lock); -+static const char *const mcu_bus_div_parents[] = { "cb_cksq_40m", "arm_ll" }; -+ -+static struct mtk_composite mcu_muxes[] = { -+ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", -+ mcu_bus_div_parents, 0x7C0, 9, 1, -1, CLK_IS_CRITICAL), -+}; -+ -+static const struct mtk_clk_desc mcusys_desc = { -+ .composite_clks = mcu_muxes, -+ .num_composite_clks = ARRAY_SIZE(mcu_muxes), -+ .clk_lock = &mt7987_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7987_mcusys[] = { -+ { .compatible = "mediatek,mt7987-mcusys", .data = &mcusys_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7987_mcusys); -+ -+static struct platform_driver clk_mt7987_mcusys_drv = { -+ .driver = { -+ .name = "clk-mt7987-mcusys", -+ .of_match_table = of_match_clk_mt7987_mcusys, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7987_mcusys_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7987-topckgen.c -@@ -0,0 +1,311 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7987_clk_lock); -+ -+static const struct mtk_fixed_factor top_divs[] __initconst = { -+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), -+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 6), -+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", "net1pll", 1, 3), -+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", "net1pll", 1, 7), -+ FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", "net1pll", 1, 14), -+ FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", "net1pll", 1, 28), -+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", "net1pll", 1, 64), -+ FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", "net1pll", 1, 128), -+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", "net2pll", 1, 32), -+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", "net2pll", 1, 14), -+ FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", "net2pll", 1, 8), -+ FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", "msdcpll", 1, 2), -+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), -+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), -+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), -+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1221), -+}; -+ -+static const char *const netsys_parents[] = { "cb_cksq_40m", "cb_net2_d2" }; -+ -+static const char *const netsys_500m_parents[] = { "cb_cksq_40m", "cb_net1_d5", -+ "net1_d5_d2" }; -+ -+static const char *const netsys_2x_parents[] = { "cb_cksq_40m", "net2pll" }; -+ -+static const char *const eth_gmii_parents[] = { "cb_cksq_40m", "net1_d5_d4" }; -+ -+static const char *const eip_parents[] = { "cb_cksq_40m", "cb_net1_d3", -+ "net2pll", "cb_net1_d4", -+ "cb_net1_d5" }; -+ -+static const char *const axi_infra_parents[] = { "cb_cksq_40m", "net1_d8_d2" }; -+ -+static const char *const uart_parents[] = { "cb_cksq_40m", "cb_m_d8", -+ "m_d8_d2" }; -+ -+static const char *const emmc_250m_parents[] = { "cb_cksq_40m", "net1_d5_d2", -+ "net1_d7_d2" }; -+ -+static const char *const emmc_400m_parents[] = { "cb_cksq_40m", "msdcpll", -+ "cb_net1_d7", "cb_m_d2", -+ "net1_d7_d2", "cb_net2_d6" }; -+ -+static const char *const spi_parents[] = { "cb_cksq_40m", "cb_m_d2", -+ "net1_d7_d2", "net1_d8_d2", -+ "cb_net2_d6", "net1_d5_d4", -+ "cb_m_d4", "net1_d8_d4" }; -+ -+static const char *const nfi_parents[] = { -+ "cksq_40m_d2", "net1_d8_d2", "cb_m_d3", "net1_d5_d4", "cb_m_d4", -+ "net1_d7_d4", "net1_d8_d4", "m_d3_d2", "net2_d7_d2", "cb_m_d8" -+}; -+ -+static const char *const pwm_parents[] = { "cb_cksq_40m", "net1_d8_d2", -+ "net1_d5_d4", "cb_m_d4", -+ "m_d8_d2", "cb_rtc_32k" }; -+ -+static const char *const i2c_parents[] = { "cb_cksq_40m", "net1_d5_d4", -+ "cb_m_d4", "net1_d8_d4" }; -+ -+static const char *const pcie_mbist_250m_parents[] = { "cb_cksq_40m", -+ "net1_d5_d2" }; -+ -+static const char *const pextp_tl_ck_parents[] = { "cb_cksq_40m", "cb_net2_d6", -+ "net1_d7_d4", "m_d8_d2", -+ "cb_rtc_32k" }; -+ -+static const char *const aud_parents[] = { "cb_cksq_40m", "apll2" }; -+ -+static const char *const a1sys_parents[] = { "cb_cksq_40m", "cb_apll2_d4" }; -+ -+static const char *const aud_l_parents[] = { "cb_cksq_40m", "apll2", -+ "m_d8_d2" }; -+ -+static const char *const usb_phy_parents[] = { "cksq_40m_d2", "m_d8_d2" }; -+ -+static const char *const sgm_0_parents[] = { "cb_cksq_40m", "sgmpll" }; -+ -+static const char *const sgm_sbus_0_parents[] = { "cb_cksq_40m", -+ "net1_d8_d4" }; -+ -+static const char *const sysapb_parents[] = { "cb_cksq_40m", "m_d3_d2" }; -+ -+static const char *const eth_refck_50m_parents[] = { "cb_cksq_40m", -+ "net2_d4_d4" }; -+ -+static const char *const eth_sys_200m_parents[] = { "cb_cksq_40m", -+ "cb_net2_d4" }; -+ -+static const char *const eth_xgmii_parents[] = { "cksq_40m_d2", "net1_d8_d8", -+ "net1_d8_d16" }; -+ -+static const char *const dramc_md32_parents[] = { "cb_cksq_40m", "cb_m_d2", -+ "wedmcupll" }; -+ -+static const char *const da_xtp_glb_p0_parents[] = { "cb_cksq_40m", -+ "cb_net2_d8" }; -+ -+static const char *const da_ckm_xtal_parents[] = { "cb_cksq_40m", "m_d8_d2" }; -+ -+static const char *const eth_mii_parents[] = { "cksq_40m_d2", "net2_d4_d8" }; -+ -+static const char *const emmc_200m_parents[] = { "cb_cksq_40m", "msdc_d2", -+ "net1_d7_d2", "cb_net2_d6", -+ "net1_d7_d4" }; -+ -+static struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, -+ 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", -+ netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, -+ 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", -+ netsys_2x_parents, 0x000, 0x004, 0x008, 16, 1, 23, -+ 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", -+ eth_gmii_parents, 0x000, 0x004, 0x008, 24, 1, 31, -+ 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EIP_SEL, "eip_sel", eip_parents, -+ 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4, -+ CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", -+ axi_infra_parents, 0x010, 0x014, 0x018, 8, -+ 1, 15, 0x1C0, 5, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, -+ 0x014, 0x018, 16, 2, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", -+ emmc_250m_parents, 0x010, 0x014, 0x018, 24, 2, 31, -+ 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", -+ emmc_400m_parents, 0x020, 0x024, 0x028, 0, 3, 7, -+ 0x1C0, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x020, -+ 0x024, 0x028, 8, 3, 15, 0x1C0, 9), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, -+ 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents, 0x020, -+ 0x024, 0x028, 24, 4, 31, 0x1C0, 11), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x030, -+ 0x034, 0x038, 0, 3, 7, 0x1C0, 12), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x030, -+ 0x034, 0x038, 8, 2, 15, 0x1C0, 13), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, -+ "pcie_mbist_250m_sel", pcie_mbist_250m_parents, -+ 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", -+ pextp_tl_ck_parents, 0x030, 0x034, 0x038, 24, 3, -+ 31, 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", -+ pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, -+ 0x1C0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", -+ eth_gmii_parents, 0x040, 0x044, 0x048, 8, 1, 15, -+ 0x1C0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", -+ eth_gmii_parents, 0x040, 0x044, 0x048, 16, 1, 23, -+ 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x040, -+ 0x044, 0x048, 24, 1, 31, 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, -+ 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, -+ 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, -+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", -+ usb_phy_parents, 0x050, 0x054, 0x058, 24, 1, 31, -+ 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, -+ 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", -+ sgm_sbus_0_parents, 0x060, 0x064, 0x068, 8, -+ 1, 15, 0x1C0, 25, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, -+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", -+ sgm_sbus_0_parents, 0x060, 0x064, 0x068, 24, -+ 1, 31, 0x1C0, 27, CLK_IS_CRITICAL), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ axi_infra_parents, 0x070, 0x074, 0x078, 0, -+ 1, 7, 0x1C0, 28, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x070, 0x074, 0x078, 8, 1, -+ 15, 0x1C0, 29, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", -+ eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, -+ 23, 0x1C0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", -+ eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, -+ 31, 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", -+ pcie_mbist_250m_parents, 0x080, 0x084, 0x088, 0, -+ 1, 7, 0x1C4, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", -+ eth_xgmii_parents, 0x080, 0x084, 0x088, 8, 2, 15, -+ 0x1C4, 2), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ usb_phy_parents, 0x080, 0x084, 0x088, 16, 1, -+ 23, 0x1C4, 3, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x080, 0x084, 0x088, 24, -+ 2, 31, 0x1C4, 4, CLK_IS_CRITICAL), -+ /* CLK_CFG_9 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, -+ "csw_infra_f26m_sel", usb_phy_parents, -+ 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5, -+ CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", -+ usb_phy_parents, 0x090, 0x094, 0x098, 8, 1, -+ 15, 0x1C4, 6, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", -+ usb_phy_parents, 0x090, 0x094, 0x098, 16, 1, -+ 23, 0x1C4, 7, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", -+ da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, -+ 31, 0x1C4, 8), -+ /* CLK_CFG_10 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", -+ da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, -+ 7, 0x1C4, 9), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, -+ 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel", -+ da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, -+ 23, 0x1C4, 11), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents, -+ 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12), -+ /* CLK_CFG_11 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", -+ eth_mii_parents, 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, -+ 0x1C4, 13), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", -+ emmc_200m_parents, 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, -+ 0x1C4, 14), -+}; -+ -+static const struct mtk_composite top_adj_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, -+ 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_adj_divs, -+ .num_composite_clks = ARRAY_SIZE(top_adj_divs), -+ .clk_lock = &mt7987_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7987_topckgen[] = { -+ { .compatible = "mediatek,mt7987-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7987_topckgen); -+ -+static struct platform_driver clk_mt7987_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7987-topckgen", -+ .of_match_table = of_match_clk_mt7987_topckgen, -+ }, -+}; -+module_platform_driver(clk_mt7987_topckgen_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7987-clk.h -@@ -0,0 +1,206 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2024 MediaTek Inc. -+ * Author: Lu Tang -+ * Author: Sam Shih -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7987_H -+#define _DT_BINDINGS_CLK_MT7987_H -+ -+/* INFRACFG */ -+ -+#define CLK_INFRA_MUX_UART0_SEL 0 -+#define CLK_INFRA_MUX_UART1_SEL 1 -+#define CLK_INFRA_MUX_UART2_SEL 2 -+#define CLK_INFRA_MUX_SPI0_SEL 3 -+#define CLK_INFRA_MUX_SPI1_SEL 4 -+#define CLK_INFRA_MUX_SPI2_BCK_SEL 5 -+#define CLK_INFRA_PWM_BCK_SEL 6 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 -+#define CLK_INFRA_66M_GPT_BCK 9 -+#define CLK_INFRA_66M_PWM_HCK 10 -+#define CLK_INFRA_66M_PWM_BCK 11 -+#define CLK_INFRA_133M_CQDMA_BCK 12 -+#define CLK_INFRA_66M_AUD_SLV_BCK 13 -+#define CLK_INFRA_AUD_26M 14 -+#define CLK_INFRA_AUD_L 15 -+#define CLK_INFRA_AUD_AUD 16 -+#define CLK_INFRA_AUD_EG2 17 -+#define CLK_INFRA_DRAMC_F26M 18 -+#define CLK_INFRA_133M_DBG_ACKM 19 -+#define CLK_INFRA_66M_AP_DMA_BCK 20 -+#define CLK_INFRA_MSDC200_SRC 21 -+#define CLK_INFRA_66M_SEJ_BCK 22 -+#define CLK_INFRA_PRE_CK_SEJ_F13M 23 -+#define CLK_INFRA_66M_TRNG 24 -+#define CLK_INFRA_26M_THERM_SYSTEM 25 -+#define CLK_INFRA_I2C_BCK 26 -+#define CLK_INFRA_66M_UART0_PCK 27 -+#define CLK_INFRA_66M_UART1_PCK 28 -+#define CLK_INFRA_66M_UART2_PCK 29 -+#define CLK_INFRA_52M_UART0_CK 30 -+#define CLK_INFRA_52M_UART1_CK 31 -+#define CLK_INFRA_52M_UART2_CK 32 -+#define CLK_INFRA_NFI 33 -+#define CLK_INFRA_66M_NFI_HCK 34 -+#define CLK_INFRA_104M_SPI0 35 -+#define CLK_INFRA_104M_SPI1 36 -+#define CLK_INFRA_104M_SPI2_BCK 37 -+#define CLK_INFRA_66M_SPI0_HCK 38 -+#define CLK_INFRA_66M_SPI1_HCK 39 -+#define CLK_INFRA_66M_SPI2_HCK 40 -+#define CLK_INFRA_66M_FLASHIF_AXI 41 -+#define CLK_INFRA_RTC 42 -+#define CLK_INFRA_26M_ADC_BCK 43 -+#define CLK_INFRA_RC_ADC 44 -+#define CLK_INFRA_MSDC400 45 -+#define CLK_INFRA_MSDC2_HCK 46 -+#define CLK_INFRA_133M_MSDC_0_HCK 47 -+#define CLK_INFRA_66M_MSDC_0_HCK 48 -+#define CLK_INFRA_133M_CPUM_BCK 49 -+#define CLK_INFRA_BIST2FPC 50 -+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 -+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 -+#define CLK_INFRA_133M_USB_HCK 53 -+#define CLK_INFRA_133M_USB_HCK_CK_P1 54 -+#define CLK_INFRA_66M_USB_HCK 55 -+#define CLK_INFRA_66M_USB_HCK_CK_P1 56 -+#define CLK_INFRA_USB_SYS_CK_P1 57 -+#define CLK_INFRA_USB_CK_P1 58 -+#define CLK_INFRA_USB_FRMCNT_CK_P1 59 -+#define CLK_INFRA_USB_PIPE_CK_P1 60 -+#define CLK_INFRA_USB_UTMI_CK_P1 61 -+#define CLK_INFRA_USB_XHCI_CK_P1 62 -+#define CLK_INFRA_PCIE_GFMUX_TL_P0 63 -+#define CLK_INFRA_PCIE_GFMUX_TL_P1 64 -+#define CLK_INFRA_PCIE_PIPE_P0 65 -+#define CLK_INFRA_PCIE_PIPE_P1 66 -+#define CLK_INFRA_133M_PCIE_CK_P0 67 -+#define CLK_INFRA_133M_PCIE_CK_P1 68 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 -+#define CLK_INFRA_NR_CLK 71 -+ -+/* TOPCKGEN */ -+ -+#define CLK_TOP_CB_M_D2 0 -+#define CLK_TOP_CB_M_D3 1 -+#define CLK_TOP_M_D3_D2 2 -+#define CLK_TOP_CB_M_D4 3 -+#define CLK_TOP_CB_M_D8 4 -+#define CLK_TOP_M_D8_D2 5 -+#define CLK_TOP_CB_APLL2_D4 6 -+#define CLK_TOP_CB_NET1_D3 7 -+#define CLK_TOP_CB_NET1_D4 8 -+#define CLK_TOP_CB_NET1_D5 9 -+#define CLK_TOP_NET1_D5_D2 10 -+#define CLK_TOP_NET1_D5_D4 11 -+#define CLK_TOP_CB_NET1_D7 12 -+#define CLK_TOP_NET1_D7_D2 13 -+#define CLK_TOP_NET1_D7_D4 14 -+#define CLK_TOP_NET1_D8_D2 15 -+#define CLK_TOP_NET1_D8_D4 16 -+#define CLK_TOP_NET1_D8_D8 17 -+#define CLK_TOP_NET1_D8_D16 18 -+#define CLK_TOP_CB_NET2_D2 19 -+#define CLK_TOP_CB_NET2_D4 20 -+#define CLK_TOP_NET2_D4_D4 21 -+#define CLK_TOP_NET2_D4_D8 22 -+#define CLK_TOP_CB_NET2_D6 23 -+#define CLK_TOP_NET2_D7_D2 24 -+#define CLK_TOP_CB_NET2_D8 25 -+#define CLK_TOP_MSDC_D2 26 -+#define CLK_TOP_CB_CKSQ_40M 27 -+#define CLK_TOP_CKSQ_40M_D2 28 -+#define CLK_TOP_CB_RTC_32K 29 -+#define CLK_TOP_CB_RTC_32P7K 30 -+#define CLK_TOP_NETSYS_SEL 31 -+#define CLK_TOP_NETSYS_500M_SEL 32 -+#define CLK_TOP_NETSYS_2X_SEL 33 -+#define CLK_TOP_ETH_GMII_SEL 34 -+#define CLK_TOP_EIP_SEL 35 -+#define CLK_TOP_AXI_INFRA_SEL 36 -+#define CLK_TOP_UART_SEL 37 -+#define CLK_TOP_EMMC_250M_SEL 38 -+#define CLK_TOP_EMMC_400M_SEL 39 -+#define CLK_TOP_SPI_SEL 40 -+#define CLK_TOP_SPIM_MST_SEL 41 -+#define CLK_TOP_NFI_SEL 42 -+#define CLK_TOP_PWM_SEL 43 -+#define CLK_TOP_I2C_SEL 44 -+#define CLK_TOP_PCIE_MBIST_250M_SEL 45 -+#define CLK_TOP_PEXTP_TL_SEL 46 -+#define CLK_TOP_PEXTP_TL_P1_SEL 47 -+#define CLK_TOP_USB_SYS_P1_SEL 48 -+#define CLK_TOP_USB_XHCI_P1_SEL 49 -+#define CLK_TOP_AUD_SEL 50 -+#define CLK_TOP_A1SYS_SEL 51 -+#define CLK_TOP_AUD_L_SEL 52 -+#define CLK_TOP_A_TUNER_SEL 53 -+#define CLK_TOP_USB_PHY_SEL 54 -+#define CLK_TOP_SGM_0_SEL 55 -+#define CLK_TOP_SGM_SBUS_0_SEL 56 -+#define CLK_TOP_SGM_1_SEL 57 -+#define CLK_TOP_SGM_SBUS_1_SEL 58 -+#define CLK_TOP_SYSAXI_SEL 59 -+#define CLK_TOP_SYSAPB_SEL 60 -+#define CLK_TOP_ETH_REFCK_50M_SEL 61 -+#define CLK_TOP_ETH_SYS_200M_SEL 62 -+#define CLK_TOP_ETH_SYS_SEL 63 -+#define CLK_TOP_ETH_XGMII_SEL 64 -+#define CLK_TOP_DRAMC_SEL 65 -+#define CLK_TOP_DRAMC_MD32_SEL 66 -+#define CLK_TOP_INFRA_F26M_SEL 67 -+#define CLK_TOP_PEXTP_P0_SEL 68 -+#define CLK_TOP_PEXTP_P1_SEL 69 -+#define CLK_TOP_DA_XTP_GLB_P0_SEL 70 -+#define CLK_TOP_DA_XTP_GLB_P1_SEL 71 -+#define CLK_TOP_CKM_SEL 72 -+#define CLK_TOP_DA_CKM_XTAL_SEL 73 -+#define CLK_TOP_PEXTP_SEL 74 -+#define CLK_TOP_ETH_MII_SEL 75 -+#define CLK_TOP_EMMC_200M_SEL 76 -+#define CLK_TOP_AUD_I2S_M 77 -+#define CLK_TOP_NR_CLK 78 -+ -+/* APMIXEDSYS */ -+ -+#define CLK_APMIXED_MPLL 0 -+#define CLK_APMIXED_APLL2 1 -+#define CLK_APMIXED_NET1PLL 2 -+#define CLK_APMIXED_NET2PLL 3 -+#define CLK_APMIXED_WEDMCUPLL 4 -+#define CLK_APMIXED_SGMPLL 5 -+#define CLK_APMIXED_ARM_LL 6 -+#define CLK_APMIXED_MSDCPLL 7 -+#define CLK_APMIXED_NR_CLK 8 -+ -+/* MCUSYS */ -+ -+#define CLK_MCU_BUS_DIV_SEL 0 -+#define CLK_MCU_NR_CLK 1 -+ -+/* SGMIISYS_0 */ -+ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGMII0_NR_CLK 2 -+ -+/* SGMIISYS_1 */ -+ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGMII1_NR_CLK 2 -+ -+/* ETHDMA */ -+ -+#define CLK_ETHDMA_FE_EN 0 -+#define CLK_ETHDMA_GP2_EN 1 -+#define CLK_ETHDMA_GP1_EN 2 -+#define CLK_ETHDMA_GP3_EN 3 -+#define CLK_ETHDMA_NR_CLK 4 -+ -+#endif /* _DT_BINDINGS_CLK_MT7987_H */ -+ ---- /dev/null -+++ b/include/dt-bindings/reset/mediatek,mt7987-resets.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+ -+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7987 -+#define _DT_BINDINGS_RESET_CONTROLLER_MT7987 -+ -+/* INFRA resets */ -+#define MT7987_INFRA_RST0_PEXTP_MAC_SWRST 0 -+#define MT7987_INFRA_RST1_THERM_CTRL_SWRST 1 -+ -+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7987 */ diff --git a/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index 5727f5ecec..0000000000 --- a/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 127ad76311079a842578e788a8af364f3910c676 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 4 Jun 2020 14:20:34 +0200 -Subject: [PATCH] crypto: inside-secure: set TX max commands for EIP97 HW2.1/2.3 - -EIP97 HW2.1 and HW2.3 use a different register field for the maximum -number of TX commands than EIP197. Add an else branch to set -EIP97_MST_CTRL_TX_MAX_CMD(4) (16 commands) for the EIP97 hardware -variant, and add the corresponding EIP97_MST_CTRL_TX_MAX_CMD() macro. - -Signed-off-by: John Crispin ---- ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -608,6 +608,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -315,6 +315,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index eb15990d09..0000000000 --- a/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 4841ac042e00df7e29d305eb92f68994ebc739fd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 1 Sep 2020 09:09:13 +0200 -Subject: [PATCH] crypto: inside-secure: align ahash state and len to cache line size - -On non-coherent DMA systems the ahash request state[] array and the len -field must each be aligned to the system cache line size (64 bytes) to -prevent DMA coherency issues. Add SYSTEM_CACHELINE_SIZE (64) and use it -as the alignment for both fields. - -Signed-off-by: John Crispin ---- ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -743,6 +743,9 @@ struct safexcel_priv_data { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -55,9 +55,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch deleted file mode 100644 index cce3dcadf8..0000000000 --- a/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 66458c49aa14ebc9ba2e4f9b6a323b8ff122807b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 2 Aug 2019 10:33:28 +0200 -Subject: [PATCH] serial: 8250: add UART_CAP_NMOD flag to skip set_termios for MT Bluetooth UART - -The Bluetooth UART on MediaTek SoCs does not support termios -configuration. Add a new UART_CAP_NMOD capability flag and set it on -PORT_NPCM so that serial8250_do_set_termios() returns immediately -without touching the hardware when this flag is present. - -Signed-off-by: John Crispin ---- ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -86,6 +86,7 @@ struct serial8250_config { - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ - #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ -+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ - - #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -276,7 +276,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2735,6 +2735,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-6.12/411-mtd-spinand-fix-support-for-FORESEE.patch b/target/linux/mediatek/patches-6.12/411-mtd-spinand-fix-support-for-FORESEE.patch deleted file mode 100644 index b88c138082..0000000000 --- a/target/linux/mediatek/patches-6.12/411-mtd-spinand-fix-support-for-FORESEE.patch +++ /dev/null @@ -1,32 +0,0 @@ -From edc7cb910433e05eac61b13d94163f1e07fa6af4 Mon Sep 17 00:00:00 2001 -From: Dim Fish -Date: Thu, 3 Jul 2025 18:06:18 +0300 -Subject: [PATCH] mediatek: spinand: force update_cache_variants to use reset for Foresee NAND - -Force update_cache_variantsvariants to use reset for Foresee NAND with bad blocks. - -Tested on Xiaomi AX3000T + F35SQA001G with bad blocks and without bad blocks - -Signed-off-by: Dim Fish -Link: https://github.com/openwrt/openwrt/pull/17963 -Signed-off-by: Chuanhong Guo ---- -Force update_cache_variants to use reset for Foresee NAND with bad blocks - -Tested on Xiaomi AX3000T + F35SQA001G with bad blocks and without bad blocks - -Signed-off-by: Dim Fish - ---- a/drivers/mtd/nand/spi/foresee.c -+++ b/drivers/mtd/nand/spi/foresee.c -@@ -22,8 +22,8 @@ static SPINAND_OP_VARIANTS(write_cache_v - SPINAND_PROG_LOAD(true, 0, NULL, 0)); - - static SPINAND_OP_VARIANTS(update_cache_variants, -- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), -- SPINAND_PROG_LOAD(false, 0, NULL, 0)); -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); - - static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) diff --git a/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch deleted file mode 100644 index 74e9bd9d7a..0000000000 --- a/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ /dev/null @@ -1,131 +0,0 @@ -From bfa7cf42e610d820b935b4805aa80484d591cb1f Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:29:51 +0800 -Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private - data - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 28 ++++++++++-------------- - include/linux/platform_data/spi-mt65xx.h | 17 -------------- - 2 files changed, 11 insertions(+), 34 deletions(-) - delete mode 100644 include/linux/platform_data/spi-mt65xx.h - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -15,7 +15,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -172,6 +171,8 @@ struct mtk_spi { - struct device *dev; - dma_addr_t tx_dma; - dma_addr_t rx_dma; -+ u32 sample_sel; -+ u32 get_tick_dly; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -217,15 +218,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, - }; - --/* -- * A piece of default chip info unless the platform -- * supplies it. -- */ --static const struct mtk_chip_config mtk_default_chip_info = { -- .sample_sel = 0, -- .tick_delay = 0, --}; -- - static const struct of_device_id mtk_spi_of_match[] = { - { .compatible = "mediatek,spi-ipm", - .data = (void *)&mtk_ipm_compat, -@@ -353,7 +345,6 @@ static int mtk_spi_hw_init(struct spi_co - { - u16 cpha, cpol; - u32 reg_val; -- struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_controller_get_devdata(host); - - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -403,7 +394,7 @@ static int mtk_spi_hw_init(struct spi_co - else - reg_val &= ~SPI_CMD_CS_POL; - -- if (chip_config->sample_sel) -+ if (mdata->sample_sel) - reg_val |= SPI_CMD_SAMPLE_SEL; - else - reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -430,20 +421,20 @@ static int mtk_spi_hw_init(struct spi_co - if (mdata->dev_comp->ipm_design) { - reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); - writel(reg_val, mdata->base + SPI_CMD_REG); - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; -- reg_val |= ((chip_config->tick_delay & 0x3) -+ reg_val |= ((mdata->get_tick_dly & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -733,9 +724,6 @@ static int mtk_spi_setup(struct spi_devi - { - struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); - -- if (!spi->controller_data) -- spi->controller_data = (void *)&mtk_default_chip_info; -- - if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) - /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi_get_csgpiod(spi, 0), 0); -@@ -1146,6 +1134,11 @@ static int mtk_spi_probe(struct platform - host->use_gpio_descriptors = true; - - mdata = spi_controller_get_devdata(host); -+ -+ /* Set device configs to default first. Calibrate it later. */ -+ mdata->sample_sel = 0; -+ mdata->get_tick_dly = 2; -+ - mdata->dev_comp = device_get_match_data(dev); - - if (mdata->dev_comp->enhance_timing) ---- a/include/linux/platform_data/spi-mt65xx.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * MTK SPI bus driver definitions -- * -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Leilk Liu -- */ -- --#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H --#define ____LINUX_PLATFORM_DATA_SPI_MTK_H -- --/* Board specific platform_data */ --struct mtk_chip_config { -- u32 sample_sel; -- u32 tick_delay; --}; --#endif diff --git a/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch deleted file mode 100644 index 4e51dc21c6..0000000000 --- a/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ /dev/null @@ -1,236 +0,0 @@ -From aaff78437f09d4b86da84ce5983fb7c5be0538d2 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:35:52 +0800 -Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ - include/linux/spi/spi.h | 42 ++++++++++++ - 2 files changed, 179 insertions(+) - ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1489,6 +1489,70 @@ static int spi_transfer_wait(struct spi_ - return 0; - } - -+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) -+{ -+ int datalen = ctlr->cal_rule->datalen; -+ int addrlen = ctlr->cal_rule->addrlen; -+ u8 *buf; -+ int ret; -+ int i; -+ struct list_head *cal_head, *listptr; -+ struct spi_cal_target *target; -+ -+ /* Calculate calibration result */ -+ int hit_val, total_hit, origin; -+ bool hit; -+ -+ /* Make sure we can start calibration */ -+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) -+ return 0; -+ -+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); -+ if(!buf) -+ return -ENOMEM; -+ -+ ret = ctlr->append_caldata(ctlr); -+ if (ret) -+ goto cal_end; -+ -+ cal_head = ctlr->cal_target; -+ list_for_each(listptr, cal_head) { -+ target = list_entry(listptr, struct spi_cal_target, list); -+ -+ hit = false; -+ hit_val = 0; -+ total_hit = 0; -+ origin = *target->cal_item; -+ -+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { -+ *target->cal_item = i; -+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); -+ if(ret) -+ break; -+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); -+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { -+ hit = true; -+ hit_val += i; -+ total_hit++; -+ dev_dbg(&spi->dev, "golden data matches data read!\n"); -+ } -+ } -+ if(hit) { -+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); -+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); -+ } else { -+ *target->cal_item = origin; -+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); -+ } -+ } -+ -+cal_end: -+ kfree(buf); -+ return ret? ret: 0; -+} -+EXPORT_SYMBOL_GPL(spi_do_calibration); -+ - static void _spi_transfer_delay_ns(u32 ns) - { - if (!ns) -@@ -2347,6 +2411,75 @@ void spi_flush_queue(struct spi_controll - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_OF) -+static inline void alloc_cal_data(struct list_head **cal_target, -+ struct spi_cal_rule **cal_rule, bool enable) -+{ -+ if(enable) { -+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); -+ INIT_LIST_HEAD(*cal_target); -+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); -+ } else { -+ kfree(*cal_target); -+ kfree(*cal_rule); -+ } -+} -+ -+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, -+ struct device_node *nc) -+{ -+ u32 value; -+ int rc; -+ const char *cal_mode; -+ -+ rc = of_property_read_bool(nc, "spi-cal-enable"); -+ if (rc) -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); -+ else -+ return 0; -+ -+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); -+ if(!rc) { -+ if(strcmp("read-data", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; -+ } else if(strcmp("read-pp", cal_mode) == 0) { -+ ctlr->cal_rule->mode = SPI_CAL_READ_PP; -+ return 0; -+ } else if(strcmp("read-sfdp", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; -+ return 0; -+ } -+ } else -+ goto err; -+ -+ ctlr->cal_rule->datalen = 0; -+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->datalen = value; -+ -+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); -+ rc = of_property_read_u8_array(nc, "spi-cal-data", -+ ctlr->cal_rule->match_data, value); -+ if(rc) -+ kfree(ctlr->cal_rule->match_data); -+ } -+ -+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->addrlen = value; -+ -+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); -+ rc = of_property_read_u32_array(nc, "spi-cal-addr", -+ ctlr->cal_rule->addr, value); -+ if(rc) -+ kfree(ctlr->cal_rule->addr); -+ } -+ return 0; -+ -+err: -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); -+ return 0; -+} -+ - static void of_spi_parse_dt_cs_delay(struct device_node *nc, - struct spi_delay *delay, const char *prop) - { -@@ -2511,6 +2644,10 @@ of_register_spi_device(struct spi_contro - if (rc) - goto err_out; - -+ rc = of_spi_parse_cal_dt(ctlr, spi, nc); -+ if (rc) -+ goto err_out; -+ - /* Store a pointer to the node in the device structure */ - of_node_get(nc); - ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -348,6 +348,40 @@ struct spi_driver { - struct device_driver driver; - }; - -+enum { -+ SPI_CAL_READ_DATA = 0, -+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ -+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ -+}; -+ -+struct nand_addr { -+ unsigned int lun; -+ unsigned int plane; -+ unsigned int eraseblock; -+ unsigned int page; -+ unsigned int dataoffs; -+}; -+ -+/** -+ * Read calibration rule from device dts node. -+ * Once calibration result matches the rule, we regard is as success. -+ */ -+struct spi_cal_rule { -+ int datalen; -+ u8 *match_data; -+ int addrlen; -+ u32 *addr; -+ int mode; -+}; -+ -+struct spi_cal_target { -+ u32 *cal_item; -+ int cal_min; /* min of cal_item */ -+ int cal_max; /* max of cal_item */ -+ int step; /* Increase/decrease cal_item */ -+ struct list_head list; -+}; -+ - #define to_spi_driver(__drv) \ - ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) - -@@ -754,6 +788,11 @@ struct spi_controller { - void *dummy_rx; - void *dummy_tx; - -+ /* For calibration */ -+ int (*append_caldata)(struct spi_controller *ctlr); -+ struct list_head *cal_target; -+ struct spi_cal_rule *cal_rule; -+ - int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); - - /* -@@ -1657,6 +1696,9 @@ spi_register_board_info(struct spi_board - { return 0; } - #endif - -+extern int spi_do_calibration(struct spi_controller *ctlr, -+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); -+ - /* - * If you're hotplugging an adapter with devices (parport, USB, etc) - * use spi_new_device() to describe each device. You can also call diff --git a/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch deleted file mode 100644 index 60c8f81925..0000000000 --- a/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fa0aaf2a0532053b925f6fbb9c8d0e516370fb68 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:37:55 +0800 -Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mem.c | 8 ++++++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -497,6 +497,14 @@ int spi_mem_exec_op(struct spi_mem *mem, - } - EXPORT_SYMBOL_GPL(spi_mem_exec_op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), -+ void *priv) -+{ -+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); -+} -+EXPORT_SYMBOL_GPL(spi_mem_do_calibration); -+ - /** - * spi_mem_get_name() - Return the SPI mem device name to be used by the - * upper layer if necessary ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -390,6 +390,10 @@ bool spi_mem_supports_op(struct spi_mem - int spi_mem_exec_op(struct spi_mem *mem, - const struct spi_mem_op *op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *, u32 *, int, u8 *, int), -+ void *priv); -+ - const char *spi_mem_get_name(struct spi_mem *mem); - - struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch deleted file mode 100644 index a7815d5ead..0000000000 --- a/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 655dfc90d438a8e223317f197b888a92de3df3a1 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:03 +0800 -Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration - paramter - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -842,6 +842,21 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_WAKE_THREAD; - } - -+static int mtk_spi_append_caldata(struct spi_controller *ctlr) -+{ -+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); -+ struct mtk_spi *mdata = spi_controller_get_devdata(ctlr); -+ -+ cal_target->cal_item = &mdata->get_tick_dly; -+ cal_target->cal_min = 0; -+ cal_target->cal_max = 7; -+ cal_target->step = 1; -+ -+ list_add(&cal_target->list, ctlr->cal_target); -+ -+ return 0; -+} -+ - static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, - struct spi_mem_op *op) - { -@@ -1132,6 +1147,7 @@ static int mtk_spi_probe(struct platform - host->setup = mtk_spi_setup; - host->set_cs_timing = mtk_spi_set_hw_cs_timing; - host->use_gpio_descriptors = true; -+ host->append_caldata = mtk_spi_append_caldata; - - mdata = spi_controller_get_devdata(host); - diff --git a/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch deleted file mode 100644 index b33315f164..0000000000 --- a/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ /dev/null @@ -1,81 +0,0 @@ -From eef758fee8d25f56086eaaf7df1edb19929ced1a Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:56 +0800 -Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for - spinand - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1228,6 +1228,56 @@ static int spinand_manufacturer_match(st - return -EOPNOTSUPP; - } - -+static int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { -+ struct spinand_device *spinand = (struct spinand_device *)priv; -+ struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); -+ struct nand_pos pos; -+ struct nand_page_io_req req; -+ u8 status; -+ int ret; -+ -+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { -+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); -+ return -EINVAL; -+ } -+ -+ ret = spinand_reset_op(spinand); -+ if (ret) -+ return ret; -+ -+ /* We should store our golden data in first target because -+ * we can't switch target at this moment. -+ */ -+ pos = (struct nand_pos){ -+ .target = 0, -+ .lun = *addr, -+ .plane = *(addr+1), -+ .eraseblock = *(addr+2), -+ .page = *(addr+3), -+ }; -+ -+ req = (struct nand_page_io_req){ -+ .pos = pos, -+ .dataoffs = *(addr+4), -+ .datalen = readlen, -+ .databuf.in = buf, -+ .mode = MTD_OPS_AUTO_OOB, -+ }; -+ -+ ret = spinand_load_page_op(spinand, &req); -+ if (ret) -+ return ret; -+ -+ ret = spinand_wait(spinand, &status); -+ if (ret < 0) -+ return ret; -+ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ -+ return 0; -+} -+ - static int spinand_id_detect(struct spinand_device *spinand) - { - u8 *id = spinand->id.data; -@@ -1481,6 +1531,10 @@ static int spinand_init(struct spinand_d - if (!spinand->scratchbuf) - return -ENOMEM; - -+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); -+ if (ret) -+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); -+ - ret = spinand_detect(spinand); - if (ret) - goto err_free_bufs; diff --git a/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch deleted file mode 100644 index 04fa9eeb04..0000000000 --- a/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7ec7de94c87654e6cc3f8f604b2f65c003f3e5dc Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:40:59 +0800 -Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for - spi-nor - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 5 ++++- - drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1269,7 +1269,10 @@ static int spinand_cal_read(void *priv, - if (ret) - return ret; - -- ret = spinand_wait(spinand, &status); -+ ret = spinand_wait(spinand, -+ SPINAND_READ_INITIAL_DELAY_US, -+ SPINAND_READ_POLL_DELAY_US, -+ &status); - if (ret < 0) - return ret; - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -3441,6 +3441,18 @@ static const struct flash_info *spi_nor_ - return NULL; - } - -+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) -+{ -+ struct spi_nor *nor = (struct spi_nor *)priv; -+ -+ nor->reg_proto = SNOR_PROTO_1_1_1; -+ nor->read_proto = SNOR_PROTO_1_1_1; -+ nor->read_opcode = SPINOR_OP_READ; -+ nor->read_dummy = 0; -+ -+ return nor->controller_ops->read(nor, *addr, readlen, buf); -+} -+ - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, - const char *name) - { -@@ -3615,6 +3627,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (ret) - return ret; - -+ if(nor->spimem) -+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); -+ - info = spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) - return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch b/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch deleted file mode 100644 index e1852e5cd6..0000000000 --- a/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch +++ /dev/null @@ -1,192 +0,0 @@ -From c22bc82183c2dea64919f975473ec518738baa3e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 12 Jul 2023 13:38:35 +0100 -Subject: [PATCH] nvmem: add layout for Adtran devices - -Adtran stores unique factory data on GPT partitions on the eMMC. -Using blk-nvmem the 'mfginfo' partition gets exposes as NVMEM provider. - -Add layout driver to parse mfginfo, mainly to provide MAC addresses to -Ethernet and wireless interfaces. - -Variable names are converted to lower-case and '_' is replaced with '-' -in order to comply with the device tree node naming convention. -The main MAC address always ends on a 0 and up to 16 addresses are -alocated for each device to use for various interfaces. - -Implement post-processing function for 'MFG_MAC' variable ('mfg-mac' -node name in device tree) adding the nvmem cell index to the least -significant digit of the MAC address. - -Signed-off-by: Daniel Golle ---- - drivers/nvmem/layouts/Kconfig | 9 +++ - drivers/nvmem/layouts/Makefile | 1 + - drivers/nvmem/layouts/adtran.c | 135 +++++++++++++++++++++++++++++++++ - 3 files changed, 145 insertions(+) - create mode 100644 drivers/nvmem/layouts/adtran.c - ---- a/drivers/nvmem/layouts/Kconfig -+++ b/drivers/nvmem/layouts/Kconfig -@@ -8,6 +8,15 @@ if NVMEM_LAYOUTS - - menu "Layout Types" - -+config NVMEM_LAYOUT_ADTRAN -+ tristate "Adtran mfginfo layout support" -+ select GENERIC_NET_UTILS -+ help -+ Say Y here if you want to support the layout used by Adtran for -+ mfginfo. -+ -+ If unsure, say N. -+ - config NVMEM_LAYOUT_SL28_VPD - tristate "Kontron sl28 VPD layout support" - select CRC8 ---- a/drivers/nvmem/layouts/Makefile -+++ b/drivers/nvmem/layouts/Makefile -@@ -6,4 +6,5 @@ - obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o - obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o - obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) += u-boot-env.o -+obj-$(CONFIG_NVMEM_LAYOUT_ADTRAN) += adtran.o - obj-$(CONFIG_NVMEM_LAYOUT_ASCII_ENV) += ascii-env.o ---- /dev/null -+++ b/drivers/nvmem/layouts/adtran.c -@@ -0,0 +1,135 @@ -+// SPDX-License-Identifier: GPL-2.0 -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * Adtran devices usually come with a main MAC address ending on 0 and -+ * hence may have up to 16 MAC addresses per device. -+ * The main MAC address is stored as variable MFG_MAC in ASCII format. -+ */ -+static int adtran_mac_address_pp(void *priv, const char *id, int index, -+ unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ u8 mac[ETH_ALEN]; -+ -+ if (WARN_ON(bytes != 3 * ETH_ALEN - 1)) -+ return -EINVAL; -+ -+ if (!mac_pton(buf, mac)) -+ return -EINVAL; -+ -+ if (index) -+ eth_addr_add(mac, index); -+ -+ ether_addr_copy(buf, mac); -+ -+ return 0; -+} -+ -+static int adtran_add_cells(struct nvmem_layout *layout) -+{ -+ struct nvmem_device *nvmem = layout->nvmem; -+ struct nvmem_cell_info info; -+ struct device_node *layout_np; -+ char mfginfo[1024], *c, *t, *p; -+ int ret = -EINVAL; -+ -+ ret = nvmem_device_read(nvmem, 0, sizeof(mfginfo), mfginfo); -+ if (ret < 0) -+ return ret; -+ else if (ret != sizeof(mfginfo)) -+ return -EIO; -+ -+ layout_np = of_nvmem_layout_get_container(nvmem); -+ if (!layout_np) -+ return -ENOENT; -+ -+ c = mfginfo; -+ while (*c != 0xff) { -+ memset(&info, 0, sizeof(info)); -+ if (*c == '#') -+ goto nextline; -+ -+ t = strchr(c, '='); -+ if (!t) -+ goto nextline; -+ -+ *t = '\0'; -+ ++t; -+ info.offset = t - mfginfo; -+ /* process variable name: convert to lower-case, '_' -> '-' */ -+ p = c; -+ do { -+ *p = tolower(*p); -+ if (*p == '_') -+ *p = '-'; -+ } while (*++p); -+ info.name = c; -+ c = strchr(t, 0xa); /* find newline */ -+ if (!c) -+ break; -+ -+ info.bytes = c - t; -+ if (!strcmp(info.name, "mfg-mac")) { -+ info.raw_len = info.bytes; -+ info.bytes = ETH_ALEN; -+ info.read_post_process = adtran_mac_address_pp; -+ } -+ -+ info.np = of_get_child_by_name(layout_np, info.name); -+ ret = nvmem_add_one_cell(nvmem, &info); -+ if (ret) -+ break; -+ -+ ++c; -+ continue; -+ -+nextline: -+ c = strchr(c, 0xa); /* find newline */ -+ if (!c) -+ break; -+ ++c; -+ } -+ -+ of_node_put(layout_np); -+ -+ return ret; -+} -+ -+static int adtran_probe(struct nvmem_layout *layout) -+{ -+ layout->add_cells = adtran_add_cells; -+ -+ return nvmem_layout_register(layout); -+} -+ -+static void adtran_remove(struct nvmem_layout *layout) -+{ -+ nvmem_layout_unregister(layout); -+} -+ -+static const struct of_device_id adtran_of_match_table[] = { -+ { .compatible = "adtran,mfginfo" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, adtran_of_match_table); -+ -+static struct nvmem_layout_driver adtran_layout = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "adtran-layout", -+ .of_match_table = adtran_of_match_table, -+ }, -+ .probe = adtran_probe, -+ .remove = adtran_remove, -+}; -+module_nvmem_layout_driver(adtran_layout); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Daniel Golle "); -+MODULE_DESCRIPTION("NVMEM layout driver for Adtran mfginfo"); diff --git a/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index c558ce3537..0000000000 --- a/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c46ccb69d17e584479df849a107423175a143c83 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 24 Oct 2020 21:15:20 +0200 -Subject: [PATCH] net: phy: add RTL8367S gigabit switch Kconfig/Makefile entry for MT7622 - -Add a CONFIG_RTL8367S_GSW Kconfig option and the corresponding -obj-$(CONFIG_RTL8367S_GSW) Makefile entry to allow building the -out-of-tree RTL8367S gigabit switch driver used on MT7622 boards. - -Signed-off-by: Felix Fietkau ---- ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -443,6 +443,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - select CRC16 ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -113,6 +113,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/ - obj-y += rtl8261n/ - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch deleted file mode 100644 index 764fe763e1..0000000000 --- a/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ /dev/null @@ -1,39 +0,0 @@ -From ade563ba84496406243b3699a27b3de7e08399e7 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sun, 27 Mar 2022 12:54:03 +0200 -Subject: [PATCH] arm64: dts: mediatek: mt7622: add PCIe slot child nodes - -Add named slot0 and slot1 child nodes to the pcie0 and pcie1 host -controllers in mt7622.dtsi so that device tree overlays can target -specific PCIe slots by phandle. - -Signed-off-by: Felix Fietkau ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -844,6 +844,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - pcie1: pcie@1a145000 { -@@ -882,6 +888,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index e31e02d2c2..0000000000 --- a/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -601,9 +601,9 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - generic_handle_domain_irq(port->irq_domain, - bit - INTX_SHIFT); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch deleted file mode 100644 index f3d308a294..0000000000 --- a/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6a2e17d5c1451025396ba523e9f2d112212c7261 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 3 Oct 2023 02:32:35 +0100 -Subject: [PATCH] mediatek: fix PCIe #PERST being de-asserted too early - -The driver for MediaTek gen3 PCIe hosts de-asserts all reset -signals at the same time using a single register write operation. -Delay the de-assertion of the #PERST signal by 100ms as some PCIe -devices fail to come up otherwise. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -416,7 +416,13 @@ static int mtk_pcie_startup_port(struct - msleep(100); - - /* De-assert reset signals */ -- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); -+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); -+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); -+ -+ msleep(100); -+ -+ /* De-assert PERST# signals */ -+ val &= ~(PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* Check if the link is up or not */ diff --git a/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch b/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch deleted file mode 100644 index 9996501427..0000000000 --- a/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 955a80b20fad77dd73ec17ab64d7eb8014cb59c7 Mon Sep 17 00:00:00 2001 -From: Sky Huang -Date: Wed, 19 Feb 2025 16:39:08 +0800 -Subject: [PATCH 19/20] net: phy: mediatek: Add 2.5Gphy firmware dt-bindings - and dts node - -Add 2.5Gphy firmware dt-bindings and dts node since mtk-2p5ge -driver requires firmware to run. Also, update MAINTAINERS for -MediaTek's built-in 2.5Gphy dt-bindings and change MAINTAINER's name. - -Signed-off-by: Sky Huang ---- - .../bindings/net/mediatek,2p5gphy-fw.yaml | 37 +++++++++++++++++++ - MAINTAINERS | 3 +- - 2 files changed, 39 insertions(+), 1 deletion(-) - create mode 100644 Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml -@@ -0,0 +1,37 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/mediatek,2p5gphy-fw.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek Built-in 2.5G Ethernet PHY -+ -+maintainers: -+ - Sky Huang -+ -+description: | -+ MediaTek Built-in 2.5G Ethernet PHY needs to load firmware so it can -+ run correctly. -+ -+properties: -+ compatible: -+ const: "mediatek,2p5gphy-fw" -+ -+ reg: -+ items: -+ - description: pmb firmware load address -+ - description: firmware trigger register -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phyfw: phy-firmware@f000000 { -+ compatible = "mediatek,2p5gphy-fw"; -+ reg = <0 0x0f100000 0 0x20000>, -+ <0 0x0f0f0018 0 0x20>; -+ }; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14439,9 +14439,10 @@ F: include/linux/pcs/pcs-mtk-usxgmii.h - MEDIATEK ETHERNET PHY DRIVERS - M: Daniel Golle - M: Qingfang Deng --M: SkyLake Huang -+M: Sky Huang - L: netdev@vger.kernel.org - S: Maintained -+F: Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml - F: drivers/net/phy/mediatek/mtk-ge-soc.c - F: drivers/net/phy/mediatek/mtk-phy-lib.c - F: drivers/net/phy/mediatek/mtk-ge.c diff --git a/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch b/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch deleted file mode 100644 index ff7aa40f53..0000000000 --- a/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch +++ /dev/null @@ -1,399 +0,0 @@ -From 4eb44972db02c2b704f0ef5c891f29f25440a063 Mon Sep 17 00:00:00 2001 -From: Sky Huang -Date: Wed, 19 Feb 2025 16:39:10 +0800 -Subject: [PATCH 20/20] net: phy: mediatek: add driver for built-in 2.5G - ethernet PHY on MT7988 - -Add support for internal 2.5Gphy on MT7988. This driver will load -necessary firmware and add appropriate time delay to make sure -that firmware works stably. Also, certain control registers will -be set to fix link-up issues. - -Signed-off-by: Sky Huang ---- - MAINTAINERS | 1 + - drivers/net/phy/mediatek/Kconfig | 11 + - drivers/net/phy/mediatek/Makefile | 1 + - drivers/net/phy/mediatek/mtk-2p5ge.c | 342 +++++++++++++++++++++++++++ - 4 files changed, 355 insertions(+) - create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14443,6 +14443,7 @@ M: Sky Huang -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mtk.h" -+ -+#define MTK_2P5GPHY_ID_MT7988 (0x00339c11) -+ -+#define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" -+#define MT7988_2P5GE_PMB_FW_SIZE (0x20000) -+#define MD32_EN_CFG (0x18) -+#define MD32_EN BIT(0) -+ -+#define BASE100T_STATUS_EXTEND (0x10) -+#define BASE1000T_STATUS_EXTEND (0x11) -+#define EXTEND_CTRL_AND_STATUS (0x16) -+ -+#define PHY_AUX_CTRL_STATUS (0x1d) -+#define PHY_AUX_DPX_MASK GENMASK(5, 5) -+#define PHY_AUX_SPEED_MASK GENMASK(4, 2) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121) -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_HOST_CMD1 0x800e -+#define MTK_PHY_HOST_CMD2 0x800f -+/* Registers on Token Ring debug nodes */ -+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ -+#define AUTO_NP_10XEN BIT(6) -+ -+struct mtk_i2p5ge_phy_priv { -+ bool fw_loaded; -+}; -+ -+enum { -+ PHY_AUX_SPD_10 = 0, -+ PHY_AUX_SPD_100, -+ PHY_AUX_SPD_1000, -+ PHY_AUX_SPD_2500, -+}; -+ -+static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev) -+{ -+ struct mtk_i2p5ge_phy_priv *priv = phydev->priv; -+ void __iomem *mcu_csr_base, *pmb_addr; -+ struct device *dev = &phydev->mdio.dev; -+ const struct firmware *fw; -+ struct device_node *np; -+ int ret, i; -+ u32 reg; -+ -+ np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); -+ if (!np) -+ return -ENOENT; -+ -+ pmb_addr = of_iomap(np, 0); -+ if (!pmb_addr) -+ return -ENOMEM; -+ mcu_csr_base = of_iomap(np, 1); -+ if (!mcu_csr_base) { -+ ret = -ENOMEM; -+ goto free_pmb; -+ } -+ -+ ret = request_firmware(&fw, MT7988_2P5GE_PMB_FW, dev); -+ if (ret) { -+ dev_err(dev, "failed to load firmware: %s, ret: %d\n", -+ MT7988_2P5GE_PMB_FW, ret); -+ goto free; -+ } -+ -+ if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) { -+ dev_err(dev, "Firmware size 0x%zx != 0x%x\n", -+ fw->size, MT7988_2P5GE_PMB_FW_SIZE); -+ ret = -EINVAL; -+ goto release_fw; -+ } -+ -+ reg = readw(mcu_csr_base + MD32_EN_CFG); -+ if (reg & MD32_EN) { -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ usleep_range(10000, 11000); -+ } -+ phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); -+ -+ /* Write magic number to safely stall MCU */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df); -+ -+ for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4) -+ writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); -+ -+ if (!priv->fw_loaded) -+ dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n", -+ be16_to_cpu(*((__be16 *)(fw->data + -+ MT7988_2P5GE_PMB_FW_SIZE - 8))), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2), -+ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1)); -+ -+ writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ /* We need a delay here to stabilize initialization of MCU */ -+ usleep_range(7000, 8000); -+ -+ priv->fw_loaded = true; -+ -+release_fw: -+ release_firmware(fw); -+free: -+ iounmap(mcu_csr_base); -+free_pmb: -+ iounmap(pmb_addr); -+ -+ return ret; -+} -+ -+static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) -+{ -+ struct pinctrl *pinctrl; -+ int ret; -+ -+ /* Check if PHY interface type is compatible */ -+ if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) -+ return -ENODEV; -+ -+ ret = mt798x_2p5ge_phy_load_fw(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Setup LED */ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 | -+ MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 | -+ MTK_PHY_LED_ON_LINK2500); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, -+ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); -+ -+ /* Switch pinctrl after setting polarity to avoid bogus blinking */ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); -+ if (IS_ERR(pinctrl) && PTR_ERR(pinctrl) != -ENODEV) -+ dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); -+ -+ /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */ -+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN, -+ FIELD_PREP(AUTO_NP_10XEN, 0x1)); -+ -+ /* Enable HW auto downshift */ -+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, -+ MTK_PHY_AUX_CTRL_AND_STATUS, -+ 0, MTK_PHY_ENABLE_DOWNSHIFT); -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) -+{ -+ bool changed = false; -+ u32 adv; -+ int ret; -+ -+ ret = genphy_c45_an_config_aneg(phydev); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ /* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in -+ * our design. -+ */ -+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); -+ ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ return __genphy_config_aneg(phydev, changed); -+} -+ -+static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = genphy_c45_pma_read_abilities(phydev); -+ if (ret) -+ return ret; -+ -+ /* This phy can't handle collision, and neither can (XFI)MAC it's -+ * connected to. Although it can do HDX handshake, it doesn't support -+ * CSMA/CD that HDX requires. -+ */ -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, -+ phydev->supported); -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy -+ * actually hasn't finished AN. So use CL22's link update function -+ * instead. -+ */ -+ ret = genphy_update_link(phydev); -+ if (ret) -+ return ret; -+ -+ phydev->speed = SPEED_UNKNOWN; -+ phydev->duplex = DUPLEX_UNKNOWN; -+ phydev->pause = 0; -+ phydev->asym_pause = 0; -+ -+ /* We'll read link speed through vendor specific registers down below. -+ * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma -+ * (AN off). -+ */ -+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { -+ ret = genphy_c45_read_lpa(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Clause 45 doesn't define 1000BaseT support. Read the link -+ * partner's 1G advertisement via Clause 22. -+ */ -+ ret = phy_read(phydev, MII_STAT1000); -+ if (ret < 0) -+ return ret; -+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); -+ } else if (phydev->autoneg == AUTONEG_DISABLE) { -+ linkmode_zero(phydev->lp_advertising); -+ } -+ -+ if (phydev->link) { -+ ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); -+ if (ret < 0) -+ return ret; -+ -+ switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { -+ case PHY_AUX_SPD_10: -+ phydev->speed = SPEED_10; -+ break; -+ case PHY_AUX_SPD_100: -+ phydev->speed = SPEED_100; -+ break; -+ case PHY_AUX_SPD_1000: -+ phydev->speed = SPEED_1000; -+ break; -+ case PHY_AUX_SPD_2500: -+ phydev->speed = SPEED_2500; -+ break; -+ } -+ -+ phydev->duplex = DUPLEX_FULL; -+ /* FIXME: -+ * The current firmware always enables rate adaptation mode. -+ */ -+ phydev->rate_matching = RATE_MATCH_PAUSE; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev, -+ phy_interface_t iface) -+{ -+ return RATE_MATCH_PAUSE; -+} -+ -+static int mt798x_2p5ge_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_i2p5ge_phy_priv *priv; -+ -+ priv = devm_kzalloc(&phydev->mdio.dev, -+ sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ switch (phydev->drv->phy_id) { -+ case MTK_2P5GPHY_ID_MT7988: -+ /* The original hardware only sets MDIO_DEVS_PMAPMD */ -+ phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS | -+ MDIO_DEVS_AN | -+ MDIO_DEVS_VEND1 | -+ MDIO_DEVS_VEND2; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ priv->fw_loaded = false; -+ phydev->priv = priv; -+ -+ return 0; -+} -+ -+static struct phy_driver mtk_2p5gephy_driver[] = { -+ { -+ PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 2.5GbE PHY", -+ .probe = mt798x_2p5ge_phy_probe, -+ .config_init = mt798x_2p5ge_phy_config_init, -+ .config_aneg = mt798x_2p5ge_phy_config_aneg, -+ .get_features = mt798x_2p5ge_phy_get_features, -+ .read_status = mt798x_2p5ge_phy_read_status, -+ .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_phy_read_page, -+ .write_page = mtk_phy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_2p5gephy_driver); -+ -+static const struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { -+ { PHY_ID_MATCH_VENDOR(0x00339c00) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -+MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW); diff --git a/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 1642cfe22a..0000000000 --- a/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,91 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -832,6 +832,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -876,6 +879,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -937,7 +943,7 @@ - }; - - hifsys: clock-controller@1af00000 { -- compatible = "mediatek,mt7622-hifsys"; -+ compatible = "mediatek,mt7622-hifsys", "syscon"; - reg = <0 0x1af00000 0 0x70>; - #clock-cells = <1>; - }; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1047,6 +1053,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err, slot; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - slot = of_get_pci_domain_nr(dev->of_node); - if (slot < 0) { - for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0d..0000000000 --- a/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch deleted file mode 100644 index 003e8b6aaa..0000000000 --- a/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch +++ /dev/null @@ -1,42 +0,0 @@ -From d0d6b8e1833c587d0c50cac4f6324aa93b0bc8fc Mon Sep 17 00:00:00 2001 -From: John Audia -Date: Wed, 6 Jul 2022 11:49:50 -0400 -Subject: [PATCH] mt7622: remove 300 MHz from dts - -Due to the bug described here[1], remove the 300 MHz clock to avoid a low -voltage condition that can cause a hang when rebooting the RT3200/E8450. - -This solution is probably better than the script-based work-around[2]. - -1. https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -2. https://github.com/openwrt/openwrt/pull/5025 - -Signed-off-by: John Audia -Tested-by: Rui Salvaterra -Tested-by: John Audia ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -23,11 +23,17 @@ - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <950000>; -- }; -- -+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low -+ * voltage condition that can cause a hang when rebooting the RT3200/E8450. -+ * -+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -+ * -+ * opp-300000000 { -+ * opp-hz = /bits/ 64 <300000000>; -+ * opp-microvolt = <950000>; -+ * }; -+ * -+ */ - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch b/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch deleted file mode 100644 index 4ebaffd1dd..0000000000 --- a/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 23 Mar 2024 20:21:14 +0100 -Subject: [PATCH] net: phy: add Airoha EN8801SC PHY - -Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a -modified version of MTK SDK driver. - -Signed-off-by: Robert Marko ---- - drivers/net/phy/Kconfig | 5 +++++ - drivers/net/phy/Makefile | 1 + - 2 files changed, 6 insertions(+) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -165,6 +165,11 @@ config AS21XXX_PHY - AS21210PB1 that all register with the PHY ID 0x7500 0x7500 - before the firmware is loaded. - -+config AIROHA_EN8801SC_PHY -+ tristate "Airoha EN8801SC Gigabit PHY" -+ help -+ Currently supports the Airoha EN8801SC PHY. -+ - config AIR_EN8811H_PHY - tristate "Airoha EN8811H 2.5 Gigabit PHY" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -50,6 +50,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) - - obj-$(CONFIG_ADIN_PHY) += adin.o - obj-$(CONFIG_ADIN1100_PHY) += adin1100.o -+obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o - obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o - obj-$(CONFIG_AMD_PHY) += amd.o - obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o diff --git a/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch b/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch deleted file mode 100644 index 3b0b06bc10..0000000000 --- a/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch +++ /dev/null @@ -1,65 +0,0 @@ -From ddfae94a14bf0fc301505da75825dfe473525a33 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 29 Oct 2024 13:40:11 +0100 -Subject: [PATCH] mediatek: add support for swapping the polarity on usxgmii interfaces - -This patch comes from the MTK SDK. - -Signed-off-by: John Crispin ---- ---- a/drivers/net/pcs/pcs-mtk-usxgmii.c -+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c -@@ -52,6 +52,12 @@ - #define USXGMII_LPA GENMASK(15, 0) - #define USXGMII_LPA_LATCH BIT(31) - -+/* Register to control PCS polarity */ -+#define RG_PHY_TOP_CTRL0 0x82C -+#define USXGMII_PN_SWAP_MASK GENMASK(1, 0) -+#define USXGMII_PN_SWAP_RX BIT(1) -+#define USXGMII_PN_SWAP_TX BIT(0) -+ - /* Register to read PCS link status */ - #define RG_PCS_RX_STATUS0 0x904 - #define RG_PCS_RX_STATUS_UPDATE BIT(16) -@@ -74,6 +80,7 @@ struct mtk_usxgmii_pcs { - struct clk *clk; - struct reset_control *reset; - phy_interface_t interface; -+ unsigned int polarity; - unsigned int neg_mode; - struct list_head node; - }; -@@ -155,6 +162,10 @@ static int mtk_usxgmii_pcs_config(struct - - mtk_usxgmii_reset(mpcs); - -+ /* Configure the interface polarity */ -+ mtk_m32(mpcs, RG_PHY_TOP_CTRL0, -+ USXGMII_PN_SWAP_MASK, mpcs->polarity); -+ - /* Setup USXGMII AN ctrl */ - mtk_m32(mpcs, RG_PCS_AN_CTRL0, - USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, -@@ -332,6 +343,7 @@ static const struct phylink_pcs_ops mtk_ - static int mtk_usxgmii_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; - struct mtk_usxgmii_pcs *mpcs; - - mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL); -@@ -342,6 +354,13 @@ static int mtk_usxgmii_probe(struct plat - if (IS_ERR(mpcs->base)) - return PTR_ERR(mpcs->base); - -+ if (of_property_read_bool(np->parent, "mediatek,pnswap")) -+ mpcs->polarity = USXGMII_PN_SWAP_TX | USXGMII_PN_SWAP_RX; -+ else if (of_property_read_bool(np, "mediatek,pnswap-tx")) -+ mpcs->polarity = USXGMII_PN_SWAP_TX; -+ else if (of_property_read_bool(np, "mediatek,pnswap-rx")) -+ mpcs->polarity = USXGMII_PN_SWAP_RX; -+ - mpcs->dev = dev; - mpcs->pcs.ops = &mtk_usxgmii_pcs_ops; - mpcs->pcs.poll = true; diff --git a/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch b/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch deleted file mode 100644 index 188540591e..0000000000 --- a/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch +++ /dev/null @@ -1,309 +0,0 @@ -From: Christian Marangi -To: Christian Marangi , - Lee Jones , Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Andrew Lunn , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , Paolo Abeni , - Vladimir Oltean , - Srinivas Kandagatla , - Heiner Kallweit , - Russell King , - Matthias Brugger , - AngeloGioacchino Del Regno - , - linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, - devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, - upstream@airoha.com -Subject: [net-next PATCH v11 0/9] net: dsa: Add Airoha AN8855 support -Date: Mon, 9 Dec 2024 14:44:17 +0100 [thread overview] -Message-ID: <20241209134459.27110-1-ansuelsmth@gmail.com> (raw) - -This small series add the initial support for the Airoha AN8855 Switch. - -It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port. - -This is starting to get in the wild and there are already some router -having this switch chip. - -It's conceptually similar to mediatek switch but register and bits -are different. And there is that massive Hell that is the PCS -configuration. -Saddly for that part we have absolutely NO documentation currently. - -There is this special thing where PHY needs to be calibrated with values -from the switch efuse. (the thing have a whole cpu timer and MCU) - -Changes v11: -- Address reviews from Christophe (spell mistake + dev_err_probe) -- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO) - (indirectly fix link error for mdio APIs) -- Fix copy-paste error for MFD driver of_table -- Fix compilation error for PHY (move NVMEM to .config) -- Drop unneeded NVMEM node from MDIO example schema (from Andrew) -- Adapt MFD example schema to MDIO reg property restrictions -Changes v10: -- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers -- Drop EEE OPs (while Russell finish RFC for EEE changes) -- Use new pcs_inpand OPs -- Drop AN restart function and move to pcs_config -- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation) -- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER - (needed now that NVMEM driver is register externally instead of internally to switch - node) -Changes v9: -- Error out on using 5G speed as currently not supported -- Add missing MAC_2500FD in phylink mac_capabilities -- Add comment and improve if condition for an8855_phylink_mac_config -Changes v8: -- Add port Fast Age support -- Add support for Port Isolation -- Use correct register for Learning Disable -- Add support for Ageing Time OP -- Set default PVID to 0 by default -- Add mdb OPs -- Add port change MTU -- Fix support for Upper VLAN -Changes v7: -- Fix devm_dsa_register_switch wrong export symbol -Changes v6: -- Drop standard MIB and handle with ethtool OPs (as requested by Jakub) -- Cosmetic: use bool instead of 0 or 1 -Changes v5: -- Add devm_dsa_register_switch() patch -- Add Reviewed-by tag for DT patch -Changes v4: -- Set regmap readable_table static (mute compilation warning) -- Add support for port_bridge flags (LEARNING, FLOOD) -- Reset fdb struct in fdb_dump -- Drop support_asym_pause in port_enable -- Add define for get_phy_flags -- Fix bug for port not inititially part of a bridge - (in an8855_setup the port matrix was always cleared but - the CPU port was never initially added) -- Disable learning and flood for user port by default -- Set CPU port to flood and learning by default -- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up -- Drop RGMII from pcs_config -- Check ret in "Disable AN if not in autoneg" -- Use devm_mutex_init -- Fix typo for AN8855_PORT_CHECK_MODE -- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING -- Fix typo in AN8855_PHY_EN_DOWN_SHIFT -- Use paged helper for PHY -- Skip calibration in config_init if priv not defined -Changes v3: -- Out of RFC -- Switch PHY code to select_page API -- Better describe masks and bits in PHY driver for ADC register -- Drop raw values and use define for mii read/write -- Switch to absolute PHY address -- Replace raw values with mask and bits for pcs_config -- Fix typo for ext-surge property name -- Drop support for relocating Switch base PHY address on the bus -Changes v2: -- Drop mutex guard patch -- Drop guard usage in DSA driver -- Use __mdiobus_write/read -- Check return condition and return errors for mii read/write -- Fix wrong logic for EEE -- Fix link_down (don't force link down with autoneg) -- Fix forcing speed on sgmii autoneg -- Better document link speed for sgmii reg -- Use standard define for sgmii reg -- Imlement nvmem support to expose switch EFUSE -- Rework PHY calibration with the use of NVMEM producer/consumer -- Update DT with new NVMEM property -- Move aneg validation for 2500-basex in pcs_config -- Move r50Ohm table and function to PHY driver - -Christian Marangi (9): - dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE - dt-bindings: net: Document support for Airoha AN8855 Switch Virtual - MDIO - dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch - dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC - mfd: an8855: Add support for Airoha AN8855 Switch MFD - net: mdio: Add Airoha AN8855 Switch MDIO Passtrough - nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE - net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver - net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY - - .../bindings/mfd/airoha,an8855-mfd.yaml | 178 ++ - .../bindings/net/airoha,an8855-mdio.yaml | 56 + - .../net/dsa/airoha,an8855-switch.yaml | 105 + - .../bindings/nvmem/airoha,an8855-efuse.yaml | 123 + - MAINTAINERS | 17 + - drivers/mfd/Kconfig | 10 + - drivers/mfd/Makefile | 1 + - drivers/mfd/airoha-an8855.c | 278 ++ - drivers/net/dsa/Kconfig | 9 + - drivers/net/dsa/Makefile | 1 + - drivers/net/dsa/an8855.c | 2310 +++++++++++++++++ - drivers/net/dsa/an8855.h | 783 ++++++ - drivers/net/mdio/Kconfig | 9 + - drivers/net/mdio/Makefile | 1 + - drivers/net/mdio/mdio-an8855.c | 113 + - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/air_an8855.c | 267 ++ - drivers/nvmem/Kconfig | 11 + - drivers/nvmem/Makefile | 2 + - drivers/nvmem/an8855-efuse.c | 63 + - include/linux/mfd/airoha-an8855-mfd.h | 41 + - 22 files changed, 4384 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855-mfd.yaml - create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml - create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml - create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml - create mode 100644 drivers/mfd/airoha-an8855.c - create mode 100644 drivers/net/dsa/an8855.c - create mode 100644 drivers/net/dsa/an8855.h - create mode 100644 drivers/net/mdio/mdio-an8855.c - create mode 100644 drivers/net/phy/air_an8855.c - create mode 100644 drivers/nvmem/an8855-efuse.c - create mode 100644 include/linux/mfd/airoha-an8855-mfd.h - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -53,6 +53,16 @@ config MFD_ALTERA_SYSMGR - using regmap_mmio accesses for ARM32 parts and SMC calls to - EL3 for ARM64 parts. - -+config MFD_AIROHA_AN8855 -+ tristate "Airoha AN8855 Switch MFD" -+ select MFD_CORE -+ select MDIO_DEVICE -+ depends on NETDEVICES && OF -+ help -+ Support for the Airoha AN8855 Switch MFD. This is a SoC Switch -+ that provides various peripherals. Currently it provides a -+ DSA switch and a NVMEM provider. -+ - config MFD_ACT8945A - tristate "Active-semi ACT8945A" - select MFD_CORE ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_MFD_88PM800) += 88pm800.o 8 - obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o - obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o - obj-$(CONFIG_MFD_ACT8945A) += act8945a.o -+obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o - obj-$(CONFIG_MFD_SM501) += sm501.o - obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o - obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o ---- a/drivers/net/dsa/Kconfig -+++ b/drivers/net/dsa/Kconfig -@@ -24,6 +24,15 @@ config NET_DSA_LOOP - This enables support for a fake mock-up switch chip which - exercises the DSA APIs. - -+config NET_DSA_AN8855 -+ tristate "Airoha AN8855 Ethernet switch support" -+ depends on MFD_AIROHA_AN8855 -+ depends on NET_DSA -+ select NET_DSA_TAG_MTK -+ help -+ This enables support for the Airoha AN8855 Ethernet switch -+ chip. -+ - source "drivers/net/dsa/hirschmann/Kconfig" - - config NET_DSA_LANTIQ_GSWIP ---- a/drivers/net/dsa/Makefile -+++ b/drivers/net/dsa/Makefile -@@ -6,6 +6,7 @@ ifdef CONFIG_NET_DSA_LOOP - obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o - endif - obj-$(CONFIG_NET_DSA_KS8995) += ks8995.o -+obj-$(CONFIG_NET_DSA_AN8855) += an8855.o - obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o - obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o - obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o ---- a/drivers/net/mdio/Kconfig -+++ b/drivers/net/mdio/Kconfig -@@ -61,6 +61,15 @@ config MDIO_XGENE - This module provides a driver for the MDIO busses found in the - APM X-Gene SoC's. - -+config MDIO_AN8855 -+ tristate "Airoha AN8855 Switch MDIO bus controller" -+ depends on MFD_AIROHA_AN8855 -+ depends on OF_MDIO -+ help -+ This module provides a driver for the Airoha AN8855 Switch -+ that requires a MDIO passtrough as switch address is shared -+ with the internal PHYs and requires additional page handling. -+ - config MDIO_ASPEED - tristate "ASPEED MDIO bus controller" - depends on ARCH_ASPEED || COMPILE_TEST ---- a/drivers/net/mdio/Makefile -+++ b/drivers/net/mdio/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o - obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o - obj-$(CONFIG_OF_MDIO) += of_mdio.o - -+obj-$(CONFIG_MDIO_AN8855) += mdio-an8855.o - obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o - obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o - obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -170,6 +170,11 @@ config AIROHA_EN8801SC_PHY - help - Currently supports the Airoha EN8801SC PHY. - -+config AIR_AN8855_PHY -+ tristate "Airoha AN8855 Internal Gigabit PHY" -+ help -+ Currently supports the internal Airoha AN8855 Switch PHY. -+ - config AIR_EN8811H_PHY - tristate "Airoha EN8811H 2.5 Gigabit PHY" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -51,6 +51,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) - obj-$(CONFIG_ADIN_PHY) += adin.o - obj-$(CONFIG_ADIN1100_PHY) += adin1100.o - obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o -+obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o - obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o - obj-$(CONFIG_AMD_PHY) += amd.o - obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -29,6 +29,17 @@ source "drivers/nvmem/layouts/Kconfig" - - # Devices - -+config NVMEM_AN8855_EFUSE -+ tristate "Airoha AN8855 eFuse support" -+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST -+ help -+ Say y here to enable support for reading eFuses on Airoha AN8855 -+ Switch. These are e.g. used to store factory programmed -+ calibration data required for the PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-an8855-efuse. -+ - config NVMEM_APPLE_EFUSES - tristate "Apple eFuse support" - depends on ARCH_APPLE || COMPILE_TEST ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o - obj-y += layouts/ - - # Devices -+obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o -+nvmem-an8855-efuse-y := an8855-efuse.o - obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o - nvmem-apple-efuses-y := apple-efuses.o - obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o diff --git a/target/linux/mediatek/patches-6.12/740-net-pcs-mtk_lynxi-add-mt7987-support.patch b/target/linux/mediatek/patches-6.12/740-net-pcs-mtk_lynxi-add-mt7987-support.patch deleted file mode 100644 index d4d09b64fd..0000000000 --- a/target/linux/mediatek/patches-6.12/740-net-pcs-mtk_lynxi-add-mt7987-support.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 6e9ec5ade644eeb136c6b827d72fac80bf2c3817 Mon Sep 17 00:00:00 2001 -From: Bo-Cun Chen -Date: Fri, 9 May 2025 13:22:14 +0800 -Subject: [PATCH] net: pcs: mtk_lynxi add mt7987 support - -Signed-off-by: Bo-Cun Chen ---- - drivers/net/pcs/pcs-mtk-lynxi.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/net/pcs/pcs-mtk-lynxi.c -+++ b/drivers/net/pcs/pcs-mtk-lynxi.c -@@ -413,9 +413,12 @@ static int mtk_pcs_lynxi_probe(struct pl - if (of_property_read_bool(np->parent, "mediatek,pnswap")) - flags |= MTK_SGMII_FLAG_PN_SWAP; - -- mpcs->rstc = of_reset_control_get_shared(np->parent, NULL); -- if (IS_ERR(mpcs->rstc)) -- return PTR_ERR(mpcs->rstc); -+ if (of_parse_phandle(np->parent, "resets", 0)) { -+ mpcs->rstc = of_reset_control_get_shared(np->parent, NULL); -+ if (IS_ERR(mpcs->rstc)) -+ return PTR_ERR(mpcs->rstc); -+ } else -+ mpcs->rstc = NULL; - - reset_control_deassert(mpcs->rstc); - mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel"); -@@ -462,6 +465,7 @@ static void mtk_pcs_lynxi_remove(struct - } - - static const struct of_device_id mtk_pcs_lynxi_of_match[] = { -+ { .compatible = "mediatek,mt7987-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 }, - { .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 }, - { /* sentinel */ }, - }; diff --git a/target/linux/mediatek/patches-6.12/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch b/target/linux/mediatek/patches-6.12/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch deleted file mode 100644 index eef6e361a9..0000000000 --- a/target/linux/mediatek/patches-6.12/741-net-pcs-mtk-lynxi-add-phya-tx-rx-clock-path.patch +++ /dev/null @@ -1,89 +0,0 @@ -From be193994deca7cc3ca6ddedc6efd06182b032f21 Mon Sep 17 00:00:00 2001 -From: Bo-Cun Chen -Date: Tue, 6 May 2025 12:53:37 +0800 -Subject: [PATCH] net: pcs: mtk-lynxi: add phya tx rx clock path - -In NETSYSv3.1, the SGMII hardware introduces a new clock path from PHYA. -Consequently, users can switch the SGMII PCS to this new clock source -for better performance on the MT7987. - -Signed-off-by: Bo-Cun Chen ---- ---- a/drivers/net/pcs/pcs-mtk-lynxi.c -+++ b/drivers/net/pcs/pcs-mtk-lynxi.c -@@ -25,6 +25,7 @@ - #define SGMSYS_PCS_CONTROL_1 0x0 - #define SGMII_BMCR GENMASK(15, 0) - #define SGMII_BMSR GENMASK(31, 16) -+#define SGMII_REF_CK_SEL BIT(24) - - #define SGMSYS_PCS_DEVICE_ID 0x4 - #define SGMII_LYNXI_DEV_ID 0x4d544950 -@@ -52,6 +53,8 @@ - #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) - #define SGMII_DUPLEX_HALF BIT(4) - #define SGMII_REMOTE_FAULT_DIS BIT(8) -+#define SGMII_TRXBUF_THR_MASK GENMASK(31, 16) -+#define SGMII_TRXBUF_THR(x) FIELD_PREP(SGMII_TRXBUF_THR_MASK, (x)) - - /* Register to reset SGMII design */ - #define SGMSYS_RESERVED_0 0x34 -@@ -166,7 +169,7 @@ static int mtk_pcs_lynxi_config(struct p - { - struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); - bool mode_changed = false, changed; -- unsigned int rgc3, sgm_mode, bmcr = 0; -+ unsigned int rgc3, sgm_mode, bmcr = 0, trxbuf_thr = 0x3112; - int advertise, link_timer; - - advertise = phylink_mii_c22_pcs_encode_advertisement(interface, -@@ -193,6 +196,12 @@ static int mtk_pcs_lynxi_config(struct p - bmcr = BMCR_ANENABLE; - } - -+ /* Configure SGMII PCS clock source */ -+ if (mpcs->flags & MTK_SGMII_FLAG_PHYA_TRX_CK) { -+ bmcr |= SGMII_REF_CK_SEL; -+ trxbuf_thr = 0x2111; -+ } -+ - if (mpcs->interface != interface) { - link_timer = phylink_get_link_timer_ns(interface); - if (link_timer < 0) -@@ -235,12 +244,14 @@ static int mtk_pcs_lynxi_config(struct p - - /* Update the sgmsys mode register */ - regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, -+ SGMII_TRXBUF_THR_MASK | - SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN | -- SGMII_IF_MODE_SGMII, sgm_mode); -+ SGMII_IF_MODE_SGMII, -+ SGMII_TRXBUF_THR(trxbuf_thr) | sgm_mode); - - /* Update the BMCR */ - regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, -- BMCR_ANENABLE, bmcr); -+ SGMII_REF_CK_SEL | BMCR_ANENABLE, bmcr); - - /* Release PHYA power down state - * Only removing bit SGMII_PHYA_PWD isn't enough. -@@ -413,6 +424,9 @@ static int mtk_pcs_lynxi_probe(struct pl - if (of_property_read_bool(np->parent, "mediatek,pnswap")) - flags |= MTK_SGMII_FLAG_PN_SWAP; - -+ if (of_property_read_bool(np->parent, "mediatek,phya_trx_ck")) -+ flags |= MTK_SGMII_FLAG_PHYA_TRX_CK; -+ - if (of_parse_phandle(np->parent, "resets", 0)) { - mpcs->rstc = of_reset_control_get_shared(np->parent, NULL); - if (IS_ERR(mpcs->rstc)) ---- a/include/linux/pcs/pcs-mtk-lynxi.h -+++ b/include/linux/pcs/pcs-mtk-lynxi.h -@@ -6,6 +6,7 @@ - #include - - #define MTK_SGMII_FLAG_PN_SWAP BIT(0) -+#define MTK_SGMII_FLAG_PHYA_TRX_CK BIT(2) - struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, - struct regmap *regmap, - u32 ana_rgc3, u32 flags); diff --git a/target/linux/mediatek/patches-6.12/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch b/target/linux/mediatek/patches-6.12/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch deleted file mode 100644 index d27425592c..0000000000 --- a/target/linux/mediatek/patches-6.12/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch +++ /dev/null @@ -1,325 +0,0 @@ -From 56973433cbea9f91f5f7eddebbc361ffc2bd6156 Mon Sep 17 00:00:00 2001 -From: Bo-Cun Chen -Date: Mon, 26 May 2025 13:20:42 +0800 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add mt7987 support - -Without this patch, users are unable to bring up ETH driver on the -mt7987. - -Signed-off-by: Bo-Cun Chen ---- - drivers/net/ethernet/mediatek/mtk_eth_path.c | 9 +- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 138 ++++++++++++++++--- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 70 ++++++++-- - 3 files changed, 179 insertions(+), 38 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_path.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c -@@ -106,13 +106,14 @@ static int set_mux_gmac2_gmac0_to_gephy( - return 0; - } - --static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path) -+static int set_mux_u3_gmac23_to_qphy(struct mtk_eth *eth, u64 path) - { - unsigned int val = 0, mask = 0, reg = 0; - bool updated = true; - - switch (path) { - case MTK_ETH_PATH_GMAC2_SGMII: -+ case MTK_ETH_PATH_GMAC3_SGMII: - if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) { - reg = USB_PHY_SWITCH_REG; - val = SGMII_QPHY_SEL; -@@ -281,9 +282,9 @@ static const struct mtk_eth_muxc mtk_eth - .cap_bit = MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY, - .set_path = set_mux_gmac2_gmac0_to_gephy, - }, { -- .name = "mux_u3_gmac2_to_qphy", -- .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, -- .set_path = set_mux_u3_gmac2_to_qphy, -+ .name = "mux_u3_gmac23_to_qphy", -+ .cap_bit = MTK_ETH_MUX_U3_GMAC23_TO_QPHY, -+ .set_path = set_mux_u3_gmac23_to_qphy, - }, { - .name = "mux_gmac2_to_2p5gphy", - .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -817,10 +817,16 @@ static void mtk_set_queue_speed(struct m - return; - - val = MTK_QTX_SCH_MIN_RATE_EN | -- /* minimum: 10 Mbps */ -- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | -- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -+ /* minimum: 10 Mbps */ -+ if (mtk_is_netsys_v3_or_greater(eth) && -+ (eth->soc->caps != MT7988_CAPS)) { -+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4); -+ } else { -+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4); -+ } - if (mtk_is_netsys_v1(eth)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - -@@ -847,6 +853,30 @@ static void mtk_set_queue_speed(struct m - default: - break; - } -+ } else if (mtk_is_netsys_v3_or_greater(eth) && -+ (eth->soc->caps != MT7988_CAPS)) { -+ switch (speed) { -+ case SPEED_10: -+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 4) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1); -+ break; -+ case SPEED_100: -+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 5) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1); -+ break; -+ case SPEED_1000: -+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 6) | -+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 10); -+ break; -+ default: -+ break; -+ } - } else { - switch (speed) { - case SPEED_10: -@@ -935,7 +965,7 @@ static void mtk_xgdm_mac_link_up(struct - return; - - /* Eliminate the interference(before link-up) caused by PHY noise */ -- mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); -+ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->hw, mac->id)); - mdelay(20); - mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id)); - -@@ -2908,10 +2938,16 @@ static int mtk_tx_alloc(struct mtk_eth * - mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); - - val = MTK_QTX_SCH_MIN_RATE_EN | -- /* minimum: 10 Mbps */ -- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | -- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | - MTK_QTX_SCH_LEAKY_BUCKET_SIZE; -+ /* minimum: 10 Mbps */ -+ if (mtk_is_netsys_v3_or_greater(eth) && -+ (eth->soc->caps != MT7988_CAPS)) { -+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4); -+ } else { -+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | -+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4); -+ } - if (mtk_is_netsys_v1(eth)) - val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; - mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); -@@ -5892,6 +5928,36 @@ static const struct mtk_soc_data mt7986_ - }, - }; - -+static const struct mtk_soc_data mt7987_data = { -+ .reg_map = &mt7988_reg_map, -+ .ana_rgc3 = 0x128, -+ .caps = MT7987_CAPS, -+ .hw_features = MTK_HW_FEATURES, -+ .required_clks = MT7987_CLKS_BITMAP, -+ .required_pctl = false, -+ .version = 3, -+ .offload_version = 2, -+ .ppe_num = 2, -+ .hash_offset = 4, -+ .has_accounting = true, -+ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, -+ .tx = { -+ DESC_SIZE(struct mtk_tx_dma_v2), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ .dma_size = MTK_DMA_SIZE(2K), -+ .fq_dma_size = MTK_DMA_SIZE(4K), -+ }, -+ .rx = { -+ DESC_SIZE(struct mtk_rx_dma_v2), -+ .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ .dma_size = MTK_DMA_SIZE(2K), -+ }, -+}; -+ - static const struct mtk_soc_data mt7988_data = { - .reg_map = &mt7988_reg_map, - .ana_rgc3 = 0x128, -@@ -5953,6 +6019,7 @@ const struct of_device_id of_mtk_match[] - { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, - { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, - { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, -+ { .compatible = "mediatek,mt7987-eth", .data = &mt7987_data }, - { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, - { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, - {}, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -262,6 +262,13 @@ - #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) - #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) - -+#define MTK_QTX_SCH_MAX_RATE_EN_V3 BIT(26) -+#define MTK_QTX_SCH_MIN_RATE_MAN_V3 GENMASK(25, 19) -+#define MTK_QTX_SCH_MIN_RATE_EXP_V3 GENMASK(18, 16) -+#define MTK_QTX_SCH_MAX_RATE_WEIGHT_V3 GENMASK(15, 10) -+#define MTK_QTX_SCH_MAX_RATE_MAN_V3 GENMASK(9, 3) -+#define MTK_QTX_SCH_MAX_RATE_EXP_V3 GENMASK(2, 0) -+ - /* QDMA TX Scheduler Rate Control Register */ - #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) - -@@ -536,9 +543,23 @@ - #define XMAC_MCR_FORCE_RX_FC BIT(4) - - /* XFI Mac logic reset registers */ --#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10) -+#define MTK_XMAC_LOGIC_RST(eth, x) (MTK_XMAC_BASE(x) + \ -+ (MTK_HAS_CAPS((eth)->soc->caps, MTK_XGMAC_V2) ? \ -+ 0x820 : 0x10)) - #define XMAC_LOGIC_RST BIT(0) - -+/* XFI Mac status force registers */ -+#define MTK_XMAC_STS(x) (MTK_XMAC_MCR(x) + 0x14) -+ -+/* XFI Mac status force registers */ -+#define MTK_XMAC_STS_FRC(x) (MTK_XMAC_MCR(x) + 0x18) -+#define XMAC_FORCE_RX_FC_MODE BIT(13) -+#define XMAC_FORCE_TX_FC_MODE BIT(12) -+#define XMAC_FORCE_LINK_MODE BIT(8) -+#define XMAC_FORCE_RX_FC BIT(5) -+#define XMAC_FORCE_TX_FC BIT(4) -+#define XMAC_FORCE_LINK BIT(0) -+ - /* XFI Mac count global control */ - #define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100) - #define XMAC_GLB_CNTCLR BIT(0) -@@ -834,6 +855,17 @@ enum mtk_clks_map { - BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ - BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ - BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) -+#define MT7987_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP1) | \ -+ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP3) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ -+ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL)) - #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ - BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ - BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ -@@ -990,12 +1022,14 @@ enum mkt_eth_capabilities { - MTK_RSTCTRL_PPE2_BIT, - MTK_U3_COPHY_V2_BIT, - MTK_SRAM_BIT, -+ MTK_XGMAC_BIT, -+ MTK_XGMAC_V2_BIT, - MTK_36BIT_DMA_BIT, - - /* MUX BITS*/ - MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, - MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, -- MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, -+ MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT, - MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, - MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, - MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, -@@ -1037,14 +1071,16 @@ enum mkt_eth_capabilities { - #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) - #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) - #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) -+#define MTK_XGMAC BIT_ULL(MTK_XGMAC_BIT) -+#define MTK_XGMAC_V2 BIT_ULL(MTK_XGMAC_V2_BIT) - #define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT) - - #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ - BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) - #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ - BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) --#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ -- BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) -+#define MTK_ETH_MUX_U3_GMAC23_TO_QPHY \ -+ BIT_ULL(MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT) - #define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ - BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) - #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ -@@ -1076,12 +1112,13 @@ enum mkt_eth_capabilities { - #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) - #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) - #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) --#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) -+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC) -+#define MTK_GMAC2_2P5GPHY_V2 (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC_V2) - #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) - #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) --#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) --#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) --#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) -+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII | MTK_XGMAC) -+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII | MTK_XGMAC) -+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII | MTK_XGMAC) - - /* MUXes present on SoCs */ - /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ -@@ -1091,9 +1128,9 @@ enum mkt_eth_capabilities { - #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ - (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) - --/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ --#define MTK_MUX_U3_GMAC2_TO_QPHY \ -- (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) -+/* 0: U3 -> QPHY, 1: GMACx -> QPHY where x is 2 or 3 */ -+#define MTK_MUX_U3_GMAC23_TO_QPHY \ -+ (MTK_ETH_MUX_U3_GMAC23_TO_QPHY | MTK_MUX | MTK_INFRA) - - /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ - #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ -@@ -1133,18 +1170,24 @@ enum mkt_eth_capabilities { - #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ - MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ - MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ -- MTK_MUX_U3_GMAC2_TO_QPHY | \ -+ MTK_MUX_U3_GMAC23_TO_QPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) - - #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ -- MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ -+ MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \ - MTK_RSTCTRL_PPE1 | MTK_SRAM) - - #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ - MTK_RSTCTRL_PPE1 | MTK_SRAM) - -+#define MT7987_CAPS (MTK_36BIT_DMA | MTK_GMAC1_SGMII | \ -+ MTK_GMAC2_2P5GPHY_V2 | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \ -+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \ -+ MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \ -+ MTK_QDMA | MTK_RSTCTRL_PPE1) -+ - #define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \ - MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \ - MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \ diff --git a/target/linux/mediatek/patches-6.12/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch b/target/linux/mediatek/patches-6.12/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch deleted file mode 100644 index cef30ef64e..0000000000 --- a/target/linux/mediatek/patches-6.12/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 5ef0b04d30efff8f171e30bfbe876c00e3b9036a Mon Sep 17 00:00:00 2001 -From: Bo-Cun Chen -Date: Fri, 9 May 2025 09:49:04 +0800 -Subject: [PATCH] net: ethernet: mtk_eth_soc: revise hardware configuration for - mt7987 - -Change hardware configuration for the MT7987. - - Enable PSE drop mechanism when the WDMA Rx ring full - - Enable PSE no-drop mechanism for packets from the WDMA Tx - -Signed-off-by: Bo-Cun Chen ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 +++++++++++++-------- - 1 file changed, 31 insertions(+), 18 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4461,27 +4461,40 @@ static int mtk_hw_init(struct mtk_eth *e - mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) | - PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ); - -- /* PSE free buffer drop threshold */ -- mtk_w32(eth, 0x00600009, PSE_IQ_REV(8)); -- -- /* PSE should not drop port8, port9 and port13 packets from -- * WDMA Tx -- */ -- mtk_w32(eth, 0x00002300, PSE_DROP_CFG); -- -- /* PSE should drop packets to port8, port9 and port13 on WDMA Rx -- * ring full -- */ -- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0)); -- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1)); -- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2)); -- -- /* GDM and CDM Threshold */ -- mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES); -- mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); -- -- /* Disable GDM1 RX CRC stripping */ -- mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); -+ if (eth->soc->caps == MT7988_CAPS) { -+ /* PSE free buffer drop threshold */ -+ mtk_w32(eth, 0x00600009, PSE_IQ_REV(8)); -+ -+ /* PSE should not drop port8, port9 and port13 packets -+ * from WDMA Tx -+ */ -+ mtk_w32(eth, 0x00002300, PSE_DROP_CFG); -+ -+ /* PSE should drop packets to port8, port9 and port13 -+ * on WDMA Rx ring full -+ */ -+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0)); -+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1)); -+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2)); -+ -+ /* GDM and CDM Threshold */ -+ mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES); -+ mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); -+ } else if (eth->soc->caps == MT7987_CAPS) { -+ /* PSE should not drop port8 packets from WDMA Tx */ -+ mtk_w32(eth, 0x00000100, PSE_DROP_CFG); -+ -+ /* PSE should drop packets to port8 on WDMA Rx ring -+ * full -+ */ -+ mtk_w32(eth, 0x00000100, PSE_PPE_DROP(0)); -+ mtk_w32(eth, 0x00000100, PSE_PPE_DROP(1)); -+ } -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_ESW)) { -+ /* Disable GDM1 RX CRC stripping */ -+ mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); -+ } - - /* PSE GDM3 MIB counter has incorrect hw default values, - * so the driver ought to read clear the values beforehand diff --git a/target/linux/mediatek/patches-6.12/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch b/target/linux/mediatek/patches-6.12/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch deleted file mode 100644 index 54a5ae3d86..0000000000 --- a/target/linux/mediatek/patches-6.12/752-net-phy-mediatek-i2p5g-add-support-for-mt7987.patch +++ /dev/null @@ -1,419 +0,0 @@ -From d62fc50ff42223df2bd82c1ea0f1786ea26d3f08 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 5 Oct 2025 03:39:52 +0100 -Subject: [PATCH] net: phy: mediatek: add 2.5G PHY support for MT7987 - -Add MT7987 PHY ID, firmware file paths (PMB and DSPBitTb blobs), and the -necessary PMD/XBZ register definitions. Extend the driver probe path to -load and initialise the MT7987-specific firmware and configure the -internal 2.5G PHY hardware. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/net/phy/mediatek/mtk-2p5ge.c -+++ b/drivers/net/phy/mediatek/mtk-2p5ge.c -@@ -12,13 +12,77 @@ - - #include "mtk.h" - -+#define MTK_2P5GPHY_ID_MT7987 (0x00339c91) - #define MTK_2P5GPHY_ID_MT7988 (0x00339c11) - -+#define MT7987_2P5GE_PMB_FW "mediatek/mt7987/i2p5ge-phy-pmb.bin" -+#define MT7987_2P5GE_PMB_FW_SIZE (0x18000) -+#define MT7987_2P5GE_DSPBITTB \ -+ "mediatek/mt7987/i2p5ge-phy-DSPBitTb.bin" -+#define MT7987_2P5GE_DSPBITTB_SIZE (0x7000) -+ - #define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" - #define MT7988_2P5GE_PMB_FW_SIZE (0x20000) -+ -+#define MTK_2P5GPHY_PMD_REG_BASE (0x0f010000) -+#define MTK_2P5GPHY_PMD_REG_LEN (0x210) -+#define DO_NOT_RESET (0x28) -+#define DO_NOT_RESET_XBZ BIT(0) -+#define DO_NOT_RESET_PMA BIT(3) -+#define DO_NOT_RESET_RX BIT(5) -+#define FNPLL_PWR_CTRL1 (0x208) -+#define RG_SPEED_MASK GENMASK(3, 0) -+#define RG_SPEED_2500 BIT(3) -+#define RG_SPEED_100 BIT(0) -+#define FNPLL_PWR_CTRL_STATUS (0x20c) -+#define RG_STABLE_MASK GENMASK(3, 0) -+#define RG_SPEED_2500_STABLE BIT(3) -+#define RG_SPEED_100_STABLE BIT(0) -+ -+#define MTK_2P5GPHY_XBZ_PCS_REG_BASE (0x0f030000) -+#define MTK_2P5GPHY_XBZ_PCS_REG_LEN (0x844) -+#define PHY_CTRL_CONFIG (0x200) -+#define PMU_WP (0x800) -+#define WRITE_PROTECT_KEY (0xCAFEF00D) -+#define PMU_PMA_AUTO_CFG (0x820) -+#define POWER_ON_AUTO_MODE BIT(16) -+#define PMU_AUTO_MODE_EN BIT(0) -+#define PMU_PMA_STATUS (0x840) -+#define CLK_IS_DISABLED BIT(3) -+ -+#define MTK_2P5GPHY_XBZ_PMA_RX_BASE (0x0f080000) -+#define MTK_2P5GPHY_XBZ_PMA_RX_LEN (0x5228) -+#define SMEM_WDAT0 (0x5000) -+#define SMEM_WDAT1 (0x5004) -+#define SMEM_WDAT2 (0x5008) -+#define SMEM_WDAT3 (0x500c) -+#define SMEM_CTRL (0x5024) -+#define SMEM_HW_RDATA_ZERO BIT(24) -+#define SMEM_ADDR_REF_ADDR (0x502c) -+#define CM_CTRL_P01 (0x5100) -+#define CM_CTRL_P23 (0x5124) -+#define DM_CTRL_P01 (0x5200) -+#define DM_CTRL_P23 (0x5224) -+ -+#define MTK_2P5GPHY_CHIP_SCU_BASE (0x0f0cf800) -+#define MTK_2P5GPHY_CHIP_SCU_LEN (0x12c) -+#define SYS_SW_RESET (0x128) -+#define RESET_RST_CNT BIT(0) -+ -+#define MTK_2P5GPHY_MCU_CSR_BASE (0x0f0f0000) -+#define MTK_2P5GPHY_MCU_CSR_LEN (0x20) - #define MD32_EN_CFG (0x18) - #define MD32_EN BIT(0) - -+#define MTK_2P5GPHY_PMB_FW_BASE (0x0f100000) -+//#define MTK_2P5GPHY_PMB_FW_LEN MT7988_2P5GE_PMB_FW_SIZE -+ -+#define MTK_2P5GPHY_APB_BASE (0x11c30000) -+#define MTK_2P5GPHY_APB_LEN (0x9c) -+#define SW_RESET (0x94) -+#define MD32_RESTART_EN_CLEAR BIT(9) -+ -+ - #define BASE100T_STATUS_EXTEND (0x10) - #define BASE1000T_STATUS_EXTEND (0x11) - #define EXTEND_CTRL_AND_STATUS (0x16) -@@ -31,6 +95,14 @@ - #define MTK_PHY_LPI_PCS_DSP_CTRL (0x121) - #define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) - -+#define MTK_PHY_LINK_STATUS_RELATED (0x147) -+#define MTK_PHY_BYPASS_LINK_STATUS_OK BIT(4) -+#define MTK_PHY_FORCE_LINK_STATUS_HCD BIT(3) -+ -+#define MTK_PHY_AN_FORCE_SPEED_REG (0x313) -+#define MTK_PHY_MASTER_FORCE_SPEED_SEL_EN BIT(7) -+#define MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK GENMASK(6, 0) -+ - #define MTK_PHY_HOST_CMD1 0x800e - #define MTK_PHY_HOST_CMD2 0x800f - /* Registers on Token Ring debug nodes */ -@@ -48,7 +120,249 @@ enum { - PHY_AUX_SPD_2500, - }; - --static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev) -+static int mt7987_2p5ge_phy_load_fw(struct phy_device *phydev) -+{ -+ struct mtk_i2p5ge_phy_priv *priv = phydev->priv; -+ struct device *dev = &phydev->mdio.dev; -+ void __iomem *xbz_pcs_reg_base; -+ void __iomem *xbz_pma_rx_base; -+ void __iomem *chip_scu_base; -+ void __iomem *pmd_reg_base; -+ void __iomem *mcu_csr_base; -+ const struct firmware *fw; -+ void __iomem *apb_base; -+ void __iomem *pmb_addr; -+ int ret, i; -+ u32 reg; -+ -+ if (priv->fw_loaded) -+ return 0; -+ -+ apb_base = ioremap(MTK_2P5GPHY_APB_BASE, -+ MTK_2P5GPHY_APB_LEN); -+ if (!apb_base) -+ return -ENOMEM; -+ -+ pmd_reg_base = ioremap(MTK_2P5GPHY_PMD_REG_BASE, -+ MTK_2P5GPHY_PMD_REG_LEN); -+ if (!pmd_reg_base) { -+ ret = -ENOMEM; -+ goto free_apb; -+ } -+ -+ xbz_pcs_reg_base = ioremap(MTK_2P5GPHY_XBZ_PCS_REG_BASE, -+ MTK_2P5GPHY_XBZ_PCS_REG_LEN); -+ if (!xbz_pcs_reg_base) { -+ ret = -ENOMEM; -+ goto free_pmd; -+ } -+ -+ xbz_pma_rx_base = ioremap(MTK_2P5GPHY_XBZ_PMA_RX_BASE, -+ MTK_2P5GPHY_XBZ_PMA_RX_LEN); -+ if (!xbz_pma_rx_base) { -+ ret = -ENOMEM; -+ goto free_pcs; -+ } -+ -+ chip_scu_base = ioremap(MTK_2P5GPHY_CHIP_SCU_BASE, -+ MTK_2P5GPHY_CHIP_SCU_LEN); -+ if (!chip_scu_base) { -+ ret = -ENOMEM; -+ goto free_pma; -+ } -+ -+ mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE, -+ MTK_2P5GPHY_MCU_CSR_LEN); -+ if (!mcu_csr_base) { -+ ret = -ENOMEM; -+ goto free_chip_scu; -+ } -+ -+ pmb_addr = ioremap(MTK_2P5GPHY_PMB_FW_BASE, MT7987_2P5GE_PMB_FW_SIZE); -+ if (!pmb_addr) { -+ return -ENOMEM; -+ goto free_mcu_csr; -+ } -+ -+ ret = request_firmware(&fw, MT7987_2P5GE_PMB_FW, dev); -+ if (ret) { -+ dev_err(dev, "failed to load firmware: %s, ret: %d\n", -+ MT7987_2P5GE_PMB_FW, ret); -+ goto free_pmb_addr; -+ } -+ -+ if (fw->size != MT7987_2P5GE_PMB_FW_SIZE) { -+ dev_err(dev, "PMb firmware size 0x%zx != 0x%x\n", -+ fw->size, MT7987_2P5GE_PMB_FW_SIZE); -+ ret = -EINVAL; -+ goto release_fw; -+ } -+ -+ /* Force 2.5Gphy back to AN state */ -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ usleep_range(5000, 6000); -+ phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); -+ -+ reg = readw(apb_base + SW_RESET); -+ writew(reg & ~MD32_RESTART_EN_CLEAR, apb_base + SW_RESET); -+ writew(reg | MD32_RESTART_EN_CLEAR, apb_base + SW_RESET); -+ writew(reg & ~MD32_RESTART_EN_CLEAR, apb_base + SW_RESET); -+ -+ reg = readw(mcu_csr_base + MD32_EN_CFG); -+ writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ -+ for (i = 0; i < MT7987_2P5GE_PMB_FW_SIZE - 1; i += 4) -+ writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); -+ dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n", -+ be16_to_cpu(*((__be16 *)(fw->data + -+ MT7987_2P5GE_PMB_FW_SIZE - 8))), -+ *(fw->data + MT7987_2P5GE_PMB_FW_SIZE - 6), -+ *(fw->data + MT7987_2P5GE_PMB_FW_SIZE - 5), -+ *(fw->data + MT7987_2P5GE_PMB_FW_SIZE - 2), -+ *(fw->data + MT7987_2P5GE_PMB_FW_SIZE - 1)); -+ release_firmware(fw); -+ -+ /* Enable 100Mbps module clock. */ -+ writel(FIELD_PREP(RG_SPEED_MASK, RG_SPEED_100), -+ pmd_reg_base + FNPLL_PWR_CTRL1); -+ -+ /* Check if 100Mbps module clock is ready. */ -+ ret = readl_poll_timeout(pmd_reg_base + FNPLL_PWR_CTRL_STATUS, reg, -+ reg & RG_SPEED_100_STABLE, 1, 10000); -+ if (ret) -+ dev_err(dev, "Fail to enable 100Mbps module clock: %d\n", ret); -+ -+ /* Enable 2.5Gbps module clock. */ -+ writel(FIELD_PREP(RG_SPEED_MASK, RG_SPEED_2500), -+ pmd_reg_base + FNPLL_PWR_CTRL1); -+ -+ /* Check if 2.5Gbps module clock is ready. */ -+ ret = readl_poll_timeout(pmd_reg_base + FNPLL_PWR_CTRL_STATUS, reg, -+ reg & RG_SPEED_2500_STABLE, 1, 10000); -+ -+ if (ret) -+ dev_err(dev, "Fail to enable 2.5Gbps module clock: %d\n", ret); -+ -+ /* Disable AN */ -+ phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE); -+ -+ /* Force to run at 2.5G speed */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_AN_FORCE_SPEED_REG, -+ MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK, -+ MTK_PHY_MASTER_FORCE_SPEED_SEL_EN | -+ FIELD_PREP(MTK_PHY_MASTER_FORCE_SPEED_SEL_MASK, 0x1b)); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_RELATED, -+ MTK_PHY_BYPASS_LINK_STATUS_OK | -+ MTK_PHY_FORCE_LINK_STATUS_HCD); -+ -+ /* Set xbz, pma and rx as "do not reset" in order to input DSP code. */ -+ reg = readl(pmd_reg_base + DO_NOT_RESET); -+ reg |= DO_NOT_RESET_XBZ | DO_NOT_RESET_PMA | DO_NOT_RESET_RX; -+ writel(reg, pmd_reg_base + DO_NOT_RESET); -+ -+ reg = readl(chip_scu_base + SYS_SW_RESET); -+ writel(reg & ~RESET_RST_CNT, chip_scu_base + SYS_SW_RESET); -+ -+ writel(WRITE_PROTECT_KEY, xbz_pcs_reg_base + PMU_WP); -+ -+ reg = readl(xbz_pcs_reg_base + PMU_PMA_AUTO_CFG); -+ reg |= PMU_AUTO_MODE_EN | POWER_ON_AUTO_MODE; -+ writel(reg, xbz_pcs_reg_base + PMU_PMA_AUTO_CFG); -+ -+ /* Check if clock in auto mode is disabled. */ -+ ret = readl_poll_timeout(xbz_pcs_reg_base + PMU_PMA_STATUS, reg, -+ (reg & CLK_IS_DISABLED) == 0x0, 1, 100000); -+ if (ret) -+ dev_err(dev, "Clock isn't disabled in auto mode: %d\n", ret); -+ -+ reg = readl(xbz_pma_rx_base + SMEM_CTRL); -+ writel(reg | SMEM_HW_RDATA_ZERO, xbz_pma_rx_base + SMEM_CTRL); -+ -+ reg = readl(xbz_pcs_reg_base + PHY_CTRL_CONFIG); -+ writel(reg | BIT(16), xbz_pcs_reg_base + PHY_CTRL_CONFIG); -+ -+ /* Initialize data memory */ -+ reg = readl(xbz_pma_rx_base + DM_CTRL_P01); -+ writel(reg | BIT(28), xbz_pma_rx_base + DM_CTRL_P01); -+ reg = readl(xbz_pma_rx_base + DM_CTRL_P23); -+ writel(reg | BIT(28), xbz_pma_rx_base + DM_CTRL_P23); -+ -+ /* Initialize coefficient memory */ -+ reg = readl(xbz_pma_rx_base + CM_CTRL_P01); -+ writel(reg | BIT(28), xbz_pma_rx_base + CM_CTRL_P01); -+ reg = readl(xbz_pma_rx_base + CM_CTRL_P23); -+ writel(reg | BIT(28), xbz_pma_rx_base + CM_CTRL_P23); -+ -+ /* Initilize PM offset */ -+ writel(0, xbz_pma_rx_base + SMEM_ADDR_REF_ADDR); -+ -+ ret = request_firmware(&fw, MT7987_2P5GE_DSPBITTB, dev); -+ if (ret) { -+ dev_err(dev, "failed to load firmware: %s, ret: %d\n", -+ MT7987_2P5GE_DSPBITTB, ret); -+ goto free_pmb_addr; -+ } -+ if (fw->size != MT7987_2P5GE_DSPBITTB_SIZE) { -+ dev_err(dev, "DSPBITTB size 0x%zx != 0x%x\n", -+ fw->size, MT7987_2P5GE_DSPBITTB_SIZE); -+ ret = -EINVAL; -+ goto release_fw; -+ } -+ -+ for (i = 0; i < fw->size - 1; i += 16) { -+ writel(*((uint32_t *)(fw->data + i)), -+ xbz_pma_rx_base + SMEM_WDAT0); -+ writel(*((uint32_t *)(fw->data + i + 0x4)), -+ xbz_pma_rx_base + SMEM_WDAT1); -+ writel(*((uint32_t *)(fw->data + i + 0x8)), -+ xbz_pma_rx_base + SMEM_WDAT2); -+ writel(*((uint32_t *)(fw->data + i + 0xc)), -+ xbz_pma_rx_base + SMEM_WDAT3); -+ } -+ -+ reg = readl(xbz_pma_rx_base + DM_CTRL_P01); -+ writel(reg & ~BIT(28), xbz_pma_rx_base + DM_CTRL_P01); -+ -+ reg = readl(xbz_pma_rx_base + DM_CTRL_P23); -+ writel(reg & ~BIT(28), xbz_pma_rx_base + DM_CTRL_P23); -+ -+ reg = readl(xbz_pma_rx_base + CM_CTRL_P01); -+ writel(reg & ~BIT(28), xbz_pma_rx_base + CM_CTRL_P01); -+ -+ reg = readl(xbz_pma_rx_base + CM_CTRL_P23); -+ writel(reg & ~BIT(28), xbz_pma_rx_base + CM_CTRL_P23); -+ -+ reg = readw(mcu_csr_base + MD32_EN_CFG); -+ writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG); -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); -+ /* We need a delay here to stabilize initialization of MCU */ -+ usleep_range(7000, 8000); -+ dev_info(dev, "Firmware loading/trigger ok.\n"); -+ -+ priv->fw_loaded = true; -+ -+release_fw: -+ release_firmware(fw); -+free_pmb_addr: -+ iounmap(pmb_addr); -+free_mcu_csr: -+ iounmap(mcu_csr_base); -+free_chip_scu: -+ iounmap(chip_scu_base); -+free_pma: -+ iounmap(xbz_pma_rx_base); -+free_pcs: -+ iounmap(xbz_pcs_reg_base); -+free_pmd: -+ iounmap(pmd_reg_base); -+free_apb: -+ iounmap(apb_base); -+ -+ return ret; -+} -+ -+static int mt7988_2p5ge_phy_load_fw(struct phy_device *phydev) - { - struct mtk_i2p5ge_phy_priv *priv = phydev->priv; - void __iomem *mcu_csr_base, *pmb_addr; -@@ -135,15 +449,27 @@ static int mt798x_2p5ge_phy_config_init( - if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) - return -ENODEV; - -- ret = mt798x_2p5ge_phy_load_fw(phydev); -+ switch (phydev->drv->phy_id) { -+ case MTK_2P5GPHY_ID_MT7987: -+ ret = mt7987_2p5ge_phy_load_fw(phydev); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY); -+ break; -+ case MTK_2P5GPHY_ID_MT7988: -+ ret = mt7988_2p5ge_phy_load_fw(phydev); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY); -+ break; -+ default: -+ return -EINVAL; -+ } - if (ret < 0) - return ret; - - /* Setup LED */ - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -- MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 | -- MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 | -- MTK_PHY_LED_ON_LINK2500); -+ MTK_PHY_LED_ON_LINK10 | MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK2500); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); - -@@ -293,6 +619,7 @@ static int mt798x_2p5ge_phy_probe(struct - return -ENOMEM; - - switch (phydev->drv->phy_id) { -+ case MTK_2P5GPHY_ID_MT7987: - case MTK_2P5GPHY_ID_MT7988: - /* The original hardware only sets MDIO_DEVS_PMAPMD */ - phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS | -@@ -312,6 +639,20 @@ static int mt798x_2p5ge_phy_probe(struct - - static struct phy_driver mtk_2p5gephy_driver[] = { - { -+ PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7987), -+ .name = "MediaTek MT7987 2.5GbE PHY", -+ .probe = mt798x_2p5ge_phy_probe, -+ .config_init = mt798x_2p5ge_phy_config_init, -+ .config_aneg = mt798x_2p5ge_phy_config_aneg, -+ .get_features = mt798x_2p5ge_phy_get_features, -+ .read_status = mt798x_2p5ge_phy_read_status, -+ .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_phy_read_page, -+ .write_page = mtk_phy_write_page, -+ }, -+ { - PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), - .name = "MediaTek MT7988 2.5GbE PHY", - .probe = mt798x_2p5ge_phy_probe, diff --git a/target/linux/mediatek/patches-6.12/821-add-pwm-feature-for-mt7987.patch b/target/linux/mediatek/patches-6.12/821-add-pwm-feature-for-mt7987.patch deleted file mode 100644 index 5b8fe7efcf..0000000000 --- a/target/linux/mediatek/patches-6.12/821-add-pwm-feature-for-mt7987.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 7f4532a2bffdb0aebcabc2a672c4b97670e002a5 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Mon, 3 Mar 2025 14:33:33 +0800 -Subject: [PATCH] add pwm reg-v3 support for mt7987 - ---- - drivers/pwm/pwm-mediatek.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -64,6 +64,10 @@ static const unsigned int mtk_pwm_reg_of - 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 - }; - -+static const unsigned int mtk_pwm_reg_offset_v3[] = { -+ 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800 -+}; -+ - static inline struct pwm_mediatek_chip * - to_pwm_mediatek_chip(struct pwm_chip *chip) - { -@@ -350,6 +354,13 @@ static const struct pwm_mediatek_of_data - .reg_offset = mtk_pwm_reg_offset_v1, - }; - -+static const struct pwm_mediatek_of_data mt7987_pwm_data = { -+ .num_pwms = 3, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v3, -+}; -+ - static const struct pwm_mediatek_of_data mt7988_pwm_data = { - .num_pwms = 8, - .pwm45_fixup = false, -@@ -387,6 +398,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, - { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, -+ { .compatible = "mediatek,mt7987-pwm", .data = &mt7987_pwm_data }, - { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, diff --git a/target/linux/mediatek/patches-6.12/830-thermal-drivers-mediatek-lvts_thermal-Add-irq_enable-support.patch b/target/linux/mediatek/patches-6.12/830-thermal-drivers-mediatek-lvts_thermal-Add-irq_enable-support.patch deleted file mode 100644 index ff1fd3e016..0000000000 --- a/target/linux/mediatek/patches-6.12/830-thermal-drivers-mediatek-lvts_thermal-Add-irq_enable-support.patch +++ /dev/null @@ -1,148 +0,0 @@ -From: Chad Monroe -Date: Mon, 01 Sep 2025 06:42:10 -0700 -Subject: [PATCH] thermal/drivers/mediatek/lvts_thermal: Add irq_enable - support. - -Allow interrupt support to be disabled as some SoCs don't support it. - -Signed-off-by: Chad Monroe ---- - drivers/thermal/mediatek/lvts_thermal.c | 33 ++++++++++++++++------ - 1 file changed, 25 insertions(+), 8 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -127,6 +127,7 @@ struct lvts_data { - const struct lvts_ctrl_data *lvts_ctrl; - const u32 *conn_cmd; - const u32 *init_cmd; -+ bool irq_enable; - int num_lvts_ctrl; - int num_conn_cmd; - int num_init_cmd; -@@ -408,6 +409,10 @@ static int lvts_set_trips(struct thermal - lvts_ctrl->high_thresh = high; - lvts_ctrl->low_thresh = low; - } -+ -+ if (!lvts_data->irq_enable) -+ return 0; -+ - lvts_update_irq_mask(lvts_ctrl); - - if (!should_update_thresh) -@@ -921,6 +926,8 @@ static void lvts_write_config(struct lvt - - static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) - { -+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; -+ - /* - * LVTS_PROTCTL : Thermal Protection Sensor Selection - * -@@ -954,7 +961,8 @@ static int lvts_irq_init(struct lvts_ctr - * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS - * register, except we set the bits to enable the interrupt. - */ -- writel(0, LVTS_MONINT(lvts_ctrl->base)); -+ if (lvts_data->irq_enable) -+ writel(0, LVTS_MONINT(lvts_ctrl->base)); - - return 0; - } -@@ -1338,9 +1346,11 @@ static int lvts_probe(struct platform_de - if (IS_ERR(lvts_td->reset)) - return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); - -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -- return irq; -+ if (lvts_data->irq_enable) { -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ } - - golden_temp_offset = lvts_data->temp_offset; - -@@ -1352,10 +1362,12 @@ static int lvts_probe(struct platform_de - * At this point the LVTS is initialized and enabled. We can - * safely enable the interrupt. - */ -- ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, -- IRQF_ONESHOT, dev_name(dev), lvts_td); -- if (ret) -- return dev_err_probe(dev, ret, "Failed to request interrupt\n"); -+ if (lvts_data->irq_enable) { -+ ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, -+ IRQF_ONESHOT, dev_name(dev), lvts_td); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to request interrupt\n"); -+ } - - platform_set_drvdata(pdev, lvts_td); - -@@ -1754,6 +1766,7 @@ static const struct lvts_ctrl_data mt819 - }; - - static const struct lvts_data mt7988_lvts_ap_data = { -+ .irq_enable = true, - .lvts_ctrl = mt7988_lvts_ap_data_ctrl, - .conn_cmd = mt7988_conn_cmds, - .init_cmd = mt7988_init_cmds, -@@ -1766,6 +1779,7 @@ static const struct lvts_data mt7988_lvt - }; - - static const struct lvts_data mt8186_lvts_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8186_lvts_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1779,6 +1793,7 @@ static const struct lvts_data mt8186_lvt - }; - - static const struct lvts_data mt8188_lvts_mcu_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1792,6 +1807,7 @@ static const struct lvts_data mt8188_lvt - }; - - static const struct lvts_data mt8188_lvts_ap_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8188_lvts_ap_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1805,6 +1821,7 @@ static const struct lvts_data mt8188_lvt - }; - - static const struct lvts_data mt8192_lvts_mcu_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1818,6 +1835,7 @@ static const struct lvts_data mt8192_lvt - }; - - static const struct lvts_data mt8192_lvts_ap_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8192_lvts_ap_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1831,6 +1849,7 @@ static const struct lvts_data mt8192_lvt - }; - - static const struct lvts_data mt8195_lvts_mcu_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, -@@ -1844,6 +1863,7 @@ static const struct lvts_data mt8195_lvt - }; - - static const struct lvts_data mt8195_lvts_ap_data = { -+ .irq_enable = true, - .lvts_ctrl = mt8195_lvts_ap_data_ctrl, - .conn_cmd = default_conn_cmds, - .init_cmd = default_init_cmds, diff --git a/target/linux/mediatek/patches-6.12/831-thermal-drivers-mediatek-lvts_thermal-Add-MT7987-support.patch b/target/linux/mediatek/patches-6.12/831-thermal-drivers-mediatek-lvts_thermal-Add-MT7987-support.patch deleted file mode 100644 index 7cd4affae6..0000000000 --- a/target/linux/mediatek/patches-6.12/831-thermal-drivers-mediatek-lvts_thermal-Add-MT7987-support.patch +++ /dev/null @@ -1,106 +0,0 @@ -From: Chad Monroe -Date: Mon, 01 Sep 2025 06:44:04 -0700 -Subject: [PATCH] thermal/drivers/mediatek/lvts_thermal: Add MT7987 support - -Add support for Mediatek MT7987 LVTS. Based patch[1] from vendor SDK. - -1: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/742007e189ffcc95783924cea1150f574b6eb71e - -Signed-off-by: Chad Monroe ---- - drivers/thermal/mediatek/lvts_thermal.c | 36 ++++++++++ - include/dt-bindings/thermal/mediatek,lvts-thermal.h | 3 - 2 files changed, 39 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -87,6 +87,8 @@ - #define LVTS_COEFF_B_MT8195 250460 - #define LVTS_COEFF_A_MT7988 -204650 - #define LVTS_COEFF_B_MT7988 204650 -+#define LVTS_COEFF_A_MT7987 -204650 -+#define LVTS_COEFF_B_MT7987 204650 - - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 -@@ -1385,6 +1387,19 @@ static void lvts_remove(struct platform_ - lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); - } - -+static const struct lvts_ctrl_data mt7987_lvts_ap_data_ctrl[] = { -+ { -+ .lvts_sensor = { -+ { .dt_id = MT7987_CPU, -+ .cal_offsets = { 0x04, 0x05, 0x06 } }, -+ { .dt_id = MT7987_ETH2P5G, -+ .cal_offsets = { 0x08, 0x09, 0x0a } }, -+ }, -+ VALID_SENSOR_MAP(1, 1, 0, 0), -+ .offset = 0x0, -+ }, -+}; -+ - static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { - { - .lvts_sensor = { -@@ -1455,6 +1470,7 @@ static int lvts_resume(struct device *de - } - - static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; -+static const u32 mt7987_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 }; - static const u32 mt7988_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 }; - - /* -@@ -1467,6 +1483,12 @@ static const u32 default_init_cmds[] = { - 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 - }; - -+static const u32 mt7987_init_cmds[] = { -+ 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC10308C7, -+ 0xC103098D, 0xC1030C7C, 0xC1030AA8, 0xC10308CE, 0xC10308C7, -+ 0xC1030B04, 0xC1030E01, 0xC10306B8 -+}; -+ - static const u32 mt7988_init_cmds[] = { - 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, - 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, -@@ -1765,6 +1787,19 @@ static const struct lvts_ctrl_data mt819 - } - }; - -+static const struct lvts_data mt7987_lvts_ap_data = { -+ .irq_enable = false, -+ .lvts_ctrl = mt7987_lvts_ap_data_ctrl, -+ .conn_cmd = mt7987_conn_cmds, -+ .init_cmd = mt7987_init_cmds, -+ .num_lvts_ctrl = ARRAY_SIZE(mt7987_lvts_ap_data_ctrl), -+ .num_conn_cmd = ARRAY_SIZE(mt7987_conn_cmds), -+ .num_init_cmd = ARRAY_SIZE(mt7987_init_cmds), -+ .temp_factor = LVTS_COEFF_A_MT7987, -+ .temp_offset = LVTS_COEFF_B_MT7987, -+ .gt_calib_bit_offset = 24, -+}; -+ - static const struct lvts_data mt7988_lvts_ap_data = { - .irq_enable = true, - .lvts_ctrl = mt7988_lvts_ap_data_ctrl, -@@ -1877,6 +1912,7 @@ static const struct lvts_data mt8195_lvt - }; - - static const struct of_device_id lvts_of_match[] = { -+ { .compatible = "mediatek,mt7987-lvts-ap", .data = &mt7987_lvts_ap_data }, - { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, - { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, - { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -7,6 +7,9 @@ - #ifndef __MEDIATEK_LVTS_DT_H - #define __MEDIATEK_LVTS_DT_H - -+#define MT7987_CPU 0 -+#define MT7987_ETH2P5G 1 -+ - #define MT7988_CPU_0 0 - #define MT7988_CPU_1 1 - #define MT7988_ETH2P5G_0 2 diff --git a/target/linux/mediatek/patches-6.12/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch b/target/linux/mediatek/patches-6.12/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch deleted file mode 100644 index 9aebab6689..0000000000 --- a/target/linux/mediatek/patches-6.12/840-cpufreq-add-support-to-adjust-cpu-volt-by-efuse-cali.patch +++ /dev/null @@ -1,106 +0,0 @@ -From fbb1d181782f990c0ac5f39d4aa9eda5c39cb442 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 4 Mar 2025 19:28:14 +0800 -Subject: [PATCH 1/2] cpufreq: add support to adjust cpu volt by efuse - calibration data - ---- - drivers/cpufreq/mediatek-cpufreq.c | 81 ++++++++++++++++++++++++++++-- - 1 file changed, 76 insertions(+), 5 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -15,14 +15,26 @@ - #include - #include - #include -+#include -+ -+struct mtk_cpufreq_corr_data { -+ unsigned int freq; -+ unsigned int vbase; -+ unsigned int vscale; -+ unsigned int vmax; -+}; - - struct mtk_cpufreq_platform_data { -+ /* cpufreq correction data specification */ -+ const struct mtk_cpufreq_corr_data *corr_data; - int min_volt_shift; - int max_volt_shift; - int proc_max_volt; - int sram_min_volt; - int sram_max_volt; - bool ccifreq_supported; -+ /* whether voltage correction via nvmem is supported */ -+ bool nvmem_volt_corr; - }; - - /* -@@ -197,6 +209,50 @@ static bool is_ccifreq_ready(struct mtk_ - return true; - } - -+static int mtk_cpufreq_nvmem_volt_corr(struct mtk_cpu_dvfs_info *info, -+ struct cpufreq_policy *policy) -+{ -+ const struct mtk_cpufreq_corr_data *corr_data; -+ unsigned int target_voltage; -+ struct nvmem_cell *cell; -+ unsigned int cal_data; -+ const u8 *buf; -+ size_t len; -+ int i; -+ -+ cell = nvmem_cell_get(info->cpu_dev, "calibration-data"); -+ if (IS_ERR(cell)) -+ return PTR_ERR(cell); -+ -+ buf = nvmem_cell_read(cell, &len); -+ nvmem_cell_put(cell); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ -+ cal_data = buf[0] & 0x1f; -+ pr_debug("%s: read vbinning value: %d\n", __func__, cal_data); -+ kfree(buf); -+ if (!info->soc_data->corr_data) { -+ pr_err("voltage correction data not found\n"); -+ return -EINVAL; -+ } -+ -+ corr_data = &info->soc_data->corr_data[0]; -+ for (i = 0 ; i < corr_data->freq ; i++) { -+ target_voltage = corr_data->vbase + cal_data * corr_data->vscale; -+ if (target_voltage > corr_data->vmax) { -+ pr_warn("freq %u exceeds max voltage\n", corr_data->freq); -+ pr_warn("force update voltage to %u\n", corr_data->vmax); -+ target_voltage = corr_data->vmax; -+ } -+ dev_pm_opp_remove(info->cpu_dev, corr_data->freq); -+ dev_pm_opp_add(info->cpu_dev, corr_data->freq, target_voltage); -+ corr_data = &info->soc_data->corr_data[i + 1]; -+ } -+ -+ return 0; -+} -+ - static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, - unsigned int index) - { -@@ -584,6 +640,15 @@ static int mtk_cpufreq_init(struct cpufr - return -EINVAL; - } - -+ if (info->soc_data->nvmem_volt_corr) { -+ ret = mtk_cpufreq_nvmem_volt_corr(info, policy); -+ if (ret) { -+ pr_err("failed to correction voltage for cpu%d: %d\n", -+ policy->cpu, ret); -+ return ret; -+ } -+ } -+ - ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); - if (ret) { - dev_err(info->cpu_dev, diff --git a/target/linux/mediatek/patches-6.12/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch b/target/linux/mediatek/patches-6.12/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch deleted file mode 100644 index a6422b6402..0000000000 --- a/target/linux/mediatek/patches-6.12/841-cpufreq-add-cpu-volt-correction-support-for-mt7988.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 2595e31220f8e515714a71deb781e3fdf8c483ef Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 5 Oct 2025 03:42:19 +0100 -Subject: [PATCH] cpufreq: mediatek: add nvmem-based CPU voltage correction for MT7988 - -Add mt7988_volt_corr_data[] with correction parameters for the 1800 MHz -OPP and enable the nvmem_volt_corr path in the MT7988 platform data, -allowing the CPU voltage to be adjusted based on calibration values read -from the efuse. Raise proc_max_volt to 1120000 uV accordingly. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -741,6 +741,16 @@ static struct platform_driver mtk_cpufre - .probe = mtk_cpufreq_probe, - }; - -+struct mtk_cpufreq_corr_data mt7988_volt_corr_data[] = { -+ { -+ .freq = 1800000000, -+ .vbase = 850000, -+ .vscale = 10000, -+ .vmax = 1120000, -+ }, -+ { } /* sentinel */ -+}; -+ - static const struct mtk_cpufreq_platform_data mt2701_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -769,10 +779,12 @@ static const struct mtk_cpufreq_platform - static const struct mtk_cpufreq_platform_data mt7988_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -- .proc_max_volt = 900000, -+ .proc_max_volt = 1120000, - .sram_min_volt = 0, - .sram_max_volt = 1150000, - .ccifreq_supported = true, -+ .nvmem_volt_corr = 1, -+ .corr_data = mt7988_volt_corr_data, - }; - - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { diff --git a/target/linux/mediatek/patches-6.12/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch b/target/linux/mediatek/patches-6.12/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch deleted file mode 100644 index 30115a2358..0000000000 --- a/target/linux/mediatek/patches-6.12/842-mediatek-enable-using-efuse-cali-data-for-mt7988-cpu-volt.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c776eb44070d009375559d8c6eb8790edfe129a9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 4 Mar 2025 19:35:14 +0800 -Subject: [PATCH 2/2] cpufreq: mt7988: enable using efuse calibration data for - adjusting cpu volt - ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -55,6 +55,8 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ nvmem-cells = <&cpufreq_calibration>; -+ nvmem-cell-names = "calibration-data"; - mediatek,cci = <&cci>; - }; - -@@ -67,6 +69,8 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ nvmem-cells = <&cpufreq_calibration>; -+ nvmem-cell-names = "calibration-data"; - mediatek,cci = <&cci>; - }; - -@@ -79,6 +83,8 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ nvmem-cells = <&cpufreq_calibration>; -+ nvmem-cell-names = "calibration-data"; - mediatek,cci = <&cci>; - }; - -@@ -91,6 +97,8 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ nvmem-cells = <&cpufreq_calibration>; -+ nvmem-cell-names = "calibration-data"; - mediatek,cci = <&cci>; - }; - diff --git a/target/linux/mediatek/patches-6.12/843-cpufreq-add-support-to-fix-voltage-cpu.patch b/target/linux/mediatek/patches-6.12/843-cpufreq-add-support-to-fix-voltage-cpu.patch deleted file mode 100644 index 8185cdaf3a..0000000000 --- a/target/linux/mediatek/patches-6.12/843-cpufreq-add-support-to-fix-voltage-cpu.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2595e31220f8e515714a71deb781e3fdf8c483ef Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 5 Oct 2025 03:42:19 +0100 -Subject: [PATCH] cpufreq: mediatek: add proc_fixed_volt flag to skip voltage scaling - -Add a proc_fixed_volt boolean to mtk_cpufreq_platform_data. When set, -mtk_cpufreq_set_voltage() returns immediately without programming the -regulator, for SoCs where the CPU core voltage is fixed in hardware and -must not be touched by software. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -35,6 +35,8 @@ struct mtk_cpufreq_platform_data { - bool ccifreq_supported; - /* whether voltage correction via nvmem is supported */ - bool nvmem_volt_corr; -+ /* Flag indicating whether the processor voltage is fixed */ -+ bool proc_fixed_volt; - }; - - /* -@@ -176,6 +178,9 @@ static int mtk_cpufreq_set_voltage(struc - const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; - int ret; - -+ if (soc_data->proc_fixed_volt) -+ return 0; -+ - if (info->need_voltage_tracking) - ret = mtk_cpufreq_voltage_tracking(info, vproc); - else diff --git a/target/linux/mediatek/patches-6.12/844-cpufreq-mediatek-Add-support-for-MT7987.patch b/target/linux/mediatek/patches-6.12/844-cpufreq-mediatek-Add-support-for-MT7987.patch deleted file mode 100644 index 5901b45b9b..0000000000 --- a/target/linux/mediatek/patches-6.12/844-cpufreq-mediatek-Add-support-for-MT7987.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 2595e31220f8e515714a71deb781e3fdf8c483ef Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 5 Oct 2025 03:42:19 +0100 -Subject: [PATCH] cpufreq: mediatek: add platform data and DT match for MT7987 - -Add mt7987_platform_data with proc_max_volt=1023000 uV and -proc_fixed_volt=true (the MT7987 CPU voltage is not software- -controllable), and register it for the "mediatek,mt7987" DT compatible. - -Signed-off-by: Daniel Golle ---- ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -781,6 +781,12 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7987_platform_data = { -+ .proc_max_volt = 1023000, -+ .ccifreq_supported = false, -+ .proc_fixed_volt = true, -+}; -+ - static const struct mtk_cpufreq_platform_data mt7988_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -825,6 +831,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, -+ { .compatible = "mediatek,mt7987", .data = &mt7987_platform_data }, - { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt7988d", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, diff --git a/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch deleted file mode 100644 index 1b768f652c..0000000000 --- a/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 7 Sep 2023 10:54:37 +0800 -Subject: [PATCH] arm64: dts: mt7986: add afe - ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++ - 1 files changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -202,6 +202,29 @@ - #interrupt-cells = <2>; - }; - -+ afe: audio-controller@11210000 { -+ compatible = "mediatek,mt7986-afe"; -+ reg = <0 0x11210000 0 0x9000>; -+ #sound-dai-cells = <0>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, -+ <&infracfg CLK_INFRA_AUD_26M_CK>, -+ <&infracfg CLK_INFRA_AUD_L_CK>, -+ <&infracfg CLK_INFRA_AUD_AUD_CK>, -+ <&infracfg CLK_INFRA_AUD_EG2_CK>; -+ clock-names = "aud_bus_ck", -+ "aud_26m_ck", -+ "aud_l_ck", -+ "aud_aud_ck", -+ "aud_eg2_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, -+ <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ }; -+ - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch deleted file mode 100644 index db51bf1779..0000000000 --- a/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 7 Sep 2023 10:54:37 +0800 -Subject: [PATCH] arm64: dts: mt7986: add sound wm8960 - ---- - .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++ - 1 files changed, 39 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts -@@ -4,6 +4,36 @@ - - / { - compatible = "mediatek,mt7986a-rfb-snand"; -+ -+ sound_wm8960 { -+ compatible = "mediatek,mt7986-wm8960-sound"; -+ audio-routing = "Headphone", "HP_L", -+ "Headphone", "HP_R", -+ "LINPUT1", "AMIC", -+ "RINPUT1", "AMIC"; -+ -+ status = "okay"; -+ -+ platform { -+ sound-dai = <&afe>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ #sound-dai-cells = <0>; -+ reg = <0x1a>; -+ }; - }; - - &spi0 { -@@ -48,3 +78,13 @@ - &wifi { - mediatek,mtd-eeprom = <&factory 0>; - }; -+ -+&pio { -+ i2c_pins: i2c-pins-3-4 { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+}; -+ diff --git a/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch deleted file mode 100644 index dd21397db2..0000000000 --- a/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 957a0921e20257bd94b7f5ace6e07a68e8388499 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 10 Dec 2023 23:09:00 +0000 -Subject: [PATCH] mediatek: bananapi-r3: add overlay for ReSpeaker 2-mic hat - -Add DT overlay to allow using the ReSpeaker 2-mic hat connected to -the 26-pin header of the BananaPi BPi-R3. - -Supported sample formats: S16_LE, S24_LE, S32_LE -Supported sample rates: 8/12/16/24/32/48/96/192 kHz - - | BPi-R3 | ReSpeaker 2-mic - Signal | 26-pin | 40-pin -----------+----------+------------------- - VCC 5V | 2 | 2 - I2C SDA | 3 | 3 - I2C SCL | 5 | 5 - GND | 6 | 6 - PCM CLK | 12 | 12 - PCM FS | 15 | 35 - PCM DIN | 26 | 38 - GND | 25 | 39 - PCM DOUT | 22 | 40 - -Once connected, install the driver and tell U-Boot to apply the DT -overlay: - -opkg kmod-sound-soc-mt7986-wm8960 -fw_setenv bootconf_base "config-mt7986a-bananapi-bpi-r3#mt7986a-bananapi-bpi-r3-respeaker-2mics" -reboot - -To setup the ReSpeaker for Stereo out on the Headphone plug: - -amixer sset 'Right Output Mixer PCM' on -amixer sset 'Left Output Mixer PCM' on -amixer sset 'PCM Playback -6dB' off -amixer sset 'O018 I150_Switch' on -amixer sset 'O019 I151_Switch' on -amixer sset 'O124 I032_Switch' on -amixer sset 'O125 I033_Switch' on -amixer sset 'Headphone' 121 -amixer sset 'Playback' 255 - -Signed-off-by: Daniel Golle ---- ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ * Author: Maso Huang -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ sound_wm8960 { -+ compatible = "mediatek,mt7986-wm8960-sound"; -+ audio-routing = "Headphone", "HP_L", -+ "Headphone", "HP_R", -+ "LINPUT1", "AMIC", -+ "RINPUT1", "AMIC"; -+ -+ status = "okay"; -+ -+ platform { -+ sound-dai = <&afe>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2c0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ #sound-dai-cells = <0>; -+ reg = <0x1a>; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&pio>; -+ __overlay__ { -+ i2c_pins: i2c-pins-3-4 { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb diff --git a/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 03038d35d4..0000000000 --- a/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b40f707f71d4e1fee9b2c20d62e235c5aba5533b Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 17 Mar 2021 17:36:54 +0000 -Subject: [PATCH] arm64: dts: mediatek: mt7622-bpi-r64: add SATA/PCIe1 DT overlays - -The Bananapi BPi-R64 got a SATA interface which cannot be used at the -same time as the second mPCIe slot. The decission is made by hogging -GPIO 90. -Embed two addtional DT overlay blobs into the image to allow bootloader -selection of either SATA or PCIE1 feature. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -323,7 +323,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch deleted file mode 100644 index b127b0e348..0000000000 --- a/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch +++ /dev/null @@ -1,68 +0,0 @@ -From c27279dc26a26b8ad054882d4c5f86a85526fd16 Mon Sep 17 00:00:00 2001 -From: Yoonji Park -Date: Mon, 6 Jun 2022 07:44:48 +0000 -Subject: [PATCH] arm: arm64: of: add CMDLINE_OVERRIDE to support chosen/bootargs-override - -Add a CONFIG_CMDLINE_OVERRIDE Kconfig option for both ARM and ARM64 and -handle the corresponding "bootargs-override" property in -early_init_dt_scan_chosen(). When the property is present in the DT -chosen node its value fully replaces the kernel command line, which is -useful on devices where the bootloader sets bootargs that cannot be -edited. - -Signed-off-by: Yoonji Park ---- ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1505,6 +1505,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1053,6 +1053,17 @@ int __init early_init_dt_scan_chosen(cha - if (p != NULL && l > 0) - strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strscpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - handle_cmdline: - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -2383,6 +2383,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EFI_STUB - bool - diff --git a/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index 0e6eb3eac3..0000000000 --- a/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3a93704a63cf018187411108d241c35ec83992c0 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 20 Aug 2021 18:31:48 +0100 -Subject: [PATCH] mediatek: add EEPROM data for BPi-R64 2.4GHz wmac - -EEPROM data extracted from vendor image found at -http://forum.banana-pi.org/t/bpi-r64-mt7622-mac80211-wifi-driver/10246/77 -http://forum.banana-pi.org/uploads/short-url/jworbyBYpvrw9VQ2sx92B9z6DWS.bin - -MAC address in the EEPROM has been zero'd which results in random -address on boot. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -650,5 +650,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch deleted file mode 100644 index c6c50454cb..0000000000 --- a/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 208f6c1232901835708eb4ace44ae17628fc12f5 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 21 Jan 2024 23:50:02 +0000 -Subject: [PATCH] mediatek: mt7622: convert BPi-R64 to all-UBI layout and fitblk - -Modernize bootloader and flash memory layout of the BPi-R64 similar to -how it has also been done for the BPi-R3. - -Signed-off-by: Daniel Golle ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -32,6 +32,9 @@ - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; -+ rootdisk-emmc = <&emmc_rootfs>; -+ rootdisk-sd = <&sd_rootfs>; -+ rootdisk-snfi = <&ubi_rootfs>; - }; - - cpus { -@@ -245,6 +248,28 @@ - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env"; -+ }; -+ }; -+ emmc_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; - }; - - &mmc1 { -@@ -260,6 +285,28 @@ - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env"; -+ }; -+ }; -+ sd_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; - }; - - &nandc { -@@ -293,15 +340,30 @@ - read-only; - }; - -- partition@80000 { -- label = "fip"; -- reg = <0x80000 0x200000>; -- read-only; -- }; -- -- ubi: partition@280000 { -+ ubi: partition@80000 { - label = "ubi"; -- reg = <0x280000 0x7d80000>; -+ reg = <0x80000 0x7f80000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ ubi-volume-ubootenv { -+ volname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ ubi-volume-ubootenv2 { -+ volname = "ubootenv2"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool"; -+ }; -+ }; -+ -+ ubi_rootfs: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.12/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch b/target/linux/mediatek/patches-6.12/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch deleted file mode 100644 index 752303394f..0000000000 --- a/target/linux/mediatek/patches-6.12/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch +++ /dev/null @@ -1,314 +0,0 @@ -From 561e3cf678970ae29a719e559943d260a9ba18bb Mon Sep 17 00:00:00 2001 -From: Daniel Pawlik -Date: Mon, 16 Mar 2026 14:26:51 +0100 -Subject: [PATCH] mediatek: device tree overlay for BPI-R4 with BE14 module - -Some Banana Pi BPI-R4 BE14 WiFi modules are shipped with zeroed -tx_power fields in EEPROM (2G/5G/6G). This leads to low transmit power -on affected bands. -This overlay provides known-good EEPROM data (including correct tx_power -values for 2G/5G/6G bands) dumped from a working BE14 module. - -To enable BE14 overlay, add into u-boot bootconf_extra -parameter: 'mt7988a-bananapi-bpi-r4-wifi-be14'. -You can use example script: - - overlay="mt7988a-bananapi-bpi-r4-wifi-be14" - current="$(fw_printenv -n bootconf_extra 2>/dev/null)" - if [ -n "${current}" ]; then - fw_setenv bootconf_extra "${current}#${overlay}" - else - fw_setenv bootconf_extra "${overlay}" - fi - -Earlier proposal proposed in [1] was fallback to default values if -invalid EEPROM content is detected. - -[1] https://github.com/openwrt/openwrt/pull/19503/ - -Fixes: https://github.com/openwrt/openwrt/issues/17489 -Signed-off-by: Daniel Pawlik ---- ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-be14.dtso -@@ -0,0 +1,280 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Device tree overlay for the BananaPi BPI-R4 with BE14 WiFi module. -+ * Some BE14 modules are shipped with zeroed or incorrect EEPROM -+ * calibration data. This overlay provides known-good EEPROM data -+ * (including correct tx_power values for 2G/5G/6G bands) dumped -+ * from a working BE14 module. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; -+}; -+ -+&i2c_wifi { -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ address-bits = <8>; -+ page-size = <8>; -+ size = <256>; -+ }; -+}; -+ -+&pcie0 { -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ wifi@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ -+ mediatek,eeprom-data = <0x90790400 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0xae682613 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 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partitions: msdos: add OF node by partition number - -A hack for some legacy boards... - -Signed-off-by: Daniel Golle ---- - block/partitions/msdos.c | 66 +++++++++++++++++++++++++++++++++------- - 1 file changed, 55 insertions(+), 11 deletions(-) - ---- a/block/partitions/msdos.c -+++ b/block/partitions/msdos.c -@@ -27,6 +27,7 @@ - */ - #include - #include -+#include - - #include "check.h" - #include "efi.h" -@@ -116,6 +117,26 @@ static void set_info(struct parsed_parti - state->parts[slot].has_info = true; - } - -+static struct device_node *find_partno_of_node(struct device_node *partitions_np, -+ int partno) -+{ -+ int np_partno; -+ -+ if (!partitions_np || -+ !of_device_is_compatible(partitions_np, "msdos-partitions")) -+ return NULL; -+ -+ for_each_available_child_of_node_scoped(partitions_np, np) { -+ if (!of_property_read_u32(np, "partno", &np_partno) && -+ partno != np_partno) -+ continue; -+ -+ return np; -+ } -+ -+ return NULL; -+} -+ - /* - * Create devices for each logical partition in an extended partition. - * The logical partitions form a linked list, with each entry being -@@ -131,6 +152,8 @@ static void parse_extended(struct parsed - sector_t first_sector, sector_t first_size, - u32 disksig) - { -+ struct device *ddev = disk_to_dev(state->disk); -+ struct device_node *partitions_np = of_node_get(ddev->of_node); - struct msdos_partition *p; - Sector sect; - unsigned char *data; -@@ -190,7 +213,8 @@ static void parse_extended(struct parsed - continue; - } - -- put_partition(state, state->next, next, size); -+ of_put_partition(state, state->next, next, size, -+ find_partno_of_node(partitions_np, state->next)); - set_info(state, state->next, disksig); - if (p->sys_ind == LINUX_RAID_PARTITION) - state->parts[state->next].flags = ADDPART_FLAG_RAID; -@@ -580,6 +604,8 @@ static struct { - - int msdos_partition(struct parsed_partitions *state) - { -+ struct device *ddev = disk_to_dev(state->disk); -+ struct device_node *partitions_np = of_node_get(ddev->of_node); - sector_t sector_size; - Sector sect; - unsigned char *data; -@@ -676,14 +702,18 @@ int msdos_partition(struct parsed_partit - sector_t n = 2; - - n = min(size, max(sector_size, n)); -- put_partition(state, slot, start, n); -+ of_put_partition(state, slot, start, n, -+ find_partno_of_node(partitions_np, -+ slot)); - - strlcat(state->pp_buf, " <", PAGE_SIZE); - parse_extended(state, start, size, disksig); - strlcat(state->pp_buf, " >", PAGE_SIZE); - continue; - } -- put_partition(state, slot, start, size); -+ of_put_partition(state, slot, start, size, -+ find_partno_of_node(partitions_np, -+ slot)); - set_info(state, slot, disksig); - if (p->sys_ind == LINUX_RAID_PARTITION) - state->parts[slot].flags = ADDPART_FLAG_RAID; diff --git a/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch deleted file mode 100644 index b15dde1c3b..0000000000 --- a/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 335c1e7cfdfd477a1106ca05c96ff8949ecd953f Mon Sep 17 00:00:00 2001 -From: Furong Xu -Date: Fri, 16 Dec 2022 21:13:37 +0800 -Subject: [PATCH] mediatek: enable sel_clk for spi-mt65xx - -Without explicitly enabling sel_clk, clk_disable_unused() will disable -it when boot is done, causing CPU hang on SPI1 register access on MT7986. -Explicitly enable sel_clk to make SPI1 functional. - -Signed-off-by: Furong Xu -Signed-off-by: Chuanhong Guo ---- ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -1237,8 +1237,15 @@ static int mtk_spi_probe(struct platform - if (ret < 0) - return dev_err_probe(dev, ret, "failed to enable hclk\n"); - -+ ret = clk_prepare_enable(mdata->sel_clk); -+ if (ret < 0) { -+ clk_disable_unprepare(mdata->spi_hclk); -+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { -+ clk_disable_unprepare(mdata->sel_clk); - clk_disable_unprepare(mdata->spi_hclk); - return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); - } diff --git a/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch deleted file mode 100644 index 465f0eaf27..0000000000 --- a/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 -Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 16:40:31 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename - mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region - -This is a preliminary patch to move wed ilm/dlm and cpuboot properties in -dedicated dts nodes. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we - } - - static int --mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index, -- struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index, -+ struct mtk_wed_wo_memory_region *region) - { - struct reserved_mem *rmem; - struct device_node *np; -@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; - -- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); - if (ret) - return ret; - } diff --git a/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch deleted file mode 100644 index a75a297e04..0000000000 --- a/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 -Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 16:32:41 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -121,12 +121,6 @@ - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; -- -- wo_boot: wo-boot@15194000 { -- reg = <0 0x15194000 0 0x1000>; -- no-map; -- }; -- - }; - - soc { -@@ -533,10 +527,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wed1: wed@15011000 { -@@ -546,10 +541,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { -@@ -607,6 +603,11 @@ - interrupts = ; - }; - -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ - wifi: wifi@18000000 { - compatible = "mediatek,mt7986-wmac"; - reg = <0 0x18000000 0 0x1000000>, diff --git a/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch deleted file mode 100644 index 43014c5d12..0000000000 --- a/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ /dev/null @@ -1,103 +0,0 @@ -From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 18:13:04 +0100 -Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a - dedicated dts node - -Since the cpuboot memory region is not part of the RAM SoC, move cpuboot -in a deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where cpuboot was -defined as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -32,14 +32,25 @@ static struct mtk_wed_wo_memory_region m - }, - }; - --static u32 wo_r32(u32 reg) -+static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) - { -- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ u32 val; -+ -+ if (!wo->boot_regmap) -+ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ -+ if (regmap_read(wo->boot_regmap, reg, &val)) -+ val = ~0; -+ -+ return val; - } - --static void wo_w32(u32 reg, u32 val) -+static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) - { -- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ if (wo->boot_regmap) -+ regmap_write(wo->boot_regmap, reg, val); -+ else -+ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); - } - - static struct sk_buff * -@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, -+ "mediatek,wo-cpuboot"); -+ - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { - int index = of_property_match_string(wo->hw->node, -@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; - -+ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) -+ continue; -+ - ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); - if (ret) - return ret; -@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR; - else - boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR; -- wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16); -+ wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16); - /* wo firmware reset */ -- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00); -+ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00); - -- val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) | -+ val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) | - MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK; -- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val); -+ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val); - out: - release_firmware(fw); - ---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h -@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue { - struct mtk_wed_wo { - struct mtk_wed_hw *hw; - -+ struct regmap *boot_regmap; - struct mtk_wed_wo_queue q_tx; - struct mtk_wed_wo_queue q_rx; - diff --git a/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch deleted file mode 100644 index 641c2597f7..0000000000 --- a/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,86 +0,0 @@ -From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 18:51:47 +0100 -Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts - node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where ilm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- - 1 file changed, 49 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -320,6 +320,39 @@ next: - } - - static int -+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo) -+{ -+ struct mtk_wed_wo_memory_region *ilm_region; -+ struct resource res; -+ struct device_node *np; -+ int ret; -+ -+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); -+ if (!np) -+ return 0; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ ilm_region = &mem_region[MTK_WED_WO_REGION_ILM]; -+ ilm_region->phy_addr = res.start; -+ ilm_region->size = resource_size(&res); -+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, -+ resource_size(&res)); -+ -+ if (!IS_ERR(ilm_region->addr)) -+ return 0; -+ -+ ret = PTR_ERR(ilm_region->addr); -+ ilm_region->addr = NULL; -+ -+ return ret; -+} -+ -+static int - mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) - { - const struct mtk_wed_fw_trailer *trailer; -@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -+ mtk_wed_mcu_load_ilm(wo); - wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, - "mediatek,wo-cpuboot"); - - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- int index = of_property_match_string(wo->hw->node, -- "memory-region-names", -- mem_region[i].name); -+ int index; -+ -+ if (mem_region[i].addr) -+ continue; -+ -+ index = of_property_match_string(wo->hw->node, -+ "memory-region-names", -+ mem_region[i].name); - if (index < 0) - continue; - diff --git a/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch deleted file mode 100644 index a7a854dd6e..0000000000 --- a/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: -References: -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:45:16 +0100 -Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts - node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where dlm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -1333,6 +1333,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; - -+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); -+ if (np) { -+ struct resource res; -+ int ret; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ dev->rro.miod_phys = res.start; -+ goto out; -+ } -+ -+ /* For backward compatibility, we need to check if DLM -+ * node is defined through reserved memory property. -+ */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -1349,6 +1367,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; - - dev->rro.miod_phys = rmem->base; -+out: - dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; - - return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch deleted file mode 100644 index c64b3b37c3..0000000000 --- a/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 -Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:10:56 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -97,16 +97,6 @@ - no-map; - }; - -- wo_ilm0: wo-ilm@151e0000 { -- reg = <0 0x151e0000 0 0x8000>; -- no-map; -- }; -- -- wo_ilm1: wo-ilm@151f0000 { -- reg = <0 0x151f0000 0 0x8000>; -- no-map; -- }; -- - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; -@@ -526,11 +516,10 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -540,11 +529,10 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -603,6 +591,16 @@ - interrupts = ; - }; - -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@151f0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151f0000 0 0x8000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch deleted file mode 100644 index 13fe1f792c..0000000000 --- a/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 -Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:53:30 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- - 1 file changed, 16 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -101,16 +101,6 @@ - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; -- -- wo_dlm0: wo-dlm@151e8000 { -- reg = <0 0x151e8000 0 0x2000>; -- no-map; -- }; -- -- wo_dlm1: wo-dlm@151f8000 { -- reg = <0 0x151f8000 0 0x2000>; -- no-map; -- }; - }; - - soc { -@@ -516,10 +506,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -529,10 +520,11 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -601,6 +593,16 @@ - reg = <0 0x151f0000 0 0x8000>; - }; - -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@151f8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151f8000 0 0x2000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch deleted file mode 100644 index 5bc3debc82..0000000000 --- a/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch +++ /dev/null @@ -1,44 +0,0 @@ -From a270f61c00c7d5a62664b85baa56a8ab1a242f8d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 17 Nov 2023 02:01:34 +0000 -Subject: [PATCH] mediatek: import driver for Adtran SmartRG RGBW LED - -Import driver for I2C-connected HolTek MCU controlling the RGBW LED -found in Adtran SmartRG devices. - -Signed-off-by: Daniel Golle ---- ---- - drivers/leds/Kconfig | 10 ++++++++++ - drivers/leds/Makefile | 1 + - 2 files changed, 11 insertions(+) - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -977,6 +977,16 @@ source "drivers/leds/flash/Kconfig" - comment "RGB LED drivers" - source "drivers/leds/rgb/Kconfig" - -+config LEDS_SMARTRG_LED -+ tristate "LED support for Adtran SmartRG" -+ depends on LEDS_CLASS && I2C && OF -+ help -+ This option enables support for the Adtran SmartRG platform -+ system LED driver. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-smartrg-system. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o - obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o - obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o -+obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o - obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o - obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o - obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o diff --git a/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch b/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch deleted file mode 100644 index b0c3bc018a..0000000000 --- a/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 84fc59c0d5285a0a0fe50e3cb2a85f6224362c55 Mon Sep 17 00:00:00 2001 -From: Jonas Jelonek -Date: Sun, 10 Nov 2024 00:43:23 +0000 -Subject: [PATCH] mediatek: filogic: bpi-r3: set netdev-name for sfp1 port - -Sets openwrt,netdev-name for the gmac1 node in the dts of BPI-R3, which -corresponds to the sfp1 slot, to have a proper naming and match the -label on the official BPI-R3 metal case. This renames the port from eth1 -to sfp1. -The COMPAT_VERSION is increased to denote that configuration has to be -adjusted manually. - -Signed-off-by: Jonas Jelonek ---- ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -195,6 +195,7 @@ - phy-mode = "2500base-x"; - sfp = <&sfp1>; - managed = "in-band-status"; -+ openwrt,netdev-name = "sfp1"; - }; - - mdio: mdio-bus { diff --git a/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch b/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch deleted file mode 100644 index da27916469..0000000000 --- a/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 30a04cf5b6ffa1249df72ccd98cef05f37890f89 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 6 Feb 2025 05:07:20 +0000 -Subject: [PATCH] mtd: spinand: add work-around to prevent bootloader wiping - mtdparts - -ASUS makes use of U-Boot's fdt_fixup_mtdparts() function which applies -the partitions defined in U-Boot's mtdparts and mtdids environment -variables to the devicetree passed over to Linux. - -The undesired side-effect is that in this way also all additional -properties and child nodes get wiped, preventing NVMEM cells to be -defined for MTD partitions or UBI volumes. - -To work-around this issue, add an additional compatible string -'u-boot-dont-touch-spi-nand' which can be used instead of 'spi-nand' in -case the replacement of the MTD partitions by U-Boot should be skipped -alltogether. - -In practise this is mostly relevant for SPI-NAND which anyway comes only -with two partitions nowadays: 'Bootloader' and 'UBI_DEV'. Hence this -work-around is applicable for SPI-NAND only. Similar work-arounds for -other MTD devices can be created as well should they actually be needed. - -Signed-off-by: Daniel Golle ---- - drivers/mtd/nand/spi/core.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1698,6 +1698,7 @@ static int spinand_remove(struct spi_mem - - static const struct spi_device_id spinand_ids[] = { - { .name = "spi-nand" }, -+ { .name = "u-boot-dont-touch-spi-nand" }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(spi, spinand_ids); -@@ -1705,6 +1706,7 @@ MODULE_DEVICE_TABLE(spi, spinand_ids); - #ifdef CONFIG_OF - static const struct of_device_id spinand_of_ids[] = { - { .compatible = "spi-nand" }, -+ { .compatible = "u-boot-dont-touch-spi-nand" }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, spinand_of_ids); diff --git a/target/linux/mediatek/patches-6.12/965-dts-mt7988a-add-trng-support.patch b/target/linux/mediatek/patches-6.12/965-dts-mt7988a-add-trng-support.patch deleted file mode 100644 index 1c3eb583c1..0000000000 --- a/target/linux/mediatek/patches-6.12/965-dts-mt7988a-add-trng-support.patch +++ /dev/null @@ -1,30 +0,0 @@ -From afcec128c572eb1064472b772ffba3f44e2dbfeb Mon Sep 17 00:00:00 2001 -From: Marcos Alano -Date: Sun, 14 Sep 2025 22:32:12 -0300 -Subject: [PATCH] mediatek: add support for trng on mt7988a - -Add support for trng on mt7988a. - -Tested on Banana Pi BPI-R4. - -Signed-off-by: Marcos Alano ---- -arm64: dts: mediatek: mt7988: add trng node - -Add support for trng on mt7988a. - -Tested on Banana Pi BPI-R4. - -Signed-off-by: Marcos Alano ---- ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -1327,4 +1327,8 @@ - , - ; - }; -+ -+ trng { -+ compatible = "mediatek,mt7988-rng"; -+ }; - }; diff --git a/target/linux/mediatek/patches-6.12/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch b/target/linux/mediatek/patches-6.12/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch deleted file mode 100644 index ae60a9645f..0000000000 --- a/target/linux/mediatek/patches-6.12/966-pcie-mediatek-gen3-Add-WIFI-HW-reset-flow.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f566462daef92eb0074013e32d0332116fc3a2eb Mon Sep 17 00:00:00 2001 -From: Jianguo Zhang -Date: Tue, 14 Oct 2025 16:00:03 +0800 -Subject: [PATCH] pcie: mediatek-gen3: Add WIFI HW reset flow - -[Description] -Add WIFI HW reset before PCIe host detects EP device for reboot. - -[Release-log] -NA - -Signed-off-by: Jianguo Zhang ---- - drivers/pci/controller/pcie-mediatek-gen3.c | 29 +++++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -10,6 +10,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -18,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -160,6 +163,8 @@ struct mtk_msi_set { - * @phy: PHY controller block - * @clks: PCIe clocks - * @num_clks: PCIe clocks count for this port -+ * @wifi_reset: reset pin for WIFI chip -+ * @wifi_reset_delay_ms: delay time for WIFI chip reset - * @irq: PCIe controller interrupt number - * @saved_irq_state: IRQ enable state saved at suspend time - * @irq_lock: lock protecting IRQ register access -@@ -181,6 +186,9 @@ struct mtk_gen3_pcie { - struct clk_bulk_data *clks; - int num_clks; - -+ struct gpio_desc *wifi_reset; -+ u32 wifi_reset_delay_ms; -+ - int irq; - u32 saved_irq_state; - raw_spinlock_t irq_lock; -@@ -402,6 +410,12 @@ static int mtk_pcie_startup_port(struct - val |= PCIE_DISABLE_DVFSRC_VLT_REQ; - writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); - -+ if (pcie->wifi_reset) { -+ gpiod_set_value_cansleep(pcie->wifi_reset, 1); -+ msleep(pcie->wifi_reset_delay_ms); -+ gpiod_set_value_cansleep(pcie->wifi_reset, 0); -+ } -+ - /* Assert all reset signals */ - val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; -@@ -864,6 +878,20 @@ static int mtk_pcie_parse_port(struct mt - return pcie->num_clks; - } - -+ ret = of_property_read_u32(dev->of_node, "wifi-reset-msleep", -+ &pcie->wifi_reset_delay_ms); -+ if (!ret) { -+ pcie->wifi_reset = devm_gpiod_get_optional(dev, "wifi-reset", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(pcie->wifi_reset)) { -+ ret = PTR_ERR(pcie->wifi_reset); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, -+ "failed to request WIFI reset gpio\n"); -+ return ret; -+ } -+ } -+ - return 0; - } - From 8ef7b4ee4ba77a8d58e734753d1c87b1d4d332d7 Mon Sep 17 00:00:00 2001 From: Sander van Deijck Date: Fri, 24 Apr 2026 02:43:03 +0200 Subject: [PATCH 11/46] wolfssl: update to 5.9.1 For changes, see: https://github.com/wolfSSL/wolfssl/releases/tag/v5.9.1-stable This includes a fix for a critical (CVSS 9.3) vulnerability: https://github.com/advisories/GHSA-f5h9-5q52-qrx7 Signed-off-by: Sander van Deijck Link: https://github.com/openwrt/openwrt/pull/23072 Signed-off-by: Nick Hainke --- package/libs/wolfssl/Makefile | 4 ++-- .../libs/wolfssl/patches/100-disable-hardening-check.patch | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/wolfssl/Makefile b/package/libs/wolfssl/Makefile index 866ccb635f..958a569a4e 100644 --- a/package/libs/wolfssl/Makefile +++ b/package/libs/wolfssl/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=wolfssl -PKG_VERSION:=5.9.0 +PKG_VERSION:=5.9.1 PKG_REAL_VERSION:=$(PKG_VERSION)-stable PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_REAL_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_REAL_VERSION) -PKG_HASH:=6efc62b86f145a5c52bfd62294ca66c20ce85b54e9033f5d7e0ee73eb30306c1 +PKG_HASH:=d5ca7af48cd2d9a91d539e9baedeba55a0605a28d7ac8b01dc3d5254a13ca341 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_REAL_VERSION) diff --git a/package/libs/wolfssl/patches/100-disable-hardening-check.patch b/package/libs/wolfssl/patches/100-disable-hardening-check.patch index 7a2674327d..a31905ad89 100644 --- a/package/libs/wolfssl/patches/100-disable-hardening-check.patch +++ b/package/libs/wolfssl/patches/100-disable-hardening-check.patch @@ -1,6 +1,6 @@ --- a/wolfssl/wolfcrypt/settings.h +++ b/wolfssl/wolfcrypt/settings.h -@@ -4122,7 +4122,7 @@ extern void uITRON4_free(void *p) ; +@@ -4154,7 +4154,7 @@ extern void uITRON4_free(void *p) ; /* warning for not using harden build options (default with ./configure) */ /* do not warn if big integer support is disabled */ From 017bf1c37e6913857ca33ba79b408ef296f4cb39 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 24 Apr 2026 08:50:21 +0200 Subject: [PATCH 12/46] kernel: rtl8261n: drop unreachable PHY register patch The PHY register patch in question is gated by `CONFIG_MACH_REALTEK_RTL`, has no documented/expected behavior, and is in practice unreachable: `phy_patch()` is only called from `rtkphy_config_init()`, which is exits (too) early for `CONFIG_MACH_REALTEK_RTL` builds. Remove it as a cleanup step before enabling standard USXGMII configuration for these PHYs. Fixes: b77fa45d1278 ("kernel: fix rtl8261n driver for realtek") Co-authored-by: Jonas Jelonek Signed-off-by: Sven Eckelmann Link: https://github.com/openwrt/openwrt/pull/23076 Signed-off-by: Hauke Mehrtens --- .../files/drivers/net/phy/rtl8261n/phy_patch.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_patch.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_patch.c index 3614dc2833..4d2cefe6a7 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_patch.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_patch.c @@ -98,11 +98,6 @@ static int32 _phy_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset, return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; } -rtk_hwpatch_t rtl826XB_patch_rtk_conf[] = { - {RTK_PATCH_OP_PSDS0 , 0xff , 0x07 , 0x10 , 15, 0, 0x80aa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, - {RTK_PATCH_OP_PSDS0 , 0xff , 0x06 , 0x12 , 15, 0, 0x5078, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, -}; - /* Function Name: * phy_patch * Description: @@ -175,16 +170,6 @@ int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode break; } } -#ifdef CONFIG_MACH_REALTEK_RTL - ret = _phy_patch_process(unit, port, portOffset, rtl826XB_patch_rtk_conf, sizeof(rtl826XB_patch_rtk_conf), patch_mode); - if (ret == RT_ERR_CHECK_FAILED) - chk_ret = ret; - else if (ret != RT_ERR_OK) - { - RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret); - return ret; - } -#endif return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; } From dd5bd85a1ffbef075eb32c35e63d6e6eb1277982 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 24 Apr 2026 08:50:21 +0200 Subject: [PATCH 13/46] kernel: rtl8261n: always configure as USXGMII In the past, all the configuration of SerDes and PHYs on the realtek switches were done using u-boot (`rtk init`). But since RTL930x switched to SerDes configuration under Linux, the SoC side is no longer using the Realtek-proprietary variant of USXGMII. The communication to the RTL8261N PHYs on those switches broke because of this incompatibility. Enabling the full initialization on `CONFIG_MACH_REALTEK_RTL` converts also the PHY side to the standard USXGMII and therefore ensures that both sides speak the same dialect. Co-authored-by: Jonas Jelonek Signed-off-by: Sven Eckelmann Link: https://github.com/openwrt/openwrt/pull/23076 Signed-off-by: Hauke Mehrtens --- target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c index 8c142afee6..7307bd30ad 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c @@ -78,9 +78,6 @@ static int rtkphy_config_init(struct phy_device *phydev) case REALTEK_PHY_ID_RTL8264B: case REALTEK_PHY_ID_RTL8264: phydev_info(phydev, "%s:%u [RTL8261N/RTL8264/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr); -#ifdef CONFIG_MACH_REALTEK_RTL - return 0; -#endif #if 1 /* toggle reset */ phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1); From 51992c87c8d1cee54cffa3eacf7f15e6afd48b1c Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Fri, 24 Apr 2026 11:07:34 +0200 Subject: [PATCH 14/46] kernel: rtl8261n: add post-reset MDIO stabilization delay After the RTL8261N asserts a reset, the MDIO bus becomes temporarily unavailable during the chip's reinitialization sequence. Any subsequent read or write issued before the PHY has stabilized will fail. Add a 30ms delay after triggering the reset to ensure the chip is reachable via MDIO before resuming communication. Signed-off-by: Jonas Jelonek Signed-off-by: Sven Eckelmann Link: https://github.com/openwrt/openwrt/pull/23076 Signed-off-by: Hauke Mehrtens --- target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c index 7307bd30ad..925f2b3a29 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c @@ -81,6 +81,7 @@ static int rtkphy_config_init(struct phy_device *phydev) #if 1 /* toggle reset */ phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1); + mdelay(30); phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 0); mdelay(30); #endif From aaf91b7b6236b47370c8643d436f8c4f30a262c9 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 22:30:04 +0200 Subject: [PATCH 15/46] realtek: mdio: harden defines Add brackets to avoid silent bugs. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23070 Signed-off-by: Hauke Mehrtens --- .../files-6.18/drivers/net/mdio/mdio-realtek-otto.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c index 0af6787da9..30ef0df317 100644 --- a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c @@ -29,7 +29,7 @@ #define RTMDIO_PHY_MAC_1G 3 #define RTMDIO_PHY_MAC_2G_PLUS 1 -#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((bit << 21) | (dev << 16) | reg) +#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((bit << 21) | (dev << 16) | (reg)) /* MDIO bus registers/fields */ #define RTMDIO_RUN BIT(0) @@ -42,7 +42,7 @@ #define RTMDIO_838X_CMD_READ_C22 0 #define RTMDIO_838X_CMD_READ_C45 BIT(1) #define RTMDIO_838X_CMD_WRITE_C22 BIT(2) -#define RTMDIO_838X_CMD_WRITE_C45 BIT(1) | BIT(2) +#define RTMDIO_838X_CMD_WRITE_C45 (BIT(1) | BIT(2)) #define RTMDIO_838X_CMD_MASK GENMASK(2, 0) #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) @@ -56,7 +56,7 @@ #define RTMDIO_839X_CMD_READ_C22 0 #define RTMDIO_839X_CMD_READ_C45 BIT(2) #define RTMDIO_839X_CMD_WRITE_C22 BIT(3) -#define RTMDIO_839X_CMD_WRITE_C45 BIT(2) | BIT(3) +#define RTMDIO_839X_CMD_WRITE_C45 (BIT(2) | BIT(3)) #define RTMDIO_839X_CMD_MASK GENMASK(3, 0) #define RTMDIO_839X_PHYREG_DATA_CTRL (0x03F0) #define RTMDIO_839X_PHYREG_MMD_CTRL (0x03F4) @@ -70,8 +70,8 @@ #define RTMDIO_930X_CMD_READ_C22 0 #define RTMDIO_930X_CMD_READ_C45 BIT(1) #define RTMDIO_930X_CMD_WRITE_C22 BIT(2) -#define RTMDIO_930X_CMD_WRITE_C45 BIT(1) | BIT(2) -#define RTMDIO_930X_CMD_MASK GENMASK(2, 0) | BIT(25) +#define RTMDIO_930X_CMD_WRITE_C45 (BIT(1) | BIT(2)) +#define RTMDIO_930X_CMD_MASK (GENMASK(2, 0) | BIT(25)) #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78) #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3 (0xCB7C) #define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL (0xCA08) @@ -92,7 +92,7 @@ #define RTMDIO_931X_CMD_READ_C22 0 #define RTMDIO_931X_CMD_READ_C45 BIT(3) #define RTMDIO_931X_CMD_WRITE_C22 BIT(4) -#define RTMDIO_931X_CMD_WRITE_C45 BIT(3) | BIT(4) +#define RTMDIO_931X_CMD_WRITE_C45 (BIT(3) | BIT(4)) #define RTMDIO_931X_CMD_MASK GENMASK(4, 0) #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04) #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08) From a4a6a06c9f25440e446ad174576a4699e3ef9c2e Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 22:32:08 +0200 Subject: [PATCH 16/46] realtek: mdio: fix "SMY" typo The defines should have been named SMI like everywhere else. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23070 Signed-off-by: Hauke Mehrtens --- .../realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c index 30ef0df317..8c2a349df6 100644 --- a/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c @@ -99,7 +99,7 @@ #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10) #define RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL (0x0C18) #define RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL (0x0CAC) -#define RTMDIO_931X_SMY_PHY_ABLTY_MDIO 0x0 +#define RTMDIO_931X_SMI_PHY_ABLTY_MDIO 0x0 #define RTMDIO_931X_SMI_PHY_ABLTY_SDS 0x2 #define RTMDIO_931X_SMI_PORT_POLLING_SEL (0x0C9C) #define RTMDIO_931X_SMI_PORT_ADDR_CTRL (0x0C74) @@ -827,7 +827,7 @@ static void rtmdio_931x_setup_polling(struct rtmdio_ctrl *ctrl) /* set to "PHY driven" */ mask = GENMASK(1, 0) << ((pn % 16) * 2); - val = RTMDIO_931X_SMY_PHY_ABLTY_MDIO << (ffs(mask) - 1); + val = RTMDIO_931X_SMI_PHY_ABLTY_MDIO << (ffs(mask) - 1); regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (pn / 16) * 4, mask, val); mask = val = 0; From 45633073fe057b51d3c7397e28b6c5703c88686e Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Thu, 23 Apr 2026 16:58:40 +0200 Subject: [PATCH 17/46] generic: net: phy: realtek: don't disable MDIO address 0 for PHY in SFP module At least the XikeStor SKT-2.5G-100M SFP module seems to internally use MDIO address 0 to access the PHY. This module allows accessing PHY registers using Rollball protocol on address 0x51, and also provides read-only C22 access on address 0x56. However, after disabling the PHYAD0 configuration bit, only 0xffff can be read via both methods (except for MMD device 30 which can still be accessed). Since having MDIO address 0 enabled shouldn't do any harm on SFP modules just leave the configuration bit alone in that case. Signed-off-by: Jan Hoffmann Link: https://github.com/openwrt/openwrt/pull/23065 Signed-off-by: Hauke Mehrtens --- ...t-phy-realtek-disable-MDIO-broadcast.patch | 22 +++++++++++++++---- ...phy-realtek-rate-adapter-in-C22-mode.patch | 2 +- ...t-phy-realtek-disable-MDIO-broadcast.patch | 22 +++++++++++++++---- ...phy-realtek-rate-adapter-in-C22-mode.patch | 2 +- ...altek-add-RTL8224-pair-order-support.patch | 4 ++-- ...realtek-add-RTL8224-polarity-support.patch | 2 +- ...tek-support-MDI-swapping-for-RTL8226.patch | 4 ++-- ...743-net-realtek-serdes-configuration.patch | 4 ++-- 8 files changed, 45 insertions(+), 17 deletions(-) diff --git a/target/linux/generic/pending-6.12/720-07-net-phy-realtek-disable-MDIO-broadcast.patch b/target/linux/generic/pending-6.12/720-07-net-phy-realtek-disable-MDIO-broadcast.patch index e37faaca43..8b0755c85d 100644 --- a/target/linux/generic/pending-6.12/720-07-net-phy-realtek-disable-MDIO-broadcast.patch +++ b/target/linux/generic/pending-6.12/720-07-net-phy-realtek-disable-MDIO-broadcast.patch @@ -21,13 +21,27 @@ Signed-off-by: Daniel Golle #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -@@ -1358,7 +1359,8 @@ static int rtl822x_init_phycr1(struct ph +@@ -1351,14 +1352,21 @@ static int rtl822xb_write_mmd(struct phy + static int rtl822x_init_phycr1(struct phy_device *phydev, bool no_aldps) + { + struct rtl822x_priv *priv = phydev->priv; ++ u16 mask = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN; + u16 val = 0; + ++ /* The controller in some SFP modules uses MDIO address 0 to access the ++ * PHY. Leave the MDIO broadcast configuration bit alone for SFP ++ * modules, as it won't cause any issues there anyways. ++ */ ++ if (!phydev->is_on_sfp_module) ++ mask |= RTL8221B_PHYCR1_PHYAD_0_EN; ++ + if (priv->enable_aldps && !no_aldps) + val = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN; return phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_PHYCR1, - RTL8221B_PHYCR1_ALDPS_EN | +- RTL8221B_PHYCR1_ALDPS_EN | - RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN, val); -+ RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN | -+ RTL8221B_PHYCR1_PHYAD_0_EN, val); ++ mask, val); } static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) diff --git a/target/linux/generic/pending-6.12/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch b/target/linux/generic/pending-6.12/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch index f8a28d570b..72757a18bc 100644 --- a/target/linux/generic/pending-6.12/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch +++ b/target/linux/generic/pending-6.12/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch @@ -11,7 +11,7 @@ interface mode if the PHY is connected using Clause-45 MDIO. Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c -@@ -1387,7 +1387,7 @@ static int rtl822x_set_serdes_option_mod +@@ -1393,7 +1393,7 @@ static int rtl822x_set_serdes_option_mod return 0; /* determine SerDes option mode */ diff --git a/target/linux/generic/pending-6.18/720-07-net-phy-realtek-disable-MDIO-broadcast.patch b/target/linux/generic/pending-6.18/720-07-net-phy-realtek-disable-MDIO-broadcast.patch index e37faaca43..8b0755c85d 100644 --- a/target/linux/generic/pending-6.18/720-07-net-phy-realtek-disable-MDIO-broadcast.patch +++ b/target/linux/generic/pending-6.18/720-07-net-phy-realtek-disable-MDIO-broadcast.patch @@ -21,13 +21,27 @@ Signed-off-by: Daniel Golle #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -@@ -1358,7 +1359,8 @@ static int rtl822x_init_phycr1(struct ph +@@ -1351,14 +1352,21 @@ static int rtl822xb_write_mmd(struct phy + static int rtl822x_init_phycr1(struct phy_device *phydev, bool no_aldps) + { + struct rtl822x_priv *priv = phydev->priv; ++ u16 mask = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN; + u16 val = 0; + ++ /* The controller in some SFP modules uses MDIO address 0 to access the ++ * PHY. Leave the MDIO broadcast configuration bit alone for SFP ++ * modules, as it won't cause any issues there anyways. ++ */ ++ if (!phydev->is_on_sfp_module) ++ mask |= RTL8221B_PHYCR1_PHYAD_0_EN; ++ + if (priv->enable_aldps && !no_aldps) + val = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN; return phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_PHYCR1, - RTL8221B_PHYCR1_ALDPS_EN | +- RTL8221B_PHYCR1_ALDPS_EN | - RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN, val); -+ RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN | -+ RTL8221B_PHYCR1_PHYAD_0_EN, val); ++ mask, val); } static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) diff --git a/target/linux/generic/pending-6.18/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch b/target/linux/generic/pending-6.18/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch index f8a28d570b..72757a18bc 100644 --- a/target/linux/generic/pending-6.18/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch +++ b/target/linux/generic/pending-6.18/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch @@ -11,7 +11,7 @@ interface mode if the PHY is connected using Clause-45 MDIO. Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c -@@ -1387,7 +1387,7 @@ static int rtl822x_set_serdes_option_mod +@@ -1393,7 +1393,7 @@ static int rtl822x_set_serdes_option_mod return 0; /* determine SerDes option mode */ diff --git a/target/linux/realtek/patches-6.18/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch b/target/linux/realtek/patches-6.18/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch index dd79064599..7de7fc98c1 100644 --- a/target/linux/realtek/patches-6.18/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch +++ b/target/linux/realtek/patches-6.18/024-02-v7.1-net-phy-realtek-add-RTL8224-pair-order-support.patch @@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -@@ -1865,6 +1868,66 @@ static int rtl8224_cable_test_get_status +@@ -1871,6 +1874,66 @@ static int rtl8224_cable_test_get_status return rtl8224_cable_test_report(phydev, finished); } @@ -121,7 +121,7 @@ Signed-off-by: Jakub Kicinski static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) { int val; -@@ -2466,6 +2529,8 @@ static struct phy_driver realtek_drvs[] +@@ -2472,6 +2535,8 @@ static struct phy_driver realtek_drvs[] PHY_ID_MATCH_EXACT(0x001ccad0), .name = "RTL8224 2.5Gbps PHY", .flags = PHY_POLL_CABLE_TEST, diff --git a/target/linux/realtek/patches-6.18/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch b/target/linux/realtek/patches-6.18/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch index 2c9ac752a0..101b35b0b9 100644 --- a/target/linux/realtek/patches-6.18/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch +++ b/target/linux/realtek/patches-6.18/024-04-v7.1-net-phy-realtek-add-RTL8224-polarity-support.patch @@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -@@ -1916,9 +1917,40 @@ static int rtl8224_mdi_config_order(stru +@@ -1922,9 +1923,40 @@ static int rtl8224_mdi_config_order(stru order ? BIT(port_offset) : 0); } diff --git a/target/linux/realtek/patches-6.18/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch b/target/linux/realtek/patches-6.18/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch index b0d490f2ce..398c19f179 100644 --- a/target/linux/realtek/patches-6.18/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch +++ b/target/linux/realtek/patches-6.18/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch @@ -30,7 +30,7 @@ Signed-off-by: Jan Hoffmann --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c -@@ -1490,6 +1490,148 @@ static unsigned int rtl822x_inband_caps( +@@ -1496,6 +1496,148 @@ static unsigned int rtl822x_inband_caps( } } @@ -179,7 +179,7 @@ Signed-off-by: Jan Hoffmann static int rtl822xb_get_rate_matching(struct phy_device *phydev, phy_interface_t iface) { -@@ -2453,7 +2595,7 @@ static struct phy_driver realtek_drvs[] +@@ -2459,7 +2601,7 @@ static struct phy_driver realtek_drvs[] .soft_reset = rtl822x_c45_soft_reset, .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, diff --git a/target/linux/realtek/patches-6.18/743-net-realtek-serdes-configuration.patch b/target/linux/realtek/patches-6.18/743-net-realtek-serdes-configuration.patch index 1562e65eba..2e820fbcc5 100644 --- a/target/linux/realtek/patches-6.18/743-net-realtek-serdes-configuration.patch +++ b/target/linux/realtek/patches-6.18/743-net-realtek-serdes-configuration.patch @@ -42,7 +42,7 @@ #define RTL8221B_PHYCR1 0xa430 #define RTL8221B_PHYCR1_ALDPS_EN BIT(2) #define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12) -@@ -2034,6 +2069,147 @@ exit: +@@ -2040,6 +2075,147 @@ exit: return ret; } @@ -190,7 +190,7 @@ static int rtl8224_mdi_config_order(struct phy_device *phydev) { struct device_node *np = phydev->mdio.dev.of_node; -@@ -2088,6 +2264,10 @@ static int rtl8224_config_init(struct ph +@@ -2094,6 +2270,10 @@ static int rtl8224_config_init(struct ph { int ret; From c78e2fe26dde403179da1622c4197e74a9f1cb93 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Wed, 22 Apr 2026 17:48:20 +0200 Subject: [PATCH 18/46] realtek: fix SMBus Rollball access The Rollball command byte needs to be written last. Otherwise the controller might access the wrong register or write the wrong value. Fixes: 1fc19bc06edc ("realtek: rtl93xx: mdio-smbus support for clause 45 and Rollball SFPs") Signed-off-by: Jan Hoffmann Link: https://github.com/openwrt/openwrt/pull/23049 Signed-off-by: Hauke Mehrtens --- .../712-net-phy-add-an-MDIO-SMBus-library.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/realtek/patches-6.18/712-net-phy-add-an-MDIO-SMBus-library.patch b/target/linux/realtek/patches-6.18/712-net-phy-add-an-MDIO-SMBus-library.patch index 0b471be1ec..6f79964db9 100644 --- a/target/linux/realtek/patches-6.18/712-net-phy-add-an-MDIO-SMBus-library.patch +++ b/target/linux/realtek/patches-6.18/712-net-phy-add-an-MDIO-SMBus-library.patch @@ -260,8 +260,8 @@ Signed-off-by: Antoine Tenart + buf[2] = reg >> 8; + buf[3] = reg & 0xff; + -+ /* send address */ -+ for (i = 0; i < 4; i++) { ++ /* send address, making sure to send the command byte last */ ++ for (i = 3; i >= 0; i--) { + data.byte = buf[i]; + ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, ROLLBALL_CMD_ADDR + i, I2C_SMBUS_BYTE_DATA, &data); + if (ret < 0) @@ -311,8 +311,8 @@ Signed-off-by: Antoine Tenart + buf[4] = val >> 8; + buf[5] = val & 0xff; + -+ /* send address and value */ -+ for (i = 0; i < 6; i++) { ++ /* send address and value, making sure to send the command byte last */ ++ for (i = 5; i >= 0; i--) { + data.byte = buf[i]; + ret = __i2c_smbus_xfer(i2c, bus_addr, 0, I2C_SMBUS_WRITE, ROLLBALL_CMD_ADDR + i, I2C_SMBUS_BYTE_DATA, &data); + if (ret < 0) From a7fd866a2caf4b5549d099e1f42a3da35c51772f Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Fri, 24 Apr 2026 22:35:44 +0200 Subject: [PATCH 19/46] kernel: backport RTL8157 support to 6.18 Backport support for the RTL8157. The RTL8157 is a low-cost chipset designed for USB to 5Gb Ethernet adapters. Tested on Sabrent NT-C5GA (RTL8157), Wavlink WL-NWU340G (RTL8157) and UGREEN CM648 (RTL8156BG) adapters. Signed-off-by: Aleksander Jan Bajkowski Link: https://github.com/openwrt/openwrt/pull/23088 Signed-off-by: Hauke Mehrtens --- ...rtise-software-timestamp-information.patch | 27 + ...seT-EEE-status-configuration-support.patch | 148 ++ ...rect-register-write-to-USB_UPHY_XTAL.patch | 31 + ...-functions-for-PLA-USB-OCP-registers.patch | 2182 +++++++++++++++++ ...lper-functions-for-PHY-OCP-registers.patch | 1127 +++++++++ ...r8152-Add-helper-functions-for-SRAM2.patch | 252 ++ ...upport-for-5Gbit-Link-Speeds-and-EEE.patch | 235 ++ ...Add-support-for-the-RTL8157-hardware.patch | 1553 ++++++++++++ ...-r8152-add-LED-configuration-from-OF.patch | 16 +- 9 files changed, 5563 insertions(+), 8 deletions(-) create mode 100644 target/linux/generic/backport-6.18/740-v6.19-r8152-Advertise-software-timestamp-information.patch create mode 100644 target/linux/generic/backport-6.18/741-v7.1-r8152-Add-2500baseT-EEE-status-configuration-support.patch create mode 100644 target/linux/generic/backport-6.18/742-v7.1-r8152-fix-incorrect-register-write-to-USB_UPHY_XTAL.patch create mode 100644 target/linux/generic/backport-6.18/743-v7.1-r8152-add-helper-functions-for-PLA-USB-OCP-registers.patch create mode 100644 target/linux/generic/backport-6.18/744-v7.1-r8152-add-helper-functions-for-PHY-OCP-registers.patch create mode 100644 target/linux/generic/backport-6.18/745-v7.1-r8152-Add-helper-functions-for-SRAM2.patch create mode 100644 target/linux/generic/backport-6.18/746-v7.1-r8152-Add-support-for-5Gbit-Link-Speeds-and-EEE.patch create mode 100644 target/linux/generic/backport-6.18/747-v7.1-r8152-Add-support-for-the-RTL8157-hardware.patch diff --git a/target/linux/generic/backport-6.18/740-v6.19-r8152-Advertise-software-timestamp-information.patch b/target/linux/generic/backport-6.18/740-v6.19-r8152-Advertise-software-timestamp-information.patch new file mode 100644 index 0000000000..5fe99fe769 --- /dev/null +++ b/target/linux/generic/backport-6.18/740-v6.19-r8152-Advertise-software-timestamp-information.patch @@ -0,0 +1,27 @@ +From a8e846b8d93de748485653dd8a6a8efd8f5d7613 Mon Sep 17 00:00:00 2001 +From: Abhishek Rawal +Date: Tue, 14 Oct 2025 11:22:33 +0530 +Subject: [PATCH] r8152: Advertise software timestamp information. + +Driver calls skb_tx_timestamp(skb) in rtl8152_start_xmit(), but does not advertise the capability in ethtool. +Advertise software timestamp capabilities on struct ethtool_ops. + +Signed-off-by: Abhishek Rawal +Reviewed-by: Jamie Bainbridge +Reviewed-by: Vadim Fedorenko +Link: https://patch.msgid.link/20251014055234.46527-1-rawal.abhishek92@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/usb/r8152.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -9314,6 +9314,7 @@ static const struct ethtool_ops ops = { + .set_ringparam = rtl8152_set_ringparam, + .get_pauseparam = rtl8152_get_pauseparam, + .set_pauseparam = rtl8152_set_pauseparam, ++ .get_ts_info = ethtool_op_get_ts_info, + }; + + static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) diff --git a/target/linux/generic/backport-6.18/741-v7.1-r8152-Add-2500baseT-EEE-status-configuration-support.patch b/target/linux/generic/backport-6.18/741-v7.1-r8152-Add-2500baseT-EEE-status-configuration-support.patch new file mode 100644 index 0000000000..39c573a873 --- /dev/null +++ b/target/linux/generic/backport-6.18/741-v7.1-r8152-Add-2500baseT-EEE-status-configuration-support.patch @@ -0,0 +1,148 @@ +From e8e83b67960c20a9e60d4181631509d59f03488b Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Tue, 24 Feb 2026 18:40:14 +0100 +Subject: [PATCH] r8152: Add 2500baseT EEE status/configuration support + +The r8152 driver supports the RTL8156, which is a 2.5Gbit Ethernet controller for +USB 3.0, for which support is added for configuring and displaying the EEE +advertisement status for 2.5GBit connections. + +The patch also corrects the determination of whether EEE is active to include +the 2.5GBit connection status and make the determination dependent not on the +desired speed configuration (tp->speed), but on the actual speed used by +the controller. For consistency, this is corrected also for the RTL8152/3. + +This was tested on an Edimax EU-4307 V1.0 USB-Ethernet adapter with RTL8156, +and a SECOMP Value 12.99.1115 USB-C 3.1 Ethernet converter with RTL8153. + +Signed-off-by: Birger Koblitz +Link: https://patch.msgid.link/20260224-b4-eee2g5-v2-1-cf5c83df036e@birger-koblitz.de +Signed-off-by: Jakub Kicinski +--- + drivers/net/usb/r8152.c | 50 ++++++++++++++++++++++++++++++++++------- + 1 file changed, 42 insertions(+), 8 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -213,6 +213,7 @@ + #define OCP_EEE_LPABLE 0xa5d2 + #define OCP_10GBT_CTRL 0xa5d4 + #define OCP_10GBT_STAT 0xa5d6 ++#define OCP_EEE_LPABLE2 0xa6d0 + #define OCP_EEE_ADV2 0xa6d4 + #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ + #define OCP_PHY_PATCH_STAT 0xb800 +@@ -954,6 +955,7 @@ struct r8152 { + u16 ocp_base; + u16 speed; + u16 eee_adv; ++ u16 eee_adv2; + u8 *intr_buff; + u8 version; + u8 duplex; +@@ -5399,7 +5401,7 @@ static void r8156_eee_en(struct r8152 *t + + config = ocp_reg_read(tp, OCP_EEE_ADV2); + +- if (enable) ++ if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT)) + config |= MDIO_EEE_2_5GT; + else + config &= ~MDIO_EEE_2_5GT; +@@ -8929,7 +8931,8 @@ static void rtl8152_get_strings(struct n + + static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee) + { +- __ETHTOOL_DECLARE_LINK_MODE_MASK(common); ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(common) = {}; ++ u16 speed = rtl8152_get_speed(tp); + u16 val; + + val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); +@@ -8943,8 +8946,14 @@ static int r8152_get_eee(struct r8152 *t + + eee->eee_enabled = tp->eee_en; + +- linkmode_and(common, eee->advertised, eee->lp_advertised); +- eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); ++ if (speed & _1000bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, common); ++ if (speed & _100bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, common); ++ ++ linkmode_and(common, common, eee->advertised); ++ linkmode_and(common, common, eee->lp_advertised); ++ eee->eee_active = !linkmode_empty(common); + + return 0; + } +@@ -8955,7 +8964,10 @@ static int r8152_set_eee(struct r8152 *t + + tp->eee_en = eee->eee_enabled; + tp->eee_adv = val; +- ++ if (tp->support_2500full) { ++ val = linkmode_to_mii_eee_cap2_t(eee->advertised); ++ tp->eee_adv2 = val; ++ } + rtl_eee_enable(tp, tp->eee_en); + + return 0; +@@ -8963,7 +8975,8 @@ static int r8152_set_eee(struct r8152 *t + + static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee) + { +- __ETHTOOL_DECLARE_LINK_MODE_MASK(common); ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(common) = {}; ++ u16 speed = rtl8152_get_speed(tp); + u16 val; + + val = ocp_reg_read(tp, OCP_EEE_ABLE); +@@ -8975,10 +8988,29 @@ static int r8153_get_eee(struct r8152 *t + val = ocp_reg_read(tp, OCP_EEE_LPABLE); + mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); + ++ if (tp->support_2500full) { ++ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); ++ ++ val = ocp_reg_read(tp, OCP_EEE_ADV2); ++ mii_eee_cap2_mod_linkmode_adv_t(eee->advertised, val); ++ ++ val = ocp_reg_read(tp, OCP_EEE_LPABLE2); ++ mii_eee_cap2_mod_linkmode_adv_t(eee->lp_advertised, val); ++ ++ if (speed & _2500bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, common); ++ } ++ + eee->eee_enabled = tp->eee_en; + +- linkmode_and(common, eee->advertised, eee->lp_advertised); +- eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); ++ if (speed & _1000bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, common); ++ if (speed & _100bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, common); ++ ++ linkmode_and(common, common, eee->advertised); ++ linkmode_and(common, common, eee->lp_advertised); ++ eee->eee_active = !linkmode_empty(common); + + return 0; + } +@@ -9519,6 +9551,7 @@ static int rtl_ops_init(struct r8152 *tp + case RTL_VER_11: + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ tp->eee_adv2 = MDIO_EEE_2_5GT; + fallthrough; + case RTL_VER_10: + ops->init = r8156_init; +@@ -9544,6 +9577,7 @@ static int rtl_ops_init(struct r8152 *tp + case RTL_VER_15: + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ tp->eee_adv2 = MDIO_EEE_2_5GT; + ops->init = r8156b_init; + ops->enable = rtl8156b_enable; + ops->disable = rtl8153_disable; diff --git a/target/linux/generic/backport-6.18/742-v7.1-r8152-fix-incorrect-register-write-to-USB_UPHY_XTAL.patch b/target/linux/generic/backport-6.18/742-v7.1-r8152-fix-incorrect-register-write-to-USB_UPHY_XTAL.patch new file mode 100644 index 0000000000..1dee906123 --- /dev/null +++ b/target/linux/generic/backport-6.18/742-v7.1-r8152-fix-incorrect-register-write-to-USB_UPHY_XTAL.patch @@ -0,0 +1,31 @@ +From 48afd5124fd6129c46fd12cb06155384b1c4a0c4 Mon Sep 17 00:00:00 2001 +From: Chih Kai Hsu +Date: Thu, 26 Mar 2026 15:39:23 +0800 +Subject: [PATCH] r8152: fix incorrect register write to USB_UPHY_XTAL + +The old code used ocp_write_byte() to clear the OOBS_POLLING bit +(BIT(8)) in the USB_UPHY_XTAL register, but this doesn't correctly +clear a bit in the upper byte of the 16-bit register. + +Fix this by using ocp_write_word() instead. + +Fixes: 195aae321c82 ("r8152: support new chips") +Signed-off-by: Chih Kai Hsu +Reviewed-by: Hayes Wang +Link: https://patch.msgid.link/20260326073925.32976-454-nic_swsd@realtek.com +Signed-off-by: Paolo Abeni +--- + drivers/net/usb/r8152.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -3898,7 +3898,7 @@ static void r8156_ups_en(struct r8152 *t + case RTL_VER_15: + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); + ocp_data &= ~OOBS_POLLING; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); ++ ocp_write_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); + break; + default: + break; diff --git a/target/linux/generic/backport-6.18/743-v7.1-r8152-add-helper-functions-for-PLA-USB-OCP-registers.patch b/target/linux/generic/backport-6.18/743-v7.1-r8152-add-helper-functions-for-PLA-USB-OCP-registers.patch new file mode 100644 index 0000000000..1d6d9f6bc9 --- /dev/null +++ b/target/linux/generic/backport-6.18/743-v7.1-r8152-add-helper-functions-for-PLA-USB-OCP-registers.patch @@ -0,0 +1,2182 @@ +From d16133f177fea620d6b413990683b6a8b2641be5 Mon Sep 17 00:00:00 2001 +From: Chih Kai Hsu +Date: Thu, 26 Mar 2026 15:39:24 +0800 +Subject: [PATCH] r8152: add helper functions for PLA/USB OCP registers + +Add the following bitwise operation functions for PLA/USB OCP registers +to simplify the code. + +- ocp_dword_w0w1() +- ocp_word_w0w1() +- ocp_byte_w0w1() +- ocp_dword_clr_bits() +- ocp_dword_set_bits() +- ocp_word_clr_bits() +- ocp_word_set_bits() +- ocp_word_test_and_clr_bits() +- ocp_byte_clr_bits() +- ocp_byte_set_bits() + +Signed-off-by: Chih Kai Hsu +Reviewed-by: Hayes Wang +Link: https://patch.msgid.link/20260326073925.32976-455-nic_swsd@realtek.com +Signed-off-by: Paolo Abeni +--- + drivers/net/usb/r8152.c | 1103 +++++++++++++++------------------------ + 1 file changed, 408 insertions(+), 695 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -1660,6 +1660,78 @@ void write_mii_word(struct net_device *n + r8152_mdio_write(tp, reg, val); + } + ++static void ++ocp_dword_w0w1(struct r8152 *tp, u16 type, u16 index, u32 clear, u32 set) ++{ ++ u32 ocp_data; ++ ++ ocp_data = ocp_read_dword(tp, type, index); ++ ocp_data = (ocp_data & ~clear) | set; ++ ocp_write_dword(tp, type, index, ocp_data); ++} ++ ++static void ++ocp_word_w0w1(struct r8152 *tp, u16 type, u16 index, u16 clear, u16 set) ++{ ++ u16 ocp_data; ++ ++ ocp_data = ocp_read_word(tp, type, index); ++ ocp_data = (ocp_data & ~clear) | set; ++ ocp_write_word(tp, type, index, ocp_data); ++} ++ ++static void ++ocp_byte_w0w1(struct r8152 *tp, u16 type, u16 index, u8 clear, u8 set) ++{ ++ u8 ocp_data; ++ ++ ocp_data = ocp_read_byte(tp, type, index); ++ ocp_data = (ocp_data & ~clear) | set; ++ ocp_write_byte(tp, type, index, ocp_data); ++} ++ ++static void ocp_dword_clr_bits(struct r8152 *tp, u16 type, u16 index, u32 clear) ++{ ++ ocp_dword_w0w1(tp, type, index, clear, 0); ++} ++ ++static void ocp_dword_set_bits(struct r8152 *tp, u16 type, u16 index, u32 set) ++{ ++ ocp_dword_w0w1(tp, type, index, 0, set); ++} ++ ++static void ocp_word_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 clear) ++{ ++ ocp_word_w0w1(tp, type, index, clear, 0); ++} ++ ++static void ocp_word_set_bits(struct r8152 *tp, u16 type, u16 index, u16 set) ++{ ++ ocp_word_w0w1(tp, type, index, 0, set); ++} ++ ++static int ++ocp_word_test_and_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 clear) ++{ ++ u16 ocp_data; ++ ++ ocp_data = ocp_read_word(tp, type, index); ++ if (ocp_data & clear) ++ ocp_write_word(tp, type, index, ocp_data & ~clear); ++ ++ return ocp_data & clear; ++} ++ ++static void ocp_byte_clr_bits(struct r8152 *tp, u16 type, u16 index, u8 clear) ++{ ++ ocp_byte_w0w1(tp, type, index, clear, 0); ++} ++ ++static void ocp_byte_set_bits(struct r8152 *tp, u16 type, u16 index, u8 set) ++{ ++ ocp_byte_w0w1(tp, type, index, 0, set); ++} ++ + static int + r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); + +@@ -2962,47 +3034,31 @@ static netdev_tx_t rtl8152_start_xmit(st + + static void r8152b_reset_packet_filter(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); +- ocp_data &= ~FMC_FCR_MCU_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); +- ocp_data |= FMC_FCR_MCU_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN); + } + + static void rtl8152_nic_reset(struct r8152 *tp) + { +- u32 ocp_data; + int i; + + switch (tp->version) { + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); +- ocp_data &= ~CR_TE; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); +- ocp_data &= ~BMU_RESET_EP_IN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data |= CDC_ECM_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); +- ocp_data &= ~CR_RE; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); +- ocp_data |= BMU_RESET_EP_IN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~CDC_ECM_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_TE); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, ++ BMU_RESET_EP_IN); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); ++ ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, ++ BMU_RESET_EP_IN); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); + break; + + default: +@@ -3031,14 +3087,12 @@ static inline u16 rtl8152_get_speed(stru + + static void rtl_eee_plus_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); + if (enable) +- ocp_data |= EEEP_CR_EEEP_TX; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ++ EEEP_CR_EEEP_TX); + else +- ocp_data &= ~EEEP_CR_EEEP_TX; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ++ EEEP_CR_EEEP_TX); + } + + static void rtl_set_eee_plus(struct r8152 *tp) +@@ -3051,14 +3105,10 @@ static void rtl_set_eee_plus(struct r815 + + static void rxdy_gated_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); + if (enable) +- ocp_data |= RXDY_GATED_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN); + else +- ocp_data &= ~RXDY_GATED_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN); + } + + static int rtl_start_rx(struct r8152 *tp) +@@ -3146,24 +3196,16 @@ static int rtl_stop_rx(struct r8152 *tp) + + static void rtl_set_ifg(struct r8152 *tp, u16 speed) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); +- ocp_data &= ~IFG_MASK; + if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { +- ocp_data |= IFG_144NS; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_144NS); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); +- ocp_data &= ~TX10MIDLE_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ TX10MIDLE_EN); + } else { +- ocp_data |= IFG_96NS; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_96NS); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); +- ocp_data |= TX10MIDLE_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ TX10MIDLE_EN); + } + } + +@@ -3175,13 +3217,9 @@ static inline void r8153b_rx_agg_chg_ind + + static int rtl_enable(struct r8152 *tp) + { +- u32 ocp_data; +- + r8152b_reset_packet_filter(tp); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); +- ocp_data |= CR_RE | CR_TE; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE); + + switch (tp->version) { + case RTL_VER_01: +@@ -3289,8 +3327,6 @@ static void r8153_set_rx_early_size(stru + + static int rtl8153_enable(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return -ENODEV; + +@@ -3304,12 +3340,9 @@ static int rtl8153_enable(struct r8152 * + switch (tp->version) { + case RTL_VER_09: + case RTL_VER_14: +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data &= ~FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + usleep_range(1000, 2000); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + break; + default: + break; +@@ -3328,9 +3361,7 @@ static void rtl_disable(struct r8152 *tp + return; + } + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~RCR_ACPT_ALL; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rtl_drop_queued_tx(tp); + +@@ -3363,24 +3394,17 @@ static void rtl_disable(struct r8152 *tp + + static void r8152_power_cut_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); + if (enable) +- ocp_data |= POWER_CUT; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT); + else +- ocp_data &= ~POWER_CUT; +- ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); +- ocp_data &= ~RESUME_INDICATE; +- ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ++ RESUME_INDICATE); + } + + static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: +@@ -3392,12 +3416,12 @@ static void rtl_rx_vlan_en(struct r8152 + case RTL_VER_08: + case RTL_VER_09: + case RTL_VER_14: +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); + if (enable) +- ocp_data |= CPCR_RX_VLAN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, ++ CPCR_RX_VLAN); + else +- ocp_data &= ~CPCR_RX_VLAN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CPCR, ++ CPCR_RX_VLAN); + break; + + case RTL_TEST_01: +@@ -3407,12 +3431,12 @@ static void rtl_rx_vlan_en(struct r8152 + case RTL_VER_13: + case RTL_VER_15: + default: +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); + if (enable) +- ocp_data |= OUTER_VLAN | INNER_VLAN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1, ++ OUTER_VLAN | INNER_VLAN); + else +- ocp_data &= ~(OUTER_VLAN | INNER_VLAN); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, ++ OUTER_VLAN | INNER_VLAN); + break; + } + } +@@ -3473,33 +3497,33 @@ static u32 __rtl_get_wol(struct r8152 *t + + static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) + { +- u32 ocp_data; ++ u16 ocp_data; + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); +- ocp_data &= ~LINK_ON_WAKE_EN; + if (wolopts & WAKE_PHY) +- ocp_data |= LINK_ON_WAKE_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, ++ LINK_ON_WAKE_EN); ++ else ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, ++ LINK_ON_WAKE_EN); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); +- ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); ++ ocp_data = 0; + if (wolopts & WAKE_UCAST) + ocp_data |= UWF_EN; + if (wolopts & WAKE_BCAST) + ocp_data |= BWF_EN; + if (wolopts & WAKE_MCAST) + ocp_data |= MWF_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_CONFIG5, UWF_EN | BWF_EN | MWF_EN, ++ ocp_data); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); +- ocp_data &= ~MAGIC_EN; + if (wolopts & WAKE_MAGIC) +- ocp_data |= MAGIC_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN); ++ else ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN); + + if (wolopts & WAKE_ANY) + device_set_wakeup_enable(&tp->udev->dev, true); +@@ -3509,35 +3533,27 @@ static void __rtl_set_wol(struct r8152 * + + static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) + { +- u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); +- + /* MAC clock speed down */ + if (enable) +- ocp_data |= MAC_CLK_SPDWN_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ++ MAC_CLK_SPDWN_EN); + else +- ocp_data &= ~MAC_CLK_SPDWN_EN; +- +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ++ MAC_CLK_SPDWN_EN); + } + + static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- + /* MAC clock speed down */ + if (enable) { + /* aldps_spdwn_ratio, tp10_spdwn_ratio */ +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, +- 0x0403); ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0x0403); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); +- ocp_data &= ~EEE_SPDWN_RATIO_MASK; +- ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ++ EEE_SPDWN_RATIO_MASK, MAC_CLK_SPDWN_EN | 0x03); + } else { +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); +- ocp_data &= ~MAC_CLK_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ++ MAC_CLK_SPDWN_EN); + } + } + +@@ -3555,27 +3571,20 @@ static void r8153_u1u2en(struct r8152 *t + + static void r8153b_u1u2en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); + if (enable) +- ocp_data |= LPM_U1U2_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ++ LPM_U1U2_EN); + else +- ocp_data &= ~LPM_U1U2_EN; +- +- ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ++ LPM_U1U2_EN); + } + + static void r8153_u2p3en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); + if (enable) +- ocp_data |= U2P3_ENABLE; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); + else +- ocp_data &= ~U2P3_ENABLE; +- ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); + } + + static void r8153b_ups_flags(struct r8152 *tp) +@@ -3790,24 +3799,20 @@ static u16 r8153_phy_status(struct r8152 + + static void r8153b_ups_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); +- + if (enable) { + r8153b_ups_flags(tp); + +- ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE | PHASE2_EN); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data |= UPS_FORCE_PWR_DOWN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, ++ UPS_FORCE_PWR_DOWN); + } else { +- ocp_data &= ~(UPS_EN | USP_PREWAKE); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data &= ~UPS_FORCE_PWR_DOWN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, ++ UPS_FORCE_PWR_DOWN); + + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { + int i; +@@ -3831,25 +3836,20 @@ static void r8153b_ups_en(struct r8152 * + + static void r8153c_ups_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); +- + if (enable) { + r8153b_ups_flags(tp); + +- ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE | PHASE2_EN); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data |= UPS_FORCE_PWR_DOWN; +- ocp_data &= ~BIT(7); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_w0w1(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7), ++ UPS_FORCE_PWR_DOWN); + } else { +- ocp_data &= ~(UPS_EN | USP_PREWAKE); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data &= ~UPS_FORCE_PWR_DOWN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, ++ UPS_FORCE_PWR_DOWN); + + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { + int i; +@@ -3871,9 +3871,7 @@ static void r8153c_ups_en(struct r8152 * + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); +- ocp_data |= BIT(8); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8)); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + } +@@ -3881,35 +3879,30 @@ static void r8153c_ups_en(struct r8152 * + + static void r8156_ups_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); +- + if (enable) { + r8156_ups_flags(tp); + +- ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE | PHASE2_EN); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data |= UPS_FORCE_PWR_DOWN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, ++ UPS_FORCE_PWR_DOWN); + + switch (tp->version) { + case RTL_VER_13: + case RTL_VER_15: +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); +- ocp_data &= ~OOBS_POLLING; +- ocp_write_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ++ OOBS_POLLING); + break; + default: + break; + } + } else { +- ocp_data &= ~(UPS_EN | USP_PREWAKE); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ UPS_EN | USP_PREWAKE); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data &= ~UPS_FORCE_PWR_DOWN; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, ++ UPS_FORCE_PWR_DOWN); + + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { + tp->rtl_ops.hw_phy_cfg(tp); +@@ -3922,54 +3915,38 @@ static void r8156_ups_en(struct r8152 *t + + static void r8153_power_cut_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); + if (enable) +- ocp_data |= PWR_EN | PHASE2_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ PWR_EN | PHASE2_EN); + else +- ocp_data &= ~(PWR_EN | PHASE2_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ PWR_EN | PHASE2_EN); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- ocp_data &= ~PCUT_STATUS; +- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + } + + static void r8153b_power_cut_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); + if (enable) +- ocp_data |= PWR_EN | PHASE2_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, ++ PWR_EN | PHASE2_EN); + else +- ocp_data &= ~PWR_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- ocp_data &= ~PCUT_STATUS; +- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + } + + static void r8153_queue_wake(struct r8152 *tp, bool enable) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); + if (enable) +- ocp_data |= UPCOMING_RUNTIME_D3; ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ++ UPCOMING_RUNTIME_D3); + else +- ocp_data &= ~UPCOMING_RUNTIME_D3; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ++ UPCOMING_RUNTIME_D3); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); +- ocp_data &= ~LINK_CHG_EVENT; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); +- ocp_data &= ~LINK_CHANGE_FLAG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, LINK_CHG_EVENT); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, LINK_CHANGE_FLAG); + } + + static bool rtl_can_wakeup(struct r8152 *tp) +@@ -3982,27 +3959,21 @@ static bool rtl_can_wakeup(struct r8152 + static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) + { + if (enable) { +- u32 ocp_data; +- + __rtl_set_wol(tp, WAKE_ANY); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); +- ocp_data |= LINK_OFF_WAKE_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, ++ LINK_OFF_WAKE_EN); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + } else { +- u32 ocp_data; +- + __rtl_set_wol(tp, tp->saved_wolopts); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); +- ocp_data &= ~LINK_OFF_WAKE_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, ++ LINK_OFF_WAKE_EN); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + } +@@ -4083,8 +4054,6 @@ static void rtl8156_runtime_enable(struc + + static void r8153_teredo_off(struct r8152 *tp) + { +- u32 ocp_data; +- + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: +@@ -4093,10 +4062,9 @@ static void r8153_teredo_off(struct r815 + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); +- ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | +- OOB_TEREDO_EN); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ++ TEREDO_SEL | TEREDO_RS_EVENT_MASK | ++ OOB_TEREDO_EN); + break; + + case RTL_VER_08: +@@ -4123,13 +4091,10 @@ static void r8153_teredo_off(struct r815 + + static void rtl_reset_bmu(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); +- ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); +- ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, ++ BMU_RESET_EP_IN | BMU_RESET_EP_OUT); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, ++ BMU_RESET_EP_IN | BMU_RESET_EP_OUT); + } + + /* Clear the bp to stop the firmware before loading a new one */ +@@ -4950,7 +4915,7 @@ static void rtl_ram_code_speed_up(struct + return; + + while (len) { +- u32 ocp_data, size; ++ u32 size; + int i; + + if (len < 2048) +@@ -4958,18 +4923,16 @@ static void rtl_ram_code_speed_up(struct + else + size = 2048; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); +- ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; +- ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ++ GPHY_PATCH_DONE | BACKUP_RESTRORE); + + generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); + + data += size; + len -= size; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); +- ocp_data |= POL_GPHY_PATCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ++ POL_GPHY_PATCH); + + for (i = 0; i < 1000; i++) { + if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) +@@ -5343,21 +5306,21 @@ static void r8152_mmd_write(struct r8152 + static void r8152_eee_en(struct r8152 *tp, bool enable) + { + u16 config1, config2, config3; +- u32 ocp_data; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); + config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; + config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); + config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; + + if (enable) { +- ocp_data |= EEE_RX_EN | EEE_TX_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, ++ EEE_RX_EN | EEE_TX_EN); + config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; + config1 |= sd_rise_time(1); + config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; + config3 |= fast_snr(42); + } else { +- ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, ++ EEE_RX_EN | EEE_TX_EN); + config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | + RX_QUIET_EN); + config1 |= sd_rise_time(7); +@@ -5365,7 +5328,6 @@ static void r8152_eee_en(struct r8152 *t + config3 |= fast_snr(511); + } + +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); + ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); + ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); + ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); +@@ -5373,21 +5335,20 @@ static void r8152_eee_en(struct r8152 *t + + static void r8153_eee_en(struct r8152 *tp, bool enable) + { +- u32 ocp_data; + u16 config; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); + config = ocp_reg_read(tp, OCP_EEE_CFG); + + if (enable) { +- ocp_data |= EEE_RX_EN | EEE_TX_EN; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, ++ EEE_RX_EN | EEE_TX_EN); + config |= EEE10_EN; + } else { +- ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, ++ EEE_RX_EN | EEE_TX_EN); + config &= ~EEE10_EN; + } + +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); + ocp_reg_write(tp, OCP_EEE_CFG, config); + + tp->ups_info.eee = enable; +@@ -5518,30 +5479,20 @@ static void r8156b_wait_loading_flash(st + + static void r8152b_exit_oob(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~RCR_ACPT_ALL; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data &= ~MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + wait_oob_link_list_ready(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= RE_INIT_LL; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); + + wait_oob_link_list_ready(tp); + +@@ -5577,18 +5528,12 @@ static void r8152b_exit_oob(struct r8152 + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); +- ocp_data |= TCR0_AUTO_FIFO; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO); + } + + static void r8152b_enter_oob(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); +@@ -5598,9 +5543,7 @@ static void r8152b_enter_oob(struct r815 + + wait_oob_link_list_ready(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= RE_INIT_LL; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); + + wait_oob_link_list_ready(tp); + +@@ -5608,19 +5551,15 @@ static void r8152b_enter_oob(struct r815 + + rtl_rx_vlan_en(tp, true); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); +- ocp_data |= ALDPS_PROXY_MODE; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ++ NOW_IS_OOB | DIS_MCU_CLROOB); + + rxdy_gated_en(tp, false); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data |= RCR_APM | RCR_AM | RCR_AB; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, ++ RCR_APM | RCR_AM | RCR_AB); + } + + static int r8153_pre_firmware_1(struct r8152 *tp) +@@ -5655,27 +5594,18 @@ static int r8153_post_firmware_1(struct + + static int r8153_pre_firmware_2(struct r8152 *tp) + { +- u32 ocp_data; +- + r8153_pre_firmware_1(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); +- ocp_data &= ~FW_FIX_SUSPEND; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND); + + return 0; + } + + static int r8153_post_firmware_2(struct r8152 *tp) + { +- u32 ocp_data; +- + /* enable bp0 if support USB_SPEED_SUPER only */ +- if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); +- ocp_data |= BIT(0); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); +- } ++ if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0)); + + /* reset UPHY timer to 36 ms */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); +@@ -5683,28 +5613,20 @@ static int r8153_post_firmware_2(struct + /* enable U3P3 check, set the counter to 4 */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); +- ocp_data |= FW_FIX_SUSPEND; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); +- ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND); ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, ++ USB2PHY_L1 | USB2PHY_SUSPEND); + + return 0; + } + + static int r8153_post_firmware_3(struct r8152 *tp) + { +- u32 ocp_data; ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, ++ USB2PHY_L1 | USB2PHY_SUSPEND); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); +- ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); +- ocp_data |= FW_IP_RESET_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); + + return 0; + } +@@ -5724,49 +5646,30 @@ static int r8153b_post_firmware_1(struct + + /* enable bp0 for RTL8153-BND */ + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); +- if (ocp_data & BND_MASK) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); +- ocp_data |= BIT(0); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); +- } +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); +- ocp_data |= FLOW_CTRL_PATCH_OPT; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); +- ocp_data |= FW_IP_RESET_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); ++ if (ocp_data & BND_MASK) ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0)); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_OPT); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); + + return 0; + } + + static int r8153c_post_firmware_1(struct r8152 *tp) + { +- u32 ocp_data; ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_2); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); +- ocp_data |= FLOW_CTRL_PATCH_2; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + + return 0; + } + + static int r8156a_post_firmware_1(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); +- ocp_data |= FW_IP_RESET_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); + + /* Modify U3PHY parameter for compatibility issue */ + ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); +@@ -5802,7 +5705,6 @@ static void r8153_aldps_en(struct r8152 + + static void r8153_hw_phy_cfg(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + + /* disable ALDPS before updating the PHY parameters */ +@@ -5829,11 +5731,10 @@ static void r8153_hw_phy_cfg(struct r815 + data = ocp_reg_read(tp, OCP_POWER_CFG); + data |= EN_10M_PLLOFF; + ocp_reg_write(tp, OCP_POWER_CFG, data); ++ + sram_write(tp, SRAM_IMPEDANCE, 0x0b13); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= PFM_PWM_SWITCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + + /* Enable LPF corner auto tune */ + sram_write(tp, SRAM_LPF_CFG, 0xf70f); +@@ -5879,11 +5780,7 @@ static void r8153b_hw_phy_cfg(struct r81 + u32 ocp_data; + u16 data; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- if (ocp_data & PCUT_STATUS) { +- ocp_data &= ~PCUT_STATUS; +- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); +- } ++ ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + + /* disable ALDPS before updating the PHY parameters */ + r8153_aldps_en(tp, false); +@@ -5940,14 +5837,11 @@ static void r8153b_hw_phy_cfg(struct r81 + u32 swr_cnt_1ms_ini; + + swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); +- ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; +- ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_UPS_CFG, SAW_CNT_1MS_MASK, ++ swr_cnt_1ms_ini); + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= PFM_PWM_SWITCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + + /* Advnace EEE */ + if (!rtl_phy_patch_request(tp, true, true)) { +@@ -5994,31 +5888,21 @@ static void rtl8153_change_mtu(struct r8 + + static void r8153_first_init(struct r8152 *tp) + { +- u32 ocp_data; +- + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~RCR_ACPT_ALL; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rtl8152_nic_reset(tp); + rtl_reset_bmu(tp); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data &= ~MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + wait_oob_link_list_ready(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= RE_INIT_LL; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); + + wait_oob_link_list_ready(tp); + +@@ -6026,9 +5910,7 @@ static void r8153_first_init(struct r815 + + rtl8153_change_mtu(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); +- ocp_data |= TCR0_AUTO_FIFO; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO); + + rtl8152_nic_reset(tp); + +@@ -6042,11 +5924,7 @@ static void r8153_first_init(struct r815 + + static void r8153_enter_oob(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + + /* RX FIFO settings for OOB */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); +@@ -6058,9 +5936,7 @@ static void r8153_enter_oob(struct r8152 + + wait_oob_link_list_ready(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= RE_INIT_LL; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); + + wait_oob_link_list_ready(tp); + +@@ -6072,9 +5948,8 @@ static void r8153_enter_oob(struct r8152 + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); +- ocp_data &= ~TEREDO_WAKE_MASK; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ++ TEREDO_WAKE_MASK); + break; + + case RTL_VER_08: +@@ -6093,23 +5968,17 @@ static void r8153_enter_oob(struct r8152 + + rtl_rx_vlan_en(tp, true); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); +- ocp_data |= ALDPS_PROXY_MODE; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ++ NOW_IS_OOB | DIS_MCU_CLROOB); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rxdy_gated_en(tp, false); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data |= RCR_APM | RCR_AM | RCR_AB; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, ++ RCR_APM | RCR_AM | RCR_AB); + } + + static void rtl8153_disable(struct r8152 *tp) +@@ -6141,7 +6010,6 @@ static void r8156_fc_parameter(struct r8 + + static int rtl8156_enable(struct r8152 *tp) + { +- u32 ocp_data; + u16 speed; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +@@ -6156,12 +6024,12 @@ static int rtl8156_enable(struct r8152 * + speed = rtl8152_get_speed(tp); + rtl_set_ifg(tp, speed); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); + if (speed & _2500bps) +- ocp_data &= ~IDLE_SPDWN_EN; ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ IDLE_SPDWN_EN); + else +- ocp_data |= IDLE_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ IDLE_SPDWN_EN); + + if (speed & _1000bps) + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); +@@ -6170,21 +6038,15 @@ static int rtl8156_enable(struct r8152 * + + if (tp->udev->speed == USB_SPEED_HIGH) { + /* USB 0xb45e[3:0] l1_nyet_hird */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); +- ocp_data &= ~0xf; + if (is_flow_control(speed)) +- ocp_data |= 0xf; ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); + else +- ocp_data |= 0x1; +- ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data &= ~FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + usleep_range(1000, 2000); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + + return rtl_enable(tp); + } +@@ -6199,7 +6061,6 @@ static void rtl8156_disable(struct r8152 + + static int rtl8156b_enable(struct r8152 *tp) + { +- u32 ocp_data; + u16 speed; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +@@ -6208,9 +6069,7 @@ static int rtl8156b_enable(struct r8152 + set_tx_qlen(tp); + rtl_set_eee_plus(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); +- ocp_data &= ~RX_AGGR_NUM_MASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); + + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); +@@ -6218,29 +6077,23 @@ static int rtl8156b_enable(struct r8152 + speed = rtl8152_get_speed(tp); + rtl_set_ifg(tp, speed); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); + if (speed & _2500bps) +- ocp_data &= ~IDLE_SPDWN_EN; ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ IDLE_SPDWN_EN); + else +- ocp_data |= IDLE_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ IDLE_SPDWN_EN); + + if (tp->udev->speed == USB_SPEED_HIGH) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); +- ocp_data &= ~0xf; + if (is_flow_control(speed)) +- ocp_data |= 0xf; ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); + else +- ocp_data |= 0x1; +- ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data &= ~FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + usleep_range(1000, 2000); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + + return rtl_enable(tp); + } +@@ -6411,8 +6264,6 @@ static void rtl8152_down(struct r8152 *t + + static void rtl8153_up(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +@@ -6421,17 +6272,11 @@ static void rtl8153_up(struct r8152 *tp) + r8153_aldps_en(tp, false); + r8153_first_init(tp); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); +- ocp_data |= LANWAKE_CLR_EN; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); +- ocp_data &= ~LANWAKE_PIN; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); +- ocp_data &= ~DELAY_PHY_PWR_CHG; +- ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); ++ ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SSPHYLINK1, DELAY_PHY_PWR_CHG); + + r8153_aldps_en(tp, true); + +@@ -6451,16 +6296,12 @@ static void rtl8153_up(struct r8152 *tp) + + static void rtl8153_down(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { + rtl_drop_queued_tx(tp); + return; + } + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); +- ocp_data &= ~LANWAKE_CLR_EN; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); + + r8153_u1u2en(tp, false); + r8153_u2p3en(tp, false); +@@ -6472,8 +6313,6 @@ static void rtl8153_down(struct r8152 *t + + static void rtl8153b_up(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +@@ -6484,9 +6323,8 @@ static void rtl8153b_up(struct r8152 *tp + r8153_first_init(tp); + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + + r8153_aldps_en(tp, true); + +@@ -6496,16 +6334,13 @@ static void rtl8153b_up(struct r8152 *tp + + static void rtl8153b_down(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { + rtl_drop_queued_tx(tp); + return; + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data |= PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + + r8153b_u1u2en(tp, false); + r8153_u2p3en(tp, false); +@@ -6533,8 +6368,6 @@ static void rtl8153c_change_mtu(struct r + + static void rtl8153c_up(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +@@ -6545,26 +6378,18 @@ static void rtl8153c_up(struct r8152 *tp + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~RCR_ACPT_ALL; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rtl8152_nic_reset(tp); + rtl_reset_bmu(tp); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data &= ~MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + wait_oob_link_list_ready(tp); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= RE_INIT_LL; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); + + wait_oob_link_list_ready(tp); + +@@ -6584,15 +6409,12 @@ static void rtl8153c_up(struct r8152 *tp + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); +- ocp_data |= BIT(8); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8)); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + + r8153_aldps_en(tp, true); + r8153b_u1u2en(tp, true); +@@ -6614,8 +6436,6 @@ static void rtl8156_change_mtu(struct r8 + + static void rtl8156_up(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +@@ -6626,20 +6446,14 @@ static void rtl8156_up(struct r8152 *tp) + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~RCR_ACPT_ALL; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); + + rtl8152_nic_reset(tp); + rtl_reset_bmu(tp); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data &= ~MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); + +@@ -6649,27 +6463,21 @@ static void rtl8156_up(struct r8152 *tp) + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); +- ocp_data |= ACT_ODMA; +- ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); + break; + default: + break; + } + + /* share FIFO settings */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); +- ocp_data &= ~RXFIFO_FULL_MASK; +- ocp_data |= 0x08; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); +- ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); +- ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK, ++ 0x08); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ++ RG_PWRDN_EN | ALL_SPEED_OFF); + + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); + +@@ -6687,25 +6495,20 @@ static void rtl8156_up(struct r8152 *tp) + + static void rtl8156_down(struct r8152 *tp) + { +- u32 ocp_data; +- + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { + rtl_drop_queued_tx(tp); + return; + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data |= PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + + r8153b_u1u2en(tp, false); + r8153_u2p3en(tp, false); + r8153b_power_cut_en(tp, false); + r8153_aldps_en(tp, false); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data &= ~NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + + /* RX FIFO settings for OOB */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); +@@ -6724,20 +6527,15 @@ static void rtl8156_down(struct r8152 *t + */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); +- ocp_data |= NOW_IS_OOB; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); +- ocp_data |= MCU_BORW_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rtl_rx_vlan_en(tp, true); + rxdy_gated_en(tp, false); + +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data |= RCR_APM | RCR_AM | RCR_AB; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); ++ ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, ++ RCR_APM | RCR_AM | RCR_AB); + + r8153_aldps_en(tp, true); + } +@@ -7014,11 +6812,7 @@ static int rtl8152_close(struct net_devi + + static void rtl_tally_reset(struct r8152 *tp) + { +- u32 ocp_data; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); +- ocp_data |= TALLY_RESET; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RSTTALLY, TALLY_RESET); + } + + static void r8152b_init(struct r8152 *tp) +@@ -7037,21 +6831,18 @@ static void r8152b_init(struct r8152 *tp + + r8152_aldps_en(tp, false); + +- if (tp->version == RTL_VER_01) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); +- ocp_data &= ~LED_MODE_MASK; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); +- } ++ if (tp->version == RTL_VER_01) ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ++ LED_MODE_MASK); + + r8152_power_cut_en(tp, false); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); +- ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); +- ocp_data &= ~MCU_CLK_RATIO_MASK; +- ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; +- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ++ TX_10M_IDLE_EN | PFM_PWM_SWITCH); ++ ++ ocp_dword_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, MCU_CLK_RATIO_MASK, ++ MCU_CLK_RATIO | D3_CLK_GATED_EN); ++ + ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | + SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); +@@ -7059,9 +6850,8 @@ static void r8152b_init(struct r8152 *tp + rtl_tally_reset(tp); + + /* enable rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); + } + + static void r8153_init(struct r8152 *tp) +@@ -7102,55 +6892,43 @@ static void r8153_init(struct r8152 *tp) + r8153_u2p3en(tp, false); + + if (tp->version == RTL_VER_04) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); +- ocp_data &= ~pwd_dn_scale_mask; +- ocp_data |= pwd_dn_scale(96); +- ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); +- ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ++ pwd_dn_scale_mask, pwd_dn_scale(96)); ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, ++ USB2PHY_L1 | USB2PHY_SUSPEND); + } else if (tp->version == RTL_VER_05) { +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); +- ocp_data &= ~ECM_ALDPS; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ECM_ALDPS); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); + if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) +- ocp_data &= ~DYNAMIC_BURST; ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ++ DYNAMIC_BURST); + else +- ocp_data |= DYNAMIC_BURST; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ++ DYNAMIC_BURST); + } else if (tp->version == RTL_VER_06) { +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); + if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) +- ocp_data &= ~DYNAMIC_BURST; ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ++ DYNAMIC_BURST); + else +- ocp_data |= DYNAMIC_BURST; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ++ DYNAMIC_BURST); + + r8153_queue_wake(tp, false); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_data |= CUR_LINK_OK; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK | POLL_LINK_CHG); + else +- ocp_data &= ~CUR_LINK_OK; +- ocp_data |= POLL_LINK_CHG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); +- } +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); +- ocp_data |= EP4_FULL_FC; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); +- ocp_data &= ~TIMER11_EN; +- ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); +- ocp_data &= ~LED_MODE_MASK; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK, POLL_LINK_CHG); ++ } ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, EP4_FULL_FC); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_WDT11_CTRL, TIMER11_EN); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, LED_MODE_MASK); + + ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; + if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) +@@ -7159,10 +6937,8 @@ static void r8153_init(struct r8152 *tp) + ocp_data |= LPM_TIMER_500US; + ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); +- ocp_data &= ~SEN_VAL_MASK; +- ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; +- ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_AFE_CTRL2, SEN_VAL_MASK, ++ SEN_VAL_NORMAL | SEL_RXIDLE); + + ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); + +@@ -7172,21 +6948,17 @@ static void r8153_init(struct r8152 *tp) + r8153_u1u2en(tp, true); + usb_enable_lpm(tp->udev); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); +- ocp_data |= LANWAKE_CLR_EN; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); +- ocp_data &= ~LANWAKE_PIN; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); ++ ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN); + + /* rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + if (tp->dell_tb_rx_agg_bug) +- ocp_data |= RX_AGG_DISABLE; +- +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_ZERO_EN, ++ RX_AGG_DISABLE); ++ else ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); + + rtl_tally_reset(tp); + +@@ -7206,7 +6978,6 @@ static void r8153_init(struct r8152 *tp) + + static void r8153b_init(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + int i; + +@@ -7245,13 +7016,12 @@ static void r8153b_init(struct r8152 *tp + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_data |= CUR_LINK_OK; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK | POLL_LINK_CHG); + else +- ocp_data &= ~CUR_LINK_OK; +- ocp_data |= POLL_LINK_CHG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, ++ POLL_LINK_CHG); + + if (tp->udev->speed >= USB_SPEED_SUPER) + r8153b_u1u2en(tp, true); +@@ -7261,25 +7031,20 @@ static void r8153b_init(struct r8152 *tp + /* MAC clock speed down */ + r8153_mac_clk_speed_down(tp, true); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + +- if (tp->version == RTL_VER_09) { ++ if (tp->version == RTL_VER_09) + /* Disable Test IO for 32QFN */ +- if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= TEST_IO_OFF; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); +- } +- } ++ if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ++ TEST_IO_OFF); + + set_bit(GREEN_ETHERNET, &tp->flags); + + /* rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); + + rtl_tally_reset(tp); + +@@ -7288,7 +7053,6 @@ static void r8153b_init(struct r8152 *tp + + static void r8153c_init(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + int i; + +@@ -7299,12 +7063,10 @@ static void r8153c_init(struct r8152 *tp + + /* Disable spi_en */ + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); +- ocp_data &= ~BIT(3); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); +- ocp_data |= BIT(1); +- ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); ++ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG5, BIT(3)); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, 0xcbf0, BIT(1)); + + for (i = 0; i < 500; i++) { + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & +@@ -7336,14 +7098,12 @@ static void r8153c_init(struct r8152 *tp + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_data |= CUR_LINK_OK; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK | POLL_LINK_CHG); + else +- ocp_data &= ~CUR_LINK_OK; +- +- ocp_data |= POLL_LINK_CHG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, ++ POLL_LINK_CHG); + + r8153b_u1u2en(tp, true); + +@@ -7352,16 +7112,13 @@ static void r8153c_init(struct r8152 *tp + /* MAC clock speed down */ + r8153_mac_clk_speed_down(tp, true); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); +- ocp_data &= ~BIT(7); +- ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7)); + + set_bit(GREEN_ETHERNET, &tp->flags); + + /* rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); + + rtl_tally_reset(tp); + +@@ -7370,14 +7127,9 @@ static void r8153c_init(struct r8152 *tp + + static void r8156_hw_phy_cfg(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- if (ocp_data & PCUT_STATUS) { +- ocp_data &= ~PCUT_STATUS; +- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); +- } ++ ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + + data = r8153_phy_status(tp, 0); + switch (data) { +@@ -7404,9 +7156,7 @@ static void r8156_hw_phy_cfg(struct r815 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON); + WARN_ON_ONCE(data != PHY_STAT_LAN_ON); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= PFM_PWM_SWITCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + + switch (tp->version) { + case RTL_VER_10: +@@ -7567,9 +7317,8 @@ static void r8156_hw_phy_cfg(struct r815 + /* EEE parameter */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); +- ocp_data |= EN_XG_LIP | EN_G_LIP; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG, ++ EN_XG_LIP | EN_G_LIP); + + sram_write(tp, 0x8257, 0x020f); /* XG PLL */ + sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ +@@ -7578,9 +7327,8 @@ static void r8156_hw_phy_cfg(struct r815 + return; + + /* Advance EEE */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); +- ocp_data |= EEE_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ++ EEE_SPDWN_EN); + + data = ocp_reg_read(tp, OCP_DOWN_SPEED); + data &= ~(EN_EEE_100 | EN_EEE_1000); +@@ -7720,7 +7468,6 @@ static void r8156_hw_phy_cfg(struct r815 + + static void r8156b_hw_phy_cfg(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + + switch (tp->version) { +@@ -7750,11 +7497,7 @@ static void r8156b_hw_phy_cfg(struct r81 + break; + } + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- if (ocp_data & PCUT_STATUS) { +- ocp_data &= ~PCUT_STATUS; +- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); +- } ++ ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + + data = r8153_phy_status(tp, 0); + switch (data) { +@@ -7791,9 +7534,7 @@ static void r8156b_hw_phy_cfg(struct r81 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON); + WARN_ON_ONCE(data != PHY_STAT_LAN_ON); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); +- ocp_data |= PFM_PWM_SWITCH; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + + switch (tp->version) { + case RTL_VER_12: +@@ -7880,9 +7621,9 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xb87c, 0x8fd8); + ocp_reg_write(tp, 0xb87e, 0xf600); + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); +- ocp_data |= EN_XG_LIP | EN_G_LIP; +- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); ++ ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG, ++ EN_XG_LIP | EN_G_LIP); ++ + ocp_reg_write(tp, 0xb87c, 0x813d); + ocp_reg_write(tp, 0xb87e, 0x390e); + ocp_reg_write(tp, 0xb87c, 0x814f); +@@ -8096,9 +7837,7 @@ static void r8156b_hw_phy_cfg(struct r81 + if (rtl_phy_patch_request(tp, true, true)) + return; + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); +- ocp_data |= EEE_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); + + data = ocp_reg_read(tp, OCP_DOWN_SPEED); + data &= ~(EN_EEE_100 | EN_EEE_1000); +@@ -8137,22 +7876,17 @@ static void r8156b_hw_phy_cfg(struct r81 + + static void r8156_init(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); +- ocp_data &= ~EN_ALL_SPEED; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); +- ocp_data |= BYPASS_MAC_RESET; +- ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); + + r8153b_u1u2en(tp, false); + +@@ -8202,28 +7936,23 @@ static void r8156_init(struct r8152 *tp) + + r8156_mac_clk_spd(tp, true); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_data |= CUR_LINK_OK; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK | POLL_LINK_CHG); + else +- ocp_data &= ~CUR_LINK_OK; +- ocp_data |= POLL_LINK_CHG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, ++ POLL_LINK_CHG); + + set_bit(GREEN_ETHERNET, &tp->flags); + + /* rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +- +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); +- ocp_data |= ACT_ODMA; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); ++ ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); +@@ -8233,26 +7962,19 @@ static void r8156_init(struct r8152 *tp) + + static void r8156b_init(struct r8152 *tp) + { +- u32 ocp_data; + u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); +- ocp_data &= ~EN_ALL_SPEED; +- ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); +- ocp_data |= BYPASS_MAC_RESET; +- ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); +- ocp_data |= RX_DETECT8; +- ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); + + r8153b_u1u2en(tp, false); + +@@ -8312,48 +8034,39 @@ static void r8156b_init(struct r8152 *tp + + usb_enable_lpm(tp->udev); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); +- ocp_data &= ~SLOT_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); +- ocp_data |= FLOW_CTRL_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); + + /* enable fc timer and set timer to 600 ms. */ + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, + CTRL_TIMER_EN | (600 / 8)); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); + if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) +- ocp_data |= FLOW_CTRL_PATCH_2; +- ocp_data &= ~AUTO_SPEEDUP; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); +- ocp_data |= FC_PATCH_TASK; +- ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP, ++ FLOW_CTRL_PATCH_2); ++ else ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); ++ ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); + + r8156_mac_clk_spd(tp, true); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); +- ocp_data &= ~PLA_MCU_SPDWN_EN; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ++ PLA_MCU_SPDWN_EN); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_data |= CUR_LINK_OK; ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ++ CUR_LINK_OK | POLL_LINK_CHG); + else +- ocp_data &= ~CUR_LINK_OK; +- ocp_data |= POLL_LINK_CHG; +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); ++ ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, ++ POLL_LINK_CHG); + + set_bit(GREEN_ETHERNET, &tp->flags); + + /* rx aggregation */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); +- ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); +- ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, ++ RX_AGG_DISABLE | RX_ZERO_EN); + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); diff --git a/target/linux/generic/backport-6.18/744-v7.1-r8152-add-helper-functions-for-PHY-OCP-registers.patch b/target/linux/generic/backport-6.18/744-v7.1-r8152-add-helper-functions-for-PHY-OCP-registers.patch new file mode 100644 index 0000000000..d0abdbef22 --- /dev/null +++ b/target/linux/generic/backport-6.18/744-v7.1-r8152-add-helper-functions-for-PHY-OCP-registers.patch @@ -0,0 +1,1127 @@ +From 7db154aa58e18bb663cc317f0b62631f8b3d2b87 Mon Sep 17 00:00:00 2001 +From: Chih Kai Hsu +Date: Thu, 26 Mar 2026 15:39:25 +0800 +Subject: [PATCH] r8152: add helper functions for PHY OCP registers + +Add the following bitwise operation functions for PHY OCP registers to +simplify the code. + +- ocp_reg_w0w1() +- ocp_reg_clr_bits() +- ocp_reg_set_bits() +- sram_write_w0w1() +- sram_clr_bits() +- sram_set_bits() +- r8152_mdio_clr_bit() +- r8152_mdio_set_bit() +- r8152_mdio_test_and_clr_bit() + +In addition, remove variable set but not used from r8153_init(), +r8153b_init() and r8153c_init(). + +Signed-off-by: Chih Kai Hsu +Reviewed-by: Hayes Wang +Link: https://patch.msgid.link/20260326073925.32976-456-nic_swsd@realtek.com +Signed-off-by: Paolo Abeni +--- + drivers/net/usb/r8152.c | 697 +++++++++++++--------------------------- + 1 file changed, 226 insertions(+), 471 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -1732,6 +1732,71 @@ static void ocp_byte_set_bits(struct r81 + ocp_byte_w0w1(tp, type, index, 0, set); + } + ++static void ocp_reg_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set) ++{ ++ u16 data; ++ ++ data = ocp_reg_read(tp, addr); ++ data = (data & ~clear) | set; ++ ocp_reg_write(tp, addr, data); ++} ++ ++static void ocp_reg_clr_bits(struct r8152 *tp, u16 addr, u16 clear) ++{ ++ ocp_reg_w0w1(tp, addr, clear, 0); ++} ++ ++static void ocp_reg_set_bits(struct r8152 *tp, u16 addr, u16 set) ++{ ++ ocp_reg_w0w1(tp, addr, 0, set); ++} ++ ++static void sram_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set) ++{ ++ u16 data; ++ ++ data = sram_read(tp, addr); ++ data = (data & ~clear) | set; ++ ocp_reg_write(tp, OCP_SRAM_DATA, data); ++} ++ ++static void sram_clr_bits(struct r8152 *tp, u16 addr, u16 clear) ++{ ++ sram_write_w0w1(tp, addr, clear, 0); ++} ++ ++static void sram_set_bits(struct r8152 *tp, u16 addr, u16 set) ++{ ++ sram_write_w0w1(tp, addr, 0, set); ++} ++ ++static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear) ++{ ++ int data; ++ ++ data = r8152_mdio_read(tp, addr); ++ r8152_mdio_write(tp, addr, data & ~clear); ++} ++ ++static void r8152_mdio_set_bit(struct r8152 *tp, u16 addr, u16 set) ++{ ++ int data; ++ ++ data = r8152_mdio_read(tp, addr); ++ r8152_mdio_write(tp, addr, data | set); ++} ++ ++static int r8152_mdio_test_and_clr_bit(struct r8152 *tp, u16 addr, u16 clear) ++{ ++ int data; ++ ++ data = r8152_mdio_read(tp, addr); ++ if (data & clear) ++ r8152_mdio_write(tp, addr, data & ~clear); ++ ++ return data & clear; ++} ++ + static int + r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); + +@@ -3746,14 +3811,10 @@ static void r8156_ups_flags(struct r8152 + + static void rtl_green_en(struct r8152 *tp, bool enable) + { +- u16 data; +- +- data = sram_read(tp, SRAM_GREEN_CFG); + if (enable) +- data |= GREEN_ETH_EN; ++ sram_set_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN); + else +- data &= ~GREEN_ETH_EN; +- sram_write(tp, SRAM_GREEN_CFG, data); ++ sram_clr_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN); + + tp->ups_info.green = enable; + } +@@ -4149,18 +4210,16 @@ static inline void rtl_reset_ocp_base(st + + static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) + { +- u16 data, check; ++ u16 check; + int i; + +- data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); + if (request) { +- data |= PATCH_REQUEST; ++ ocp_reg_set_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST); + check = 0; + } else { +- data &= ~PATCH_REQUEST; ++ ocp_reg_clr_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST); + check = PATCH_READY; + } +- ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); + + for (i = 0; wait && i < 5000; i++) { + u32 ocp_data; +@@ -4190,14 +4249,8 @@ static void rtl_patch_key_set(struct r81 + sram_write(tp, key_addr, patch_key); + sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); + } else if (key_addr) { +- u16 data; +- + sram_write(tp, 0x0000, 0x0000); +- +- data = ocp_reg_read(tp, OCP_PHY_LOCK); +- data &= ~PATCH_LOCK; +- ocp_reg_write(tp, OCP_PHY_LOCK, data); +- ++ ocp_reg_clr_bits(tp, OCP_PHY_LOCK, PATCH_LOCK); + sram_write(tp, key_addr, 0x0000); + } else { + WARN_ON_ONCE(1); +@@ -5305,69 +5358,58 @@ static void r8152_mmd_write(struct r8152 + + static void r8152_eee_en(struct r8152 *tp, bool enable) + { +- u16 config1, config2, config3; +- +- config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; +- config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); +- config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; +- + if (enable) { + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); +- config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; +- config1 |= sd_rise_time(1); +- config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; +- config3 |= fast_snr(42); ++ ++ ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask, ++ EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | ++ RX_QUIET_EN | sd_rise_time(1)); ++ ++ ocp_reg_set_bits(tp, OCP_EEE_CONFIG2, ++ RG_DACQUIET_EN | RG_LDVQUIET_EN); ++ ++ ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(42)); + } else { + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); +- config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | +- RX_QUIET_EN); +- config1 |= sd_rise_time(7); +- config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); +- config3 |= fast_snr(511); +- } + +- ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); +- ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); +- ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); ++ ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask | ++ EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | ++ RX_QUIET_EN, sd_rise_time(7)); ++ ++ ocp_reg_clr_bits(tp, OCP_EEE_CONFIG2, ++ RG_DACQUIET_EN | RG_LDVQUIET_EN); ++ ++ ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(511)); ++ } + } + + static void r8153_eee_en(struct r8152 *tp, bool enable) + { +- u16 config; +- +- config = ocp_reg_read(tp, OCP_EEE_CFG); +- + if (enable) { + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); +- config |= EEE10_EN; ++ ++ ocp_reg_set_bits(tp, OCP_EEE_CFG, EEE10_EN); + } else { + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); +- config &= ~EEE10_EN; +- } + +- ocp_reg_write(tp, OCP_EEE_CFG, config); ++ ocp_reg_clr_bits(tp, OCP_EEE_CFG, EEE10_EN); ++ } + + tp->ups_info.eee = enable; + } + + static void r8156_eee_en(struct r8152 *tp, bool enable) + { +- u16 config; +- + r8153_eee_en(tp, enable); + +- config = ocp_reg_read(tp, OCP_EEE_ADV2); +- + if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT)) +- config |= MDIO_EEE_2_5GT; ++ ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); + else +- config &= ~MDIO_EEE_2_5GT; +- +- ocp_reg_write(tp, OCP_EEE_ADV2, config); ++ ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); + } + + static void rtl_eee_enable(struct r8152 *tp, bool enable) +@@ -5420,11 +5462,8 @@ static void rtl_eee_enable(struct r8152 + + static void r8152b_enable_fc(struct r8152 *tp) + { +- u16 anar; +- +- anar = r8152_mdio_read(tp, MII_ADVERTISE); +- anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; +- r8152_mdio_write(tp, MII_ADVERTISE, anar); ++ r8152_mdio_set_bit(tp, MII_ADVERTISE, ++ ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + + tp->ups_info.flow_control = true; + } +@@ -5680,17 +5719,12 @@ static int r8156a_post_firmware_1(struct + + static void r8153_aldps_en(struct r8152 *tp, bool enable) + { +- u16 data; +- +- data = ocp_reg_read(tp, OCP_POWER_CFG); + if (enable) { +- data |= EN_ALDPS; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_ALDPS); + } else { + int i; + +- data &= ~EN_ALDPS; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ ocp_reg_clr_bits(tp, OCP_POWER_CFG, EN_ALDPS); + for (i = 0; i < 20; i++) { + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; +@@ -5705,8 +5739,6 @@ static void r8153_aldps_en(struct r8152 + + static void r8153_hw_phy_cfg(struct r8152 *tp) + { +- u16 data; +- + /* disable ALDPS before updating the PHY parameters */ + r8153_aldps_en(tp, false); + +@@ -5715,22 +5747,14 @@ static void r8153_hw_phy_cfg(struct r815 + + rtl8152_apply_firmware(tp, false); + +- if (tp->version == RTL_VER_03) { +- data = ocp_reg_read(tp, OCP_EEE_CFG); +- data &= ~CTAP_SHORT_EN; +- ocp_reg_write(tp, OCP_EEE_CFG, data); +- } +- +- data = ocp_reg_read(tp, OCP_POWER_CFG); +- data |= EEE_CLKDIV_EN; +- ocp_reg_write(tp, OCP_POWER_CFG, data); +- +- data = ocp_reg_read(tp, OCP_DOWN_SPEED); +- data |= EN_10M_BGOFF; +- ocp_reg_write(tp, OCP_DOWN_SPEED, data); +- data = ocp_reg_read(tp, OCP_POWER_CFG); +- data |= EN_10M_PLLOFF; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ if (tp->version == RTL_VER_03) ++ ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN); ++ ++ ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); ++ ++ ocp_reg_set_bits(tp, OCP_DOWN_SPEED, EN_10M_BGOFF); ++ ++ ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF); + + sram_write(tp, SRAM_IMPEDANCE, 0x0b13); + +@@ -5798,9 +5822,7 @@ static void r8153b_hw_phy_cfg(struct r81 + case PHY_STAT_EXT_INIT: + rtl8152_apply_firmware(tp, true); + +- data = r8152_mdio_read(tp, MII_BMCR); +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); ++ r8152_mdio_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + break; + case PHY_STAT_LAN_ON: + default: +@@ -5810,12 +5832,9 @@ static void r8153b_hw_phy_cfg(struct r81 + + r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + +- data = sram_read(tp, SRAM_GREEN_CFG); +- data |= R_TUNE_EN; +- sram_write(tp, SRAM_GREEN_CFG, data); +- data = ocp_reg_read(tp, OCP_NCTL_CFG); +- data |= PGA_RETURN_EN; +- ocp_reg_write(tp, OCP_NCTL_CFG, data); ++ sram_set_bits(tp, SRAM_GREEN_CFG, R_TUNE_EN); ++ ++ ocp_reg_set_bits(tp, OCP_NCTL_CFG, PGA_RETURN_EN); + + /* ADC Bias Calibration: + * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake +@@ -5845,14 +5864,11 @@ static void r8153b_hw_phy_cfg(struct r81 + + /* Advnace EEE */ + if (!rtl_phy_patch_request(tp, true, true)) { +- data = ocp_reg_read(tp, OCP_POWER_CFG); +- data |= EEE_CLKDIV_EN; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); + tp->ups_info.eee_ckdiv = true; + +- data = ocp_reg_read(tp, OCP_DOWN_SPEED); +- data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; +- ocp_reg_write(tp, OCP_DOWN_SPEED, data); ++ ocp_reg_set_bits(tp, OCP_DOWN_SPEED, ++ EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV); + tp->ups_info.eee_cmod_lv = true; + tp->ups_info._10m_ckdiv = true; + tp->ups_info.eee_plloff_giga = true; +@@ -6818,16 +6834,11 @@ static void rtl_tally_reset(struct r8152 + static void r8152b_init(struct r8152 *tp) + { + u32 ocp_data; +- u16 data; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + r8152_aldps_en(tp, false); + +@@ -6857,7 +6868,6 @@ static void r8152b_init(struct r8152 *tp + static void r8153_init(struct r8152 *tp) + { + u32 ocp_data; +- u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +@@ -6875,19 +6885,15 @@ static void r8153_init(struct r8152 *tp) + break; + } + +- data = r8153_phy_status(tp, 0); ++ r8153_phy_status(tp, 0); + + if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || + tp->version == RTL_VER_05) + ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + +- data = r8153_phy_status(tp, PHY_STAT_LAN_ON); ++ r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8153_u2p3en(tp, false); + +@@ -6978,7 +6984,6 @@ static void r8153_init(struct r8152 *tp) + + static void r8153b_init(struct r8152 *tp) + { +- u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +@@ -6996,15 +7001,11 @@ static void r8153b_init(struct r8152 *tp + break; + } + +- data = r8153_phy_status(tp, 0); ++ r8153_phy_status(tp, 0); + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + +- data = r8153_phy_status(tp, PHY_STAT_LAN_ON); ++ r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8153_u2p3en(tp, false); + +@@ -7053,7 +7054,6 @@ static void r8153b_init(struct r8152 *tp + + static void r8153c_init(struct r8152 *tp) + { +- u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +@@ -7078,15 +7078,11 @@ static void r8153c_init(struct r8152 *tp + return; + } + +- data = r8153_phy_status(tp, 0); ++ r8153_phy_status(tp, 0); + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + +- data = r8153_phy_status(tp, PHY_STAT_LAN_ON); ++ r8153_phy_status(tp, PHY_STAT_LAN_ON); + + r8153_u2p3en(tp, false); + +@@ -7136,9 +7132,7 @@ static void r8156_hw_phy_cfg(struct r815 + case PHY_STAT_EXT_INIT: + rtl8152_apply_firmware(tp, true); + +- data = ocp_reg_read(tp, 0xa468); +- data &= ~(BIT(3) | BIT(1)); +- ocp_reg_write(tp, 0xa468, data); ++ ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + break; + case PHY_STAT_LAN_ON: + case PHY_STAT_PWRDN: +@@ -7160,153 +7154,57 @@ static void r8156_hw_phy_cfg(struct r815 + + switch (tp->version) { + case RTL_VER_10: +- data = ocp_reg_read(tp, 0xad40); +- data &= ~0x3ff; +- data |= BIT(7) | BIT(2); +- ocp_reg_write(tp, 0xad40, data); +- +- data = ocp_reg_read(tp, 0xad4e); +- data |= BIT(4); +- ocp_reg_write(tp, 0xad4e, data); +- data = ocp_reg_read(tp, 0xad16); +- data &= ~0x3ff; +- data |= 0x6; +- ocp_reg_write(tp, 0xad16, data); +- data = ocp_reg_read(tp, 0xad32); +- data &= ~0x3f; +- data |= 6; +- ocp_reg_write(tp, 0xad32, data); +- data = ocp_reg_read(tp, 0xac08); +- data &= ~(BIT(12) | BIT(8)); +- ocp_reg_write(tp, 0xac08, data); +- data = ocp_reg_read(tp, 0xac8a); +- data |= BIT(12) | BIT(13) | BIT(14); +- data &= ~BIT(15); +- ocp_reg_write(tp, 0xac8a, data); +- data = ocp_reg_read(tp, 0xad18); +- data |= BIT(10); +- ocp_reg_write(tp, 0xad18, data); +- data = ocp_reg_read(tp, 0xad1a); +- data |= 0x3ff; +- ocp_reg_write(tp, 0xad1a, data); +- data = ocp_reg_read(tp, 0xad1c); +- data |= 0x3ff; +- ocp_reg_write(tp, 0xad1c, data); +- +- data = sram_read(tp, 0x80ea); +- data &= ~0xff00; +- data |= 0xc400; +- sram_write(tp, 0x80ea, data); +- data = sram_read(tp, 0x80eb); +- data &= ~0x0700; +- data |= 0x0300; +- sram_write(tp, 0x80eb, data); +- data = sram_read(tp, 0x80f8); +- data &= ~0xff00; +- data |= 0x1c00; +- sram_write(tp, 0x80f8, data); +- data = sram_read(tp, 0x80f1); +- data &= ~0xff00; +- data |= 0x3000; +- sram_write(tp, 0x80f1, data); +- +- data = sram_read(tp, 0x80fe); +- data &= ~0xff00; +- data |= 0xa500; +- sram_write(tp, 0x80fe, data); +- data = sram_read(tp, 0x8102); +- data &= ~0xff00; +- data |= 0x5000; +- sram_write(tp, 0x8102, data); +- data = sram_read(tp, 0x8015); +- data &= ~0xff00; +- data |= 0x3300; +- sram_write(tp, 0x8015, data); +- data = sram_read(tp, 0x8100); +- data &= ~0xff00; +- data |= 0x7000; +- sram_write(tp, 0x8100, data); +- data = sram_read(tp, 0x8014); +- data &= ~0xff00; +- data |= 0xf000; +- sram_write(tp, 0x8014, data); +- data = sram_read(tp, 0x8016); +- data &= ~0xff00; +- data |= 0x6500; +- sram_write(tp, 0x8016, data); +- data = sram_read(tp, 0x80dc); +- data &= ~0xff00; +- data |= 0xed00; +- sram_write(tp, 0x80dc, data); +- data = sram_read(tp, 0x80df); +- data |= BIT(8); +- sram_write(tp, 0x80df, data); +- data = sram_read(tp, 0x80e1); +- data &= ~BIT(8); +- sram_write(tp, 0x80e1, data); +- +- data = ocp_reg_read(tp, 0xbf06); +- data &= ~0x003f; +- data |= 0x0038; +- ocp_reg_write(tp, 0xbf06, data); ++ ocp_reg_w0w1(tp, 0xad40, 0x3ff, BIT(7) | BIT(2)); ++ ++ ocp_reg_set_bits(tp, 0xad4e, BIT(4)); ++ ocp_reg_w0w1(tp, 0xad16, 0x3ff, 0x6); ++ ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6); ++ ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8)); ++ ocp_reg_w0w1(tp, 0xac8a, BIT(15), BIT(12) | BIT(13) | BIT(14)); ++ ocp_reg_set_bits(tp, 0xad18, BIT(10)); ++ ocp_reg_set_bits(tp, 0xad1a, 0x3ff); ++ ocp_reg_set_bits(tp, 0xad1c, 0x3ff); ++ ++ sram_write_w0w1(tp, 0x80ea, 0xff00, 0xc400); ++ sram_write_w0w1(tp, 0x80eb, 0x0700, 0x0300); ++ sram_write_w0w1(tp, 0x80f8, 0xff00, 0x1c00); ++ sram_write_w0w1(tp, 0x80f1, 0xff00, 0x3000); ++ ++ sram_write_w0w1(tp, 0x80fe, 0xff00, 0xa500); ++ sram_write_w0w1(tp, 0x8102, 0xff00, 0x5000); ++ sram_write_w0w1(tp, 0x8015, 0xff00, 0x3300); ++ sram_write_w0w1(tp, 0x8100, 0xff00, 0x7000); ++ sram_write_w0w1(tp, 0x8014, 0xff00, 0xf000); ++ sram_write_w0w1(tp, 0x8016, 0xff00, 0x6500); ++ sram_write_w0w1(tp, 0x80dc, 0xff00, 0xed00); ++ sram_set_bits(tp, 0x80df, BIT(8)); ++ sram_clr_bits(tp, 0x80e1, BIT(8)); ++ ++ ocp_reg_w0w1(tp, 0xbf06, 0x003f, 0x0038); + + sram_write(tp, 0x819f, 0xddb6); + + ocp_reg_write(tp, 0xbc34, 0x5555); +- data = ocp_reg_read(tp, 0xbf0a); +- data &= ~0x0e00; +- data |= 0x0a00; +- ocp_reg_write(tp, 0xbf0a, data); +- +- data = ocp_reg_read(tp, 0xbd2c); +- data &= ~BIT(13); +- ocp_reg_write(tp, 0xbd2c, data); ++ ocp_reg_w0w1(tp, 0xbf0a, 0x0e00, 0x0a00); ++ ++ ocp_reg_clr_bits(tp, 0xbd2c, BIT(13)); + break; + case RTL_VER_11: +- data = ocp_reg_read(tp, 0xad16); +- data |= 0x3ff; +- ocp_reg_write(tp, 0xad16, data); +- data = ocp_reg_read(tp, 0xad32); +- data &= ~0x3f; +- data |= 6; +- ocp_reg_write(tp, 0xad32, data); +- data = ocp_reg_read(tp, 0xac08); +- data &= ~(BIT(12) | BIT(8)); +- ocp_reg_write(tp, 0xac08, data); +- data = ocp_reg_read(tp, 0xacc0); +- data &= ~0x3; +- data |= BIT(1); +- ocp_reg_write(tp, 0xacc0, data); +- data = ocp_reg_read(tp, 0xad40); +- data &= ~0xe7; +- data |= BIT(6) | BIT(2); +- ocp_reg_write(tp, 0xad40, data); +- data = ocp_reg_read(tp, 0xac14); +- data &= ~BIT(7); +- ocp_reg_write(tp, 0xac14, data); +- data = ocp_reg_read(tp, 0xac80); +- data &= ~(BIT(8) | BIT(9)); +- ocp_reg_write(tp, 0xac80, data); +- data = ocp_reg_read(tp, 0xac5e); +- data &= ~0x7; +- data |= BIT(1); +- ocp_reg_write(tp, 0xac5e, data); ++ ocp_reg_set_bits(tp, 0xad16, 0x3ff); ++ ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6); ++ ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8)); ++ ocp_reg_w0w1(tp, 0xacc0, 0x3, BIT(1)); ++ ocp_reg_w0w1(tp, 0xad40, 0xe7, BIT(6) | BIT(2)); ++ ocp_reg_clr_bits(tp, 0xac14, BIT(7)); ++ ocp_reg_clr_bits(tp, 0xac80, BIT(8) | BIT(9)); ++ ocp_reg_w0w1(tp, 0xac5e, 0x7, BIT(1)); + ocp_reg_write(tp, 0xad4c, 0x00a8); + ocp_reg_write(tp, 0xac5c, 0x01ff); +- data = ocp_reg_read(tp, 0xac8a); +- data &= ~0xf0; +- data |= BIT(4) | BIT(5); +- ocp_reg_write(tp, 0xac8a, data); ++ ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5)); + ocp_reg_write(tp, 0xb87c, 0x8157); +- data = ocp_reg_read(tp, 0xb87e); +- data &= ~0xff00; +- data |= 0x0500; +- ocp_reg_write(tp, 0xb87e, data); ++ ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500); + ocp_reg_write(tp, 0xb87c, 0x8159); +- data = ocp_reg_read(tp, 0xb87e); +- data &= ~0xff00; +- data |= 0x0700; +- ocp_reg_write(tp, 0xb87e, data); ++ ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700); + + /* AAGC */ + ocp_reg_write(tp, 0xb87c, 0x80a2); +@@ -7330,17 +7228,13 @@ static void r8156_hw_phy_cfg(struct r815 + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + EEE_SPDWN_EN); + +- data = ocp_reg_read(tp, OCP_DOWN_SPEED); +- data &= ~(EN_EEE_100 | EN_EEE_1000); +- data |= EN_10M_CLKDIV; +- ocp_reg_write(tp, OCP_DOWN_SPEED, data); ++ ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, ++ EN_10M_CLKDIV); + tp->ups_info._10m_ckdiv = true; + tp->ups_info.eee_plloff_100 = false; + tp->ups_info.eee_plloff_giga = false; + +- data = ocp_reg_read(tp, OCP_POWER_CFG); +- data &= ~EEE_CLKDIV_EN; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); + tp->ups_info.eee_ckdiv = false; + + ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); +@@ -7350,34 +7244,19 @@ static void r8156_hw_phy_cfg(struct r815 + rtl_phy_patch_request(tp, false, true); + + /* enable ADC Ibias Cal */ +- data = ocp_reg_read(tp, 0xd068); +- data |= BIT(13); +- ocp_reg_write(tp, 0xd068, data); ++ ocp_reg_set_bits(tp, 0xd068, BIT(13)); + + /* enable Thermal Sensor */ +- data = sram_read(tp, 0x81a2); +- data &= ~BIT(8); +- sram_write(tp, 0x81a2, data); +- data = ocp_reg_read(tp, 0xb54c); +- data &= ~0xff00; +- data |= 0xdb00; +- ocp_reg_write(tp, 0xb54c, data); ++ sram_clr_bits(tp, 0x81a2, BIT(8)); ++ ocp_reg_w0w1(tp, 0xb54c, 0xff00, 0xdb00); + + /* Nway 2.5G Lite */ +- data = ocp_reg_read(tp, 0xa454); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa454, data); ++ ocp_reg_clr_bits(tp, 0xa454, BIT(0)); + + /* CS DSP solution */ +- data = ocp_reg_read(tp, OCP_10GBT_CTRL); +- data |= RTL_ADV2_5G_F_R; +- ocp_reg_write(tp, OCP_10GBT_CTRL, data); +- data = ocp_reg_read(tp, 0xad4e); +- data &= ~BIT(4); +- ocp_reg_write(tp, 0xad4e, data); +- data = ocp_reg_read(tp, 0xa86a); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa86a, data); ++ ocp_reg_set_bits(tp, OCP_10GBT_CTRL, RTL_ADV2_5G_F_R); ++ ocp_reg_clr_bits(tp, 0xad4e, BIT(4)); ++ ocp_reg_clr_bits(tp, 0xa86a, BIT(0)); + + /* MDI SWAP */ + if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && +@@ -7438,9 +7317,7 @@ static void r8156_hw_phy_cfg(struct r815 + } + + /* Notify the MAC when the speed is changed to force mode. */ +- data = ocp_reg_read(tp, OCP_INTR_EN); +- data |= INTR_SPEED_FORCE; +- ocp_reg_write(tp, OCP_INTR_EN, data); ++ ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE); + break; + default: + break; +@@ -7448,12 +7325,8 @@ static void r8156_hw_phy_cfg(struct r815 + + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + +- data = ocp_reg_read(tp, 0xa428); +- data &= ~BIT(9); +- ocp_reg_write(tp, 0xa428, data); +- data = ocp_reg_read(tp, 0xa5ea); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa5ea, data); ++ ocp_reg_clr_bits(tp, 0xa428, BIT(9)); ++ ocp_reg_clr_bits(tp, 0xa5ea, BIT(0)); + tp->ups_info.lite_mode = 0; + + if (tp->eee_en) +@@ -7473,21 +7346,12 @@ static void r8156b_hw_phy_cfg(struct r81 + switch (tp->version) { + case RTL_VER_12: + ocp_reg_write(tp, 0xbf86, 0x9000); +- data = ocp_reg_read(tp, 0xc402); +- data |= BIT(10); +- ocp_reg_write(tp, 0xc402, data); +- data &= ~BIT(10); +- ocp_reg_write(tp, 0xc402, data); ++ ocp_reg_set_bits(tp, 0xc402, BIT(10)); ++ ocp_reg_clr_bits(tp, 0xc402, BIT(10)); + ocp_reg_write(tp, 0xbd86, 0x1010); + ocp_reg_write(tp, 0xbd88, 0x1010); +- data = ocp_reg_read(tp, 0xbd4e); +- data &= ~(BIT(10) | BIT(11)); +- data |= BIT(11); +- ocp_reg_write(tp, 0xbd4e, data); +- data = ocp_reg_read(tp, 0xbf46); +- data &= ~0xf00; +- data |= 0x700; +- ocp_reg_write(tp, 0xbf46, data); ++ ocp_reg_w0w1(tp, 0xbd4e, BIT(10) | BIT(11), BIT(11)); ++ ocp_reg_w0w1(tp, 0xbf46, 0xf00, 0x700); + break; + case RTL_VER_13: + case RTL_VER_15: +@@ -7504,13 +7368,8 @@ static void r8156b_hw_phy_cfg(struct r81 + case PHY_STAT_EXT_INIT: + rtl8152_apply_firmware(tp, true); + +- data = ocp_reg_read(tp, 0xa466); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa466, data); +- +- data = ocp_reg_read(tp, 0xa468); +- data &= ~(BIT(3) | BIT(1)); +- ocp_reg_write(tp, 0xa468, data); ++ ocp_reg_clr_bits(tp, 0xa466, BIT(0)); ++ ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + break; + case PHY_STAT_LAN_ON: + case PHY_STAT_PWRDN: +@@ -7519,11 +7378,7 @@ static void r8156b_hw_phy_cfg(struct r81 + break; + } + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + /* disable ALDPS before updating the PHY parameters */ + r8153_aldps_en(tp, false); +@@ -7538,21 +7393,12 @@ static void r8156b_hw_phy_cfg(struct r81 + + switch (tp->version) { + case RTL_VER_12: +- data = ocp_reg_read(tp, 0xbc08); +- data |= BIT(3) | BIT(2); +- ocp_reg_write(tp, 0xbc08, data); +- +- data = sram_read(tp, 0x8fff); +- data &= ~0xff00; +- data |= 0x0400; +- sram_write(tp, 0x8fff, data); +- +- data = ocp_reg_read(tp, 0xacda); +- data |= 0xff00; +- ocp_reg_write(tp, 0xacda, data); +- data = ocp_reg_read(tp, 0xacde); +- data |= 0xf000; +- ocp_reg_write(tp, 0xacde, data); ++ ocp_reg_set_bits(tp, 0xbc08, BIT(3) | BIT(2)); ++ ++ sram_write_w0w1(tp, 0x8fff, 0xff00, 0x0400); ++ ++ ocp_reg_set_bits(tp, 0xacda, 0xff00); ++ ocp_reg_set_bits(tp, 0xacde, 0xf000); + ocp_reg_write(tp, 0xac8c, 0x0ffc); + ocp_reg_write(tp, 0xac46, 0xb7b4); + ocp_reg_write(tp, 0xac50, 0x0fbc); +@@ -7630,21 +7476,15 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xb87e, 0x790e); + ocp_reg_write(tp, 0xb87c, 0x80b0); + ocp_reg_write(tp, 0xb87e, 0x0f31); +- data = ocp_reg_read(tp, 0xbf4c); +- data |= BIT(1); +- ocp_reg_write(tp, 0xbf4c, data); +- data = ocp_reg_read(tp, 0xbcca); +- data |= BIT(9) | BIT(8); +- ocp_reg_write(tp, 0xbcca, data); ++ ocp_reg_set_bits(tp, 0xbf4c, BIT(1)); ++ ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8)); + ocp_reg_write(tp, 0xb87c, 0x8141); + ocp_reg_write(tp, 0xb87e, 0x320e); + ocp_reg_write(tp, 0xb87c, 0x8153); + ocp_reg_write(tp, 0xb87e, 0x720e); + ocp_reg_write(tp, 0xb87c, 0x8529); + ocp_reg_write(tp, 0xb87e, 0x050e); +- data = ocp_reg_read(tp, OCP_EEE_CFG); +- data &= ~CTAP_SHORT_EN; +- ocp_reg_write(tp, OCP_EEE_CFG, data); ++ ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN); + + sram_write(tp, 0x816c, 0xc4a0); + sram_write(tp, 0x8170, 0xc4a0); +@@ -7677,64 +7517,33 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xb87c, 0x817b); + ocp_reg_write(tp, 0xb87e, 0x1d0a); + +- data = sram_read(tp, 0x8217); +- data &= ~0xff00; +- data |= 0x5000; +- sram_write(tp, 0x8217, data); +- data = sram_read(tp, 0x821a); +- data &= ~0xff00; +- data |= 0x5000; +- sram_write(tp, 0x821a, data); ++ sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000); ++ sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000); + sram_write(tp, 0x80da, 0x0403); +- data = sram_read(tp, 0x80dc); +- data &= ~0xff00; +- data |= 0x1000; +- sram_write(tp, 0x80dc, data); ++ sram_write_w0w1(tp, 0x80dc, 0xff00, 0x1000); + sram_write(tp, 0x80b3, 0x0384); + sram_write(tp, 0x80b7, 0x2007); +- data = sram_read(tp, 0x80ba); +- data &= ~0xff00; +- data |= 0x6c00; +- sram_write(tp, 0x80ba, data); ++ sram_write_w0w1(tp, 0x80ba, 0xff00, 0x6c00); + sram_write(tp, 0x80b5, 0xf009); +- data = sram_read(tp, 0x80bd); +- data &= ~0xff00; +- data |= 0x9f00; +- sram_write(tp, 0x80bd, data); ++ sram_write_w0w1(tp, 0x80bd, 0xff00, 0x9f00); + sram_write(tp, 0x80c7, 0xf083); + sram_write(tp, 0x80dd, 0x03f0); +- data = sram_read(tp, 0x80df); +- data &= ~0xff00; +- data |= 0x1000; +- sram_write(tp, 0x80df, data); ++ sram_write_w0w1(tp, 0x80df, 0xff00, 0x1000); + sram_write(tp, 0x80cb, 0x2007); +- data = sram_read(tp, 0x80ce); +- data &= ~0xff00; +- data |= 0x6c00; +- sram_write(tp, 0x80ce, data); ++ sram_write_w0w1(tp, 0x80ce, 0xff00, 0x6c00); + sram_write(tp, 0x80c9, 0x8009); +- data = sram_read(tp, 0x80d1); +- data &= ~0xff00; +- data |= 0x8000; +- sram_write(tp, 0x80d1, data); ++ sram_write_w0w1(tp, 0x80d1, 0xff00, 0x8000); + sram_write(tp, 0x80a3, 0x200a); + sram_write(tp, 0x80a5, 0xf0ad); + sram_write(tp, 0x809f, 0x6073); + sram_write(tp, 0x80a1, 0x000b); +- data = sram_read(tp, 0x80a9); +- data &= ~0xff00; +- data |= 0xc000; +- sram_write(tp, 0x80a9, data); ++ sram_write_w0w1(tp, 0x80a9, 0xff00, 0xc000); + + if (rtl_phy_patch_request(tp, true, true)) + return; + +- data = ocp_reg_read(tp, 0xb896); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xb896, data); +- data = ocp_reg_read(tp, 0xb892); +- data &= ~0xff00; +- ocp_reg_write(tp, 0xb892, data); ++ ocp_reg_clr_bits(tp, 0xb896, BIT(0)); ++ ocp_reg_clr_bits(tp, 0xb892, 0xff00); + ocp_reg_write(tp, 0xb88e, 0xc23e); + ocp_reg_write(tp, 0xb890, 0x0000); + ocp_reg_write(tp, 0xb88e, 0xc240); +@@ -7749,41 +7558,25 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xb890, 0x1012); + ocp_reg_write(tp, 0xb88e, 0xc24a); + ocp_reg_write(tp, 0xb890, 0x1416); +- data = ocp_reg_read(tp, 0xb896); +- data |= BIT(0); +- ocp_reg_write(tp, 0xb896, data); ++ ocp_reg_set_bits(tp, 0xb896, BIT(0)); + + rtl_phy_patch_request(tp, false, true); + +- data = ocp_reg_read(tp, 0xa86a); +- data |= BIT(0); +- ocp_reg_write(tp, 0xa86a, data); +- data = ocp_reg_read(tp, 0xa6f0); +- data |= BIT(0); +- ocp_reg_write(tp, 0xa6f0, data); ++ ocp_reg_set_bits(tp, 0xa86a, BIT(0)); ++ ocp_reg_set_bits(tp, 0xa6f0, BIT(0)); + + ocp_reg_write(tp, 0xbfa0, 0xd70d); + ocp_reg_write(tp, 0xbfa2, 0x4100); + ocp_reg_write(tp, 0xbfa4, 0xe868); + ocp_reg_write(tp, 0xbfa6, 0xdc59); + ocp_reg_write(tp, 0xb54c, 0x3c18); +- data = ocp_reg_read(tp, 0xbfa4); +- data &= ~BIT(5); +- ocp_reg_write(tp, 0xbfa4, data); +- data = sram_read(tp, 0x817d); +- data |= BIT(12); +- sram_write(tp, 0x817d, data); ++ ocp_reg_clr_bits(tp, 0xbfa4, BIT(5)); ++ sram_set_bits(tp, 0x817d, BIT(12)); + break; + case RTL_VER_13: + /* 2.5G INRX */ +- data = ocp_reg_read(tp, 0xac46); +- data &= ~0x00f0; +- data |= 0x0090; +- ocp_reg_write(tp, 0xac46, data); +- data = ocp_reg_read(tp, 0xad30); +- data &= ~0x0003; +- data |= 0x0001; +- ocp_reg_write(tp, 0xad30, data); ++ ocp_reg_w0w1(tp, 0xac46, 0x00f0, 0x0090); ++ ocp_reg_w0w1(tp, 0xad30, 0x0003, 0x0001); + fallthrough; + case RTL_VER_15: + /* EEE parameter */ +@@ -7792,20 +7585,11 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xb87c, 0x8107); + ocp_reg_write(tp, 0xb87e, 0x360e); + ocp_reg_write(tp, 0xb87c, 0x8551); +- data = ocp_reg_read(tp, 0xb87e); +- data &= ~0xff00; +- data |= 0x0800; +- ocp_reg_write(tp, 0xb87e, data); ++ ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800); + + /* ADC_PGA parameter */ +- data = ocp_reg_read(tp, 0xbf00); +- data &= ~0xe000; +- data |= 0xa000; +- ocp_reg_write(tp, 0xbf00, data); +- data = ocp_reg_read(tp, 0xbf46); +- data &= ~0x0f00; +- data |= 0x0300; +- ocp_reg_write(tp, 0xbf46, data); ++ ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000); ++ ocp_reg_w0w1(tp, 0xbf46, 0x0f00, 0x0300); + + /* Green Table-PGA, 1G full viterbi */ + sram_write(tp, 0x8044, 0x2417); +@@ -7820,48 +7604,35 @@ static void r8156b_hw_phy_cfg(struct r81 + sram_write(tp, 0x807a, 0x2417); + + /* XG PLL */ +- data = ocp_reg_read(tp, 0xbf84); +- data &= ~0xe000; +- data |= 0xa000; +- ocp_reg_write(tp, 0xbf84, data); ++ ocp_reg_w0w1(tp, 0xbf84, 0xe000, 0xa000); + break; + default: + break; + } + + /* Notify the MAC when the speed is changed to force mode. */ +- data = ocp_reg_read(tp, OCP_INTR_EN); +- data |= INTR_SPEED_FORCE; +- ocp_reg_write(tp, OCP_INTR_EN, data); ++ ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE); + + if (rtl_phy_patch_request(tp, true, true)) + return; + + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); + +- data = ocp_reg_read(tp, OCP_DOWN_SPEED); +- data &= ~(EN_EEE_100 | EN_EEE_1000); +- data |= EN_10M_CLKDIV; +- ocp_reg_write(tp, OCP_DOWN_SPEED, data); ++ ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, ++ EN_10M_CLKDIV); + tp->ups_info._10m_ckdiv = true; + tp->ups_info.eee_plloff_100 = false; + tp->ups_info.eee_plloff_giga = false; + +- data = ocp_reg_read(tp, OCP_POWER_CFG); +- data &= ~EEE_CLKDIV_EN; +- ocp_reg_write(tp, OCP_POWER_CFG, data); ++ ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); + tp->ups_info.eee_ckdiv = false; + + rtl_phy_patch_request(tp, false, true); + + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + +- data = ocp_reg_read(tp, 0xa428); +- data &= ~BIT(9); +- ocp_reg_write(tp, 0xa428, data); +- data = ocp_reg_read(tp, 0xa5ea); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa5ea, data); ++ ocp_reg_clr_bits(tp, 0xa428, BIT(9)); ++ ocp_reg_clr_bits(tp, 0xa5ea, BIT(0)); + tp->ups_info.lite_mode = 0; + + if (tp->eee_en) +@@ -7901,17 +7672,10 @@ static void r8156_init(struct r8152 *tp) + } + + data = r8153_phy_status(tp, 0); +- if (data == PHY_STAT_EXT_INIT) { +- data = ocp_reg_read(tp, 0xa468); +- data &= ~(BIT(3) | BIT(1)); +- ocp_reg_write(tp, 0xa468, data); +- } ++ if (data == PHY_STAT_EXT_INIT) ++ ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + data = r8153_phy_status(tp, PHY_STAT_LAN_ON); + WARN_ON_ONCE(data != PHY_STAT_LAN_ON); +@@ -7999,20 +7763,11 @@ static void r8156b_init(struct r8152 *tp + + data = r8153_phy_status(tp, 0); + if (data == PHY_STAT_EXT_INIT) { +- data = ocp_reg_read(tp, 0xa468); +- data &= ~(BIT(3) | BIT(1)); +- ocp_reg_write(tp, 0xa468, data); +- +- data = ocp_reg_read(tp, 0xa466); +- data &= ~BIT(0); +- ocp_reg_write(tp, 0xa466, data); ++ ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); ++ ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + } + +- data = r8152_mdio_read(tp, MII_BMCR); +- if (data & BMCR_PDOWN) { +- data &= ~BMCR_PDOWN; +- r8152_mdio_write(tp, MII_BMCR, data); +- } ++ r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); + + data = r8153_phy_status(tp, PHY_STAT_LAN_ON); + diff --git a/target/linux/generic/backport-6.18/745-v7.1-r8152-Add-helper-functions-for-SRAM2.patch b/target/linux/generic/backport-6.18/745-v7.1-r8152-Add-helper-functions-for-SRAM2.patch new file mode 100644 index 0000000000..c9d2b1c82d --- /dev/null +++ b/target/linux/generic/backport-6.18/745-v7.1-r8152-Add-helper-functions-for-SRAM2.patch @@ -0,0 +1,252 @@ +From 86f5dd4e0ff282a0acf1f058e947fd5f4ba58a9d Mon Sep 17 00:00:00 2001 +From: Chih Kai Hsu +Date: Wed, 1 Apr 2026 19:55:41 +0800 +Subject: [PATCH] r8152: Add helper functions for SRAM2 + +Add the following helper functions for SRAM2 access to simplify the code +and improve readability: + +- sram2_write() - write data to SRAM2 address +- sram2_read() - read data from SRAM2 address +- sram2_write_w0w1() - read-modify-write operation + +Signed-off-by: Chih Kai Hsu +Reviewed-by: Hayes Wang +Link: https://patch.msgid.link/20260401115542.34601-1-nic_swsd@realtek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/usb/r8152.c | 178 +++++++++++++++++----------------------- + 1 file changed, 75 insertions(+), 103 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -219,6 +219,8 @@ + #define OCP_PHY_PATCH_STAT 0xb800 + #define OCP_PHY_PATCH_CMD 0xb820 + #define OCP_PHY_LOCK 0xb82e ++#define OCP_SRAM2_ADDR 0xb87c ++#define OCP_SRAM2_DATA 0xb87e + #define OCP_ADC_IOFFSET 0xbcfc + #define OCP_ADC_CFG 0xbc06 + #define OCP_SYSCLK_CFG 0xc416 +@@ -1770,6 +1772,27 @@ static void sram_set_bits(struct r8152 * + sram_write_w0w1(tp, addr, 0, set); + } + ++static void sram2_write(struct r8152 *tp, u16 addr, u16 data) ++{ ++ ocp_reg_write(tp, OCP_SRAM2_ADDR, addr); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, data); ++} ++ ++static u16 sram2_read(struct r8152 *tp, u16 addr) ++{ ++ ocp_reg_write(tp, OCP_SRAM2_ADDR, addr); ++ return ocp_reg_read(tp, OCP_SRAM2_DATA); ++} ++ ++static void sram2_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set) ++{ ++ u16 data; ++ ++ data = sram2_read(tp, addr); ++ data = (data & ~clear) | set; ++ ocp_reg_write(tp, OCP_SRAM2_DATA, data); ++} ++ + static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear) + { + int data; +@@ -7201,16 +7224,12 @@ static void r8156_hw_phy_cfg(struct r815 + ocp_reg_write(tp, 0xad4c, 0x00a8); + ocp_reg_write(tp, 0xac5c, 0x01ff); + ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5)); +- ocp_reg_write(tp, 0xb87c, 0x8157); +- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500); +- ocp_reg_write(tp, 0xb87c, 0x8159); +- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700); ++ sram2_write_w0w1(tp, 0x8157, 0xff00, 0x0500); ++ sram2_write_w0w1(tp, 0x8159, 0xff00, 0x0700); + + /* AAGC */ +- ocp_reg_write(tp, 0xb87c, 0x80a2); +- ocp_reg_write(tp, 0xb87e, 0x0153); +- ocp_reg_write(tp, 0xb87c, 0x809c); +- ocp_reg_write(tp, 0xb87e, 0x0153); ++ sram2_write(tp, 0x80a2, 0x0153); ++ sram2_write(tp, 0x809c, 0x0153); + + /* EEE parameter */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); +@@ -7408,82 +7427,48 @@ static void r8156b_hw_phy_cfg(struct r81 + ocp_reg_write(tp, 0xacc8, 0xa0d3); + ocp_reg_write(tp, 0xad08, 0x0007); + +- ocp_reg_write(tp, 0xb87c, 0x8560); +- ocp_reg_write(tp, 0xb87e, 0x19cc); +- ocp_reg_write(tp, 0xb87c, 0x8562); +- ocp_reg_write(tp, 0xb87e, 0x19cc); +- ocp_reg_write(tp, 0xb87c, 0x8564); +- ocp_reg_write(tp, 0xb87e, 0x19cc); +- ocp_reg_write(tp, 0xb87c, 0x8566); +- ocp_reg_write(tp, 0xb87e, 0x147d); +- ocp_reg_write(tp, 0xb87c, 0x8568); +- ocp_reg_write(tp, 0xb87e, 0x147d); +- ocp_reg_write(tp, 0xb87c, 0x856a); +- ocp_reg_write(tp, 0xb87e, 0x147d); +- ocp_reg_write(tp, 0xb87c, 0x8ffe); +- ocp_reg_write(tp, 0xb87e, 0x0907); +- ocp_reg_write(tp, 0xb87c, 0x80d6); +- ocp_reg_write(tp, 0xb87e, 0x2801); +- ocp_reg_write(tp, 0xb87c, 0x80f2); +- ocp_reg_write(tp, 0xb87e, 0x2801); +- ocp_reg_write(tp, 0xb87c, 0x80f4); +- ocp_reg_write(tp, 0xb87e, 0x6077); ++ sram2_write(tp, 0x8560, 0x19cc); ++ sram2_write(tp, 0x8562, 0x19cc); ++ sram2_write(tp, 0x8564, 0x19cc); ++ sram2_write(tp, 0x8566, 0x147d); ++ sram2_write(tp, 0x8568, 0x147d); ++ sram2_write(tp, 0x856a, 0x147d); ++ sram2_write(tp, 0x8ffe, 0x0907); ++ sram2_write(tp, 0x80d6, 0x2801); ++ sram2_write(tp, 0x80f2, 0x2801); ++ sram2_write(tp, 0x80f4, 0x6077); + ocp_reg_write(tp, 0xb506, 0x01e7); + +- ocp_reg_write(tp, 0xb87c, 0x8013); +- ocp_reg_write(tp, 0xb87e, 0x0700); +- ocp_reg_write(tp, 0xb87c, 0x8fb9); +- ocp_reg_write(tp, 0xb87e, 0x2801); +- ocp_reg_write(tp, 0xb87c, 0x8fba); +- ocp_reg_write(tp, 0xb87e, 0x0100); +- ocp_reg_write(tp, 0xb87c, 0x8fbc); +- ocp_reg_write(tp, 0xb87e, 0x1900); +- ocp_reg_write(tp, 0xb87c, 0x8fbe); +- ocp_reg_write(tp, 0xb87e, 0xe100); +- ocp_reg_write(tp, 0xb87c, 0x8fc0); +- ocp_reg_write(tp, 0xb87e, 0x0800); +- ocp_reg_write(tp, 0xb87c, 0x8fc2); +- ocp_reg_write(tp, 0xb87e, 0xe500); +- ocp_reg_write(tp, 0xb87c, 0x8fc4); +- ocp_reg_write(tp, 0xb87e, 0x0f00); +- ocp_reg_write(tp, 0xb87c, 0x8fc6); +- ocp_reg_write(tp, 0xb87e, 0xf100); +- ocp_reg_write(tp, 0xb87c, 0x8fc8); +- ocp_reg_write(tp, 0xb87e, 0x0400); +- ocp_reg_write(tp, 0xb87c, 0x8fca); +- ocp_reg_write(tp, 0xb87e, 0xf300); +- ocp_reg_write(tp, 0xb87c, 0x8fcc); +- ocp_reg_write(tp, 0xb87e, 0xfd00); +- ocp_reg_write(tp, 0xb87c, 0x8fce); +- ocp_reg_write(tp, 0xb87e, 0xff00); +- ocp_reg_write(tp, 0xb87c, 0x8fd0); +- ocp_reg_write(tp, 0xb87e, 0xfb00); +- ocp_reg_write(tp, 0xb87c, 0x8fd2); +- ocp_reg_write(tp, 0xb87e, 0x0100); +- ocp_reg_write(tp, 0xb87c, 0x8fd4); +- ocp_reg_write(tp, 0xb87e, 0xf400); +- ocp_reg_write(tp, 0xb87c, 0x8fd6); +- ocp_reg_write(tp, 0xb87e, 0xff00); +- ocp_reg_write(tp, 0xb87c, 0x8fd8); +- ocp_reg_write(tp, 0xb87e, 0xf600); ++ sram2_write(tp, 0x8013, 0x0700); ++ sram2_write(tp, 0x8fb9, 0x2801); ++ sram2_write(tp, 0x8fba, 0x0100); ++ sram2_write(tp, 0x8fbc, 0x1900); ++ sram2_write(tp, 0x8fbe, 0xe100); ++ sram2_write(tp, 0x8fc0, 0x0800); ++ sram2_write(tp, 0x8fc2, 0xe500); ++ sram2_write(tp, 0x8fc4, 0x0f00); ++ sram2_write(tp, 0x8fc6, 0xf100); ++ sram2_write(tp, 0x8fc8, 0x0400); ++ sram2_write(tp, 0x8fca, 0xf300); ++ sram2_write(tp, 0x8fcc, 0xfd00); ++ sram2_write(tp, 0x8fce, 0xff00); ++ sram2_write(tp, 0x8fd0, 0xfb00); ++ sram2_write(tp, 0x8fd2, 0x0100); ++ sram2_write(tp, 0x8fd4, 0xf400); ++ sram2_write(tp, 0x8fd6, 0xff00); ++ sram2_write(tp, 0x8fd8, 0xf600); + + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG, + EN_XG_LIP | EN_G_LIP); + +- ocp_reg_write(tp, 0xb87c, 0x813d); +- ocp_reg_write(tp, 0xb87e, 0x390e); +- ocp_reg_write(tp, 0xb87c, 0x814f); +- ocp_reg_write(tp, 0xb87e, 0x790e); +- ocp_reg_write(tp, 0xb87c, 0x80b0); +- ocp_reg_write(tp, 0xb87e, 0x0f31); ++ sram2_write(tp, 0x813d, 0x390e); ++ sram2_write(tp, 0x814f, 0x790e); ++ sram2_write(tp, 0x80b0, 0x0f31); + ocp_reg_set_bits(tp, 0xbf4c, BIT(1)); + ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8)); +- ocp_reg_write(tp, 0xb87c, 0x8141); +- ocp_reg_write(tp, 0xb87e, 0x320e); +- ocp_reg_write(tp, 0xb87c, 0x8153); +- ocp_reg_write(tp, 0xb87e, 0x720e); +- ocp_reg_write(tp, 0xb87c, 0x8529); +- ocp_reg_write(tp, 0xb87e, 0x050e); ++ sram2_write(tp, 0x8141, 0x320e); ++ sram2_write(tp, 0x8153, 0x720e); ++ sram2_write(tp, 0x8529, 0x050e); + ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN); + + sram_write(tp, 0x816c, 0xc4a0); +@@ -7495,27 +7480,17 @@ static void r8156b_hw_phy_cfg(struct r81 + sram_write(tp, 0x8ff1, 0x0404); + + ocp_reg_write(tp, 0xbf4a, 0x001b); +- ocp_reg_write(tp, 0xb87c, 0x8033); +- ocp_reg_write(tp, 0xb87e, 0x7c13); +- ocp_reg_write(tp, 0xb87c, 0x8037); +- ocp_reg_write(tp, 0xb87e, 0x7c13); +- ocp_reg_write(tp, 0xb87c, 0x803b); +- ocp_reg_write(tp, 0xb87e, 0xfc32); +- ocp_reg_write(tp, 0xb87c, 0x803f); +- ocp_reg_write(tp, 0xb87e, 0x7c13); +- ocp_reg_write(tp, 0xb87c, 0x8043); +- ocp_reg_write(tp, 0xb87e, 0x7c13); +- ocp_reg_write(tp, 0xb87c, 0x8047); +- ocp_reg_write(tp, 0xb87e, 0x7c13); +- +- ocp_reg_write(tp, 0xb87c, 0x8145); +- ocp_reg_write(tp, 0xb87e, 0x370e); +- ocp_reg_write(tp, 0xb87c, 0x8157); +- ocp_reg_write(tp, 0xb87e, 0x770e); +- ocp_reg_write(tp, 0xb87c, 0x8169); +- ocp_reg_write(tp, 0xb87e, 0x0d0a); +- ocp_reg_write(tp, 0xb87c, 0x817b); +- ocp_reg_write(tp, 0xb87e, 0x1d0a); ++ sram2_write(tp, 0x8033, 0x7c13); ++ sram2_write(tp, 0x8037, 0x7c13); ++ sram2_write(tp, 0x803b, 0xfc32); ++ sram2_write(tp, 0x803f, 0x7c13); ++ sram2_write(tp, 0x8043, 0x7c13); ++ sram2_write(tp, 0x8047, 0x7c13); ++ ++ sram2_write(tp, 0x8145, 0x370e); ++ sram2_write(tp, 0x8157, 0x770e); ++ sram2_write(tp, 0x8169, 0x0d0a); ++ sram2_write(tp, 0x817b, 0x1d0a); + + sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000); + sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000); +@@ -7580,12 +7555,9 @@ static void r8156b_hw_phy_cfg(struct r81 + fallthrough; + case RTL_VER_15: + /* EEE parameter */ +- ocp_reg_write(tp, 0xb87c, 0x80f5); +- ocp_reg_write(tp, 0xb87e, 0x760e); +- ocp_reg_write(tp, 0xb87c, 0x8107); +- ocp_reg_write(tp, 0xb87e, 0x360e); +- ocp_reg_write(tp, 0xb87c, 0x8551); +- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800); ++ sram2_write(tp, 0x80f5, 0x760e); ++ sram2_write(tp, 0x8107, 0x360e); ++ sram2_write_w0w1(tp, 0x8551, 0xff00, 0x0800); + + /* ADC_PGA parameter */ + ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000); diff --git a/target/linux/generic/backport-6.18/746-v7.1-r8152-Add-support-for-5Gbit-Link-Speeds-and-EEE.patch b/target/linux/generic/backport-6.18/746-v7.1-r8152-Add-support-for-5Gbit-Link-Speeds-and-EEE.patch new file mode 100644 index 0000000000..49bac39bcf --- /dev/null +++ b/target/linux/generic/backport-6.18/746-v7.1-r8152-Add-support-for-5Gbit-Link-Speeds-and-EEE.patch @@ -0,0 +1,235 @@ +From ebe5fd2ed20af5ae176dd41dd4a85a3cdc738b8a Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Sat, 4 Apr 2026 09:57:42 +0200 +Subject: [PATCH] r8152: Add support for 5Gbit Link Speeds and EEE + +The RTL8157 supports 5GBit Link speeds. Add support for this speed +in the setup and setting/getting through ethtool. Also add 5GBit EEE. +Add functionality for setup and ethtool get/set methods. + +Signed-off-by: Birger Koblitz +Link: https://patch.msgid.link/20260404-rtl8157_next-v7-1-039121318f23@birger-koblitz.de +Signed-off-by: Paolo Abeni +--- + drivers/net/usb/r8152.c | 100 ++++++++++++++++++++++++++++++++-------- + 1 file changed, 82 insertions(+), 18 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -612,6 +612,7 @@ enum spd_duplex { + FORCE_100M_FULL, + FORCE_1000M_FULL, + NWAY_2500M_FULL, ++ NWAY_5000M_FULL, + }; + + /* OCP_ALDPS_CONFIG */ +@@ -733,6 +734,7 @@ enum spd_duplex { + #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ + + enum rtl_register_content { ++ _5000bps = BIT(12), + _2500bps = BIT(10), + _1250bps = BIT(9), + _500bps = BIT(8), +@@ -746,6 +748,7 @@ enum rtl_register_content { + }; + + #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) ++#define is_speed_5000(_speed) (((_speed) & (_5000bps | LINK_STATUS)) == (_5000bps | LINK_STATUS)) + #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) + + #define RTL8152_MAX_TX 4 +@@ -952,6 +955,7 @@ struct r8152 { + unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; + + u32 support_2500full:1; ++ u32 support_5000full:1; + u32 lenovo_macpassthru:1; + u32 dell_tb_rx_agg_bug:1; + u16 ocp_base; +@@ -1202,6 +1206,7 @@ enum tx_csum_stat { + #define RTL_ADVERTISED_1000_HALF BIT(4) + #define RTL_ADVERTISED_1000_FULL BIT(5) + #define RTL_ADVERTISED_2500_FULL BIT(6) ++#define RTL_ADVERTISED_5000_FULL BIT(7) + + /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). + * The RTL chips use a 64 element hash table based on the Ethernet CRC. +@@ -5427,12 +5432,23 @@ static void r8153_eee_en(struct r8152 *t + + static void r8156_eee_en(struct r8152 *tp, bool enable) + { ++ u16 config; ++ + r8153_eee_en(tp, enable); + ++ config = ocp_reg_read(tp, OCP_EEE_ADV2); ++ + if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT)) +- ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); ++ config |= MDIO_EEE_2_5GT; + else +- ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); ++ config &= ~MDIO_EEE_2_5GT; ++ ++ if (enable && (tp->eee_adv2 & MDIO_EEE_5GT)) ++ config |= MDIO_EEE_5GT; ++ else ++ config &= ~MDIO_EEE_5GT; ++ ++ ocp_reg_write(tp, OCP_EEE_ADV2, config); + } + + static void rtl_eee_enable(struct r8152 *tp, bool enable) +@@ -6196,9 +6212,13 @@ static int rtl8152_set_speed(struct r815 + + if (tp->support_2500full) + support |= RTL_ADVERTISED_2500_FULL; ++ ++ if (tp->support_5000full) ++ support |= RTL_ADVERTISED_5000_FULL; + } + +- if (!(advertising & support)) ++ advertising &= support; ++ if (!advertising) + return -EINVAL; + + orig = r8152_mdio_read(tp, MII_ADVERTISE); +@@ -6241,15 +6261,20 @@ static int rtl8152_set_speed(struct r815 + r8152_mdio_write(tp, MII_CTRL1000, new1); + } + +- if (tp->support_2500full) { ++ if (tp->support_2500full || tp->support_5000full) { + orig = ocp_reg_read(tp, OCP_10GBT_CTRL); +- new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; ++ new1 = orig & ~(MDIO_AN_10GBT_CTRL_ADV2_5G | MDIO_AN_10GBT_CTRL_ADV5G); + + if (advertising & RTL_ADVERTISED_2500_FULL) { + new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; + tp->ups_info.speed_duplex = NWAY_2500M_FULL; + } + ++ if (advertising & RTL_ADVERTISED_5000_FULL) { ++ new1 |= MDIO_AN_10GBT_CTRL_ADV5G; ++ tp->ups_info.speed_duplex = NWAY_5000M_FULL; ++ } ++ + if (orig != new1) + ocp_reg_write(tp, OCP_10GBT_CTRL, new1); + } +@@ -8227,17 +8252,38 @@ int rtl8152_get_link_ksettings(struct ne + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.supported, tp->support_2500full); + +- if (tp->support_2500full) { +- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, +- cmd->link_modes.advertising, +- ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); +- +- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, +- cmd->link_modes.lp_advertising, +- ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, ++ cmd->link_modes.supported, tp->support_5000full); ++ ++ if (tp->support_2500full || tp->support_5000full) { ++ u16 ocp_10gbt_ctrl = ocp_reg_read(tp, OCP_10GBT_CTRL); ++ u16 ocp_10gbt_stat = ocp_reg_read(tp, OCP_10GBT_STAT); ++ ++ if (tp->support_2500full) { ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, ++ cmd->link_modes.advertising, ++ ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV2_5G); ++ ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, ++ cmd->link_modes.lp_advertising, ++ ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP2_5G); ++ ++ if (is_speed_2500(rtl8152_get_speed(tp))) ++ cmd->base.speed = SPEED_2500; ++ } ++ ++ if (tp->support_5000full) { ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, ++ cmd->link_modes.advertising, ++ ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV5G); + +- if (is_speed_2500(rtl8152_get_speed(tp))) +- cmd->base.speed = SPEED_2500; ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, ++ cmd->link_modes.lp_advertising, ++ ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP5G); ++ ++ if (is_speed_5000(rtl8152_get_speed(tp))) ++ cmd->base.speed = SPEED_5000; ++ } + } + + mutex_unlock(&tp->control); +@@ -8287,6 +8333,10 @@ static int rtl8152_set_link_ksettings(st + cmd->link_modes.advertising)) + advertising |= RTL_ADVERTISED_2500_FULL; + ++ if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, ++ cmd->link_modes.advertising)) ++ advertising |= RTL_ADVERTISED_5000_FULL; ++ + mutex_lock(&tp->control); + + ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, +@@ -8404,7 +8454,7 @@ static int r8152_set_eee(struct r8152 *t + + tp->eee_en = eee->eee_enabled; + tp->eee_adv = val; +- if (tp->support_2500full) { ++ if (tp->support_2500full || tp->support_5000full) { + val = linkmode_to_mii_eee_cap2_t(eee->advertised); + tp->eee_adv2 = val; + } +@@ -8428,19 +8478,28 @@ static int r8153_get_eee(struct r8152 *t + val = ocp_reg_read(tp, OCP_EEE_LPABLE); + mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); + +- if (tp->support_2500full) { +- linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); +- ++ if (tp->support_2500full || tp->support_5000full) { + val = ocp_reg_read(tp, OCP_EEE_ADV2); + mii_eee_cap2_mod_linkmode_adv_t(eee->advertised, val); + + val = ocp_reg_read(tp, OCP_EEE_LPABLE2); + mii_eee_cap2_mod_linkmode_adv_t(eee->lp_advertised, val); ++ } ++ ++ if (tp->support_2500full) { ++ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); + + if (speed & _2500bps) + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, common); + } + ++ if (tp->support_5000full) { ++ linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, eee->supported); ++ ++ if (speed & _5000bps) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, common); ++ } ++ + eee->eee_enabled = tp->eee_en; + + if (speed & _1000bps) +@@ -9381,6 +9440,11 @@ static int rtl8152_probe_once(struct usb + } else { + tp->speed = SPEED_1000; + } ++ if (tp->support_5000full && ++ tp->udev->speed >= USB_SPEED_SUPER) { ++ tp->speed = SPEED_5000; ++ tp->advertising |= RTL_ADVERTISED_5000_FULL; ++ } + tp->advertising |= RTL_ADVERTISED_1000_FULL; + } + tp->duplex = DUPLEX_FULL; diff --git a/target/linux/generic/backport-6.18/747-v7.1-r8152-Add-support-for-the-RTL8157-hardware.patch b/target/linux/generic/backport-6.18/747-v7.1-r8152-Add-support-for-the-RTL8157-hardware.patch new file mode 100644 index 0000000000..459c2dba11 --- /dev/null +++ b/target/linux/generic/backport-6.18/747-v7.1-r8152-Add-support-for-the-RTL8157-hardware.patch @@ -0,0 +1,1553 @@ +From fd3c7d080df53136c7e7e37f753fb7bd4640ca42 Mon Sep 17 00:00:00 2001 +From: Birger Koblitz +Date: Sat, 4 Apr 2026 09:57:43 +0200 +Subject: [PATCH] r8152: Add support for the RTL8157 hardware + +The RTL8157 uses a different packet descriptor format compared to the +previous generation of chips. Add support for this format by adding a +descriptor format structure into the r8152 structure and corresponding +desc_ops functions which abstract the vlan-tag, tx/rx len and +tx/rx checksum algorithms. + +Also, add support for the ADV indirect access interface of the RTL8157 +and PHY setup. + +For initialization of the RTL8157, combine the existing RTL8156B and +RTL8156 init functions and add RTL8157-specific functinality in order +to improve code readability and maintainability. +r8156_init() is now called with RTL_VER_10 and RTL_VER_11 for the RTL8156, +with RTL_VER_12, RTL_VER_13 and RTL_VER_15 for the RTL8156B and with +RTL_VER_16 for the RTL8157 and checks the version for chip-specific code. +Also add USB power control functions for the RTL8157. + +Add support for the USB device ID of Realtek RTL8157-based adapters. Detect +the RTL8157 as RTL_VER_16 and set it up. + +Signed-off-by: Birger Koblitz +Link: https://patch.msgid.link/20260404-rtl8157_next-v7-2-039121318f23@birger-koblitz.de +Signed-off-by: Paolo Abeni +--- + drivers/net/usb/r8152.c | 913 ++++++++++++++++++++++++++++++++-------- + 1 file changed, 729 insertions(+), 184 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -129,6 +129,7 @@ + #define USB_CSR_DUMMY1 0xb464 + #define USB_CSR_DUMMY2 0xb466 + #define USB_DEV_STAT 0xb808 ++#define USB_U2P3_V2_CTRL 0xc2c0 + #define USB_CONNECT_TIMER 0xcbf8 + #define USB_MSC_TIMER 0xcbfc + #define USB_BURST_SIZE 0xcfc0 +@@ -162,6 +163,9 @@ + #define USB_U1U2_TIMER 0xd4da + #define USB_FW_TASK 0xd4e8 /* RTL8153B */ + #define USB_RX_AGGR_NUM 0xd4ee ++#define USB_ADV_ADDR 0xd5d6 ++#define USB_ADV_DATA 0xd5d8 ++#define USB_ADV_CMD 0xd5dc + #define USB_UPS_CTRL 0xd800 + #define USB_POWER_CUT 0xd80a + #define USB_MISC_0 0xd81a +@@ -498,6 +502,12 @@ + /* USB_RX_AGGR_NUM */ + #define RX_AGGR_NUM_MASK 0x1ff + ++/* USB_ADV_CMD */ ++#define ADV_CMD_BMU 0 ++#define ADV_CMD_BUSY BIT(0) ++#define ADV_CMD_WR BIT(1) ++#define ADV_CMD_IP BIT(2) ++ + /* USB_UPS_CTRL */ + #define POWER_CUT 0x0100 + +@@ -537,11 +547,15 @@ + #define CDC_ECM_EN BIT(3) + #define RX_AGG_DISABLE 0x0010 + #define RX_ZERO_EN 0x0080 ++#define RX_DESC_16B 0x0400 + + /* USB_U2P3_CTRL */ + #define U2P3_ENABLE 0x0001 + #define RX_DETECT8 BIT(3) + ++/* USB_U2P3_V2_CTRL */ ++#define U2P3_V2_ENABLE BIT(29) ++ + /* USB_POWER_CUT */ + #define PWR_EN 0x0001 + #define PHASE2_EN 0x0008 +@@ -754,8 +768,6 @@ enum rtl_register_content { + #define RTL8152_MAX_TX 4 + #define RTL8152_MAX_RX 10 + #define INTBUFSIZE 2 +-#define TX_ALIGN 4 +-#define RX_ALIGN 8 + + #define RTL8152_RX_MAX_PENDING 4096 + #define RTL8152_RXFG_HEADSZ 256 +@@ -767,7 +779,6 @@ enum rtl_register_content { + #define RTL8152_TX_TIMEOUT (5 * HZ) + #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) + #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) +-#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) + + /* rtl8152 flags */ + enum rtl8152_flags { +@@ -852,6 +863,40 @@ struct tx_desc { + #define TX_VLAN_TAG BIT(16) + }; + ++struct rx_desc_v2 { ++ __le32 opts1; ++#define RX_LEN_MASK_2 0xfffe0000 ++#define rx_v2_get_len(x) (((x) & RX_LEN_MASK_2) >> 17) ++#define RX_VLAN_TAG_2 BIT(3) ++#define RX_VER_MASK 0x3 ++ ++ __le32 opts2; ++ ++ __le32 opts3; ++#define IPF_2 BIT(26) /* IP checksum fail */ ++#define UDPF_2 BIT(25) /* UDP checksum fail */ ++#define TCPF_2 BIT(24) /* TCP checksum fail */ ++#define RD_IPV6_CS_2 BIT(15) ++#define RD_IPV4_CS_2 BIT(14) ++#define RD_UDP_CS_2 BIT(11) ++#define RD_TCP_CS_2 BIT(10) ++ ++ __le32 opts4; ++}; ++ ++struct tx_desc_v2 { ++ __le32 opts1; ++ ++ __le32 opts2; ++#define TCPHO_MAX_2 0x3ffU ++ ++ __le32 opts3; ++#define tx_v2_set_len(x) ((x) << 4) ++ ++ __le32 opts4; ++#define TX_SIG (0x15 << 27) ++}; ++ + struct r8152; + + struct rx_agg { +@@ -925,6 +970,19 @@ struct r8152 { + u32 ctap_short_off:1; + } ups_info; + ++ struct desc_info { ++ void (*vlan_tag)(void *desc, struct sk_buff *skb); ++ u8 align; ++ u8 size; ++ } rx_desc, tx_desc; ++ ++ struct desc_ops { ++ void (*tx_len)(struct r8152 *tp, void *desc, u32 len); ++ u32 (*rx_len)(struct r8152 *tp, void *desc); ++ u8 (*rx_csum)(struct r8152 *tp, void *desc); ++ int (*tx_csum)(struct r8152 *tp, void *desc, struct sk_buff *skb, u32 len); ++ } desc_ops; ++ + #define RTL_VER_SIZE 32 + + struct rtl_fw { +@@ -1189,6 +1247,7 @@ enum rtl_version { + RTL_VER_13, + RTL_VER_14, + RTL_VER_15, ++ RTL_VER_16, + + RTL_VER_MAX + }; +@@ -1214,7 +1273,7 @@ enum tx_csum_stat { + static const int multicast_filter_limit = 32; + static unsigned int agg_buf_sz = 16384; + +-#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) ++#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - tp->tx_desc.size) + + /* If register access fails then we block access and issue a reset. If this + * happens too many times in a row without a successful access then we stop +@@ -1625,6 +1684,122 @@ static inline int r8152_mdio_read(struct + return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); + } + ++static int wait_cmd_ready(struct r8152 *tp, u16 cmd) ++{ ++ return poll_timeout_us(u16 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, cmd), ++ !(ocp_data & ADV_CMD_BUSY), 2000, 20000, false); ++} ++ ++static int ocp_adv_read(struct r8152 *tp, u16 cmd, u16 addr, u32 *data) ++{ ++ int ret; ++ ++ ret = wait_cmd_ready(tp, USB_ADV_CMD); ++ if (ret < 0) ++ goto out; ++ ++ ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_ADDR, addr); ++ ++ cmd |= ADV_CMD_BUSY; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_CMD, cmd); ++ ++ ret = wait_cmd_ready(tp, USB_ADV_CMD); ++ if (ret < 0) ++ goto out; ++ ++ *data = ocp_read_dword(tp, MCU_TYPE_USB, USB_ADV_DATA); ++ ++out: ++ return ret; ++} ++ ++static int ocp_adv_write(struct r8152 *tp, u16 cmd, u16 addr, u32 data) ++{ ++ int ret; ++ ++ ret = wait_cmd_ready(tp, USB_ADV_CMD); ++ if (ret < 0) ++ goto out; ++ ++ cmd |= ADV_CMD_WR; ++ ocp_write_dword(tp, MCU_TYPE_USB, USB_ADV_DATA, data); ++ ++ ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_ADDR, addr); ++ ++ cmd |= ADV_CMD_BUSY; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_CMD, cmd); ++ ++out: ++ return ret; ++} ++ ++static int rtl_bmu_read(struct r8152 *tp, u16 addr, u32 *data) ++{ ++ return ocp_adv_read(tp, ADV_CMD_BMU, addr, data); ++} ++ ++static int rtl_bmu_write(struct r8152 *tp, u16 addr, u32 data) ++{ ++ return ocp_adv_write(tp, ADV_CMD_BMU, addr, data); ++} ++ ++static int rtl_bmu_w0w1(struct r8152 *tp, u16 addr, u32 clear, u32 set) ++{ ++ u32 bmu; ++ int ret; ++ ++ ret = rtl_bmu_read(tp, addr, &bmu); ++ if (ret < 0) ++ goto out; ++ ++ bmu = (bmu & ~clear) | set; ++ ret = rtl_bmu_write(tp, addr, bmu); ++ ++out: ++ return ret; ++} ++ ++static int rtl_bmu_clr_bits(struct r8152 *tp, u16 addr, u32 clear) ++{ ++ return rtl_bmu_w0w1(tp, addr, clear, 0); ++} ++ ++static int rtl_ip_read(struct r8152 *tp, u16 addr, u32 *data) ++{ ++ return ocp_adv_read(tp, ADV_CMD_IP, addr, data); ++} ++ ++static int rtl_ip_write(struct r8152 *tp, u16 addr, u32 data) ++{ ++ return ocp_adv_write(tp, ADV_CMD_IP, addr, data); ++} ++ ++static int rtl_ip_w0w1(struct r8152 *tp, u16 addr, u32 clear, u32 set) ++{ ++ int ret; ++ u32 ip; ++ ++ ret = rtl_ip_read(tp, addr, &ip); ++ if (ret < 0) ++ goto out; ++ ++ ip = (ip & ~clear) | set; ++ ret = rtl_ip_write(tp, addr, ip); ++ ++out: ++ return ret; ++} ++ ++static int rtl_ip_clr_bits(struct r8152 *tp, u16 addr, u32 clear) ++{ ++ return rtl_ip_w0w1(tp, addr, clear, 0); ++} ++ ++static int rtl_ip_set_bits(struct r8152 *tp, u16 addr, u32 set) ++{ ++ return rtl_ip_w0w1(tp, addr, 0, set); ++} ++ + static void sram_write(struct r8152 *tp, u16 addr, u16 data) + { + ocp_reg_write(tp, OCP_SRAM_ADDR, addr); +@@ -2188,14 +2363,14 @@ resubmit: + } + } + +-static inline void *rx_agg_align(void *data) ++static void *rx_agg_align(struct r8152 *tp, void *data) + { +- return (void *)ALIGN((uintptr_t)data, RX_ALIGN); ++ return (void *)ALIGN((uintptr_t)data, tp->rx_desc.align); + } + +-static inline void *tx_agg_align(void *data) ++static void *tx_agg_align(struct r8152 *tp, void *data) + { +- return (void *)ALIGN((uintptr_t)data, TX_ALIGN); ++ return (void *)ALIGN((uintptr_t)data, tp->tx_desc.align); + } + + static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) +@@ -2313,9 +2488,9 @@ static int alloc_all_mem(struct r8152 *t + if (!buf) + goto err1; + +- if (buf != tx_agg_align(buf)) { ++ if (buf != tx_agg_align(tp, buf)) { + kfree(buf); +- buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, ++ buf = kmalloc_node(agg_buf_sz + tp->tx_desc.align, GFP_KERNEL, + node); + if (!buf) + goto err1; +@@ -2331,7 +2506,7 @@ static int alloc_all_mem(struct r8152 *t + tp->tx_info[i].context = tp; + tp->tx_info[i].urb = urb; + tp->tx_info[i].buffer = buf; +- tp->tx_info[i].head = tx_agg_align(buf); ++ tp->tx_info[i].head = tx_agg_align(tp, buf); + + list_add_tail(&tp->tx_info[i].list, &tp->tx_free); + } +@@ -2418,8 +2593,17 @@ drop: + } + } + +-static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) ++static void r8152_tx_len(struct r8152 *tp, void *tx_desc, u32 len) + { ++ struct tx_desc *desc = tx_desc; ++ ++ desc->opts1 |= cpu_to_le32(len); ++} ++ ++static void r8152_tx_vlan_tag(void *d, struct sk_buff *skb) ++{ ++ struct tx_desc *desc = d; ++ + if (skb_vlan_tag_present(skb)) { + u32 opts2; + +@@ -2428,8 +2612,10 @@ static inline void rtl_tx_vlan_tag(struc + } + } + +-static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) ++static void r8152_rx_vlan_tag(void *d, struct sk_buff *skb) + { ++ struct rx_desc *desc = d; ++ + u32 opts2 = le32_to_cpu(desc->opts2); + + if (opts2 & RX_VLAN_TAG) +@@ -2437,10 +2623,11 @@ static inline void rtl_rx_vlan_tag(struc + swab16(opts2 & 0xffff)); + } + +-static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, ++static int r8152_tx_csum(struct r8152 *tp, void *d, + struct sk_buff *skb, u32 len) + { + u32 mss = skb_shinfo(skb)->gso_size; ++ struct tx_desc *desc = d; + u32 opts1, opts2 = 0; + int ret = TX_CSUM_SUCCESS; + +@@ -2525,6 +2712,74 @@ unavailable: + return ret; + } + ++static u32 r8152_rx_len(struct r8152 *tp, void *d) ++{ ++ struct rx_desc *desc = d; ++ ++ return le32_to_cpu(desc->opts1) & RX_LEN_MASK; ++} ++ ++static u32 r8157_rx_len(struct r8152 *tp, void *d) ++{ ++ struct rx_desc_v2 *desc = d; ++ ++ return rx_v2_get_len(le32_to_cpu(desc->opts1)); ++} ++ ++static void r8157_rx_vlan_tag(void *desc, struct sk_buff *skb) ++{ ++ struct rx_desc_v2 *d = desc; ++ u32 opts1; ++ ++ opts1 = le32_to_cpu(d->opts1); ++ if (opts1 & RX_VLAN_TAG_2) { ++ u32 opts2 = le32_to_cpu(d->opts2); ++ ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ++ swab16((opts2 >> 16) & 0xffff)); ++ } ++} ++ ++static int r8157_tx_csum(struct r8152 *tp, void *tx_desc, struct sk_buff *skb, u32 len) ++{ ++ u32 mss = skb_shinfo(skb)->gso_size; ++ ++ if (!mss && skb->ip_summed == CHECKSUM_PARTIAL) { ++ u32 transport_offset = (u32)skb_transport_offset(skb); ++ ++ if (transport_offset > TCPHO_MAX_2) { ++ netif_warn(tp, tx_err, tp->netdev, ++ "Invalid transport offset 0x%x\n", ++ transport_offset); ++ return TX_CSUM_NONE; ++ } ++ } ++ ++ return r8152_tx_csum(tp, tx_desc, skb, len); ++} ++ ++static void r8157_tx_len(struct r8152 *tp, void *tx_desc, u32 len) ++{ ++ struct tx_desc_v2 *desc = tx_desc; ++ ++ desc->opts3 = cpu_to_le32(tx_v2_set_len(len)); ++ desc->opts4 = cpu_to_le32(TX_SIG); ++} ++ ++static int rtl_tx_csum(struct r8152 *tp, void *desc, struct sk_buff *skb, ++ u32 len) ++{ ++ int ret = TX_CSUM_SUCCESS; ++ ++ WARN_ON_ONCE(len > TX_LEN_MAX); ++ ++ ret = tp->desc_ops.tx_csum(tp, desc, skb, len); ++ if (!ret) ++ tp->desc_ops.tx_len(tp, desc, len); ++ ++ return ret; ++} ++ + static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) + { + struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; +@@ -2541,33 +2796,33 @@ static int r8152_tx_agg_fill(struct r815 + agg->skb_len = 0; + remain = agg_buf_sz; + +- while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { +- struct tx_desc *tx_desc; ++ while (remain >= ETH_ZLEN + tp->tx_desc.size) { + struct sk_buff *skb; + unsigned int len; ++ void *tx_desc; + + skb = __skb_dequeue(&skb_head); + if (!skb) + break; + +- len = skb->len + sizeof(*tx_desc); ++ len = skb->len + tp->tx_desc.size; + + if (len > remain) { + __skb_queue_head(&skb_head, skb); + break; + } + +- tx_data = tx_agg_align(tx_data); +- tx_desc = (struct tx_desc *)tx_data; ++ tx_data = tx_agg_align(tp, tx_data); ++ tx_desc = (void *)tx_data; + +- if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { ++ if (rtl_tx_csum(tp, tx_desc, skb, skb->len)) { + r8152_csum_workaround(tp, skb, &skb_head); + continue; + } + +- rtl_tx_vlan_tag(tx_desc, skb); ++ tp->tx_desc.vlan_tag(tx_desc, skb); + +- tx_data += sizeof(*tx_desc); ++ tx_data += tp->tx_desc.size; + + len = skb->len; + if (skb_copy_bits(skb, 0, tx_data, len) < 0) { +@@ -2575,7 +2830,7 @@ static int r8152_tx_agg_fill(struct r815 + + stats->tx_dropped++; + dev_kfree_skb_any(skb); +- tx_data -= sizeof(*tx_desc); ++ tx_data -= tp->tx_desc.size; + continue; + } + +@@ -2585,7 +2840,7 @@ static int r8152_tx_agg_fill(struct r815 + + dev_kfree_skb_any(skb); + +- remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); ++ remain = agg_buf_sz - (int)(tx_agg_align(tp, tx_data) - agg->head); + + if (tp->dell_tb_rx_agg_bug) + break; +@@ -2623,8 +2878,9 @@ out_tx_fill: + return ret; + } + +-static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) ++static u8 r8152_rx_csum(struct r8152 *tp, void *d) + { ++ struct rx_desc *rx_desc = d; + u8 checksum = CHECKSUM_NONE; + u32 opts2, opts3; + +@@ -2652,6 +2908,30 @@ return_result: + return checksum; + } + ++static u8 r8157_rx_csum(struct r8152 *tp, void *desc) ++{ ++ struct rx_desc_v2 *d = desc; ++ u8 checksum = CHECKSUM_NONE; ++ u32 opts3; ++ ++ if (!(tp->netdev->features & NETIF_F_RXCSUM)) ++ goto return_result; ++ ++ opts3 = le32_to_cpu(d->opts3); ++ ++ if ((opts3 & (RD_IPV4_CS_2 | IPF_2)) == (RD_IPV4_CS_2 | IPF_2)) { ++ checksum = CHECKSUM_NONE; ++ } else if (opts3 & (RD_IPV4_CS_2 | RD_IPV6_CS_2)) { ++ if ((opts3 & (RD_UDP_CS_2 | UDPF_2)) == RD_UDP_CS_2) ++ checksum = CHECKSUM_UNNECESSARY; ++ else if ((opts3 & (RD_TCP_CS_2 | TCPF_2)) == RD_TCP_CS_2) ++ checksum = CHECKSUM_UNNECESSARY; ++ } ++ ++return_result: ++ return checksum; ++} ++ + static inline bool rx_count_exceed(struct r8152 *tp) + { + return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; +@@ -2727,10 +3007,10 @@ static int rx_bottom(struct r8152 *tp, i + spin_unlock_irqrestore(&tp->rx_lock, flags); + + list_for_each_safe(cursor, next, &rx_queue) { +- struct rx_desc *rx_desc; + struct rx_agg *agg, *agg_free; + int len_used = 0; + struct urb *urb; ++ void *rx_desc; + u8 *rx_data; + + /* A bulk transfer of USB may contain may packets, so the +@@ -2753,7 +3033,7 @@ static int rx_bottom(struct r8152 *tp, i + + rx_desc = agg->buffer; + rx_data = agg->buffer; +- len_used += sizeof(struct rx_desc); ++ len_used += tp->rx_desc.size; + + while (urb->actual_length > len_used) { + struct net_device *netdev = tp->netdev; +@@ -2764,7 +3044,7 @@ static int rx_bottom(struct r8152 *tp, i + + WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000); + +- pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; ++ pkt_len = tp->desc_ops.rx_len(tp, rx_desc); + if (pkt_len < ETH_ZLEN) + break; + +@@ -2774,7 +3054,7 @@ static int rx_bottom(struct r8152 *tp, i + + pkt_len -= ETH_FCS_LEN; + len = pkt_len; +- rx_data += sizeof(struct rx_desc); ++ rx_data += tp->rx_desc.size; + + if (!agg_free || tp->rx_copybreak > len) + use_frags = false; +@@ -2805,8 +3085,8 @@ static int rx_bottom(struct r8152 *tp, i + goto find_next_rx; + } + +- skb->ip_summed = r8152_rx_csum(tp, rx_desc); +- rtl_rx_vlan_tag(rx_desc, skb); ++ skb->ip_summed = tp->desc_ops.rx_csum(tp, rx_desc); ++ tp->rx_desc.vlan_tag(rx_desc, skb); + + if (use_frags) { + if (rx_frag_head_sz) { +@@ -2843,10 +3123,10 @@ static int rx_bottom(struct r8152 *tp, i + } + + find_next_rx: +- rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN); +- rx_desc = (struct rx_desc *)rx_data; ++ rx_data = rx_agg_align(tp, rx_data + len + ETH_FCS_LEN); ++ rx_desc = rx_data; + len_used = agg_offset(agg, rx_data); +- len_used += sizeof(struct rx_desc); ++ len_used += tp->rx_desc.size; + } + + WARN_ON(!agg_free && page_count(agg->page) > 1); +@@ -3089,13 +3369,19 @@ static netdev_features_t + rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, + netdev_features_t features) + { ++ struct r8152 *tp = netdev_priv(dev); + u32 mss = skb_shinfo(skb)->gso_size; +- int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; ++ int max_offset; ++ ++ if (tp->version < RTL_VER_16) ++ max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; ++ else ++ max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX_2; + + if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && + skb_transport_offset(skb) > max_offset) + features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); +- else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) ++ else if ((skb->len + tp->tx_desc.size) > agg_buf_sz) + features &= ~NETIF_F_GSO_MASK; + + return features; +@@ -3133,31 +3419,26 @@ static void r8152b_reset_packet_filter(s + + static void rtl8152_nic_reset(struct r8152 *tp) + { +- int i; +- + switch (tp->version) { + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_TE); +- +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, +- BMU_RESET_EP_IN); +- ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, BMU_RESET_EP_IN); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); +- + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE); +- +- ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, +- BMU_RESET_EP_IN); +- ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, BMU_RESET_EP_IN); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); + break; + ++ case RTL_VER_16: ++ ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE); ++ break; ++ + default: + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); + +- for (i = 0; i < 1000; i++) { ++ for (int i = 0; i < 1000; i++) { + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + break; + if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) +@@ -3170,7 +3451,7 @@ static void rtl8152_nic_reset(struct r81 + + static void set_tx_qlen(struct r8152 *tp) + { +- tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); ++ tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + tp->tx_desc.size); + } + + static inline u16 rtl8152_get_speed(struct r8152 *tp) +@@ -3374,6 +3655,7 @@ static void r8153_set_rx_early_timeout(s + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: ++ case RTL_VER_16: + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, + 640 / 8); + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, +@@ -3385,9 +3667,14 @@ static void r8153_set_rx_early_timeout(s + } + } + ++static u32 rx_reserved_size(struct r8152 *tp, u32 mtu) ++{ ++ return mtu_to_size(mtu) + tp->rx_desc.size + tp->rx_desc.align; ++} ++ + static void r8153_set_rx_early_size(struct r8152 *tp) + { +- u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); ++ u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp, tp->netdev->mtu); + + switch (tp->version) { + case RTL_VER_03: +@@ -3412,6 +3699,10 @@ static void r8153_set_rx_early_size(stru + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, + ocp_data / 8); + break; ++ case RTL_VER_16: ++ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ++ ocp_data / 16); ++ break; + default: + WARN_ON_ONCE(1); + break; +@@ -3523,6 +3814,7 @@ static void rtl_rx_vlan_en(struct r8152 + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: ++ case RTL_VER_16: + default: + if (enable) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1, +@@ -3680,6 +3972,14 @@ static void r8153_u2p3en(struct r8152 *t + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); + } + ++static int r8157_u2p3en(struct r8152 *tp, bool enable) ++{ ++ if (enable) ++ return rtl_ip_set_bits(tp, USB_U2P3_V2_CTRL, U2P3_V2_ENABLE); ++ else ++ return rtl_ip_clr_bits(tp, USB_U2P3_V2_CTRL, U2P3_V2_ENABLE); ++} ++ + static void r8153b_ups_flags(struct r8152 *tp) + { + u32 ups_flags = 0; +@@ -4025,6 +4325,18 @@ static void r8153b_power_cut_en(struct r + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); + } + ++static void r8157_power_cut_en(struct r8152 *tp, bool enable) ++{ ++ if (enable) { ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN | PHASE2_EN); ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(1)); ++ } else { ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN); ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(1)); ++ } ++} ++ + static void r8153_queue_wake(struct r8152 *tp, bool enable) + { + if (enable) +@@ -4141,6 +4453,22 @@ static void rtl8156_runtime_enable(struc + } + } + ++static void rtl8157_runtime_enable(struct r8152 *tp, bool enable) ++{ ++ if (enable) { ++ r8153_queue_wake(tp, true); ++ r8153b_u1u2en(tp, false); ++ r8157_u2p3en(tp, false); ++ rtl_runtime_suspend_enable(tp, true); ++ } else { ++ r8153_queue_wake(tp, false); ++ rtl_runtime_suspend_enable(tp, false); ++ r8157_u2p3en(tp, true); ++ if (tp->udev->speed >= USB_SPEED_SUPER) ++ r8153b_u1u2en(tp, true); ++ } ++} ++ + static void r8153_teredo_off(struct r8152 *tp) + { + switch (tp->version) { +@@ -4165,6 +4493,7 @@ static void r8153_teredo_off(struct r815 + case RTL_VER_13: + case RTL_VER_14: + case RTL_VER_15: ++ case RTL_VER_16: + default: + /* The bit 0 ~ 7 are relative with teredo settings. They are + * W1C (write 1 to clear), so set all 1 to disable it. +@@ -4218,6 +4547,7 @@ static void rtl_clear_bp(struct r8152 *t + bp_num = 8; + break; + case RTL_VER_14: ++ case RTL_VER_16: + default: + ocp_write_word(tp, type, USB_BP2_EN, 0); + bp_num = 16; +@@ -4325,6 +4655,7 @@ static bool rtl8152_is_fw_phy_speed_up_o + case RTL_VER_11: + case RTL_VER_12: + case RTL_VER_14: ++ case RTL_VER_16: + goto out; + case RTL_VER_13: + case RTL_VER_15: +@@ -5486,6 +5817,7 @@ static void rtl_eee_enable(struct r8152 + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: ++ case RTL_VER_16: + if (enable) { + r8156_eee_en(tp, true); + ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); +@@ -6070,15 +6402,24 @@ static int rtl8156_enable(struct r8152 * + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return -ENODEV; + +- r8156_fc_parameter(tp); ++ if (tp->version < RTL_VER_12) ++ r8156_fc_parameter(tp); ++ + set_tx_qlen(tp); + rtl_set_eee_plus(tp); ++ ++ if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_16) ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); ++ + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); + + speed = rtl8152_get_speed(tp); + rtl_set_ifg(tp, speed); + ++ if (tp->version >= RTL_VER_16) ++ return rtl_enable(tp); ++ + if (speed & _2500bps) + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); +@@ -6086,10 +6427,12 @@ static int rtl8156_enable(struct r8152 * + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); + +- if (speed & _1000bps) +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); +- else if (speed & _500bps) +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); ++ if (tp->version < RTL_VER_12) { ++ if (speed & _1000bps) ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); ++ else if (speed & _500bps) ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); ++ } + + if (tp->udev->speed == USB_SPEED_HIGH) { + /* USB 0xb45e[3:0] l1_nyet_hird */ +@@ -6114,45 +6457,6 @@ static void rtl8156_disable(struct r8152 + rtl8153_disable(tp); + } + +-static int rtl8156b_enable(struct r8152 *tp) +-{ +- u16 speed; +- +- if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +- return -ENODEV; +- +- set_tx_qlen(tp); +- rtl_set_eee_plus(tp); +- +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); +- +- r8153_set_rx_early_timeout(tp); +- r8153_set_rx_early_size(tp); +- +- speed = rtl8152_get_speed(tp); +- rtl_set_ifg(tp, speed); +- +- if (speed & _2500bps) +- ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, +- IDLE_SPDWN_EN); +- else +- ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, +- IDLE_SPDWN_EN); +- +- if (tp->udev->speed == USB_SPEED_HIGH) { +- if (is_flow_control(speed)) +- ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); +- else +- ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); +- } +- +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); +- usleep_range(1000, 2000); +- ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); +- +- return rtl_enable(tp); +-} +- + static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, + u32 advertising) + { +@@ -6495,7 +6799,7 @@ static void rtl8156_change_mtu(struct r8 + /* TX share fifo free credit full threshold */ + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, +- ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); ++ ALIGN(rx_max_size + tp->tx_desc.size, 1024) / 16); + } + + static void rtl8156_up(struct r8152 *tp) +@@ -6504,7 +6808,8 @@ static void rtl8156_up(struct r8152 *tp) + return; + + r8153b_u1u2en(tp, false); +- r8153_u2p3en(tp, false); ++ if (tp->version != RTL_VER_16) ++ r8153_u2p3en(tp, false); + r8153_aldps_en(tp, false); + + rxdy_gated_en(tp, true); +@@ -6517,6 +6822,9 @@ static void rtl8156_up(struct r8152 *tp) + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); + ++ if (tp->version == RTL_VER_16) ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, BIT(3)); ++ + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); + + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); +@@ -6540,8 +6848,11 @@ static void rtl8156_up(struct r8152 *tp) + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); + +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, +- RG_PWRDN_EN | ALL_SPEED_OFF); ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); ++ ++ if (tp->version != RTL_VER_16) ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ++ RG_PWRDN_EN | ALL_SPEED_OFF); + + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); + +@@ -6551,9 +6862,10 @@ static void rtl8156_up(struct r8152 *tp) + } + + r8153_aldps_en(tp, true); +- r8153_u2p3en(tp, true); ++ if (tp->version != RTL_VER_16) ++ r8153_u2p3en(tp, true); + +- if (tp->udev->speed >= USB_SPEED_SUPER) ++ if (tp->version != RTL_VER_16 && tp->udev->speed >= USB_SPEED_SUPER) + r8153b_u1u2en(tp, true); + } + +@@ -6568,8 +6880,10 @@ static void rtl8156_down(struct r8152 *t + PLA_MCU_SPDWN_EN); + + r8153b_u1u2en(tp, false); +- r8153_u2p3en(tp, false); +- r8153b_power_cut_en(tp, false); ++ if (tp->version != RTL_VER_16) { ++ r8153_u2p3en(tp, false); ++ r8153b_power_cut_en(tp, false); ++ } + r8153_aldps_en(tp, false); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); +@@ -7642,106 +7956,241 @@ static void r8156b_hw_phy_cfg(struct r81 + set_bit(PHY_RESET, &tp->flags); + } + +-static void r8156_init(struct r8152 *tp) ++static void r8157_hw_phy_cfg(struct r8152 *tp) + { ++ u32 ocp_data; + u16 data; +- int i; +- +- if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +- return; +- +- ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); +- +- ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); +- +- ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); +- +- r8153b_u1u2en(tp, false); ++ int ret; + +- for (i = 0; i < 500; i++) { +- if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & +- AUTOLOAD_DONE) +- break; ++ r8156b_wait_loading_flash(tp); + +- msleep(20); +- if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) +- return; ++ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); ++ if (ocp_data & PCUT_STATUS) { ++ ocp_data &= ~PCUT_STATUS; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); + } + + data = r8153_phy_status(tp, 0); +- if (data == PHY_STAT_EXT_INIT) ++ switch (data) { ++ case PHY_STAT_EXT_INIT: ++ ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); ++ break; ++ case PHY_STAT_LAN_ON: ++ case PHY_STAT_PWRDN: ++ default: ++ break; ++ } + +- r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); ++ data = r8152_mdio_read(tp, MII_BMCR); ++ if (data & BMCR_PDOWN) { ++ data &= ~BMCR_PDOWN; ++ r8152_mdio_write(tp, MII_BMCR, data); ++ } + +- data = r8153_phy_status(tp, PHY_STAT_LAN_ON); +- WARN_ON_ONCE(data != PHY_STAT_LAN_ON); ++ r8153_aldps_en(tp, false); ++ rtl_eee_enable(tp, false); + +- r8153_u2p3en(tp, false); ++ ret = r8153_phy_status(tp, PHY_STAT_LAN_ON); ++ if (ret < 0) ++ return; ++ WARN_ON_ONCE(ret != PHY_STAT_LAN_ON); + +- /* MSC timer = 0xfff * 8ms = 32760 ms */ +- ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); ++ /* PFM mode */ ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); + +- /* U1/U2/L1 idle timer. 500 us */ +- ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); ++ /* Advanced Power Saving parameter */ ++ ocp_reg_set_bits(tp, 0xa430, BIT(0) | BIT(1)); + +- r8153b_power_cut_en(tp, false); +- r8156_ups_en(tp, false); +- r8153_queue_wake(tp, false); +- rtl_runtime_suspend_enable(tp, false); ++ /* aldpsce force mode */ ++ ocp_reg_clr_bits(tp, 0xa44a, BIT(2)); + +- if (tp->udev->speed >= USB_SPEED_SUPER) +- r8153b_u1u2en(tp, true); ++ switch (tp->version) { ++ case RTL_VER_16: ++ /* XG_INRX parameter */ ++ sram_write_w0w1(tp, 0x8183, 0xff00, 0x5900); ++ ocp_reg_set_bits(tp, 0xa654, BIT(11)); ++ ocp_reg_set_bits(tp, 0xb648, BIT(14)); ++ ocp_reg_clr_bits(tp, 0xad2c, BIT(15)); ++ ocp_reg_set_bits(tp, 0xad94, BIT(5)); ++ ocp_reg_set_bits(tp, 0xada0, BIT(1)); ++ ocp_reg_w0w1(tp, 0xae06, 0xfc00, 0x7c00); ++ sram2_write_w0w1(tp, 0x8647, 0xff00, 0xe600); ++ sram2_write_w0w1(tp, 0x8036, 0xff00, 0x3000); ++ sram2_write_w0w1(tp, 0x8078, 0xff00, 0x3000); ++ ++ /* green mode */ ++ sram2_write_w0w1(tp, 0x89e9, 0xff00, 0); ++ sram2_write_w0w1(tp, 0x8ffd, 0xff00, 0x0100); ++ sram2_write_w0w1(tp, 0x8ffe, 0xff00, 0x0200); ++ sram2_write_w0w1(tp, 0x8fff, 0xff00, 0x0400); ++ ++ /* recognize AQC/Bcom function */ ++ sram_write_w0w1(tp, 0x8018, 0xff00, 0x7700); ++ ocp_reg_write(tp, OCP_SRAM_ADDR, 0x8f9c); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0005); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x00ed); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0502); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0b00); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0xd401); ++ sram_write_w0w1(tp, 0x8fa8, 0xff00, 0x2900); ++ ++ /* RFI_corr_thd 5g */ ++ sram2_write_w0w1(tp, 0x814b, 0xff00, 0x1100); ++ sram2_write_w0w1(tp, 0x814d, 0xff00, 0x1100); ++ sram2_write_w0w1(tp, 0x814f, 0xff00, 0x0b00); ++ sram2_write_w0w1(tp, 0x8142, 0xff00, 0x0100); ++ sram2_write_w0w1(tp, 0x8144, 0xff00, 0x0100); ++ sram2_write_w0w1(tp, 0x8150, 0xff00, 0x0100); ++ ++ /* RFI_corr_thd 2p5g */ ++ sram2_write_w0w1(tp, 0x8118, 0xff00, 0x0700); ++ sram2_write_w0w1(tp, 0x811a, 0xff00, 0x0700); ++ sram2_write_w0w1(tp, 0x811c, 0xff00, 0x0500); ++ sram2_write_w0w1(tp, 0x810f, 0xff00, 0x0100); ++ sram2_write_w0w1(tp, 0x8111, 0xff00, 0x0100); ++ sram2_write_w0w1(tp, 0x811d, 0xff00, 0x0100); ++ ++ /* RFI parameter */ ++ ocp_reg_clr_bits(tp, 0xad1c, BIT(8)); ++ ocp_reg_w0w1(tp, 0xade8, 0xffc0, 0x1400); ++ sram2_write_w0w1(tp, 0x864b, 0xff00, 0x9d00); ++ sram2_write_w0w1(tp, 0x862c, 0xff00, 0x1200); ++ ocp_reg_write(tp, OCP_SRAM_ADDR, 0x8566); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x003f); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x3f02); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x023c); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x3b0a); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x1c00); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); ++ ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); ++ ++ /* RFI-color noise gen parameter 5g */ ++ ocp_reg_set_bits(tp, 0xad9c, BIT(5)); ++ sram2_write_w0w1(tp, 0x8122, 0xff00, 0x0c00); ++ ocp_reg_write(tp, OCP_SRAM2_ADDR, 0x82c8); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ff); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0009); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000b); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0021); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f7); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03b8); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e0); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0049); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0049); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e0); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03b8); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f7); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0021); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000b); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0009); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ff); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); ++ ++ /* RFI-color noise gen parameter 2p5g */ ++ sram2_write_w0w1(tp, 0x80ef, 0xff00, 0x0c00); ++ ocp_reg_write(tp, OCP_SRAM2_ADDR, 0x82a0); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000e); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0006); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x001a); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f1); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03d8); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0023); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0054); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0322); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x00dd); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ab); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03dc); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0027); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000e); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e5); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f9); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0012); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0001); ++ ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f1); ++ ++ /* modify thermal speed down threshold */ ++ ocp_reg_w0w1(tp, 0xb54c, 0xffc0, 0x3700); ++ ++ /* XG compatibility modification */ ++ ocp_reg_set_bits(tp, 0xb648, BIT(6)); ++ sram2_write_w0w1(tp, 0x8082, 0xff00, 0x5d00); ++ sram2_write_w0w1(tp, 0x807c, 0xff00, 0x5000); ++ sram2_write_w0w1(tp, 0x809d, 0xff00, 0x5000); ++ break; ++ default: ++ break; ++ } + +- usb_enable_lpm(tp->udev); ++ if (rtl_phy_patch_request(tp, true, true)) ++ return; + +- r8156_mac_clk_spd(tp, true); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); + +- ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, +- PLA_MCU_SPDWN_EN); ++ ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, EN_10M_CLKDIV); + +- if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, +- CUR_LINK_OK | POLL_LINK_CHG); +- else +- ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, +- POLL_LINK_CHG); ++ tp->ups_info._10m_ckdiv = true; ++ tp->ups_info.eee_plloff_100 = false; ++ tp->ups_info.eee_plloff_giga = false; + +- set_bit(GREEN_ETHERNET, &tp->flags); ++ ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); ++ tp->ups_info.eee_ckdiv = true; + +- /* rx aggregation */ +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, +- RX_AGG_DISABLE | RX_ZERO_EN); ++ rtl_phy_patch_request(tp, false, true); + +- ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); ++ rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + +- r8156_mdio_force_mode(tp); +- rtl_tally_reset(tp); ++ ocp_reg_clr_bits(tp, 0xa428, BIT(9)); ++ ocp_reg_clr_bits(tp, 0xa5ea, BIT(0) | BIT(1)); ++ tp->ups_info.lite_mode = 0; + +- tp->coalesce = 15000; /* 15 us */ ++ if (tp->eee_en) ++ rtl_eee_enable(tp, true); ++ ++ r8153_aldps_en(tp, true); ++ r8152b_enable_fc(tp); ++ ++ set_bit(PHY_RESET, &tp->flags); + } + +-static void r8156b_init(struct r8152 *tp) ++static void r8156_init(struct r8152 *tp) + { ++ u32 ocp_data; + u16 data; + int i; + + if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) + return; + ++ if (tp->version == RTL_VER_16) { ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xcffe, BIT(3)); ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(0)); ++ } ++ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); + +- ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); ++ if (tp->version != RTL_VER_16) ++ ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); + + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); + +- ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); ++ if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_15) ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); + + r8153b_u1u2en(tp, false); + + switch (tp->version) { + case RTL_VER_13: + case RTL_VER_15: ++ case RTL_VER_16: + r8156b_wait_loading_flash(tp); + break; + default: +@@ -7761,14 +8210,22 @@ static void r8156b_init(struct r8152 *tp + data = r8153_phy_status(tp, 0); + if (data == PHY_STAT_EXT_INIT) { + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); +- ocp_reg_clr_bits(tp, 0xa466, BIT(0)); ++ if (tp->version >= RTL_VER_12) ++ ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + } + +- r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); ++ data = r8152_mdio_read(tp, MII_BMCR); ++ if (data & BMCR_PDOWN) { ++ data &= ~BMCR_PDOWN; ++ r8152_mdio_write(tp, MII_BMCR, data); ++ } + + data = r8153_phy_status(tp, PHY_STAT_LAN_ON); + +- r8153_u2p3en(tp, false); ++ if (tp->version == RTL_VER_16) ++ r8157_u2p3en(tp, false); ++ else ++ r8153_u2p3en(tp, false); + + /* MSC timer = 0xfff * 8ms = 32760 ms */ + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); +@@ -7776,7 +8233,11 @@ static void r8156b_init(struct r8152 *tp + /* U1/U2/L1 idle timer. 500 us */ + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + +- r8153b_power_cut_en(tp, false); ++ if (tp->version == RTL_VER_16) ++ r8157_power_cut_en(tp, false); ++ else ++ r8153b_power_cut_en(tp, false); ++ + r8156_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); +@@ -7786,39 +8247,53 @@ static void r8156b_init(struct r8152 *tp + + usb_enable_lpm(tp->udev); + +- ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); ++ if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_15) { ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); + +- ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); ++ ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); + +- /* enable fc timer and set timer to 600 ms. */ +- ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, +- CTRL_TIMER_EN | (600 / 8)); ++ /* enable fc timer and set timer to 600 ms. */ ++ ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, CTRL_TIMER_EN | (600 / 8)); + +- if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) +- ocp_word_w0w1(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP, +- FLOW_CTRL_PATCH_2); +- else +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); ++ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); ++ if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) ++ ocp_data |= FLOW_CTRL_PATCH_2; ++ ocp_data &= ~AUTO_SPEEDUP; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); + +- ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); ++ ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); ++ } + + r8156_mac_clk_spd(tp, true); + +- ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, +- PLA_MCU_SPDWN_EN); ++ if (tp->version != RTL_VER_16) ++ ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); + ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); + if (rtl8152_get_speed(tp) & LINK_STATUS) +- ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, +- CUR_LINK_OK | POLL_LINK_CHG); ++ ocp_data |= CUR_LINK_OK; + else +- ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, +- POLL_LINK_CHG); ++ ocp_data &= ~CUR_LINK_OK; ++ ocp_data |= POLL_LINK_CHG; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + + set_bit(GREEN_ETHERNET, &tp->flags); + +- /* rx aggregation */ +- ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, +- RX_AGG_DISABLE | RX_ZERO_EN); ++ /* rx aggregation / 16 bytes Rx descriptor */ ++ if (tp->version == RTL_VER_16) ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_DESC_16B); ++ else ++ ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_ZERO_EN); ++ ++ if (tp->version < RTL_VER_12) ++ ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); ++ ++ if (tp->version == RTL_VER_16) { ++ /* Disable Rx Zero Len */ ++ rtl_bmu_clr_bits(tp, 0x2300, BIT(3)); ++ /* TX descriptor Signature */ ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); ++ } + + r8156_mdio_force_mode(tp); + rtl_tally_reset(tp); +@@ -8969,6 +9444,11 @@ static void rtl8153_unload(struct r8152 + return; + + r8153_power_cut_en(tp, false); ++ ++ if (tp->version >= RTL_VER_16) { ++ /* Disable Interrupt Mitigation */ ++ ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, BIT(0) | BIT(1) | BIT(2) | BIT(7)); ++ } + } + + static void rtl8153b_unload(struct r8152 *tp) +@@ -8979,6 +9459,38 @@ static void rtl8153b_unload(struct r8152 + r8153b_power_cut_en(tp, false); + } + ++static int r8152_desc_init(struct r8152 *tp) ++{ ++ tp->rx_desc.size = sizeof(struct rx_desc); ++ tp->rx_desc.align = 8; ++ tp->rx_desc.vlan_tag = r8152_rx_vlan_tag; ++ tp->desc_ops.rx_csum = r8152_rx_csum; ++ tp->desc_ops.rx_len = r8152_rx_len; ++ tp->tx_desc.size = sizeof(struct tx_desc); ++ tp->tx_desc.align = 4; ++ tp->tx_desc.vlan_tag = r8152_tx_vlan_tag; ++ tp->desc_ops.tx_csum = r8152_tx_csum; ++ tp->desc_ops.tx_len = r8152_tx_len; ++ ++ return 0; ++} ++ ++static int r8157_desc_init(struct r8152 *tp) ++{ ++ tp->rx_desc.size = sizeof(struct rx_desc_v2); ++ tp->rx_desc.align = 16; ++ tp->rx_desc.vlan_tag = r8157_rx_vlan_tag; ++ tp->desc_ops.rx_csum = r8157_rx_csum; ++ tp->desc_ops.rx_len = r8157_rx_len; ++ tp->tx_desc.size = sizeof(struct tx_desc_v2); ++ tp->tx_desc.align = 16; ++ tp->tx_desc.vlan_tag = r8152_tx_vlan_tag; ++ tp->desc_ops.tx_csum = r8157_tx_csum; ++ tp->desc_ops.tx_len = r8157_tx_len; ++ ++ return 0; ++} ++ + static int rtl_ops_init(struct r8152 *tp) + { + struct rtl_ops *ops = &tp->rtl_ops; +@@ -9002,6 +9514,7 @@ static int rtl_ops_init(struct r8152 *tp + tp->rx_buf_sz = 16 * 1024; + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_100TX; ++ r8152_desc_init(tp); + break; + + case RTL_VER_03: +@@ -9026,6 +9539,7 @@ static int rtl_ops_init(struct r8152 *tp + tp->rx_buf_sz = 32 * 1024; + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ r8152_desc_init(tp); + break; + + case RTL_VER_08: +@@ -9045,6 +9559,7 @@ static int rtl_ops_init(struct r8152 *tp + tp->rx_buf_sz = 32 * 1024; + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ r8152_desc_init(tp); + break; + + case RTL_VER_11: +@@ -9067,6 +9582,7 @@ static int rtl_ops_init(struct r8152 *tp + ops->change_mtu = rtl8156_change_mtu; + tp->rx_buf_sz = 48 * 1024; + tp->support_2500full = 1; ++ r8152_desc_init(tp); + break; + + case RTL_VER_12: +@@ -9077,8 +9593,8 @@ static int rtl_ops_init(struct r8152 *tp + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; + tp->eee_adv2 = MDIO_EEE_2_5GT; +- ops->init = r8156b_init; +- ops->enable = rtl8156b_enable; ++ ops->init = r8156_init; ++ ops->enable = rtl8156_enable; + ops->disable = rtl8153_disable; + ops->up = rtl8156_up; + ops->down = rtl8156_down; +@@ -9090,6 +9606,7 @@ static int rtl_ops_init(struct r8152 *tp + ops->autosuspend_en = rtl8156_runtime_enable; + ops->change_mtu = rtl8156_change_mtu; + tp->rx_buf_sz = 48 * 1024; ++ r8152_desc_init(tp); + break; + + case RTL_VER_14: +@@ -9108,6 +9625,29 @@ static int rtl_ops_init(struct r8152 *tp + tp->rx_buf_sz = 32 * 1024; + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ r8152_desc_init(tp); ++ break; ++ ++ case RTL_VER_16: ++ tp->eee_en = true; ++ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; ++ tp->eee_adv2 = MDIO_EEE_2_5GT | MDIO_EEE_5GT; ++ ops->init = r8156_init; ++ ops->enable = rtl8156_enable; ++ ops->disable = rtl8153_disable; ++ ops->up = rtl8156_up; ++ ops->down = rtl8156_down; ++ ops->unload = rtl8153_unload; ++ ops->eee_get = r8153_get_eee; ++ ops->eee_set = r8152_set_eee; ++ ops->in_nway = rtl8153_in_nway; ++ ops->hw_phy_cfg = r8157_hw_phy_cfg; ++ ops->autosuspend_en = rtl8157_runtime_enable; ++ ops->change_mtu = rtl8156_change_mtu; ++ tp->rx_buf_sz = 32 * 1024; ++ tp->support_2500full = 1; ++ tp->support_5000full = 1; ++ r8157_desc_init(tp); + break; + + default: +@@ -9260,6 +9800,9 @@ static u8 __rtl_get_hw_ver(struct usb_de + case 0x7420: + version = RTL_VER_15; + break; ++ case 0x1030: ++ version = RTL_VER_16; ++ break; + default: + version = RTL_VER_UNKNOWN; + dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); +@@ -9411,6 +9954,7 @@ static int rtl8152_probe_once(struct usb + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: ++ case RTL_VER_16: + netdev->max_mtu = size_to_mtu(16 * 1024); + break; + case RTL_VER_01: +@@ -9571,6 +10115,7 @@ static const struct usb_device_id rtl815 + { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, + { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, + { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, ++ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8157) }, + + /* Microsoft */ + { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, diff --git a/target/linux/generic/hack-6.18/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-6.18/760-net-usb-r8152-add-LED-configuration-from-OF.patch index 1948457a1e..fa8ddeca24 100644 --- a/target/linux/generic/hack-6.18/760-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/generic/hack-6.18/760-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,8 +22,8 @@ Signed-off-by: David Bauer #include #include #include -@@ -7019,6 +7020,22 @@ static void rtl_tally_reset(struct r8152 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); +@@ -7193,6 +7194,22 @@ static void rtl_tally_reset(struct r8152 + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RSTTALLY, TALLY_RESET); } +static int r8152_led_configuration(struct r8152 *tp) @@ -45,16 +45,16 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -7060,6 +7077,8 @@ static void r8152b_init(struct r8152 *tp - ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +@@ -7225,6 +7242,8 @@ static void r8152b_init(struct r8152 *tp + /* enable rx aggregation */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); + + r8152_led_configuration(tp); } static void r8153_init(struct r8152 *tp) -@@ -7200,6 +7219,8 @@ static void r8153_init(struct r8152 *tp) +@@ -7342,6 +7361,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -7282,6 +7303,8 @@ static void r8153b_init(struct r8152 *tp +@@ -7412,6 +7433,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ From 152fc0b304d2cdccef3e19ddb79face831389da2 Mon Sep 17 00:00:00 2001 From: Qingfang Deng Date: Fri, 24 Apr 2026 16:08:34 +0800 Subject: [PATCH 20/46] kernel: hide kmod-pppox The pppox module is a dependency of pppoe/pptp/pppol2tp and does not have a separate Kconfig symbol. Signed-off-by: Qingfang Deng Link: https://github.com/openwrt/openwrt/pull/23077 Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/netsupport.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/netsupport.mk b/package/kernel/linux/modules/netsupport.mk index c3720c791a..39ca0ef431 100644 --- a/package/kernel/linux/modules/netsupport.mk +++ b/package/kernel/linux/modules/netsupport.mk @@ -605,7 +605,7 @@ define KernelPackage/pppox SUBMENU:=$(NETWORK_SUPPORT_MENU) TITLE:=PPPoX helper DEPENDS:=kmod-ppp - KCONFIG:=CONFIG_PPPOE + HIDDEN:=1 FILES:=$(LINUX_DIR)/drivers/net/ppp/pppox.ko endef From b34fe80db88132c54faededff1623f05007eff1d Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Tue, 21 Apr 2026 13:18:04 +0000 Subject: [PATCH 21/46] kernel/octeon: create files for v6.18 (from v6.12) This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- target/linux/octeon/{config-6.12 => config-6.18} | 0 .../000-fix-octeon-kernel-build.patch | 0 .../100-mips_image_cmdline_hack.patch | 0 .../100-ubnt_edgerouter2_support.patch | 0 .../110-er200-ethernet_probe_order.patch | 0 .../octeon/{patches-6.12 => patches-6.18}/120-cmdline-hack.patch | 0 .../{patches-6.12 => patches-6.18}/130-add_itus_support.patch | 0 .../{patches-6.12 => patches-6.18}/150-ubnt_usg_support.patch | 0 .../{patches-6.12 => patches-6.18}/400-ubnt_dts_pruning.patch | 0 .../700-allocate_interface_by_label.patch | 0 .../701-honor_sgmii_node_device_tree_status.patch | 0 .../702-qca833x-force-pcs-reset.patch | 0 12 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/octeon/{config-6.12 => config-6.18} (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/000-fix-octeon-kernel-build.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/100-mips_image_cmdline_hack.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/100-ubnt_edgerouter2_support.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/110-er200-ethernet_probe_order.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/120-cmdline-hack.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/130-add_itus_support.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/150-ubnt_usg_support.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/400-ubnt_dts_pruning.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/700-allocate_interface_by_label.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/701-honor_sgmii_node_device_tree_status.patch (100%) rename target/linux/octeon/{patches-6.12 => patches-6.18}/702-qca833x-force-pcs-reset.patch (100%) diff --git a/target/linux/octeon/config-6.12 b/target/linux/octeon/config-6.18 similarity index 100% rename from target/linux/octeon/config-6.12 rename to target/linux/octeon/config-6.18 diff --git a/target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch b/target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch similarity index 100% rename from target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch rename to target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch diff --git a/target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch b/target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch similarity index 100% rename from target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch rename to target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch diff --git a/target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch b/target/linux/octeon/patches-6.18/100-ubnt_edgerouter2_support.patch similarity index 100% rename from target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch rename to target/linux/octeon/patches-6.18/100-ubnt_edgerouter2_support.patch diff --git a/target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch b/target/linux/octeon/patches-6.18/110-er200-ethernet_probe_order.patch similarity index 100% rename from target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch rename to target/linux/octeon/patches-6.18/110-er200-ethernet_probe_order.patch diff --git a/target/linux/octeon/patches-6.12/120-cmdline-hack.patch b/target/linux/octeon/patches-6.18/120-cmdline-hack.patch similarity index 100% rename from target/linux/octeon/patches-6.12/120-cmdline-hack.patch rename to target/linux/octeon/patches-6.18/120-cmdline-hack.patch diff --git a/target/linux/octeon/patches-6.12/130-add_itus_support.patch b/target/linux/octeon/patches-6.18/130-add_itus_support.patch similarity index 100% rename from target/linux/octeon/patches-6.12/130-add_itus_support.patch rename to target/linux/octeon/patches-6.18/130-add_itus_support.patch diff --git a/target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch b/target/linux/octeon/patches-6.18/150-ubnt_usg_support.patch similarity index 100% rename from target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch rename to target/linux/octeon/patches-6.18/150-ubnt_usg_support.patch diff --git a/target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch b/target/linux/octeon/patches-6.18/400-ubnt_dts_pruning.patch similarity index 100% rename from target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch rename to target/linux/octeon/patches-6.18/400-ubnt_dts_pruning.patch diff --git a/target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch b/target/linux/octeon/patches-6.18/700-allocate_interface_by_label.patch similarity index 100% rename from target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch rename to target/linux/octeon/patches-6.18/700-allocate_interface_by_label.patch diff --git a/target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch b/target/linux/octeon/patches-6.18/701-honor_sgmii_node_device_tree_status.patch similarity index 100% rename from target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch rename to target/linux/octeon/patches-6.18/701-honor_sgmii_node_device_tree_status.patch diff --git a/target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch b/target/linux/octeon/patches-6.18/702-qca833x-force-pcs-reset.patch similarity index 100% rename from target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch rename to target/linux/octeon/patches-6.18/702-qca833x-force-pcs-reset.patch From 467dec8f81e33c9b4653ef0c9175af2729daf614 Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Tue, 21 Apr 2026 13:18:04 +0000 Subject: [PATCH 22/46] kernel/octeon: restore files for v6.12 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- target/linux/octeon/config-6.12 | 282 ++++++++++++++++++ .../000-fix-octeon-kernel-build.patch | 116 +++++++ .../100-mips_image_cmdline_hack.patch | 38 +++ .../100-ubnt_edgerouter2_support.patch | 11 + .../110-er200-ethernet_probe_order.patch | 34 +++ .../patches-6.12/120-cmdline-hack.patch | 47 +++ .../patches-6.12/130-add_itus_support.patch | 42 +++ .../patches-6.12/150-ubnt_usg_support.patch | 46 +++ .../patches-6.12/400-ubnt_dts_pruning.patch | 90 ++++++ .../700-allocate_interface_by_label.patch | 37 +++ ...-honor_sgmii_node_device_tree_status.patch | 27 ++ .../702-qca833x-force-pcs-reset.patch | 123 ++++++++ 12 files changed, 893 insertions(+) create mode 100644 target/linux/octeon/config-6.12 create mode 100644 target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch create mode 100644 target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch create mode 100644 target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch create mode 100644 target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch create mode 100644 target/linux/octeon/patches-6.12/120-cmdline-hack.patch create mode 100644 target/linux/octeon/patches-6.12/130-add_itus_support.patch create mode 100644 target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch create mode 100644 target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch create mode 100644 target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch create mode 100644 target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch create mode 100644 target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch diff --git a/target/linux/octeon/config-6.12 b/target/linux/octeon/config-6.12 new file mode 100644 index 0000000000..6c58cb76a8 --- /dev/null +++ b/target/linux/octeon/config-6.12 @@ -0,0 +1,282 @@ +CONFIG_64BIT=y +CONFIG_AHCI_OCTEON=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS=12 +CONFIG_ARCH_MMAP_RND_BITS_MAX=18 +CONFIG_ARCH_MMAP_RND_BITS_MIN=12 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_AT803X_PHY=y +CONFIG_ATA=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_DTB=y +CONFIG_CAVIUM_CN63XXP1=y +CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0 +CONFIG_CAVIUM_OCTEON_LOCK_L2=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y +CONFIG_CAVIUM_OCTEON_SOC=y +CONFIG_CAVIUM_RESERVE32=0 +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_COMMON_CLK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CAVIUM_OCTEON=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS64=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_CPU_SUPPORTS_VZ=y +CONFIG_CRAMFS=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_MD5_OCTEON is not set +# CONFIG_CRYPTO_SHA1_OCTEON is not set +# CONFIG_CRYPTO_SHA256_OCTEON is not set +# CONFIG_CRYPTO_SHA512_OCTEON is not set +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +CONFIG_DEBUG_INFO_NONE=y +CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_OCTEON_L2C=y +CONFIG_EDAC_OCTEON_LMC=y +CONFIG_EDAC_OCTEON_PC=y +CONFIG_EDAC_OCTEON_PCI=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FAT_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_OCTEON=y +CONFIG_GRO_CELLS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OCTEON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_OCTEON=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_CAVIUM=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_OCTEON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +CONFIG_MIPS_ELF_APPENDED_DTB=y +CONFIG_MIPS_FP_SUPPORT=y +CONFIG_MIPS_L1_CACHE_SHIFT=7 +CONFIG_MIPS_L1_CACHE_SHIFT_7=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=1024 +CONFIG_MIPS_NR_CPU_NR_MAP_1024=y +CONFIG_MIPS_PGD_C0_CONTEXT=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CAVIUM_OCTEON=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_KS8995 is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NR_CPUS=16 +CONFIG_NR_CPUS_DEFAULT_64=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OCTEON_ETHERNET=y +CONFIG_OCTEON_ILM=y +CONFIG_OCTEON_MGMT_ETHERNET=y +CONFIG_OCTEON_WDT=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PATA_OCTEON_CF=y +CONFIG_PATA_TIMINGS=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QCOM_NET_PHYLIB=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGULATOR=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_HOST=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_OCTEON=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OCTEON_EHCI is not set +CONFIG_USB_OCTEON_HCD=y +# CONFIG_USB_OCTEON_OHCI is not set +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USE_OF=y +CONFIG_VFAT_FS=y +CONFIG_VITESSE_PHY=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch b/target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch new file mode 100644 index 0000000000..5381c1d9eb --- /dev/null +++ b/target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch @@ -0,0 +1,116 @@ +--- a/arch/mips/cavium-octeon/octeon-platform.c ++++ b/arch/mips/cavium-octeon/octeon-platform.c +@@ -15,6 +15,7 @@ + #include + + #include ++#include + #include + + #ifdef CONFIG_USB +--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c +@@ -34,6 +34,7 @@ + + #include + ++#include + #include + #include + #include +--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c +@@ -39,6 +39,8 @@ + + #include + ++#include ++ + /** + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass + * 1 doesn't work properly. The following code disables 2nd order +--- a/arch/mips/cavium-octeon/smp.c ++++ b/arch/mips/cavium-octeon/smp.c +@@ -92,6 +92,8 @@ static irqreturn_t mailbox_interrupt(int + return IRQ_HANDLED; + } + ++void octeon_send_ipi_single(int cpu, unsigned int action); ++ + /* + * Cause the function described by call_data to be executed on the passed + * cpu. When the function has finished, increment the finished field of +--- a/arch/mips/mm/c-octeon.c ++++ b/arch/mips/mm/c-octeon.c +@@ -16,6 +16,7 @@ + + #include + #include ++#include + #include + #include + #include +--- /dev/null ++++ b/arch/mips/include/asm/c-octeon.h +@@ -0,0 +1,9 @@ ++#ifndef __C_OCTEON_H__ ++#define __C_OCTEON_H__ ++ ++extern int register_co_cache_error_notifier(struct notifier_block *nb); ++extern int unregister_co_cache_error_notifier(struct notifier_block *nb); ++extern void cache_parity_error_octeon_recoverable(void); ++extern void cache_parity_error_octeon_non_recoverable(void); ++ ++#endif +--- /dev/null ++++ b/drivers/watchdog/octeon-wdt-main.h +@@ -0,0 +1,5 @@ ++#ifdef CONFIG_OCTEON_WDT ++ ++extern void octeon_wdt_nmi_stage3(u64 reg[32]); ++ ++#endif +--- a/drivers/watchdog/octeon-wdt-main.c ++++ b/drivers/watchdog/octeon-wdt-main.c +@@ -64,6 +64,8 @@ + #include + #include + ++#include "octeon-wdt-main.h" ++ + /* Watchdog interrupt major block number (8 MSBs of intsn) */ + #define WD_BLOCK_NUMBER 0x01 + +--- a/arch/mips/include/asm/octeon/pci-octeon.h ++++ b/arch/mips/include/asm/octeon/pci-octeon.h +@@ -24,6 +24,12 @@ + */ + #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) + ++extern int octeon_pci_pcibios_map_irq(const struct pci_dev *dev, u8 slot, ++ u8 pin); ++ ++extern int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, ++ u8 pin); ++ + /* + * pcibios_map_irq() is defined inside pci-octeon.c. All it does is + * call the Octeon specific version pointed to by this variable. This +--- /dev/null ++++ b/arch/mips/include/asm/octeon/cvmx-interrupt-decodes.h +@@ -0,0 +1,6 @@ ++#ifndef __CVMX_INTERRUPT_DECODES_H__ ++#define __CVMX_INTERRUPT_DECODES_H__ ++ ++extern void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block); ++ ++#endif +--- /dev/null ++++ b/arch/mips/include/asm/octeon/octeon-platform.h +@@ -0,0 +1,6 @@ ++#ifndef __OCTEON_PLATFORM_H__ ++#define __OCTEON_PLATFORM_H__ ++ ++extern void octeon_fill_mac_addresses(void); ++ ++#endif diff --git a/target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch b/target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch new file mode 100644 index 0000000000..a7a4ea0ada --- /dev/null +++ b/target/linux/octeon/patches-6.12/100-mips_image_cmdline_hack.patch @@ -0,0 +1,38 @@ +From: John Crispin +Subject: hack: kernel: add generic image_cmdline hack to MIPS targets + +lede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976 +Signed-off-by: Gabor Juhos +--- + arch/mips/Kconfig | 4 ++++ + arch/mips/kernel/head.S | 6 ++++++ + 2 files changed, 10 insertions(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1132,6 +1132,10 @@ config MIPS_MSC + config SYNC_R4K + bool + ++config IMAGE_CMDLINE_HACK ++ bool "OpenWrt specific image command line hack" ++ default n ++ + config NO_IOPORT_MAP + def_bool n + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif /* CONFIG_BOOT_RAW */ + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++ .ascii "CMDLINE:" ++EXPORT(__image_cmdline) ++ .fill 0x400 ++#endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++ + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch b/target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch new file mode 100644 index 0000000000..606debda7f --- /dev/null +++ b/target/linux/octeon/patches-6.12/100-ubnt_edgerouter2_support.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +@@ -174,6 +174,8 @@ int cvmx_helper_board_get_mii_address(in + return 7 - ipd_port; + else + return -1; ++ case CVMX_BOARD_TYPE_UBNT_E200: ++ return -1; + case CVMX_BOARD_TYPE_KONTRON_S1901: + if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) + return 1; diff --git a/target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch b/target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch new file mode 100644 index 0000000000..133e167d2c --- /dev/null +++ b/target/linux/octeon/patches-6.12/110-er200-ethernet_probe_order.patch @@ -0,0 +1,34 @@ +--- a/drivers/staging/octeon/ethernet.c ++++ b/drivers/staging/octeon/ethernet.c +@@ -676,6 +676,7 @@ static int cvm_oct_probe(struct platform + int interface; + int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; + int qos; ++ int i; + struct device_node *pip; + int mtu_overhead = ETH_HLEN + ETH_FCS_LEN; + +@@ -797,13 +798,19 @@ static int cvm_oct_probe(struct platform + } + + num_interfaces = cvmx_helper_get_number_of_interfaces(); +- for (interface = 0; interface < num_interfaces; interface++) { +- cvmx_helper_interface_mode_t imode = +- cvmx_helper_interface_get_mode(interface); +- int num_ports = cvmx_helper_ports_on_interface(interface); ++ for (i = 0; i < num_interfaces; i++) { ++ cvmx_helper_interface_mode_t imode; ++ int interface; ++ int num_ports; + int port; + int port_index; + ++ interface = i; ++ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200) ++ interface = num_interfaces - (i + 1); ++ ++ num_ports = cvmx_helper_ports_on_interface(interface); ++ imode = cvmx_helper_interface_get_mode(interface); + for (port_index = 0, + port = cvmx_helper_get_ipd_port(interface, 0); + port < cvmx_helper_get_ipd_port(interface, num_ports); diff --git a/target/linux/octeon/patches-6.12/120-cmdline-hack.patch b/target/linux/octeon/patches-6.12/120-cmdline-hack.patch new file mode 100644 index 0000000000..fde2f5fd4f --- /dev/null +++ b/target/linux/octeon/patches-6.12/120-cmdline-hack.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/cavium-octeon/setup.c ++++ b/arch/mips/cavium-octeon/setup.c +@@ -653,6 +653,35 @@ void octeon_user_io_init(void) + write_c0_derraddr1(0); + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init octeon_use_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strscpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ return 1; ++} ++#else ++static inline int octeon_use_image_cmdline(void) { return 0; } ++#endif ++ + /** + * prom_init - Early entry point for arch setup + */ +@@ -896,6 +925,8 @@ void __init prom_init(void) + } + } + ++ octeon_use_image_cmdline(); ++ + if (strstr(arcs_cmdline, "console=") == NULL) { + if (octeon_uart == 1) + strcat(arcs_cmdline, " console=ttyS1,115200"); diff --git a/target/linux/octeon/patches-6.12/130-add_itus_support.patch b/target/linux/octeon/patches-6.12/130-add_itus_support.patch new file mode 100644 index 0000000000..fd84a2580a --- /dev/null +++ b/target/linux/octeon/patches-6.12/130-add_itus_support.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/cavium-octeon/octeon-platform.c ++++ b/arch/mips/cavium-octeon/octeon-platform.c +@@ -776,7 +776,7 @@ int __init octeon_prune_device_tree(void + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + +- WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, ++ WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_ITUS_SHIELD, + "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.", + cvmx_board_type_to_string(octeon_bootinfo->board_type)); + +--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h ++++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h +@@ -298,7 +298,7 @@ enum cvmx_board_types_enum { + CVMX_BOARD_TYPE_UBNT_E100 = 20002, + CVMX_BOARD_TYPE_UBNT_E200 = 20003, + CVMX_BOARD_TYPE_UBNT_E220 = 20005, +- CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, ++ CVMX_BOARD_TYPE_ITUS_SHIELD = 20006, + CVMX_BOARD_TYPE_UBNT_E300 = 20300, + CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, + CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, +@@ -403,7 +403,7 @@ static inline const char *cvmx_board_typ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) +- ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N) ++ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) +--- a/arch/mips/pci/pci-octeon.c ++++ b/arch/mips/pci/pci-octeon.c +@@ -211,7 +211,7 @@ const char *octeon_get_pci_interrupts(vo + return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; + case CVMX_BOARD_TYPE_BBGW_REF: + return "AABCD"; +- case CVMX_BOARD_TYPE_CUST_DSR1000N: ++ case CVMX_BOARD_TYPE_ITUS_SHIELD: + return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; + case CVMX_BOARD_TYPE_THUNDER: + case CVMX_BOARD_TYPE_EBH3000: diff --git a/target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch b/target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch new file mode 100644 index 0000000000..bbd17af38e --- /dev/null +++ b/target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch @@ -0,0 +1,46 @@ +--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h ++++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h +@@ -297,6 +297,7 @@ enum cvmx_board_types_enum { + CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, + CVMX_BOARD_TYPE_UBNT_E200 = 20003, ++ CVMX_BOARD_TYPE_UBNT_USG = 20004, + CVMX_BOARD_TYPE_UBNT_E220 = 20005, + CVMX_BOARD_TYPE_ITUS_SHIELD = 20006, + CVMX_BOARD_TYPE_UBNT_E300 = 20300, +@@ -401,6 +402,7 @@ static inline const char *cvmx_board_typ + /* Customer private range */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) ++ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_USG) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD) +--- a/arch/mips/cavium-octeon/octeon-platform.c ++++ b/arch/mips/cavium-octeon/octeon-platform.c +@@ -637,6 +637,7 @@ static void __init octeon_rx_tx_delay(in + } + break; + case CVMX_BOARD_TYPE_UBNT_E100: ++ case CVMX_BOARD_TYPE_UBNT_USG: + if (iface == 0 && port <= 2) { + _octeon_rx_tx_delay(eth, 0x0, 0x10); + return; +--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +@@ -170,6 +170,7 @@ int cvmx_helper_board_get_mii_address(in + else + return -1; + case CVMX_BOARD_TYPE_UBNT_E100: ++ case CVMX_BOARD_TYPE_UBNT_USG: + if (ipd_port >= 0 && ipd_port <= 2) + return 7 - ipd_port; + else +@@ -337,6 +338,7 @@ enum cvmx_helper_board_usb_clock_types _ + case CVMX_BOARD_TYPE_LANAI2_G: + case CVMX_BOARD_TYPE_NIC10E_66: + case CVMX_BOARD_TYPE_UBNT_E100: ++ case CVMX_BOARD_TYPE_UBNT_USG: + return USB_CLOCK_TYPE_CRYSTAL_12; + case CVMX_BOARD_TYPE_NIC10E: + return USB_CLOCK_TYPE_REF_12; diff --git a/target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch b/target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch new file mode 100644 index 0000000000..abc9f39c1a --- /dev/null +++ b/target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch @@ -0,0 +1,90 @@ +commit eb6c3ba1d42fd087708f568ca220ff557f22104e +Author: Jakob Haufe +Date: Tue Jun 17 13:58:19 2025 +0200 + + MIPS: OCTEON: Add UBNT specific DTS pruning + + This imports device specific DTS pruning from + https://github.com/UI-Packages/kernel_e200/blob/master/arch/mips/cavium-octeon/octeon-platform.c#L1067 + + - Reduce MMC clock frequency on E200/E220 to make + MMC communication reliable again. See linked issue. + - Remove unused MMC node on E300. + + Related: https://github.com/openwrt/openwrt/issues/13762 + + Signed-off-by: Jakob Haufe + +--- a/arch/mips/cavium-octeon/octeon-platform.c ++++ b/arch/mips/cavium-octeon/octeon-platform.c +@@ -1134,6 +1134,41 @@ end_led: + } + #endif + ++ ++ return 0; ++} ++ ++int __init ubnt_prune_device_tree(void) ++{ ++ /* MMC on UBNT */ ++ pr_info("UBNT board DTS pruning...\n"); ++ if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E300) { ++ pr_info("UBNT E300 found, looking for mmc-slot@2\n"); ++ // Remove unused MMC slot definition ++ int mmc_slot2 = fdt_path_offset(initial_boot_params, "/soc/mmc/mmc-slot@2"); ++ ++ if (mmc_slot2 > 0) { ++ pr_info("UBNT E300 found, deleting mmc-slot@2\n"); ++ fdt_nop_node(initial_boot_params, mmc_slot2); ++ } else { ++ pr_info("mmc-slot@2 not found\n"); ++ } ++ } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E200 || ++ octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E220) { ++ pr_info("UBNT E200/E220 found, looking for mmc-slot@0\n"); ++ int mmc_slot0 = fdt_path_offset(initial_boot_params, "/soc/mmc/mmc-slot@0"); ++ ++ u32 freq = 26000000; ++ ++ if (mmc_slot0 > 0) { ++ pr_info("UBNT E200/E220 mmc-slot@0 found, setting frequency to 26MHz"); ++ fdt_setprop_inplace_cell(initial_boot_params, mmc_slot0, ++ "spi-max-frequency", freq); ++ } else { ++ pr_info("mmc-slot@0 not found\n"); ++ } ++ } ++ + return 0; + } + +--- a/arch/mips/cavium-octeon/setup.c ++++ b/arch/mips/cavium-octeon/setup.c +@@ -43,6 +43,7 @@ + #include + + #include ++#include + #include + #include + +@@ -1207,6 +1208,9 @@ void __init device_tree_init(void) + octeon_prune_device_tree(); + pr_info("Using internal Device Tree.\n"); + } ++ ++ ubnt_prune_device_tree(); ++ + if (fill_mac) + octeon_fill_mac_addresses(); + unflatten_and_copy_device_tree(); +--- a/arch/mips/include/asm/octeon/octeon-platform.h ++++ b/arch/mips/include/asm/octeon/octeon-platform.h +@@ -2,5 +2,6 @@ + #define __OCTEON_PLATFORM_H__ + + extern void octeon_fill_mac_addresses(void); ++extern int ubnt_prune_device_tree(void); + + #endif diff --git a/target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch b/target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch new file mode 100644 index 0000000000..22f284b2c0 --- /dev/null +++ b/target/linux/octeon/patches-6.12/700-allocate_interface_by_label.patch @@ -0,0 +1,37 @@ +From: Roman Kuzmitskii +Date: Wed, 28 Oct 2020 19:00:00 +0000 +Subject: [PATCH] staging: octeon: add net-labels support + +With this patch, device name can be set within dts file +in the same way as dsa port can. + +Add label to pip interface node to use this feature: +label = "lan0"; + +Tested-by: Johannes Kimmel +Signed-off-by: Roman Kuzmitskii +--- a/drivers/staging/octeon/ethernet.c ++++ b/drivers/staging/octeon/ethernet.c +@@ -407,8 +407,12 @@ static int cvm_oct_common_set_mac_addres + int cvm_oct_common_init(struct net_device *dev) + { + struct octeon_ethernet *priv = netdev_priv(dev); ++ const u8 *label = NULL; + int ret; + ++ if (priv->of_node) ++ label = of_get_property(priv->of_node, "label", NULL); ++ + ret = of_get_ethdev_address(priv->of_node, dev); + if (ret) + eth_hw_addr_random(dev); +@@ -441,6 +445,9 @@ int cvm_oct_common_init(struct net_devic + if (dev->netdev_ops->ndo_stop) + dev->netdev_ops->ndo_stop(dev); + ++ if (!IS_ERR_OR_NULL(label)) ++ dev_alloc_name(dev, label); ++ + return 0; + } + diff --git a/target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch b/target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch new file mode 100644 index 0000000000..fdfbc233ab --- /dev/null +++ b/target/linux/octeon/patches-6.12/701-honor_sgmii_node_device_tree_status.patch @@ -0,0 +1,27 @@ +From: Roman Kuzmitskii +Date: Sun, 01 Nov 2020 19:00:00 +0000 +Subject: [PATCH] staging: octeon: sgmii to honor disabled dt node status + +With this patch, sgmii interface device tree node could be disabled and +that disabled interface will not be unnecessarily initialized. + +It solves the problem with Octeon boards that have 8 sgmii or more ports +initialized but have nothing connected to them. + +Tested-by: Johannes Kimmel +Signed-off-by: Roman Kuzmitskii +--- a/drivers/staging/octeon/ethernet.c ++++ b/drivers/staging/octeon/ethernet.c +@@ -877,8 +877,10 @@ static int cvm_oct_probe(struct platform + + case CVMX_HELPER_INTERFACE_MODE_SGMII: + priv->phy_mode = PHY_INTERFACE_MODE_SGMII; +- dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; +- strscpy(dev->name, "eth%d", sizeof(dev->name)); ++ if (of_device_is_available(priv->of_node)) { ++ dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; ++ strscpy(dev->name, "eth%d", sizeof(dev->name)); ++ } + break; + + case CVMX_HELPER_INTERFACE_MODE_SPI: diff --git a/target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch b/target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch new file mode 100644 index 0000000000..ed405e88c0 --- /dev/null +++ b/target/linux/octeon/patches-6.12/702-qca833x-force-pcs-reset.patch @@ -0,0 +1,123 @@ +From: Andrew LaMarche +Date: Mon, 31 Mar 2025 13:00:00 +0000 +Subject: [PATCH] octeon: force pcs reset + +QCA833x devices misbehave with SGMII until a PCS reset is triggered. U-boot has +a newer vendor GPL dump that contains logic to reset the PCS. This patch +backports that functionality so that Octeon devices with QCA833{4/7} switchs +pass traffic between the switch and CPU. + +References: +- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L197-L225 +- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L701-L737 + +Signed-off-by: Andrew LaMarche +--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +@@ -125,6 +125,17 @@ static int __cvmx_helper_sgmii_hardware_ + return 0; + } + ++static int __cvmx_helper_need_g15618(void) ++{ ++ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM || ++ OCTEON_IS_MODEL(OCTEON_CN63XX) || ++ OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) || ++ OCTEON_IS_MODEL(OCTEON_CN68XX)) ++ return 1; ++ else ++ return 0; ++} ++ + /** + * Initialize the SERTES link for the first time or after a loss + * of link. +@@ -172,6 +183,39 @@ static int __cvmx_helper_sgmii_hardware_ + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + control_reg.u64); + ++ /* Force a PCS reset by powering down the PCS interface ++ * This is needed to deal with broken Qualcomm/Atheros PHYs and switches ++ * which never recover if PCS is not power cycled. The alternative ++ * is to power cycle or hardware reset the Qualcomm devices whenever ++ * SGMII is initialized. ++ * ++ * This is needed for the QCA8033 PHYs as well as the QCA833X switches ++ * to work. The QCA8337 switch has additional SGMII problems and is ++ * best avoided if at all possible. Failure to power cycle PCS prevents ++ * any traffic from flowing between Octeon and Qualcomm devices if there ++ * is a warm reset. Even a software reset to the Qualcomm device will ++ * not work. ++ * ++ * Note that this problem has been reported between Qualcomm and other ++ * vendor's processors as well so this problem is not unique to ++ * Qualcomm and Octeon. ++ * ++ * Power cycling PCS doesn't hurt anything with non-Qualcomm devices ++ * other than adding a 25ms delay during initialization. ++ */ ++ control_reg.s.pwr_dn = 1; ++ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), ++ control_reg.u64); ++ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); ++ ++ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) ++ /* 25ms should be enough, 10ms is too short */ ++ mdelay(25); ++ ++ control_reg.s.pwr_dn = 0; ++ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), ++ control_reg.u64); ++ + /* + * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating + * that sgmii autonegotiation is complete. In MAC mode this +@@ -507,9 +551,47 @@ union cvmx_helper_link_info __cvmx_helpe + int __cvmx_helper_sgmii_link_set(int ipd_port, + union cvmx_helper_link_info link_info) + { ++ union cvmx_pcsx_mrx_control_reg control_reg; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); +- __cvmx_helper_sgmii_hardware_init_link(interface, index); ++ ++ /* For some devices, i.e. the Qualcomm QCA8337 switch we need to power ++ * down the PCS interface when the link goes down and power it back ++ * up when the link returns. ++ */ ++ if (link_info.s.link_up || !__cvmx_helper_need_g15618()) { ++ __cvmx_helper_sgmii_hardware_init_link(interface, index); ++ } else { ++ union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; ++ ++ pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); ++ ++ /* Disable autonegotiation when MAC mode is enabled or ++ * autonegotiation is disabled. ++ */ ++ control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); ++ if (pcsx_miscx_ctl_reg.s.mac_phy == 0 || ++ !cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface))) { ++ ++ control_reg.s.an_en = 0; ++ control_reg.s.spdmsb = 1; ++ control_reg.s.spdlsb = 0; ++ control_reg.s.dup = 1; ++ ++ } ++ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), ++ control_reg.u64); ++ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); ++ /* ++ * Use GMXENO to force the link down it will get ++ * reenabled later... ++ */ ++ pcsx_miscx_ctl_reg.s.gmxeno = 1; ++ cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), ++ pcsx_miscx_ctl_reg.u64); ++ cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); ++ return 0; ++ } + return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, + link_info); + } From 95d7a8f1b1bb717e21c99adb6f25bdd1cf9dda49 Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Tue, 21 Apr 2026 14:01:57 +0000 Subject: [PATCH 23/46] octeon: refresh 6.18 kernel config Add missing symbols for 6.18. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- target/linux/octeon/config-6.18 | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/linux/octeon/config-6.18 b/target/linux/octeon/config-6.18 index 6c58cb76a8..341d95cbbc 100644 --- a/target/linux/octeon/config-6.18 +++ b/target/linux/octeon/config-6.18 @@ -16,6 +16,7 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BUFFER_HEAD=y CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="" CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0 CONFIG_CAVIUM_OCTEON_LOCK_L2=y @@ -73,11 +74,14 @@ CONFIG_EARLY_PRINTK=y CONFIG_EDAC=y CONFIG_EDAC_ATOMIC_SCRUB=y # CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_ECS is not set CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_MEM_REPAIR is not set CONFIG_EDAC_OCTEON_L2C=y CONFIG_EDAC_OCTEON_LMC=y CONFIG_EDAC_OCTEON_PC=y CONFIG_EDAC_OCTEON_PCI=y +# CONFIG_EDAC_SCRUB is not set CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y @@ -194,6 +198,7 @@ CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=11 CONFIG_PAGE_POOL=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y From 1cf45adb3ba9e702a380305a34b17257f7ae7e51 Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Tue, 21 Apr 2026 18:19:01 +0000 Subject: [PATCH 24/46] octeon: refresh 6.18 patches Refresh patches for 6.18. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- .../octeon/patches-6.18/000-fix-octeon-kernel-build.patch | 4 ++-- .../octeon/patches-6.18/100-mips_image_cmdline_hack.patch | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch b/target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch index 5381c1d9eb..adea180423 100644 --- a/target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch +++ b/target/linux/octeon/patches-6.18/000-fix-octeon-kernel-build.patch @@ -1,7 +1,7 @@ --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c -@@ -15,6 +15,7 @@ - #include +@@ -16,6 +16,7 @@ + #include #include +#include diff --git a/target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch b/target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch index a7a4ea0ada..b55da2f5f6 100644 --- a/target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch +++ b/target/linux/octeon/patches-6.18/100-mips_image_cmdline_hack.patch @@ -10,7 +10,7 @@ Signed-off-by: Gabor Juhos --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1132,6 +1132,10 @@ config MIPS_MSC +@@ -1178,6 +1178,10 @@ config MIPS_MSC config SYNC_R4K bool @@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S -@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry) +@@ -81,6 +81,12 @@ FEXPORT(__kernel_entry) j kernel_entry #endif /* CONFIG_BOOT_RAW */ From 907dd7bd93b92fa62ada2d77e36d93b6c8f63385 Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Wed, 22 Apr 2026 12:24:10 +0000 Subject: [PATCH 25/46] kernel: crypto: fix build with Linux >= 6.18 after octeon-md5 removal Linux commit c9e5ac0 ("lib/crypto: mips/md5: Migrate optimized code into library") removed the MIPS-Octeon-specific MD5 implementation (octeon-md5.ko) and replaced it with an optimized library implementation in lib/crypto. As a result, CONFIG_CRYPTO_MD5_OCTEON and the module arch/mips/crypto/octeon-md5.ko no longer exist in kernels >= 6.18. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- package/kernel/linux/modules/crypto.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk index 650fdd598f..aa8a52ec5f 100644 --- a/package/kernel/linux/modules/crypto.mk +++ b/package/kernel/linux/modules/crypto.mk @@ -740,7 +740,7 @@ define KernelPackage/crypto-md5 DEPENDS:=+kmod-crypto-hash KCONFIG:= \ CONFIG_CRYPTO_MD5 \ - CONFIG_CRYPTO_MD5_OCTEON \ + CONFIG_CRYPTO_MD5_OCTEON@lt6.18 \ CONFIG_CRYPTO_MD5_PPC@lt6.18 FILES:=$(LINUX_DIR)/crypto/md5.ko \ $(LINUX_DIR)/lib/crypto/libmd5.ko@ge6.18 @@ -749,8 +749,8 @@ define KernelPackage/crypto-md5 endef define KernelPackage/crypto-md5/octeon - FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko - AUTOLOAD+=$(call AutoLoad,09,octeon-md5) + FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko@lt6.18 + AUTOLOAD+=$(call AutoLoad,09,LINUX_6_12:octeon-md5) endef define KernelPackage/crypto-md5/powerpc From d1f240f03750a055f5c2d5594e3399dcae16add5 Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Tue, 21 Apr 2026 13:55:41 +0000 Subject: [PATCH 26/46] octeon: enable 6.18 testing kernel Enable the 6.18 testing kernel for Octeon. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/23031 Signed-off-by: Nick Hainke --- target/linux/octeon/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/octeon/Makefile b/target/linux/octeon/Makefile index f31badfbb6..6766f743d0 100644 --- a/target/linux/octeon/Makefile +++ b/target/linux/octeon/Makefile @@ -11,6 +11,7 @@ FEATURES:=squashfs ramdisk pci usb CPU_TYPE:=octeonplus KERNEL_PATCHVER:=6.12 +KERNEL_TESTING_PATCHVER:=6.18 define Target/Description Build firmware images for Cavium Networks Octeon-based boards. From 4f59715716fb1778168ec736a0786bf73a1390d2 Mon Sep 17 00:00:00 2001 From: Qingfang Deng Date: Sat, 25 Apr 2026 11:32:34 +0800 Subject: [PATCH 27/46] ntfs: update to 2026-04-25 Update to the latest version, and fix build on targets without FS_POSIX_ACL. Signed-off-by: Qingfang Deng Link: https://github.com/openwrt/openwrt/pull/23090 Signed-off-by: Hauke Mehrtens --- package/kernel/ntfs/Makefile | 9 ++++----- .../patches/001-conditionally-enable-posix-acl.patch | 11 +++++++++++ 2 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 package/kernel/ntfs/patches/001-conditionally-enable-posix-acl.patch diff --git a/package/kernel/ntfs/Makefile b/package/kernel/ntfs/Makefile index 52556c2b31..4dc8c5bc64 100644 --- a/package/kernel/ntfs/Makefile +++ b/package/kernel/ntfs/Makefile @@ -5,11 +5,11 @@ PKG_NAME:=linux-ntfs PKG_RELEASE:=1 PKG_BUILD_PARALLEL:=1 -PKG_SOURCE_DATE:=2026-03-03 +PKG_SOURCE_DATE:=2026-04-25 PKG_SOURCE_URL:=https://github.com/namjaejeon/linux-ntfs PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=6f6beff9ac623c691e8da7455a0e9b14bf957108 -PKG_MIRROR_HASH:=b11f051e41e9993421753961bf948380bdf705a043a83f9b55dcbd7dc664fae2 +PKG_SOURCE_VERSION:=ce7495f3e5c6a0b85d3350c18bbc06370cdcceb5 +PKG_MIRROR_HASH:=0815623624dae868c3ca0ae82cf57ebf5d19e6b42778e2b9d241f85369fe348f PKG_LICENSE:=GPL-2.0-or-later @@ -35,8 +35,7 @@ define KernelPackage/fs-ntfs/description endef NOSTDINC_FLAGS += \ - $(KERNEL_NOSTDINC_FLAGS) \ - -DCONFIG_NTFS_FS_POSIX_ACL + $(KERNEL_NOSTDINC_FLAGS) EXTRA_KCONFIG:= \ CONFIG_NTFS_FS=m diff --git a/package/kernel/ntfs/patches/001-conditionally-enable-posix-acl.patch b/package/kernel/ntfs/patches/001-conditionally-enable-posix-acl.patch new file mode 100644 index 0000000000..1e681489fe --- /dev/null +++ b/package/kernel/ntfs/patches/001-conditionally-enable-posix-acl.patch @@ -0,0 +1,11 @@ +--- a/Makefile ++++ b/Makefile +@@ -9,7 +9,7 @@ ntfs-y := aops.o attrib.o collate.o dir. + iomap.o debug.o sysctl.o quota.o object_id.o bdev-io.o + + ccflags-$(CONFIG_NTFS_DEBUG) += -DDEBUG +-ccflags-y += -DCONFIG_NTFS_FS_POSIX_ACL ++ccflags-$(CONFIG_FS_POSIX_ACL) += -DCONFIG_NTFS_FS_POSIX_ACL + else + # Called from external kernel module build + From 5dbe94d972314ee26826c142822efd901e75dbf9 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 28 Mar 2026 16:19:20 +0800 Subject: [PATCH 28/46] airoha: disable afe by default for an7581 The audio should only be enabled when the sound node is enabled. This fixes the following error: an7581-audio 1fbe2200.afe: probe with driver an7581-audio failed with error -2 Fixes: 7b55651 ("airoha: enable I2S sound driver and add nodes for eMMC RFB board") Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/22660 Signed-off-by: Hauke Mehrtens --- target/linux/airoha/dts/an7581-evb-emmc.dtsi | 4 ++++ target/linux/airoha/dts/an7581.dtsi | 1 + 2 files changed, 5 insertions(+) diff --git a/target/linux/airoha/dts/an7581-evb-emmc.dtsi b/target/linux/airoha/dts/an7581-evb-emmc.dtsi index d7ce37df2d..8201442566 100644 --- a/target/linux/airoha/dts/an7581-evb-emmc.dtsi +++ b/target/linux/airoha/dts/an7581-evb-emmc.dtsi @@ -5,6 +5,10 @@ #include #include "an7581.dtsi" +&afe { + status = "okay"; +}; + &sound { audio-routing = "Headphone", "HP_L", "Headphone", "HP_R", diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi index 056e593f39..acddd89cf0 100644 --- a/target/linux/airoha/dts/an7581.dtsi +++ b/target/linux/airoha/dts/an7581.dtsi @@ -439,6 +439,7 @@ reg = <0x0 0x1fbe2200 0x0 0x9000>; interrupts = ; + status = "disabled"; }; uart4: serial@1fbf0600 { From c686aab3402d024c0160faba5408c981a4f4c7d8 Mon Sep 17 00:00:00 2001 From: Rye Sears Date: Thu, 9 Apr 2026 00:58:51 +0000 Subject: [PATCH 29/46] x86: enable HYPERV_VMBUS enable HYPERV_VMBUS in x86/generic and x86/64. Fixes: #22846 Signed-off-by: Rye Sears Link: https://github.com/openwrt/openwrt/pull/22860 Signed-off-by: Hauke Mehrtens --- target/linux/x86/64/config-6.18 | 1 + target/linux/x86/generic/config-6.18 | 1 + 2 files changed, 2 insertions(+) diff --git a/target/linux/x86/64/config-6.18 b/target/linux/x86/64/config-6.18 index 069cae2cb6..dbc4835bf3 100644 --- a/target/linux/x86/64/config-6.18 +++ b/target/linux/x86/64/config-6.18 @@ -262,6 +262,7 @@ CONFIG_HYPERV_STORAGE=y # CONFIG_HYPERV_TESTING is not set CONFIG_HYPERV_TIMER=y CONFIG_HYPERV_UTILS=y +CONFIG_HYPERV_VMBUS=y # CONFIG_HYPERV_VSOCKETS is not set # CONFIG_HYPERV_VTL_MODE is not set # CONFIG_I2C_AMD_MP2 is not set diff --git a/target/linux/x86/generic/config-6.18 b/target/linux/x86/generic/config-6.18 index f5e83a8688..959d2b7e8f 100644 --- a/target/linux/x86/generic/config-6.18 +++ b/target/linux/x86/generic/config-6.18 @@ -186,6 +186,7 @@ CONFIG_HYPERV_STORAGE=y # CONFIG_HYPERV_TESTING is not set CONFIG_HYPERV_TIMER=y CONFIG_HYPERV_UTILS=y +CONFIG_HYPERV_VMBUS=y # CONFIG_I2C_AMD_MP2 is not set # CONFIG_I2C_ZHAOXIN is not set # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set From 7255109cad4f13413436d48ae5dd74676c3125ca Mon Sep 17 00:00:00 2001 From: Rany Hany Date: Thu, 26 Mar 2026 19:16:37 +0200 Subject: [PATCH 30/46] wifi-scripts: ucode: add bridge_isolate and network_vlan to schema These were missing from schema. Add them. Fixes: https://github.com/openwrt/openwrt/issues/22620 Signed-off-by: Rany Hany Link: https://github.com/openwrt/openwrt/pull/22617 [Reordered attributes] Signed-off-by: Hauke Mehrtens --- .../usr/share/schema/wireless.wifi-iface.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-iface.json b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-iface.json index 61d0da0170..bd8a8247b1 100644 --- a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-iface.json +++ b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-iface.json @@ -169,6 +169,10 @@ "description": "Management frame protection for Beacon frames", "type": "boolean" }, + "bridge_isolate": { + "description": "Enable bridge port isolation for the wireless interface", + "type": "boolean" + }, "bss_load_update_period": { "description": "BSS Load update period (in BUs)", "type": "number", @@ -760,6 +764,13 @@ "description": "Network Authentication Type", "type": "string" }, + "network_vlan": { + "description": "Make a wireless interface a tagged member of extra VLANs", + "type": "array", + "items": { + "type": "string" + } + }, "no_probe_resp_if_max_sta": { "description": "Do not answer probe requests if iface_max_num_sta was reached", "type": "boolean" From 5968b584bab92ef5ac8384e27e5bdd08e6e66924 Mon Sep 17 00:00:00 2001 From: Rany Hany Date: Mon, 20 Apr 2026 12:47:26 +0300 Subject: [PATCH 31/46] wifi-scripts: ucode: add missing fields for station/vlan schema This adds the missing 'iface' field for both station and VLAN. On VLAN, we add all network_config_attr to the schema as well per wireless.uc. Fixes: https://github.com/openwrt/openwrt/issues/22165 Signed-off-by: Rany Hany Link: https://github.com/openwrt/openwrt/pull/22617 Signed-off-by: Hauke Mehrtens --- .../share/schema/wireless.wifi-station.json | 7 ++++ .../usr/share/schema/wireless.wifi-vlan.json | 37 +++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-station.json b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-station.json index b594da8b4a..2cf08f2104 100644 --- a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-station.json +++ b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-station.json @@ -4,6 +4,13 @@ "description": "OpenWrt WiFi Station Schema", "type": "object", "properties": { + "iface": { + "description": "List of interfaces this station is associated with", + "type": "array", + "items": { + "type": "string" + } + }, "mac": { "description": "The station's MAC addresses", "type": "array", diff --git a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-vlan.json b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-vlan.json index a06c8dabf0..988a254cec 100644 --- a/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-vlan.json +++ b/package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-vlan.json @@ -4,10 +4,47 @@ "description": "OpenWrt WiFi VLAN Schema", "type": "object", "properties": { + "bridge_isolate": { + "description": "Enable bridge port isolation for the wireless interface", + "type": "boolean" + }, + "iface": { + "description": "List of interfaces this VLAN is associated with", + "type": "array", + "items": { + "type": "string" + } + }, + "isolate": { + "description": "Isolates wireless clients from each other", + "type": "boolean" + }, + "multicast_to_unicast": { + "description": "Request that the AP will do multicast-to-unicast conversion for ARP, IPv4, and IPv6 frames", + "type": "boolean" + }, "name": { "description": "VLAN name", "type": "string" }, + "network": { + "description": "Specifies one or multiple logical network interfaces declared in the network configuration, each one should be a L3 bridge to be able to attach this L2 wireless interface.", + "type": "array", + "items": { + "type": "string" + } + }, + "network_vlan": { + "description": "Make a wireless interface a tagged member of extra VLANs", + "type": "array", + "items": { + "type": "string" + } + }, + "proxy_arp": { + "description": "Proxy ARP", + "type": "boolean" + }, "vid": { "description": "VLAN ID", "type": "string" From ba7aa2a97153d225165115db656314548b8ddf91 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 25 Jan 2026 23:18:02 +0800 Subject: [PATCH 32/46] generic: backport MSI affinity support for DW PCIe Currently, the DesignWare PCIe driver cannot configure interrupts on SoC that do not support MSIX. All MSI interrupts are handled by CPU0. Backport MSI affinity support for the PCI dwc driver from linux-next, so now we can adjust MSI interrupts to other CPU cores. Tested on HINLINK H28K (RK3528) and OrangePi R2S (Ky X1). Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/21770 Signed-off-by: Hauke Mehrtens --- ...dw_pcie_suspend_noirq-dw_pcie_resume.patch | 57 ++++ ...elper-for-creating-MSI-parent-irq-do.patch | 70 ++++ ...ake-irq-msi-lib.h-globally-available.patch | 229 +++++++++++++ ...-msi-lib-Fix-build-with-PCI-disabled.patch | 34 ++ ...port-DWC-MSI-controller-related-APIs.patch | 144 ++++++++ ...itch-to-msi_create_parent_irq_domain.patch | 145 ++++++++ ...e-hwirq-parameter-to-irq_hw_number_t.patch | 66 ++++ ...interrupt-redirection-infrastructure.patch | 319 ++++++++++++++++++ .../908-2-v7.0-PCI-dwc-Code-cleanup.patch | 242 +++++++++++++ ...-PCI-dwc-Enable-MSI-affinity-support.patch | 92 +++++ ...fective-affinity-for-redirected-inte.patch | 56 +++ ...e-hwirq-parameter-to-irq_hw_number_t.patch | 66 ++++ ...interrupt-redirection-infrastructure.patch | 319 ++++++++++++++++++ .../908-2-v7.0-PCI-dwc-Code-cleanup.patch | 242 +++++++++++++ ...-PCI-dwc-Enable-MSI-affinity-support.patch | 92 +++++ ...fective-affinity-for-redirected-inte.patch | 56 +++ ...ci-dw-pcie-add-support-for-sf21-pcie.patch | 2 +- 17 files changed, 2230 insertions(+), 1 deletion(-) create mode 100644 target/linux/generic/backport-6.12/901-v6.14-PCI-dwc-Add-dw_pcie_suspend_noirq-dw_pcie_resume.patch create mode 100644 target/linux/generic/backport-6.12/902-v6.16-genirq-msi-Add-helper-for-creating-MSI-parent-irq-do.patch create mode 100644 target/linux/generic/backport-6.12/903-v6.16-irqchip-Make-irq-msi-lib.h-globally-available.patch create mode 100644 target/linux/generic/backport-6.12/904-v6.16-irqchip-irq-msi-lib-Fix-build-with-PCI-disabled.patch create mode 100644 target/linux/generic/backport-6.12/905-v6.17-PCI-dwc-Export-DWC-MSI-controller-related-APIs.patch create mode 100644 target/linux/generic/backport-6.12/906-v6.17-PCI-dwc-Switch-to-msi_create_parent_irq_domain.patch create mode 100644 target/linux/generic/backport-6.12/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch create mode 100644 target/linux/generic/backport-6.12/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch create mode 100644 target/linux/generic/backport-6.12/908-2-v7.0-PCI-dwc-Code-cleanup.patch create mode 100644 target/linux/generic/backport-6.12/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch create mode 100644 target/linux/generic/backport-6.12/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch create mode 100644 target/linux/generic/backport-6.18/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch create mode 100644 target/linux/generic/backport-6.18/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch create mode 100644 target/linux/generic/backport-6.18/908-2-v7.0-PCI-dwc-Code-cleanup.patch create mode 100644 target/linux/generic/backport-6.18/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch create mode 100644 target/linux/generic/backport-6.18/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch diff --git a/target/linux/generic/backport-6.12/901-v6.14-PCI-dwc-Add-dw_pcie_suspend_noirq-dw_pcie_resume.patch b/target/linux/generic/backport-6.12/901-v6.14-PCI-dwc-Add-dw_pcie_suspend_noirq-dw_pcie_resume.patch new file mode 100644 index 0000000000..45b1b397e8 --- /dev/null +++ b/target/linux/generic/backport-6.12/901-v6.14-PCI-dwc-Add-dw_pcie_suspend_noirq-dw_pcie_resume.patch @@ -0,0 +1,57 @@ +From ec57335b81d8fcf3088994c532b5ca21e839616a Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Fri, 17 Jan 2025 15:03:04 -0600 +Subject: [PATCH] PCI: dwc: Add dw_pcie_suspend_noirq(), + dw_pcie_resume_noirq() stubs for !CONFIG_PCIE_DW_HOST + +Previously pcie-designware.h declared dw_pcie_suspend_noirq() and +dw_pcie_resume_noirq() unconditionally, even though they were only +implemented when CONFIG_PCIE_DW_HOST was defined. + +Add no-op stubs for them when CONFIG_PCIE_DW_HOST is not defined so +drivers that support both Root Complex and Endpoint modes don't need + +Link: https://lore.kernel.org/r/20250117213810.GA656803@bhelgaas +Signed-off-by: Bjorn Helgaas +--- + drivers/pci/controller/dwc/pcie-designware.h | 15 ++++++++++++--- + 1 file changed, 12 insertions(+), 3 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -498,9 +498,6 @@ void dw_pcie_iatu_detect(struct dw_pcie + int dw_pcie_edma_detect(struct dw_pcie *pci); + void dw_pcie_edma_remove(struct dw_pcie *pci); + +-int dw_pcie_suspend_noirq(struct dw_pcie *pci); +-int dw_pcie_resume_noirq(struct dw_pcie *pci); +- + static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) + { + dw_pcie_write_dbi(pci, reg, 0x4, val); +@@ -678,6 +675,8 @@ static inline enum dw_pcie_ltssm dw_pcie + } + + #ifdef CONFIG_PCIE_DW_HOST ++int dw_pcie_suspend_noirq(struct dw_pcie *pci); ++int dw_pcie_resume_noirq(struct dw_pcie *pci); + irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); + int dw_pcie_setup_rc(struct dw_pcie_rp *pp); + int dw_pcie_host_init(struct dw_pcie_rp *pp); +@@ -686,6 +685,16 @@ int dw_pcie_allocate_domains(struct dw_p + void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); + #else ++static inline int dw_pcie_suspend_noirq(struct dw_pcie *pci) ++{ ++ return 0; ++} ++ ++static inline int dw_pcie_resume_noirq(struct dw_pcie *pci) ++{ ++ return 0; ++} ++ + static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) + { + return IRQ_NONE; diff --git a/target/linux/generic/backport-6.12/902-v6.16-genirq-msi-Add-helper-for-creating-MSI-parent-irq-do.patch b/target/linux/generic/backport-6.12/902-v6.16-genirq-msi-Add-helper-for-creating-MSI-parent-irq-do.patch new file mode 100644 index 0000000000..f5ed73669a --- /dev/null +++ b/target/linux/generic/backport-6.12/902-v6.16-genirq-msi-Add-helper-for-creating-MSI-parent-irq-do.patch @@ -0,0 +1,70 @@ +From e4d001b54f78769ba1a1404c2801ae95e19fd893 Mon Sep 17 00:00:00 2001 +From: Marc Zyngier +Date: Tue, 13 May 2025 18:28:12 +0100 +Subject: [PATCH] genirq/msi: Add helper for creating MSI-parent irq + domains + +Creating an irq domain that serves as an MSI parent requires +a substantial amount of esoteric boiler-plate code, some of +which is often provided twice (such as the bus token). + +To make things a bit simpler for the unsuspecting MSI tinkerer, +provide a helper that does it for them, and serves as documentation +of what needs to be provided. + +Signed-off-by: Marc Zyngier +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250513172819.2216709-3-maz@kernel.org +--- + include/linux/msi.h | 4 ++++ + kernel/irq/msi.c | 26 ++++++++++++++++++++++++++ + 2 files changed, 30 insertions(+) + +--- a/include/linux/msi.h ++++ b/include/linux/msi.h +@@ -586,6 +586,10 @@ struct irq_domain *msi_create_irq_domain + struct msi_domain_info *info, + struct irq_domain *parent); + ++struct irq_domain_info; ++struct irq_domain *msi_create_parent_irq_domain(struct irq_domain_info *info, ++ const struct msi_parent_ops *msi_parent_ops); ++ + bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, + const struct msi_domain_template *template, + unsigned int hwsize, void *domain_data, +--- a/kernel/irq/msi.c ++++ b/kernel/irq/msi.c +@@ -886,6 +886,32 @@ struct irq_domain *msi_create_irq_domain + } + + /** ++ * msi_create_parent_irq_domain - Create an MSI-parent interrupt domain ++ * @info: MSI irqdomain creation info ++ * @msi_parent_ops: MSI parent callbacks and configuration ++ * ++ * Return: pointer to the created &struct irq_domain or %NULL on failure ++ */ ++struct irq_domain *msi_create_parent_irq_domain(struct irq_domain_info *info, ++ const struct msi_parent_ops *msi_parent_ops) ++{ ++ struct irq_domain *d; ++ ++ info->hwirq_max = max(info->hwirq_max, info->size); ++ info->size = info->hwirq_max; ++ info->domain_flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; ++ info->bus_token = msi_parent_ops->bus_select_token; ++ ++ d = irq_domain_instantiate(info); ++ if (IS_ERR(d)) ++ return NULL; ++ ++ d->msi_parent_ops = msi_parent_ops; ++ return d; ++} ++EXPORT_SYMBOL_GPL(msi_create_parent_irq_domain); ++ ++/** + * msi_parent_init_dev_msi_info - Delegate initialization of device MSI info down + * in the domain hierarchy + * @dev: The device for which the domain should be created diff --git a/target/linux/generic/backport-6.12/903-v6.16-irqchip-Make-irq-msi-lib.h-globally-available.patch b/target/linux/generic/backport-6.12/903-v6.16-irqchip-Make-irq-msi-lib.h-globally-available.patch new file mode 100644 index 0000000000..bf36bcdeba --- /dev/null +++ b/target/linux/generic/backport-6.12/903-v6.16-irqchip-Make-irq-msi-lib.h-globally-available.patch @@ -0,0 +1,229 @@ +From e51b27438a10391fdc94dd2046d9ffa9c2679c74 Mon Sep 17 00:00:00 2001 +From: Marc Zyngier +Date: Tue, 13 May 2025 18:28:11 +0100 +Subject: [PATCH] irqchip: Make irq-msi-lib.h globally available + +Move irq-msi-lib.h into include/linux/irqchip, making it available +to compilation units outside of drivers/irqchip. + +This requires some churn in drivers to fetch it from the new location, +generated using this script: + + git grep -l -w \"irq-msi-lib.h\" | \ + xargs sed -i -e 's:"irq-msi-lib.h":\:' + +Signed-off-by: Marc Zyngier +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250513172819.2216709-2-maz@kernel.org +--- + drivers/irqchip/irq-bcm2712-mip.c | 2 +- + drivers/irqchip/irq-gic-v2m.c | 2 +- + drivers/irqchip/irq-gic-v3-its-msi-parent.c | 2 +- + drivers/irqchip/irq-gic-v3-its.c | 2 +- + drivers/irqchip/irq-gic-v3-mbi.c | 2 +- + drivers/irqchip/irq-imx-mu-msi.c | 2 +- + drivers/irqchip/irq-loongarch-avec.c | 2 +- + drivers/irqchip/irq-loongson-pch-msi.c | 2 +- + drivers/irqchip/irq-msi-lib.c | 2 +- + drivers/irqchip/irq-mvebu-gicp.c | 2 +- + drivers/irqchip/irq-mvebu-icu.c | 2 +- + drivers/irqchip/irq-mvebu-odmi.c | 2 +- + drivers/irqchip/irq-mvebu-sei.c | 2 +- + drivers/irqchip/irq-riscv-imsic-platform.c | 2 +- + drivers/irqchip/irq-sg2042-msi.c | 2 +- + {drivers => include/linux}/irqchip/irq-msi-lib.h | 6 +++--- + 16 files changed, 18 insertions(+), 18 deletions(-) + rename {drivers => include/linux}/irqchip/irq-msi-lib.h (84%) + +--- a/drivers/irqchip/irq-gic-v2m.c ++++ b/drivers/irqchip/irq-gic-v2m.c +@@ -26,7 +26,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + /* + * MSI_TYPER: +--- a/drivers/irqchip/irq-gic-v3-its-msi-parent.c ++++ b/drivers/irqchip/irq-gic-v3-its-msi-parent.c +@@ -8,7 +8,7 @@ + #include + + #include "irq-gic-common.h" +-#include "irq-msi-lib.h" ++#include + + #define ITS_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -38,7 +38,7 @@ + #include + + #include "irq-gic-common.h" +-#include "irq-msi-lib.h" ++#include + + #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) + #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) +--- a/drivers/irqchip/irq-gic-v3-mbi.c ++++ b/drivers/irqchip/irq-gic-v3-mbi.c +@@ -18,7 +18,7 @@ + + #include + +-#include "irq-msi-lib.h" ++#include + + struct mbi_range { + u32 spi_start; +--- a/drivers/irqchip/irq-imx-mu-msi.c ++++ b/drivers/irqchip/irq-imx-mu-msi.c +@@ -24,7 +24,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + #define IMX_MU_CHANS 4 + +--- a/drivers/irqchip/irq-loongarch-avec.c ++++ b/drivers/irqchip/irq-loongarch-avec.c +@@ -18,7 +18,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + #include "irq-loongson.h" + + #define VECTORS_PER_REG 64 +--- a/drivers/irqchip/irq-loongson-pch-msi.c ++++ b/drivers/irqchip/irq-loongson-pch-msi.c +@@ -15,7 +15,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + #include "irq-loongson.h" + + static int nr_pics; +--- a/drivers/irqchip/irq-msi-lib.c ++++ b/drivers/irqchip/irq-msi-lib.c +@@ -4,7 +4,7 @@ + + #include + +-#include "irq-msi-lib.h" ++#include + + /** + * msi_lib_init_dev_msi_info - Domain info setup for MSI domains +--- a/drivers/irqchip/irq-mvebu-gicp.c ++++ b/drivers/irqchip/irq-mvebu-gicp.c +@@ -17,7 +17,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + #include + +--- a/drivers/irqchip/irq-mvebu-icu.c ++++ b/drivers/irqchip/irq-mvebu-icu.c +@@ -20,7 +20,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + #include + +--- a/drivers/irqchip/irq-mvebu-odmi.c ++++ b/drivers/irqchip/irq-mvebu-odmi.c +@@ -18,7 +18,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + #include + +--- a/drivers/irqchip/irq-mvebu-sei.c ++++ b/drivers/irqchip/irq-mvebu-sei.c +@@ -14,7 +14,7 @@ + #include + #include + +-#include "irq-msi-lib.h" ++#include + + /* Cause register */ + #define GICP_SECR(idx) (0x0 + ((idx) * 0x4)) +--- a/drivers/irqchip/irq-msi-lib.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-// Copyright (C) 2022 Linutronix GmbH +-// Copyright (C) 2022 Intel +- +-#ifndef _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H +-#define _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H +- +-#include +-#include +-#include +- +-#ifdef CONFIG_PCI_MSI +-#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) +-#else +-#define MATCH_PCI_MSI (0) +-#endif +- +-#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) +- +-int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, +- enum irq_domain_bus_token bus_token); +- +-bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, +- struct irq_domain *real_parent, +- struct msi_domain_info *info); +- +-#endif /* _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H */ +--- /dev/null ++++ b/include/linux/irqchip/irq-msi-lib.h +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Copyright (C) 2022 Linutronix GmbH ++// Copyright (C) 2022 Intel ++ ++#ifndef _IRQCHIP_IRQ_MSI_LIB_H ++#define _IRQCHIP_IRQ_MSI_LIB_H ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_PCI_MSI ++#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) ++#else ++#define MATCH_PCI_MSI (0) ++#endif ++ ++#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) ++ ++int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, ++ enum irq_domain_bus_token bus_token); ++ ++bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, ++ struct irq_domain *real_parent, ++ struct msi_domain_info *info); ++ ++#endif /* _IRQCHIP_IRQ_MSI_LIB_H */ diff --git a/target/linux/generic/backport-6.12/904-v6.16-irqchip-irq-msi-lib-Fix-build-with-PCI-disabled.patch b/target/linux/generic/backport-6.12/904-v6.16-irqchip-irq-msi-lib-Fix-build-with-PCI-disabled.patch new file mode 100644 index 0000000000..4f945f0284 --- /dev/null +++ b/target/linux/generic/backport-6.12/904-v6.16-irqchip-irq-msi-lib-Fix-build-with-PCI-disabled.patch @@ -0,0 +1,34 @@ +From a8b289f0f2dcbadd8c207ad8f33cf7ba2b4eb088 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Thu, 10 Jul 2025 10:00:12 +0200 +Subject: [PATCH] irqchip/irq-msi-lib: Fix build with PCI disabled + +The armada-370-xp irqchip fails in some randconfig builds because +of a missing declaration: + +In file included from drivers/irqchip/irq-armada-370-xp.c:23: +include/linux/irqchip/irq-msi-lib.h:25:39: error: 'struct msi_domain_info' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] + +Add a forward declaration for the msi_domain_info structure. + +[ tglx: Fixed up the subsystem prefix. Is it really that hard to get right? ] + +Fixes: e51b27438a10 ("irqchip: Make irq-msi-lib.h globally available") +Signed-off-by: Arnd Bergmann +Signed-off-by: Thomas Gleixner +Acked-by: Marc Zyngier +Link: https://lore.kernel.org/all/20250710080021.2303640-1-arnd@kernel.org +--- + include/linux/irqchip/irq-msi-lib.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/linux/irqchip/irq-msi-lib.h ++++ b/include/linux/irqchip/irq-msi-lib.h +@@ -17,6 +17,7 @@ + + #define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) + ++struct msi_domain_info; + int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token); + diff --git a/target/linux/generic/backport-6.12/905-v6.17-PCI-dwc-Export-DWC-MSI-controller-related-APIs.patch b/target/linux/generic/backport-6.12/905-v6.17-PCI-dwc-Export-DWC-MSI-controller-related-APIs.patch new file mode 100644 index 0000000000..20d1c92fdf --- /dev/null +++ b/target/linux/generic/backport-6.12/905-v6.17-PCI-dwc-Export-DWC-MSI-controller-related-APIs.patch @@ -0,0 +1,144 @@ +From a60d92f6d941bd77bf3aaec724a7c95857c0165b Mon Sep 17 00:00:00 2001 +From: Mayank Rana +Date: Mon, 16 Jun 2025 15:42:56 -0700 +Subject: [PATCH] PCI: dwc: Export DWC MSI controller related APIs + +Export dw_pcie_msi_host_init(), dw_pcie_msi_init(), and dw_pcie_free_msi() +APIs to allow them to be reused by the upcoming DWC based ECAM driver +implementation. Also, move MSI IRQ related initialization code to +dw_pcie_msi_init(), as this code must be executed before dw_pcie_msi_init() +API can be used with ECAM driver. + +Signed-off-by: Mayank Rana +[mani: commit message rewording] +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20250616224259.3549811-2-mayank.rana@oss.qualcomm.com +--- + .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++--------- + drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++ + 2 files changed, 34 insertions(+), 18 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_p + return 0; + } + +-static void dw_pcie_free_msi(struct dw_pcie_rp *pp) ++void dw_pcie_free_msi(struct dw_pcie_rp *pp) + { + u32 ctrl; + +@@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_p + irq_domain_remove(pp->msi_domain); + irq_domain_remove(pp->irq_domain); + } ++EXPORT_SYMBOL_GPL(dw_pcie_free_msi); + +-static void dw_pcie_msi_init(struct dw_pcie_rp *pp) ++void dw_pcie_msi_init(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + u64 msi_target = (u64)pp->msi_data; ++ u32 ctrl, num_ctrls; + + if (!pci_msi_enabled() || !pp->has_msi_ctrl) + return; + ++ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; ++ ++ /* Initialize IRQ Status array */ ++ for (ctrl = 0; ctrl < num_ctrls; ctrl++) { ++ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + ++ (ctrl * MSI_REG_CTRL_BLOCK_SIZE), ++ pp->irq_mask[ctrl]); ++ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + ++ (ctrl * MSI_REG_CTRL_BLOCK_SIZE), ++ ~0); ++ } ++ + /* Program the msi_data */ + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); + } ++EXPORT_SYMBOL_GPL(dw_pcie_msi_init); + + static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) + { +@@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(s + return 0; + } + +-static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) ++int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; +@@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct + + return 0; + } ++EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init); + + static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) + { +@@ -809,7 +825,7 @@ static int dw_pcie_iatu_setup(struct dw_ + int dw_pcie_setup_rc(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- u32 val, ctrl, num_ctrls; ++ u32 val; + int ret; + + /* +@@ -820,20 +836,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp * + + dw_pcie_setup(pci); + +- if (pp->has_msi_ctrl) { +- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; +- +- /* Initialize IRQ Status array */ +- for (ctrl = 0; ctrl < num_ctrls; ctrl++) { +- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + +- (ctrl * MSI_REG_CTRL_BLOCK_SIZE), +- pp->irq_mask[ctrl]); +- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + +- (ctrl * MSI_REG_CTRL_BLOCK_SIZE), +- ~0); +- } +- } +- + dw_pcie_msi_init(pp); + + /* Setup RC BARs */ +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -678,6 +678,9 @@ static inline enum dw_pcie_ltssm dw_pcie + int dw_pcie_suspend_noirq(struct dw_pcie *pci); + int dw_pcie_resume_noirq(struct dw_pcie *pci); + irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); ++void dw_pcie_msi_init(struct dw_pcie_rp *pp); ++int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); ++void dw_pcie_free_msi(struct dw_pcie_rp *pp); + int dw_pcie_setup_rc(struct dw_pcie_rp *pp); + int dw_pcie_host_init(struct dw_pcie_rp *pp); + void dw_pcie_host_deinit(struct dw_pcie_rp *pp); +@@ -700,6 +703,17 @@ static inline irqreturn_t dw_handle_msi_ + return IRQ_NONE; + } + ++static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp) ++{ } ++ ++static inline int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) ++{ ++ return -ENODEV; ++} ++ ++static inline void dw_pcie_free_msi(struct dw_pcie_rp *pp) ++{ } ++ + static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) + { + return 0; diff --git a/target/linux/generic/backport-6.12/906-v6.17-PCI-dwc-Switch-to-msi_create_parent_irq_domain.patch b/target/linux/generic/backport-6.12/906-v6.17-PCI-dwc-Switch-to-msi_create_parent_irq_domain.patch new file mode 100644 index 0000000000..c3711cd25c --- /dev/null +++ b/target/linux/generic/backport-6.12/906-v6.17-PCI-dwc-Switch-to-msi_create_parent_irq_domain.patch @@ -0,0 +1,145 @@ +From 8e717112caf35998b198d3762b381de70711bdec Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Thu, 26 Jun 2025 16:47:51 +0200 +Subject: [PATCH] PCI: dwc: Switch to msi_create_parent_irq_domain() + +Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() +which was using legacy MSI domain setup. + +Signed-off-by: Nam Cao +[mani: reworded commit message] +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: rebase on dev_fwnode() conversion] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Thomas Gleixner +Link: https://patch.msgid.link/04d4a96046490e50139826c16423954e033cdf89.1750858083.git.namcao@linutronix.de +[Keep of_node_to_fwnode instead of dev_fwnode] +--- + drivers/pci/controller/dwc/Kconfig | 1 + + .../pci/controller/dwc/pcie-designware-host.c | 69 +++++++------------ + drivers/pci/controller/dwc/pcie-designware.h | 1 - + 3 files changed, 25 insertions(+), 46 deletions(-) + +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -9,6 +9,7 @@ config PCIE_DW + config PCIE_DW_HOST + bool + select PCIE_DW ++ select IRQ_MSI_LIB + + config PCIE_DW_EP + bool +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -10,6 +10,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -23,35 +24,21 @@ + static struct pci_ops dw_pcie_ops; + static struct pci_ops dw_child_pcie_ops; + +-static void dw_msi_ack_irq(struct irq_data *d) +-{ +- irq_chip_ack_parent(d); +-} +- +-static void dw_msi_mask_irq(struct irq_data *d) +-{ +- pci_msi_mask_irq(d); +- irq_chip_mask_parent(d); +-} +- +-static void dw_msi_unmask_irq(struct irq_data *d) +-{ +- pci_msi_unmask_irq(d); +- irq_chip_unmask_parent(d); +-} +- +-static struct irq_chip dw_pcie_msi_irq_chip = { +- .name = "PCI-MSI", +- .irq_ack = dw_msi_ack_irq, +- .irq_mask = dw_msi_mask_irq, +- .irq_unmask = dw_msi_unmask_irq, +-}; +- +-static struct msi_domain_info dw_pcie_msi_domain_info = { +- .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | +- MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX | +- MSI_FLAG_MULTI_PCI_MSI, +- .chip = &dw_pcie_msi_irq_chip, ++#define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ ++ MSI_FLAG_USE_DEF_CHIP_OPS | \ ++ MSI_FLAG_NO_AFFINITY | \ ++ MSI_FLAG_PCI_MSI_MASK_PARENT) ++#define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ ++ MSI_FLAG_PCI_MSIX | \ ++ MSI_GENERIC_FLAGS_MASK) ++ ++static const struct msi_parent_ops dw_pcie_msi_parent_ops = { ++ .required_flags = DW_PCIE_MSI_FLAGS_REQUIRED, ++ .supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED, ++ .bus_select_token = DOMAIN_BUS_PCI_MSI, ++ .chip_flags = MSI_CHIP_FLAG_SET_ACK, ++ .prefix = "DW-", ++ .init_dev_msi_info = msi_lib_init_dev_msi_info, + }; + + /* MSI int handler */ +@@ -227,26 +214,19 @@ static const struct irq_domain_ops dw_pc + int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); ++ struct irq_domain_info info = { ++ .fwnode = of_node_to_fwnode(pci->dev->of_node), ++ .ops = &dw_pcie_msi_domain_ops, ++ .size = pp->num_vectors, ++ .host_data = pp, ++ }; + +- pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, +- &dw_pcie_msi_domain_ops, pp); ++ pp->irq_domain = msi_create_parent_irq_domain(&info, &dw_pcie_msi_parent_ops); + if (!pp->irq_domain) { + dev_err(pci->dev, "Failed to create IRQ domain\n"); + return -ENOMEM; + } + +- irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); +- +- pp->msi_domain = pci_msi_create_irq_domain(fwnode, +- &dw_pcie_msi_domain_info, +- pp->irq_domain); +- if (!pp->msi_domain) { +- dev_err(pci->dev, "Failed to create MSI domain\n"); +- irq_domain_remove(pp->irq_domain); +- return -ENOMEM; +- } +- + return 0; + } + +@@ -260,7 +240,6 @@ void dw_pcie_free_msi(struct dw_pcie_rp + NULL, NULL); + } + +- irq_domain_remove(pp->msi_domain); + irq_domain_remove(pp->irq_domain); + } + EXPORT_SYMBOL_GPL(dw_pcie_free_msi); +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -368,7 +368,6 @@ struct dw_pcie_rp { + const struct dw_pcie_host_ops *ops; + int msi_irq[MAX_MSI_CTRLS]; + struct irq_domain *irq_domain; +- struct irq_domain *msi_domain; + dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; + u32 num_vectors; diff --git a/target/linux/generic/backport-6.12/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch b/target/linux/generic/backport-6.12/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch new file mode 100644 index 0000000000..d214755675 --- /dev/null +++ b/target/linux/generic/backport-6.12/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch @@ -0,0 +1,66 @@ +From 455a65260f526cedd4680d4836ebdf2eaf1ab4c6 Mon Sep 17 00:00:00 2001 +From: Tobias Schumacher +Date: Thu, 4 Dec 2025 06:05:01 +0100 +Subject: [PATCH] genirq: Change hwirq parameter to irq_hw_number_t + +The irqdomain implementation internally represents hardware IRQs as +irq_hw_number_t, which is defined as unsigned long int. When providing +an irq_hw_number_t to the generic_handle_domain() functions that expect +and unsigned int hwirq, this can lead to a loss of information. Change +the hwirq parameter to irq_hw_number_t to support the full range of +hwirqs. + +Reviewed-by: Thomas Gleixner +Reviewed-by: Niklas Schnelle +Reviewed-by: Farhan Ali +Signed-off-by: Tobias Schumacher +Signed-off-by: Heiko Carstens +--- + include/linux/irqdesc.h | 6 +++--- + kernel/irq/irqdesc.c | 6 +++--- + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/include/linux/irqdesc.h ++++ b/include/linux/irqdesc.h +@@ -183,9 +183,9 @@ int generic_handle_irq_safe(unsigned int + * and handle the result interrupt number. Return -EINVAL if + * conversion failed. + */ +-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq); +-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq); +-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq); ++int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); ++int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq); ++int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq); + #endif + + /* Test to see if a driver has successfully requested an irq */ +--- a/kernel/irq/irqdesc.c ++++ b/kernel/irq/irqdesc.c +@@ -743,7 +743,7 @@ EXPORT_SYMBOL_GPL(generic_handle_irq_saf + * This function must be called from an IRQ context with irq regs + * initialized. + */ +-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq) + { + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); + } +@@ -761,7 +761,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_ + * context). If the interrupt is marked as 'enforce IRQ-context only' then + * the function must be invoked from hard interrupt context. + */ +-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq) + { + unsigned long flags; + int ret; +@@ -784,7 +784,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_ + * This function must be called from an NMI context with irq regs + * initialized. + **/ +-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq) + { + WARN_ON_ONCE(!in_nmi()); + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); diff --git a/target/linux/generic/backport-6.12/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch b/target/linux/generic/backport-6.12/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch new file mode 100644 index 0000000000..84891eaeaf --- /dev/null +++ b/target/linux/generic/backport-6.12/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch @@ -0,0 +1,319 @@ +From fcc1d0dabdb65ca069f77e5b76d3b20277be4a15 Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:53 -0500 +Subject: [PATCH] genirq: Add interrupt redirection infrastructure + +Add infrastructure to redirect interrupt handler execution to a +different CPU when the current CPU is not part of the interrupt's CPU +affinity mask. + +This is primarily aimed at (de)multiplexed interrupts, where the child +interrupt handler runs in the context of the parent interrupt handler, +and therefore CPU affinity control for the child interrupt is typically +not available. + +With the new infrastructure, the child interrupt is allowed to freely +change its affinity setting, independently of the parent. If the +interrupt handler happens to be triggered on an "incompatible" CPU (a +CPU that's not part of the child interrupt's affinity mask), the handler +is redirected and runs in IRQ work context on a "compatible" CPU. + +No functional change is being made to any existing irqchip driver, and +irqchip drivers must be explicitly modified to use the newly added +infrastructure to support interrupt redirection. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-2-rrendec@redhat.com +--- + include/linux/irq.h | 10 +++++ + include/linux/irqdesc.h | 17 +++++++- + kernel/irq/chip.c | 22 ++++++++++- + kernel/irq/irqdesc.c | 86 ++++++++++++++++++++++++++++++++++++++++- + kernel/irq/manage.c | 15 ++++++- + 5 files changed, 144 insertions(+), 6 deletions(-) + +--- a/include/linux/irq.h ++++ b/include/linux/irq.h +@@ -469,6 +469,8 @@ static inline irq_hw_number_t irqd_to_hw + * checks against the supplied affinity mask are not + * required. This is used for CPU hotplug where the + * target CPU is not yet set in the cpu_online_mask. ++ * @irq_pre_redirect: Optional function to be invoked before redirecting ++ * an interrupt via irq_work. Called only on CONFIG_SMP. + * @irq_retrigger: resend an IRQ to the CPU + * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ + * @irq_set_wake: enable/disable power-management wake-on of an IRQ +@@ -512,6 +514,7 @@ struct irq_chip { + void (*irq_eoi)(struct irq_data *data); + + int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); ++ void (*irq_pre_redirect)(struct irq_data *data); + int (*irq_retrigger)(struct irq_data *data); + int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); +@@ -692,6 +695,13 @@ extern int irq_chip_set_vcpu_affinity_pa + extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); + extern int irq_chip_request_resources_parent(struct irq_data *data); + extern void irq_chip_release_resources_parent(struct irq_data *data); ++#ifdef CONFIG_SMP ++void irq_chip_pre_redirect_parent(struct irq_data *data); ++#endif ++#endif ++ ++#ifdef CONFIG_SMP ++int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force); + #endif + + /* Disable or mask interrupts during a kernel kexec */ +--- a/include/linux/irqdesc.h ++++ b/include/linux/irqdesc.h +@@ -2,9 +2,10 @@ + #ifndef _LINUX_IRQDESC_H + #define _LINUX_IRQDESC_H + +-#include ++#include + #include + #include ++#include + + /* + * Core internal functions to deal with irq descriptors +@@ -30,6 +31,17 @@ struct irqstat { + }; + + /** ++ * struct irq_redirect - interrupt redirection metadata ++ * @work: Harg irq_work item for handler execution on a different CPU ++ * @target_cpu: CPU to run irq handler on in case the current CPU is not part ++ * of the irq affinity mask ++ */ ++struct irq_redirect { ++ struct irq_work work; ++ unsigned int target_cpu; ++}; ++ ++/** + * struct irq_desc - interrupt descriptor + * @irq_common_data: per irq and chip data passed down to chip functions + * @kstat_irqs: irq stats per cpu +@@ -46,6 +58,7 @@ struct irqstat { + * @threads_handled: stats field for deferred spurious detection of threaded handlers + * @threads_handled_last: comparator field for deferred spurious detection of threaded handlers + * @lock: locking for SMP ++ * @redirect: Facility for redirecting interrupts via irq_work + * @affinity_hint: hint to user space for preferred irq affinity + * @affinity_notify: context for notification of affinity changes + * @pending_mask: pending rebalanced interrupts +@@ -84,6 +97,7 @@ struct irq_desc { + struct cpumask *percpu_enabled; + const struct cpumask *percpu_affinity; + #ifdef CONFIG_SMP ++ struct irq_redirect redirect; + const struct cpumask *affinity_hint; + struct irq_affinity_notify *affinity_notify; + #ifdef CONFIG_GENERIC_PENDING_IRQ +@@ -186,6 +200,7 @@ int generic_handle_irq_safe(unsigned int + int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); + int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq); + int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq); ++bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); + #endif + + /* Test to see if a driver has successfully requested an irq */ +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -1196,7 +1196,7 @@ void irq_cpu_offline(void) + } + #endif + +-#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY ++#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + + #ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS + /** +@@ -1301,6 +1301,15 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_ir + + #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ + ++#ifdef CONFIG_SMP ++void irq_chip_pre_redirect_parent(struct irq_data *data) ++{ ++ data = data->parent_data; ++ data->chip->irq_pre_redirect(data); ++} ++EXPORT_SYMBOL_GPL(irq_chip_pre_redirect_parent); ++#endif ++ + /** + * irq_chip_set_parent_state - set the state of a parent interrupt. + * +@@ -1546,6 +1555,17 @@ void irq_chip_release_resources_parent(s + data->chip->irq_release_resources(data); + } + EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent); ++#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ ++ ++#ifdef CONFIG_SMP ++int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ struct irq_redirect *redir = &irq_data_to_desc(data)->redirect; ++ ++ WRITE_ONCE(redir->target_cpu, cpumask_first(dest)); ++ return IRQ_SET_MASK_OK; ++} ++EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); + #endif + + /** +--- a/kernel/irq/irqdesc.c ++++ b/kernel/irq/irqdesc.c +@@ -77,8 +77,12 @@ static int alloc_masks(struct irq_desc * + return 0; + } + +-static void desc_smp_init(struct irq_desc *desc, int node, +- const struct cpumask *affinity) ++static void irq_redirect_work(struct irq_work *work) ++{ ++ handle_irq_desc(container_of(work, struct irq_desc, redirect.work)); ++} ++ ++static void desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) + { + if (!affinity) + affinity = irq_default_affinity; +@@ -90,6 +94,7 @@ static void desc_smp_init(struct irq_des + #ifdef CONFIG_NUMA + desc->irq_common_data.node = node; + #endif ++ desc->redirect.work = IRQ_WORK_INIT_HARD(irq_redirect_work); + } + + static void free_masks(struct irq_desc *desc) +@@ -789,6 +794,83 @@ int generic_handle_domain_nmi(struct irq + WARN_ON_ONCE(!in_nmi()); + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); + } ++ ++#ifdef CONFIG_SMP ++static bool demux_redirect_remote(struct irq_desc *desc) ++{ ++ guard(raw_spinlock)(&desc->lock); ++ const struct cpumask *m = irq_data_get_effective_affinity_mask(&desc->irq_data); ++ unsigned int target_cpu = READ_ONCE(desc->redirect.target_cpu); ++ ++ if (desc->irq_data.chip->irq_pre_redirect) ++ desc->irq_data.chip->irq_pre_redirect(&desc->irq_data); ++ ++ /* ++ * If the interrupt handler is already running on a CPU that's included ++ * in the interrupt's affinity mask, redirection is not necessary. ++ */ ++ if (cpumask_test_cpu(smp_processor_id(), m)) ++ return false; ++ ++ /* ++ * The desc->action check protects against IRQ shutdown: __free_irq() sets ++ * desc->action to NULL while holding desc->lock, which we also hold. ++ * ++ * Calling irq_work_queue_on() here is safe w.r.t. CPU unplugging: ++ * - takedown_cpu() schedules multi_cpu_stop() on all active CPUs, ++ * including the one that's taken down. ++ * - multi_cpu_stop() acts like a barrier, which means all active ++ * CPUs go through MULTI_STOP_DISABLE_IRQ and disable hard IRQs ++ * *before* the dying CPU runs take_cpu_down() in MULTI_STOP_RUN. ++ * - Hard IRQs are re-enabled at the end of multi_cpu_stop(), *after* ++ * the dying CPU has run take_cpu_down() in MULTI_STOP_RUN. ++ * - Since we run in hard IRQ context, we run either before or after ++ * take_cpu_down() but never concurrently. ++ * - If we run before take_cpu_down(), the dying CPU hasn't been marked ++ * offline yet (it's marked via take_cpu_down() -> __cpu_disable()), ++ * so the WARN in irq_work_queue_on() can't occur. ++ * - Furthermore, the work item we queue will be flushed later via ++ * take_cpu_down() -> cpuhp_invoke_callback_range_nofail() -> ++ * smpcfd_dying_cpu() -> irq_work_run(). ++ * - If we run after take_cpu_down(), target_cpu has been already ++ * updated via take_cpu_down() -> __cpu_disable(), which eventually ++ * calls irq_do_set_affinity() during IRQ migration. So, target_cpu ++ * no longer points to the dying CPU in this case. ++ */ ++ if (desc->action) ++ irq_work_queue_on(&desc->redirect.work, target_cpu); ++ ++ return true; ++} ++#else /* CONFIG_SMP */ ++static bool demux_redirect_remote(struct irq_desc *desc) ++{ ++ return false; ++} ++#endif ++ ++/** ++ * generic_handle_demux_domain_irq - Invoke the handler for a hardware interrupt ++ * of a demultiplexing domain. ++ * @domain: The domain where to perform the lookup ++ * @hwirq: The hardware interrupt number to convert to a logical one ++ * ++ * Returns: True on success, or false if lookup has failed ++ */ ++bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq) ++{ ++ struct irq_desc *desc = irq_resolve_mapping(domain, hwirq); ++ ++ if (unlikely(!desc)) ++ return false; ++ ++ if (demux_redirect_remote(desc)) ++ return true; ++ ++ return !handle_irq_desc(desc); ++} ++EXPORT_SYMBOL_GPL(generic_handle_demux_domain_irq); ++ + #endif + + /* Dynamic interrupt handling */ +--- a/kernel/irq/manage.c ++++ b/kernel/irq/manage.c +@@ -35,6 +35,16 @@ static int __init setup_forced_irqthread + early_param("threadirqs", setup_forced_irqthreads); + #endif + ++#ifdef CONFIG_SMP ++static inline void synchronize_irqwork(struct irq_desc *desc) ++{ ++ /* Synchronize pending or on the fly redirect work */ ++ irq_work_sync(&desc->redirect.work); ++} ++#else ++static inline void synchronize_irqwork(struct irq_desc *desc) { } ++#endif ++ + static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip) + { + struct irq_data *irqd = irq_desc_get_irq_data(desc); +@@ -110,7 +120,9 @@ EXPORT_SYMBOL(synchronize_hardirq); + + static void __synchronize_irq(struct irq_desc *desc) + { ++ synchronize_irqwork(desc); + __synchronize_hardirq(desc, true); ++ + /* + * We made sure that no hardirq handler is running. Now verify that no + * threaded handlers are active. +@@ -220,8 +232,7 @@ static inline void irq_validate_effectiv + + static DEFINE_PER_CPU(struct cpumask, __tmp_mask); + +-int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, +- bool force) ++int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) + { + struct cpumask *tmp_mask = this_cpu_ptr(&__tmp_mask); + struct irq_desc *desc = irq_data_to_desc(data); diff --git a/target/linux/generic/backport-6.12/908-2-v7.0-PCI-dwc-Code-cleanup.patch b/target/linux/generic/backport-6.12/908-2-v7.0-PCI-dwc-Code-cleanup.patch new file mode 100644 index 0000000000..fef5b99f1f --- /dev/null +++ b/target/linux/generic/backport-6.12/908-2-v7.0-PCI-dwc-Code-cleanup.patch @@ -0,0 +1,242 @@ +From f1875091a01dd634ff5f8b6fc57ab874f755c415 Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:54 -0500 +Subject: [PATCH] PCI: dwc: Code cleanup + +Code cleanup with no functional changes. These changes were originally +made by Thomas Gleixner (see Link tag below) in a patch that was never +submitted as is. Other parts of that patch were eventually submitted as +commit 8e717112caf3 ("PCI: dwc: Switch to msi_create_parent_irq_domain()") +and the remaining parts are the code cleanup changes: + + - Use guard()/scoped_guard() instead of open-coded lock/unlock. + - Return void in a few functions whose return value is never used. + - Simplify dw_handle_msi_irq() by using for_each_set_bit(). + +One notable deviation from the original patch is that it reverts back to a +simple 1 by 1 iteration over the controllers inside dw_handle_msi_irq. The +reason is that with the original changes, the IRQ offset was calculated +incorrectly. + +This prepares the ground for enabling MSI affinity support, which was +originally part of that same series that Thomas Gleixner prepared. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-3-rrendec@redhat.com +--- + .../pci/controller/dwc/pcie-designware-host.c | 98 ++++++------------- + drivers/pci/controller/dwc/pcie-designware.h | 7 +- + 2 files changed, 34 insertions(+), 71 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -42,35 +42,25 @@ static const struct msi_parent_ops dw_pc + }; + + /* MSI int handler */ +-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) ++void dw_handle_msi_irq(struct dw_pcie_rp *pp) + { +- int i, pos; +- unsigned long val; +- u32 status, num_ctrls; +- irqreturn_t ret = IRQ_NONE; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ unsigned int i, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { +- status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + +- (i * MSI_REG_CTRL_BLOCK_SIZE)); ++ unsigned int reg_off = i * MSI_REG_CTRL_BLOCK_SIZE; ++ unsigned int irq_off = i * MAX_MSI_IRQS_PER_CTRL; ++ unsigned long status, pos; ++ ++ status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off); + if (!status) + continue; + +- ret = IRQ_HANDLED; +- val = status; +- pos = 0; +- while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, +- pos)) != MAX_MSI_IRQS_PER_CTRL) { +- generic_handle_domain_irq(pp->irq_domain, +- (i * MAX_MSI_IRQS_PER_CTRL) + +- pos); +- pos++; +- } ++ for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) ++ generic_handle_domain_irq(pp->irq_domain, irq_off + pos); + } +- +- return ret; + } + + /* Chained MSI interrupt service routine */ +@@ -91,13 +81,10 @@ static void dw_pci_setup_msi_msg(struct + { + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- u64 msi_target; +- +- msi_target = (u64)pp->msi_data; ++ u64 msi_target = (u64)pp->msi_data; + + msg->address_lo = lower_32_bits(msi_target); + msg->address_hi = upper_32_bits(msi_target); +- + msg->data = d->hwirq; + + dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", +@@ -109,18 +96,14 @@ static void dw_pci_bottom_mask(struct ir + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + unsigned int res, bit, ctrl; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); + ++ guard(raw_spinlock)(&pp->lock); + ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] |= BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); + } + + static void dw_pci_bottom_unmask(struct irq_data *d) +@@ -128,18 +111,14 @@ static void dw_pci_bottom_unmask(struct + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + unsigned int res, bit, ctrl; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); + ++ guard(raw_spinlock)(&pp->lock); + ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] &= ~BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); + } + + static void dw_pci_bottom_ack(struct irq_data *d) +@@ -156,54 +135,42 @@ static void dw_pci_bottom_ack(struct irq + } + + static struct irq_chip dw_pci_msi_bottom_irq_chip = { +- .name = "DWPCI-MSI", +- .irq_ack = dw_pci_bottom_ack, +- .irq_compose_msi_msg = dw_pci_setup_msi_msg, +- .irq_mask = dw_pci_bottom_mask, +- .irq_unmask = dw_pci_bottom_unmask, ++ .name = "DWPCI-MSI", ++ .irq_ack = dw_pci_bottom_ack, ++ .irq_compose_msi_msg = dw_pci_setup_msi_msg, ++ .irq_mask = dw_pci_bottom_mask, ++ .irq_unmask = dw_pci_bottom_unmask, + }; + +-static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, +- unsigned int virq, unsigned int nr_irqs, +- void *args) ++static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *args) + { + struct dw_pcie_rp *pp = domain->host_data; +- unsigned long flags; +- u32 i; + int bit; + +- raw_spin_lock_irqsave(&pp->lock, flags); +- +- bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, +- order_base_2(nr_irqs)); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); ++ scoped_guard (raw_spinlock_irq, &pp->lock) { ++ bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, ++ order_base_2(nr_irqs)); ++ } + + if (bit < 0) + return -ENOSPC; + +- for (i = 0; i < nr_irqs; i++) +- irq_domain_set_info(domain, virq + i, bit + i, +- pp->msi_irq_chip, +- pp, handle_edge_irq, +- NULL, NULL); +- ++ for (unsigned int i = 0; i < nr_irqs; i++) { ++ irq_domain_set_info(domain, virq + i, bit + i, pp->msi_irq_chip, ++ pp, handle_edge_irq, NULL, NULL); ++ } + return 0; + } + +-static void dw_pcie_irq_domain_free(struct irq_domain *domain, +- unsigned int virq, unsigned int nr_irqs) ++static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs) + { + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct dw_pcie_rp *pp = domain->host_data; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); +- +- bitmap_release_region(pp->msi_irq_in_use, d->hwirq, +- order_base_2(nr_irqs)); + +- raw_spin_unlock_irqrestore(&pp->lock, flags); ++ guard(raw_spinlock_irq)(&pp->lock); ++ bitmap_release_region(pp->msi_irq_in_use, d->hwirq, order_base_2(nr_irqs)); + } + + static const struct irq_domain_ops dw_pcie_msi_domain_ops = { +@@ -236,8 +203,7 @@ void dw_pcie_free_msi(struct dw_pcie_rp + + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { + if (pp->msi_irq[ctrl] > 0) +- irq_set_chained_handler_and_data(pp->msi_irq[ctrl], +- NULL, NULL); ++ irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); + } + + irq_domain_remove(pp->irq_domain); +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -676,7 +676,7 @@ static inline enum dw_pcie_ltssm dw_pcie + #ifdef CONFIG_PCIE_DW_HOST + int dw_pcie_suspend_noirq(struct dw_pcie *pci); + int dw_pcie_resume_noirq(struct dw_pcie *pci); +-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); ++void dw_handle_msi_irq(struct dw_pcie_rp *pp); + void dw_pcie_msi_init(struct dw_pcie_rp *pp); + int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); + void dw_pcie_free_msi(struct dw_pcie_rp *pp); +@@ -697,10 +697,7 @@ static inline int dw_pcie_resume_noirq(s + return 0; + } + +-static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) +-{ +- return IRQ_NONE; +-} ++static inline void dw_handle_msi_irq(struct dw_pcie_rp *pp) { } + + static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp) + { } diff --git a/target/linux/generic/backport-6.12/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch b/target/linux/generic/backport-6.12/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch new file mode 100644 index 0000000000..1df91cb43e --- /dev/null +++ b/target/linux/generic/backport-6.12/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch @@ -0,0 +1,92 @@ +From eaf290c404f7c39f23292e9ce83b8b5b51ab598a Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:55 -0500 +Subject: [PATCH] PCI: dwc: Enable MSI affinity support + +Leverage the interrupt redirection infrastructure to enable CPU affinity +support for MSI interrupts. Since the parent interrupt affinity cannot +be changed, affinity control for the child interrupt (MSI) is achieved +by redirecting the handler to run in IRQ work context on the target CPU. + +This patch was originally prepared by Thomas Gleixner (see Link tag below) +in a patch series that was never submitted as is, and only parts of that +series have made it upstream so far. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redhat.com +--- + .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++--- + 1 file changed, 28 insertions(+), 5 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -24,9 +24,27 @@ + static struct pci_ops dw_pcie_ops; + static struct pci_ops dw_child_pcie_ops; + ++#ifdef CONFIG_SMP ++static void dw_irq_noop(struct irq_data *d) { } ++#endif ++ ++static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain, ++ struct irq_domain *real_parent, struct msi_domain_info *info) ++{ ++ if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) ++ return false; ++ ++#ifdef CONFIG_SMP ++ info->chip->irq_ack = dw_irq_noop; ++ info->chip->irq_pre_redirect = irq_chip_pre_redirect_parent; ++#else ++ info->chip->irq_ack = irq_chip_ack_parent; ++#endif ++ return true; ++} ++ + #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ +- MSI_FLAG_NO_AFFINITY | \ + MSI_FLAG_PCI_MSI_MASK_PARENT) + #define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ + MSI_FLAG_PCI_MSIX | \ +@@ -36,9 +54,8 @@ static const struct msi_parent_ops dw_pc + .required_flags = DW_PCIE_MSI_FLAGS_REQUIRED, + .supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED, + .bus_select_token = DOMAIN_BUS_PCI_MSI, +- .chip_flags = MSI_CHIP_FLAG_SET_ACK, + .prefix = "DW-", +- .init_dev_msi_info = msi_lib_init_dev_msi_info, ++ .init_dev_msi_info = dw_pcie_init_dev_msi_info, + }; + + /* MSI int handler */ +@@ -59,7 +76,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp + continue; + + for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) +- generic_handle_domain_irq(pp->irq_domain, irq_off + pos); ++ generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos); + } + } + +@@ -136,10 +153,16 @@ static void dw_pci_bottom_ack(struct irq + + static struct irq_chip dw_pci_msi_bottom_irq_chip = { + .name = "DWPCI-MSI", +- .irq_ack = dw_pci_bottom_ack, + .irq_compose_msi_msg = dw_pci_setup_msi_msg, + .irq_mask = dw_pci_bottom_mask, + .irq_unmask = dw_pci_bottom_unmask, ++#ifdef CONFIG_SMP ++ .irq_ack = dw_irq_noop, ++ .irq_pre_redirect = dw_pci_bottom_ack, ++ .irq_set_affinity = irq_chip_redirect_set_affinity, ++#else ++ .irq_ack = dw_pci_bottom_ack, ++#endif + }; + + static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, diff --git a/target/linux/generic/backport-6.12/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch b/target/linux/generic/backport-6.12/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch new file mode 100644 index 0000000000..5bbb6a9c6b --- /dev/null +++ b/target/linux/generic/backport-6.12/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch @@ -0,0 +1,56 @@ +From df439718afaf23b5aa7b5711b6c14e87b5836cae Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Mon, 12 Jan 2026 16:14:02 -0500 +Subject: [PATCH] genirq: Update effective affinity for redirected + interrupts + +For redirected interrupts, irq_chip_redirect_set_affinity() does not +update the effective affinity mask, which then triggers the warning in +irq_validate_effective_affinity(). Also, because the effective affinity +mask is empty, the cpumask_test_cpu(smp_processor_id(), m) condition in +demux_redirect_remote() is always false, and the interrupt is always +redirected, even if it's already running on the target CPU. + +Set the effective affinity mask to be the same as the requested affinity +mask. It's worth noting that irq_do_set_affinity() filters out offline +CPUs before calling chip->irq_set_affinity() (unless `force` is set), so +the mask passed to irq_chip_redirect_set_affinity() is already filtered. + +The solution is not ideal because it may lie about the effective +affinity of the demultiplexed ("child") interrupt. If the requested +affinity mask includes multiple CPUs, the effective affinity, in +reality, is the intersection between the requested mask and the +demultiplexing ("parent") interrupt's effective affinity mask, plus +the first CPU in the requested mask. + +Accurately describing the effective affinity of the demultiplexed +interrupt is not trivial because it requires keeping track of the +demultiplexing interrupt's effective affinity. That is tricky in the +context of CPU hot(un)plugging, where interrupt migration ordering is +not guaranteed. The solution in the initial version of the fixed patch, +which stored the first CPU of the demultiplexing interrupt's effective +affinity in the `target_cpu` field, has its own drawbacks and +limitations. + +Fixes: fcc1d0dabdb6 ("genirq: Add interrupt redirection infrastructure") +Reported-by: Jon Hunter +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Tested-by: Jon Hunter +Link: https://patch.msgid.link/20260112211402.2927336-1-rrendec@redhat.com +Closes: https://lore.kernel.org/all/44509520-f29b-4b8a-8986-5eae3e022eb7@nvidia.com/ +--- + kernel/irq/chip.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -1563,6 +1563,8 @@ int irq_chip_redirect_set_affinity(struc + struct irq_redirect *redir = &irq_data_to_desc(data)->redirect; + + WRITE_ONCE(redir->target_cpu, cpumask_first(dest)); ++ irq_data_update_effective_affinity(data, dest); ++ + return IRQ_SET_MASK_OK; + } + EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); diff --git a/target/linux/generic/backport-6.18/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch b/target/linux/generic/backport-6.18/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch new file mode 100644 index 0000000000..062abccc30 --- /dev/null +++ b/target/linux/generic/backport-6.18/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch @@ -0,0 +1,66 @@ +From 455a65260f526cedd4680d4836ebdf2eaf1ab4c6 Mon Sep 17 00:00:00 2001 +From: Tobias Schumacher +Date: Thu, 4 Dec 2025 06:05:01 +0100 +Subject: [PATCH] genirq: Change hwirq parameter to irq_hw_number_t + +The irqdomain implementation internally represents hardware IRQs as +irq_hw_number_t, which is defined as unsigned long int. When providing +an irq_hw_number_t to the generic_handle_domain() functions that expect +and unsigned int hwirq, this can lead to a loss of information. Change +the hwirq parameter to irq_hw_number_t to support the full range of +hwirqs. + +Reviewed-by: Thomas Gleixner +Reviewed-by: Niklas Schnelle +Reviewed-by: Farhan Ali +Signed-off-by: Tobias Schumacher +Signed-off-by: Heiko Carstens +--- + include/linux/irqdesc.h | 6 +++--- + kernel/irq/irqdesc.c | 6 +++--- + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/include/linux/irqdesc.h ++++ b/include/linux/irqdesc.h +@@ -183,9 +183,9 @@ int generic_handle_irq_safe(unsigned int + * and handle the result interrupt number. Return -EINVAL if + * conversion failed. + */ +-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq); +-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq); +-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq); ++int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); ++int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq); ++int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq); + #endif + + /* Test to see if a driver has successfully requested an irq */ +--- a/kernel/irq/irqdesc.c ++++ b/kernel/irq/irqdesc.c +@@ -720,7 +720,7 @@ EXPORT_SYMBOL_GPL(generic_handle_irq_saf + * This function must be called from an IRQ context with irq regs + * initialized. + */ +-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq) + { + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); + } +@@ -738,7 +738,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_ + * context). If the interrupt is marked as 'enforce IRQ-context only' then + * the function must be invoked from hard interrupt context. + */ +-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq) + { + unsigned long flags; + int ret; +@@ -761,7 +761,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_ + * This function must be called from an NMI context with irq regs + * initialized. + **/ +-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq) ++int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq) + { + WARN_ON_ONCE(!in_nmi()); + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); diff --git a/target/linux/generic/backport-6.18/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch b/target/linux/generic/backport-6.18/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch new file mode 100644 index 0000000000..2a54472328 --- /dev/null +++ b/target/linux/generic/backport-6.18/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch @@ -0,0 +1,319 @@ +From fcc1d0dabdb65ca069f77e5b76d3b20277be4a15 Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:53 -0500 +Subject: [PATCH] genirq: Add interrupt redirection infrastructure + +Add infrastructure to redirect interrupt handler execution to a +different CPU when the current CPU is not part of the interrupt's CPU +affinity mask. + +This is primarily aimed at (de)multiplexed interrupts, where the child +interrupt handler runs in the context of the parent interrupt handler, +and therefore CPU affinity control for the child interrupt is typically +not available. + +With the new infrastructure, the child interrupt is allowed to freely +change its affinity setting, independently of the parent. If the +interrupt handler happens to be triggered on an "incompatible" CPU (a +CPU that's not part of the child interrupt's affinity mask), the handler +is redirected and runs in IRQ work context on a "compatible" CPU. + +No functional change is being made to any existing irqchip driver, and +irqchip drivers must be explicitly modified to use the newly added +infrastructure to support interrupt redirection. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-2-rrendec@redhat.com +--- + include/linux/irq.h | 10 +++++ + include/linux/irqdesc.h | 17 +++++++- + kernel/irq/chip.c | 22 ++++++++++- + kernel/irq/irqdesc.c | 86 ++++++++++++++++++++++++++++++++++++++++- + kernel/irq/manage.c | 15 ++++++- + 5 files changed, 144 insertions(+), 6 deletions(-) + +--- a/include/linux/irq.h ++++ b/include/linux/irq.h +@@ -459,6 +459,8 @@ static inline irq_hw_number_t irqd_to_hw + * checks against the supplied affinity mask are not + * required. This is used for CPU hotplug where the + * target CPU is not yet set in the cpu_online_mask. ++ * @irq_pre_redirect: Optional function to be invoked before redirecting ++ * an interrupt via irq_work. Called only on CONFIG_SMP. + * @irq_retrigger: resend an IRQ to the CPU + * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ + * @irq_set_wake: enable/disable power-management wake-on of an IRQ +@@ -503,6 +505,7 @@ struct irq_chip { + void (*irq_eoi)(struct irq_data *data); + + int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); ++ void (*irq_pre_redirect)(struct irq_data *data); + int (*irq_retrigger)(struct irq_data *data); + int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); +@@ -688,6 +691,13 @@ extern int irq_chip_set_vcpu_affinity_pa + extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); + extern int irq_chip_request_resources_parent(struct irq_data *data); + extern void irq_chip_release_resources_parent(struct irq_data *data); ++#ifdef CONFIG_SMP ++void irq_chip_pre_redirect_parent(struct irq_data *data); ++#endif ++#endif ++ ++#ifdef CONFIG_SMP ++int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force); + #endif + + /* Disable or mask interrupts during a kernel kexec */ +--- a/include/linux/irqdesc.h ++++ b/include/linux/irqdesc.h +@@ -2,9 +2,10 @@ + #ifndef _LINUX_IRQDESC_H + #define _LINUX_IRQDESC_H + +-#include ++#include + #include + #include ++#include + + /* + * Core internal functions to deal with irq descriptors +@@ -30,6 +31,17 @@ struct irqstat { + }; + + /** ++ * struct irq_redirect - interrupt redirection metadata ++ * @work: Harg irq_work item for handler execution on a different CPU ++ * @target_cpu: CPU to run irq handler on in case the current CPU is not part ++ * of the irq affinity mask ++ */ ++struct irq_redirect { ++ struct irq_work work; ++ unsigned int target_cpu; ++}; ++ ++/** + * struct irq_desc - interrupt descriptor + * @irq_common_data: per irq and chip data passed down to chip functions + * @kstat_irqs: irq stats per cpu +@@ -46,6 +58,7 @@ struct irqstat { + * @threads_handled: stats field for deferred spurious detection of threaded handlers + * @threads_handled_last: comparator field for deferred spurious detection of threaded handlers + * @lock: locking for SMP ++ * @redirect: Facility for redirecting interrupts via irq_work + * @affinity_hint: hint to user space for preferred irq affinity + * @affinity_notify: context for notification of affinity changes + * @pending_mask: pending rebalanced interrupts +@@ -84,6 +97,7 @@ struct irq_desc { + struct cpumask *percpu_enabled; + const struct cpumask *percpu_affinity; + #ifdef CONFIG_SMP ++ struct irq_redirect redirect; + const struct cpumask *affinity_hint; + struct irq_affinity_notify *affinity_notify; + #ifdef CONFIG_GENERIC_PENDING_IRQ +@@ -186,6 +200,7 @@ int generic_handle_irq_safe(unsigned int + int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); + int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq); + int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq); ++bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq); + #endif + + /* Test to see if a driver has successfully requested an irq */ +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -1143,7 +1143,7 @@ void irq_cpu_offline(void) + } + #endif + +-#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY ++#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + + #ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS + /** +@@ -1215,6 +1215,15 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_ir + + #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ + ++#ifdef CONFIG_SMP ++void irq_chip_pre_redirect_parent(struct irq_data *data) ++{ ++ data = data->parent_data; ++ data->chip->irq_pre_redirect(data); ++} ++EXPORT_SYMBOL_GPL(irq_chip_pre_redirect_parent); ++#endif ++ + /** + * irq_chip_set_parent_state - set the state of a parent interrupt. + * +@@ -1497,6 +1506,17 @@ void irq_chip_release_resources_parent(s + data->chip->irq_release_resources(data); + } + EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent); ++#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ ++ ++#ifdef CONFIG_SMP ++int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ struct irq_redirect *redir = &irq_data_to_desc(data)->redirect; ++ ++ WRITE_ONCE(redir->target_cpu, cpumask_first(dest)); ++ return IRQ_SET_MASK_OK; ++} ++EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); + #endif + + /** +--- a/kernel/irq/irqdesc.c ++++ b/kernel/irq/irqdesc.c +@@ -78,8 +78,12 @@ static int alloc_masks(struct irq_desc * + return 0; + } + +-static void desc_smp_init(struct irq_desc *desc, int node, +- const struct cpumask *affinity) ++static void irq_redirect_work(struct irq_work *work) ++{ ++ handle_irq_desc(container_of(work, struct irq_desc, redirect.work)); ++} ++ ++static void desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) + { + if (!affinity) + affinity = irq_default_affinity; +@@ -91,6 +95,7 @@ static void desc_smp_init(struct irq_des + #ifdef CONFIG_NUMA + desc->irq_common_data.node = node; + #endif ++ desc->redirect.work = IRQ_WORK_INIT_HARD(irq_redirect_work); + } + + static void free_masks(struct irq_desc *desc) +@@ -766,6 +771,83 @@ int generic_handle_domain_nmi(struct irq + WARN_ON_ONCE(!in_nmi()); + return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); + } ++ ++#ifdef CONFIG_SMP ++static bool demux_redirect_remote(struct irq_desc *desc) ++{ ++ guard(raw_spinlock)(&desc->lock); ++ const struct cpumask *m = irq_data_get_effective_affinity_mask(&desc->irq_data); ++ unsigned int target_cpu = READ_ONCE(desc->redirect.target_cpu); ++ ++ if (desc->irq_data.chip->irq_pre_redirect) ++ desc->irq_data.chip->irq_pre_redirect(&desc->irq_data); ++ ++ /* ++ * If the interrupt handler is already running on a CPU that's included ++ * in the interrupt's affinity mask, redirection is not necessary. ++ */ ++ if (cpumask_test_cpu(smp_processor_id(), m)) ++ return false; ++ ++ /* ++ * The desc->action check protects against IRQ shutdown: __free_irq() sets ++ * desc->action to NULL while holding desc->lock, which we also hold. ++ * ++ * Calling irq_work_queue_on() here is safe w.r.t. CPU unplugging: ++ * - takedown_cpu() schedules multi_cpu_stop() on all active CPUs, ++ * including the one that's taken down. ++ * - multi_cpu_stop() acts like a barrier, which means all active ++ * CPUs go through MULTI_STOP_DISABLE_IRQ and disable hard IRQs ++ * *before* the dying CPU runs take_cpu_down() in MULTI_STOP_RUN. ++ * - Hard IRQs are re-enabled at the end of multi_cpu_stop(), *after* ++ * the dying CPU has run take_cpu_down() in MULTI_STOP_RUN. ++ * - Since we run in hard IRQ context, we run either before or after ++ * take_cpu_down() but never concurrently. ++ * - If we run before take_cpu_down(), the dying CPU hasn't been marked ++ * offline yet (it's marked via take_cpu_down() -> __cpu_disable()), ++ * so the WARN in irq_work_queue_on() can't occur. ++ * - Furthermore, the work item we queue will be flushed later via ++ * take_cpu_down() -> cpuhp_invoke_callback_range_nofail() -> ++ * smpcfd_dying_cpu() -> irq_work_run(). ++ * - If we run after take_cpu_down(), target_cpu has been already ++ * updated via take_cpu_down() -> __cpu_disable(), which eventually ++ * calls irq_do_set_affinity() during IRQ migration. So, target_cpu ++ * no longer points to the dying CPU in this case. ++ */ ++ if (desc->action) ++ irq_work_queue_on(&desc->redirect.work, target_cpu); ++ ++ return true; ++} ++#else /* CONFIG_SMP */ ++static bool demux_redirect_remote(struct irq_desc *desc) ++{ ++ return false; ++} ++#endif ++ ++/** ++ * generic_handle_demux_domain_irq - Invoke the handler for a hardware interrupt ++ * of a demultiplexing domain. ++ * @domain: The domain where to perform the lookup ++ * @hwirq: The hardware interrupt number to convert to a logical one ++ * ++ * Returns: True on success, or false if lookup has failed ++ */ ++bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq) ++{ ++ struct irq_desc *desc = irq_resolve_mapping(domain, hwirq); ++ ++ if (unlikely(!desc)) ++ return false; ++ ++ if (demux_redirect_remote(desc)) ++ return true; ++ ++ return !handle_irq_desc(desc); ++} ++EXPORT_SYMBOL_GPL(generic_handle_demux_domain_irq); ++ + #endif + + /* Dynamic interrupt handling */ +--- a/kernel/irq/manage.c ++++ b/kernel/irq/manage.c +@@ -35,6 +35,16 @@ static int __init setup_forced_irqthread + early_param("threadirqs", setup_forced_irqthreads); + #endif + ++#ifdef CONFIG_SMP ++static inline void synchronize_irqwork(struct irq_desc *desc) ++{ ++ /* Synchronize pending or on the fly redirect work */ ++ irq_work_sync(&desc->redirect.work); ++} ++#else ++static inline void synchronize_irqwork(struct irq_desc *desc) { } ++#endif ++ + static int __irq_get_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool *state); + + static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip) +@@ -107,7 +117,9 @@ EXPORT_SYMBOL(synchronize_hardirq); + + static void __synchronize_irq(struct irq_desc *desc) + { ++ synchronize_irqwork(desc); + __synchronize_hardirq(desc, true); ++ + /* + * We made sure that no hardirq handler is running. Now verify that no + * threaded handlers are active. +@@ -217,8 +229,7 @@ static inline void irq_validate_effectiv + + static DEFINE_PER_CPU(struct cpumask, __tmp_mask); + +-int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, +- bool force) ++int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) + { + struct cpumask *tmp_mask = this_cpu_ptr(&__tmp_mask); + struct irq_desc *desc = irq_data_to_desc(data); diff --git a/target/linux/generic/backport-6.18/908-2-v7.0-PCI-dwc-Code-cleanup.patch b/target/linux/generic/backport-6.18/908-2-v7.0-PCI-dwc-Code-cleanup.patch new file mode 100644 index 0000000000..d8b449e608 --- /dev/null +++ b/target/linux/generic/backport-6.18/908-2-v7.0-PCI-dwc-Code-cleanup.patch @@ -0,0 +1,242 @@ +From f1875091a01dd634ff5f8b6fc57ab874f755c415 Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:54 -0500 +Subject: [PATCH] PCI: dwc: Code cleanup + +Code cleanup with no functional changes. These changes were originally +made by Thomas Gleixner (see Link tag below) in a patch that was never +submitted as is. Other parts of that patch were eventually submitted as +commit 8e717112caf3 ("PCI: dwc: Switch to msi_create_parent_irq_domain()") +and the remaining parts are the code cleanup changes: + + - Use guard()/scoped_guard() instead of open-coded lock/unlock. + - Return void in a few functions whose return value is never used. + - Simplify dw_handle_msi_irq() by using for_each_set_bit(). + +One notable deviation from the original patch is that it reverts back to a +simple 1 by 1 iteration over the controllers inside dw_handle_msi_irq. The +reason is that with the original changes, the IRQ offset was calculated +incorrectly. + +This prepares the ground for enabling MSI affinity support, which was +originally part of that same series that Thomas Gleixner prepared. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-3-rrendec@redhat.com +--- + .../pci/controller/dwc/pcie-designware-host.c | 98 ++++++------------- + drivers/pci/controller/dwc/pcie-designware.h | 7 +- + 2 files changed, 34 insertions(+), 71 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -46,35 +46,25 @@ static const struct msi_parent_ops dw_pc + }; + + /* MSI int handler */ +-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) ++void dw_handle_msi_irq(struct dw_pcie_rp *pp) + { +- int i, pos; +- unsigned long val; +- u32 status, num_ctrls; +- irqreturn_t ret = IRQ_NONE; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ unsigned int i, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { +- status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + +- (i * MSI_REG_CTRL_BLOCK_SIZE)); ++ unsigned int reg_off = i * MSI_REG_CTRL_BLOCK_SIZE; ++ unsigned int irq_off = i * MAX_MSI_IRQS_PER_CTRL; ++ unsigned long status, pos; ++ ++ status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off); + if (!status) + continue; + +- ret = IRQ_HANDLED; +- val = status; +- pos = 0; +- while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, +- pos)) != MAX_MSI_IRQS_PER_CTRL) { +- generic_handle_domain_irq(pp->irq_domain, +- (i * MAX_MSI_IRQS_PER_CTRL) + +- pos); +- pos++; +- } ++ for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) ++ generic_handle_domain_irq(pp->irq_domain, irq_off + pos); + } +- +- return ret; + } + + /* Chained MSI interrupt service routine */ +@@ -95,13 +85,10 @@ static void dw_pci_setup_msi_msg(struct + { + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- u64 msi_target; +- +- msi_target = (u64)pp->msi_data; ++ u64 msi_target = (u64)pp->msi_data; + + msg->address_lo = lower_32_bits(msi_target); + msg->address_hi = upper_32_bits(msi_target); +- + msg->data = d->hwirq; + + dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", +@@ -113,18 +100,14 @@ static void dw_pci_bottom_mask(struct ir + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + unsigned int res, bit, ctrl; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); + ++ guard(raw_spinlock)(&pp->lock); + ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] |= BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); + } + + static void dw_pci_bottom_unmask(struct irq_data *d) +@@ -132,18 +115,14 @@ static void dw_pci_bottom_unmask(struct + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + unsigned int res, bit, ctrl; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); + ++ guard(raw_spinlock)(&pp->lock); + ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] &= ~BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); + } + + static void dw_pci_bottom_ack(struct irq_data *d) +@@ -160,54 +139,42 @@ static void dw_pci_bottom_ack(struct irq + } + + static struct irq_chip dw_pci_msi_bottom_irq_chip = { +- .name = "DWPCI-MSI", +- .irq_ack = dw_pci_bottom_ack, +- .irq_compose_msi_msg = dw_pci_setup_msi_msg, +- .irq_mask = dw_pci_bottom_mask, +- .irq_unmask = dw_pci_bottom_unmask, ++ .name = "DWPCI-MSI", ++ .irq_ack = dw_pci_bottom_ack, ++ .irq_compose_msi_msg = dw_pci_setup_msi_msg, ++ .irq_mask = dw_pci_bottom_mask, ++ .irq_unmask = dw_pci_bottom_unmask, + }; + +-static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, +- unsigned int virq, unsigned int nr_irqs, +- void *args) ++static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *args) + { + struct dw_pcie_rp *pp = domain->host_data; +- unsigned long flags; +- u32 i; + int bit; + +- raw_spin_lock_irqsave(&pp->lock, flags); +- +- bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, +- order_base_2(nr_irqs)); +- +- raw_spin_unlock_irqrestore(&pp->lock, flags); ++ scoped_guard (raw_spinlock_irq, &pp->lock) { ++ bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, ++ order_base_2(nr_irqs)); ++ } + + if (bit < 0) + return -ENOSPC; + +- for (i = 0; i < nr_irqs; i++) +- irq_domain_set_info(domain, virq + i, bit + i, +- pp->msi_irq_chip, +- pp, handle_edge_irq, +- NULL, NULL); +- ++ for (unsigned int i = 0; i < nr_irqs; i++) { ++ irq_domain_set_info(domain, virq + i, bit + i, pp->msi_irq_chip, ++ pp, handle_edge_irq, NULL, NULL); ++ } + return 0; + } + +-static void dw_pcie_irq_domain_free(struct irq_domain *domain, +- unsigned int virq, unsigned int nr_irqs) ++static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs) + { + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct dw_pcie_rp *pp = domain->host_data; +- unsigned long flags; +- +- raw_spin_lock_irqsave(&pp->lock, flags); +- +- bitmap_release_region(pp->msi_irq_in_use, d->hwirq, +- order_base_2(nr_irqs)); + +- raw_spin_unlock_irqrestore(&pp->lock, flags); ++ guard(raw_spinlock_irq)(&pp->lock); ++ bitmap_release_region(pp->msi_irq_in_use, d->hwirq, order_base_2(nr_irqs)); + } + + static const struct irq_domain_ops dw_pcie_msi_domain_ops = { +@@ -240,8 +207,7 @@ void dw_pcie_free_msi(struct dw_pcie_rp + + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { + if (pp->msi_irq[ctrl] > 0) +- irq_set_chained_handler_and_data(pp->msi_irq[ctrl], +- NULL, NULL); ++ irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); + } + + irq_domain_remove(pp->irq_domain); +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -810,7 +810,7 @@ static inline enum dw_pcie_ltssm dw_pcie + #ifdef CONFIG_PCIE_DW_HOST + int dw_pcie_suspend_noirq(struct dw_pcie *pci); + int dw_pcie_resume_noirq(struct dw_pcie *pci); +-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); ++void dw_handle_msi_irq(struct dw_pcie_rp *pp); + void dw_pcie_msi_init(struct dw_pcie_rp *pp); + int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); + void dw_pcie_free_msi(struct dw_pcie_rp *pp); +@@ -831,10 +831,7 @@ static inline int dw_pcie_resume_noirq(s + return 0; + } + +-static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) +-{ +- return IRQ_NONE; +-} ++static inline void dw_handle_msi_irq(struct dw_pcie_rp *pp) { } + + static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp) + { } diff --git a/target/linux/generic/backport-6.18/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch b/target/linux/generic/backport-6.18/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch new file mode 100644 index 0000000000..e14a6a8538 --- /dev/null +++ b/target/linux/generic/backport-6.18/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch @@ -0,0 +1,92 @@ +From eaf290c404f7c39f23292e9ce83b8b5b51ab598a Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Fri, 28 Nov 2025 16:20:55 -0500 +Subject: [PATCH] PCI: dwc: Enable MSI affinity support + +Leverage the interrupt redirection infrastructure to enable CPU affinity +support for MSI interrupts. Since the parent interrupt affinity cannot +be changed, affinity control for the child interrupt (MSI) is achieved +by redirecting the handler to run in IRQ work context on the target CPU. + +This patch was originally prepared by Thomas Gleixner (see Link tag below) +in a patch series that was never submitted as is, and only parts of that +series have made it upstream so far. + +Originally-by: Thomas Gleixner +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ +Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redhat.com +--- + .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++--- + 1 file changed, 28 insertions(+), 5 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -26,9 +26,27 @@ static struct pci_ops dw_pcie_ops; + static struct pci_ops dw_pcie_ecam_ops; + static struct pci_ops dw_child_pcie_ops; + ++#ifdef CONFIG_SMP ++static void dw_irq_noop(struct irq_data *d) { } ++#endif ++ ++static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain, ++ struct irq_domain *real_parent, struct msi_domain_info *info) ++{ ++ if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) ++ return false; ++ ++#ifdef CONFIG_SMP ++ info->chip->irq_ack = dw_irq_noop; ++ info->chip->irq_pre_redirect = irq_chip_pre_redirect_parent; ++#else ++ info->chip->irq_ack = irq_chip_ack_parent; ++#endif ++ return true; ++} ++ + #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ +- MSI_FLAG_NO_AFFINITY | \ + MSI_FLAG_PCI_MSI_MASK_PARENT) + #define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ + MSI_FLAG_PCI_MSIX | \ +@@ -40,9 +58,8 @@ static const struct msi_parent_ops dw_pc + .required_flags = DW_PCIE_MSI_FLAGS_REQUIRED, + .supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED, + .bus_select_token = DOMAIN_BUS_PCI_MSI, +- .chip_flags = MSI_CHIP_FLAG_SET_ACK, + .prefix = "DW-", +- .init_dev_msi_info = msi_lib_init_dev_msi_info, ++ .init_dev_msi_info = dw_pcie_init_dev_msi_info, + }; + + /* MSI int handler */ +@@ -63,7 +80,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp + continue; + + for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) +- generic_handle_domain_irq(pp->irq_domain, irq_off + pos); ++ generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos); + } + } + +@@ -140,10 +157,16 @@ static void dw_pci_bottom_ack(struct irq + + static struct irq_chip dw_pci_msi_bottom_irq_chip = { + .name = "DWPCI-MSI", +- .irq_ack = dw_pci_bottom_ack, + .irq_compose_msi_msg = dw_pci_setup_msi_msg, + .irq_mask = dw_pci_bottom_mask, + .irq_unmask = dw_pci_bottom_unmask, ++#ifdef CONFIG_SMP ++ .irq_ack = dw_irq_noop, ++ .irq_pre_redirect = dw_pci_bottom_ack, ++ .irq_set_affinity = irq_chip_redirect_set_affinity, ++#else ++ .irq_ack = dw_pci_bottom_ack, ++#endif + }; + + static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, diff --git a/target/linux/generic/backport-6.18/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch b/target/linux/generic/backport-6.18/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch new file mode 100644 index 0000000000..10c43608df --- /dev/null +++ b/target/linux/generic/backport-6.18/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch @@ -0,0 +1,56 @@ +From df439718afaf23b5aa7b5711b6c14e87b5836cae Mon Sep 17 00:00:00 2001 +From: Radu Rendec +Date: Mon, 12 Jan 2026 16:14:02 -0500 +Subject: [PATCH] genirq: Update effective affinity for redirected + interrupts + +For redirected interrupts, irq_chip_redirect_set_affinity() does not +update the effective affinity mask, which then triggers the warning in +irq_validate_effective_affinity(). Also, because the effective affinity +mask is empty, the cpumask_test_cpu(smp_processor_id(), m) condition in +demux_redirect_remote() is always false, and the interrupt is always +redirected, even if it's already running on the target CPU. + +Set the effective affinity mask to be the same as the requested affinity +mask. It's worth noting that irq_do_set_affinity() filters out offline +CPUs before calling chip->irq_set_affinity() (unless `force` is set), so +the mask passed to irq_chip_redirect_set_affinity() is already filtered. + +The solution is not ideal because it may lie about the effective +affinity of the demultiplexed ("child") interrupt. If the requested +affinity mask includes multiple CPUs, the effective affinity, in +reality, is the intersection between the requested mask and the +demultiplexing ("parent") interrupt's effective affinity mask, plus +the first CPU in the requested mask. + +Accurately describing the effective affinity of the demultiplexed +interrupt is not trivial because it requires keeping track of the +demultiplexing interrupt's effective affinity. That is tricky in the +context of CPU hot(un)plugging, where interrupt migration ordering is +not guaranteed. The solution in the initial version of the fixed patch, +which stored the first CPU of the demultiplexing interrupt's effective +affinity in the `target_cpu` field, has its own drawbacks and +limitations. + +Fixes: fcc1d0dabdb6 ("genirq: Add interrupt redirection infrastructure") +Reported-by: Jon Hunter +Signed-off-by: Radu Rendec +Signed-off-by: Thomas Gleixner +Tested-by: Jon Hunter +Link: https://patch.msgid.link/20260112211402.2927336-1-rrendec@redhat.com +Closes: https://lore.kernel.org/all/44509520-f29b-4b8a-8986-5eae3e022eb7@nvidia.com/ +--- + kernel/irq/chip.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -1514,6 +1514,8 @@ int irq_chip_redirect_set_affinity(struc + struct irq_redirect *redir = &irq_data_to_desc(data)->redirect; + + WRITE_ONCE(redir->target_cpu, cpumask_first(dest)); ++ irq_data_update_effective_affinity(data, dest); ++ + return IRQ_SET_MASK_OK; + } + EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); diff --git a/target/linux/siflower/patches-6.12/018-pci-dw-pcie-add-support-for-sf21-pcie.patch b/target/linux/siflower/patches-6.12/018-pci-dw-pcie-add-support-for-sf21-pcie.patch index 3be639f320..2b67e2f02b 100644 --- a/target/linux/siflower/patches-6.12/018-pci-dw-pcie-add-support-for-sf21-pcie.patch +++ b/target/linux/siflower/patches-6.12/018-pci-dw-pcie-add-support-for-sf21-pcie.patch @@ -13,7 +13,7 @@ Signed-off-by: Chuanhong Guo --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig -@@ -361,6 +361,15 @@ config PCIE_FU740 +@@ -362,6 +362,15 @@ config PCIE_FU740 Say Y here if you want PCIe controller support for the SiFive FU740. From 55cb7a0195af39b0258423a7fc68db27039d3f0e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 31 Jan 2026 18:10:15 +0800 Subject: [PATCH 33/46] rockchip: update irq affinity for RK3528 devices Since DW PCIe can adjust interrupts on SoC that only support MSI, adjust the interrupt of r8169 for the RK3528 devices. Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/21770 Signed-off-by: Hauke Mehrtens --- .../armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 66bdcb114e..ce563c24dd 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -32,9 +32,11 @@ case "$(board_name)" in armsom,sige7|\ friendlyarm,nanopi-r3s|\ friendlyarm,nanopi-r5c|\ +hinlink,h28k|\ hinlink,h66k|\ linkease,easepi-r1|\ lunzn,fastrhino-r66s|\ +radxa,e20c|\ radxa,e25|\ sinovoip,rk3568-bpi-r2pro) set_interface_core 2 "eth0" @@ -69,10 +71,6 @@ friendlyarm,nanopi-r6s) set_interface_core 20 "eth1" set_interface_core 40 "eth2" ;; -hinlink,h28k|\ -radxa,e20c) - set_interface_core 2 "eth0" - ;; hinlink,h68k) set_interface_core 2 "eth1" set_interface_core 4 "eth2" From 60fda6238c76e9ec75f8c239660309273b8951e2 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 24 Apr 2026 12:24:10 +0200 Subject: [PATCH 34/46] microchipsw: use 6.18 as default and drop 6.12 Now that 6.18 is stable there is no point in keeping 6.12 around. Signed-off-by: Robert Marko --- target/linux/microchipsw/Makefile | 3 +- target/linux/microchipsw/lan969x/config-6.12 | 266 - ...d-config-for-Microchip-SoC-platforms.patch | 74 - ...dd-support-for-Microchip-LAN969x-SoC.patch | 38 - ...-add-support-for-lan969x-SoC-pinctrl.patch | 348 - ...966x-make-clk_names-const-char-const.patch | 26 - ...x-prepare-driver-for-lan969x-support.patch | 151 - ...support-for-lan969x-SoC-clock-driver.patch | 70 - ...s-add-support-for-private-match-data.patch | 84 - ...5-serdes-add-constants-to-match-data.patch | 63 - ...s-add-constant-for-the-number-of-CMU.patch | 56 - ...-sparx5-serdes-add-ops-to-match-data.patch | 120 - ...s-add-function-for-getting-the-CMU-i.patch | 77 - ...s-add-indirection-layer-to-register-.patch | 1708 --- ...s-add-support-for-branching-on-chip-.patch | 101 - ...es-add-support-for-lan969x-serdes-dr.patch | 175 - ...-make-it-selectable-for-ARCH_LAN969X.patch | 26 - ...-Make-it-selectable-for-ARCH_LAN969X.patch | 26 - ...make-it-selectable-for-ARCH_MICROCHI.patch | 27 - ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 - ...-make-it-selectable-for-ARCH_MICROCH.patch | 29 - ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 - ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 - ...tmel-make-it-selectable-for-ARCH_MIC.patch | 28 - ...-make-it-selectable-for-ARCH_MICROCH.patch | 29 - ...5-add-support-for-private-match-data.patch | 135 - ...indirection-layer-to-register-macros.patch | 7398 ------------- ...t-sparx5-modify-SPX5_PORTS_ALL-macro.patch | 36 - ...d-sparx5-argument-to-a-few-functions.patch | 355 - ...t-sparx5-add-constants-to-match-data.patch | 88 - ...PX5_CONST-for-constants-which-alread.patch | 600 - ...PX5_CONST-for-constants-which-do-not.patch | 60 - ....13-net-sparx5-add-ops-to-match-data.patch | 227 - ...ut-chip-port-to-device-index-bit-fun.patch | 80 - ...ut-functions-for-getting-certain-arr.patch | 170 - ...ut-function-for-setting-the-port-mux.patch | 74 - ...3-net-sparx5-ops-out-PTP-IRQ-handler.patch | 56 - ...ut-function-for-DSM-calendar-calcula.patch | 137 - ...s_sparx5-macro-and-use-it-throughout.patch | 267 - ...ine-internal-ports-and-PGID-s-as-off.patch | 351 - ...upport-for-lan969x-targets-and-core-.patch | 169 - ...ge-spx5_wr-to-spx5_rmw-in-cal-update.patch | 48 - ...nge-frequency-calculation-for-SDLB-s.patch | 55 - ...parx5-context-pointer-to-a-few-funct.patch | 122 - ...x5-add-registers-required-by-lan969x.patch | 185 - ...t-lan969x-add-match-data-for-lan969x.patch | 216 - ...69x-add-register-diffs-to-match-data.patch | 365 - ...-lan969x-add-constants-to-match-data.patch | 54 - ...an969x-add-lan969x-ops-to-match-data.patch | 205 - ...net-lan969x-add-PTP-handler-function.patch | 180 - ...function-for-calculating-the-DSM-cal.patch | 359 - ...parx5-use-is_sparx5-macro-throughout.patch | 306 - ...x5-add-compatible-string-for-lan969x.patch | 38 - ...v6.13-net-sparx5-add-feature-support.patch | 130 - ...arx5-expose-some-sparx5-VCAP-symbols.patch | 116 - ...arx5-replace-SPX5_PORTS-with-n_ports.patch | 143 - ...add-new-VCAP-constants-to-match-data.patch | 97 - ...-execute-sparx5_vcap_init-on-lan969x.patch | 39 - ...x-add-autogenerated-VCAP-information.patch | 3916 ------- ...-lan969x-add-VCAP-configuration-data.patch | 166 - ...d-missing-lan969x-Kconfig-dependency.patch | 45 - ...cyclic-dependency-reported-by-depmod.patch | 9733 ----------------- ...-the-use-of-spin_lock-in-PTP-handler.patch | 33 - ...5-fix-default-value-of-monitor-ports.patch | 42 - ...-net-sparx5-do-some-preparation-work.patch | 78 - ...x5-add-function-for-RGMII-port-check.patch | 82 - ...-sparx5-use-is_port_rgmii-throughout.patch | 115 - ...low-speed-configuration-when-port-is.patch | 40 - ...return-PCS-for-modes-that-require-it.patch | 40 - ...v6.14-net-sparx5-verify-RGMII-speeds.patch | 37 - ...6.14-net-lan969x-add-RGMII-registers.patch | 211 - ...net-lan969x-add-RGMII-implementation.patch | 320 - ...14-net-sparx5-enable-FDMA-on-lan969x.patch | 32 - ...sparx5-split-sparx5_fdma_-start-stop.patch | 135 - ...net-sparx5-activate-FDMA-tx-in-start.patch | 61 - ...parx5-ops-out-certain-FDMA-functions.patch | 146 - ...-net-lan969x-add-FDMA-implementation.patch | 609 -- ...9x-Add-support-for-ethtool-pause-par.patch | 62 - ...quadspi-Add-support-for-sama7g5-QSPI.patch | 1175 -- ...i-Factor-out-switching-to-Serial-Mem.patch | 181 - ...l-quadspi-Use-devm_-clock-management.patch | 131 - ...i-Update-to-current-device-naming-te.patch | 66 - ...l-quadspi-Fix-warning-in-doc-comment.patch | 34 - ...i-remove-references-to-runtime-PM-on.patch | 41 - ...i-Fix-printed-error-code-during-DMA-.patch | 49 - ...i-Fix-unbalanced-pm_runtime-by-using.patch | 62 - ...-dmaengine-Add-devm_dma_request_chan.patch | 81 - ...el-quadspi-Use-devm_dma_request_chan.patch | 122 - ...i-add-padcalib-2xgclk-and-dllon-capa.patch | 178 - ...i-add-support-for-SAM9X7-QSPI-contro.patch | 58 - ...uadspi-Add-support-for-sama7d65-QSPI.patch | 57 - ...9x-fix-flooding-configuration-on-bri.patch | 137 - ...-make-it-selectable-for-ARCH_LAN969X.patch | 26 - ...s-make-it-selectable-for-ARCH_LAN969.patch | 29 - ....19-reset-sparx5-add-LAN969x-support.patch | 27 - ...ac-get-the-number-of-DMA-channels-fr.patch | 69 - ...arx5-lan969x-populate-netdev-of_node.patch | 26 - ...rochip-add-LAN969x-clock-header-file.patch | 44 - ...64-dts-microchip-add-LAN969x-support.patch | 508 - ...m64-dts-microchip-add-EV23X71A-board.patch | 786 -- ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 24 - ...1-implement-quirk-SDCLK-stop-while-r.patch | 66 - ...-sdhci-of-at91-add-hw_reset-callback.patch | 58 - ...f-at91-add-compatible-to-sama7g5-SoC.patch | 73 - ...91-add-support-for-HS400-and-HS400ES.patch | 95 - ...dhci-of-at91-issue-IP-reset-at-probe.patch | 28 - ...1-perform-a-hardware-reset-at-probe-.patch | 28 - ...ci-of-at91-add-preset-for-HS400-mode.patch | 36 - ...1-disable-selectively-clocks-on-pm-r.patch | 66 - ...1-do-not-advertise-SDR104-mode-suppo.patch | 40 - ...sdhci-of-at91-avoid-division-by-zero.patch | 48 - ...-of-at91-add-sama7g5-required-quirks.patch | 24 - ...i-of-at91-add-soc-data-field-quirks2.patch | 50 - ...oduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch | 37 - ...18-mmc-mmc-sdhci-of-at91-add-LAN969x.patch | 33 - ...uadspi-Add-support-for-LAN969x-QSPI0.patch | 80 - ...-lan9662-otp-add-support-for-LAN969x.patch | 68 - ...dts-microchip-lan969x-add-QSPI-nodes.patch | 51 - ...ts-microchip-lan969x-add-SDMMC-nodes.patch | 43 - ...4-dts-microchip-lan969x-add-OTP-node.patch | 26 - ...rochip-ev23x71a-enable-QSPI-and-eMMC.patch | 48 - ...69x-correct-RGMII-port-mapping-index.patch | 37 - ...-net-sparx5-add-MTU-change-framework.patch | 264 - .../128-net-sparx5-add-MTU-change.patch | 107 - .../129-net-lan969x-add-MTU-change.patch | 126 - .../130-net-sparx5-wire-in-MTU-change.patch | 33 - 126 files changed, 1 insertion(+), 37848 deletions(-) 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target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0093-v6.13-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0094-v6.20-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0095-v6.19-reset-sparx5-add-LAN969x-support.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0096-v6.20-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0098-01-v7.1-arm64-dts-microchip-add-LAN969x-clock-header-file.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0098-02-v7.1-arm64-dts-microchip-add-LAN969x-support.patch delete mode 100644 target/linux/microchipsw/patches-6.12/0098-03-v7.1-arm64-dts-microchip-add-EV23X71A-board.patch delete mode 100644 target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch delete mode 100644 target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch delete mode 100644 target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch delete mode 100644 target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch delete mode 100644 target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch delete mode 100644 target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch delete mode 100644 target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch delete mode 100644 target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch delete mode 100644 target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch delete mode 100644 target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch delete mode 100644 target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch delete mode 100644 target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch delete mode 100644 target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch delete mode 100644 target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch delete mode 100644 target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch delete mode 100644 target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch delete mode 100644 target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch delete mode 100644 target/linux/microchipsw/patches-6.12/122-arm64-dts-microchip-lan969x-add-QSPI-nodes.patch delete mode 100644 target/linux/microchipsw/patches-6.12/123-arm64-dts-microchip-lan969x-add-SDMMC-nodes.patch delete mode 100644 target/linux/microchipsw/patches-6.12/124-arm64-dts-microchip-lan969x-add-OTP-node.patch delete mode 100644 target/linux/microchipsw/patches-6.12/125-arm64-dts-microchip-ev23x71a-enable-QSPI-and-eMMC.patch delete mode 100644 target/linux/microchipsw/patches-6.12/126-net-lan969x-correct-RGMII-port-mapping-index.patch delete mode 100644 target/linux/microchipsw/patches-6.12/127-net-sparx5-add-MTU-change-framework.patch delete mode 100644 target/linux/microchipsw/patches-6.12/128-net-sparx5-add-MTU-change.patch delete mode 100644 target/linux/microchipsw/patches-6.12/129-net-lan969x-add-MTU-change.patch delete mode 100644 target/linux/microchipsw/patches-6.12/130-net-sparx5-wire-in-MTU-change.patch diff --git a/target/linux/microchipsw/Makefile b/target/linux/microchipsw/Makefile index 5881a50a7f..1eaedfd0ce 100644 --- a/target/linux/microchipsw/Makefile +++ b/target/linux/microchipsw/Makefile @@ -8,8 +8,7 @@ KERNELNAME:=Image CPU_TYPE:=cortex-a53 SUBTARGETS:=lan969x -KERNEL_PATCHVER:=6.12 -KERNEL_TESTING_PATCHVER:=6.18 +KERNEL_PATCHVER:=6.18 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/microchipsw/lan969x/config-6.12 b/target/linux/microchipsw/lan969x/config-6.12 deleted file mode 100644 index 8108574bb5..0000000000 --- a/target/linux/microchipsw/lan969x/config-6.12 +++ /dev/null @@ -1,266 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=10 -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_LAN969X=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MICROCHIP=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PKEY_BITS=3 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_EXECMEM_LATE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PLATFORM_DEVICES=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_PSCI_FW=y -CONFIG_AT_XDMAC=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_LAN966X=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPUMASK_OFFSTACK=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_RMAP=y -CONFIG_CRYPTO_DEV_ATMEL_AES=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DMADEVICES=y -CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_OF=y -CONFIG_DTC=y -CONFIG_DW_APB_TIMER=y -CONFIG_DW_APB_TIMER_OF=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FUNCTION_ALIGNMENT=4 -CONFIG_FUNCTION_ALIGNMENT_4B=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_ATMEL=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_AT91=y -# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_LIB=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LRU_GEN_WALKS_MMU=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_MSCC_MIIM=y -CONFIG_MFD_AT91_USART=y -CONFIG_MFD_ATMEL_FLEXCOM=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_AT91=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_INGRESS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_XGRESS=y -CONFIG_NLS=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_NR_CPUS=512 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAN9662_OTPC=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_SPARX5_SERDES=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MICROCHIP_SGPIO=y -CONFIG_PINCTRL_OCELOT=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_SUPPLY=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_MCHP_SPARX5=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SENSORS_SPARX5=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_ATMEL_PDC=y -CONFIG_SERIAL_ATMEL_TTYAT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -# CONFIG_SPARX5_SWITCH is not set -CONFIG_SPI=y -CONFIG_SPI_ATMEL=y -CONFIG_SPI_ATMEL_QUADSPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPLIT_PMD_PTLOCKS=y -CONFIG_SPLIT_PTE_PTLOCKS=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOOLS_SUPPORT_RELR=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_VCAP=y -CONFIG_VDSO_GETRANDOM=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch b/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch deleted file mode 100644 index 7cdd3bd45f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 83647d5b9b5b1f7315c908c8c35632cd46a47801 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:37 +0200 -Subject: [PATCH 01/25] arm64: Add config for Microchip SoC platforms - -Currently, Microchip SparX-5 SoC is supported and it has its own symbol. - -However, this means that new Microchip platforms that share drivers need -to constantly keep updating depends on various drivers. - -So, to try and reduce this lets add ARCH_MICROCHIP symbol that drivers -could instead depend on. - -LAN969x is being worked on and it will be added under ARCH_MICROCHIP. - -Signed-off-by: Robert Marko -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - arch/arm64/Kconfig.platforms | 36 ++++++++++++++++++++++-------------- - 1 file changed, 22 insertions(+), 14 deletions(-) - ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -114,20 +114,6 @@ config ARCH_EXYNOS - help - This enables support for ARMv8 based Samsung Exynos SoC family. - --config ARCH_SPARX5 -- bool "Microchip Sparx5 SoC family" -- select PINCTRL -- select DW_APB_TIMER_OF -- help -- This enables support for the Microchip Sparx5 ARMv8-based -- SoC family of TSN-capable gigabit switches. -- -- The SparX-5 Ethernet switch family provides a rich set of -- switching features such as advanced TCAM-based VLAN and QoS -- processing enabling delivery of differentiated services, and -- security through TCAM-based frame processing using versatile -- content aware processor (VCAP). -- - config ARCH_K3 - bool "Texas Instruments Inc. K3 multicore SoC architecture" - select PM_GENERIC_DOMAINS if PM -@@ -175,6 +161,28 @@ config ARCH_MESON - This enables support for the arm64 based Amlogic SoCs - such as the s905, S905X/D, S912, A113X/D or S905X/D2 - -+menu "Microchip SoC support" -+ -+config ARCH_MICROCHIP -+ bool -+ -+config ARCH_SPARX5 -+ bool "Microchip Sparx5 SoC family" -+ select PINCTRL -+ select DW_APB_TIMER_OF -+ select ARCH_MICROCHIP -+ help -+ This enables support for the Microchip Sparx5 ARMv8-based -+ SoC family of TSN-capable gigabit switches. -+ -+ The SparX-5 Ethernet switch family provides a rich set of -+ switching features such as advanced TCAM-based VLAN and QoS -+ processing enabling delivery of differentiated services, and -+ security through TCAM-based frame processing using versatile -+ content aware processor (VCAP). -+ -+endmenu -+ - config ARCH_MVEBU - bool "Marvell EBU SoC Family" - select ARMADA_AP806_SYSCON diff --git a/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch b/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch deleted file mode 100644 index 727fcb65a0..0000000000 --- a/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 64016a564b81491c092ef03c7e11305650d8641a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:39 +0200 -Subject: [PATCH 02/25] arm64: lan969x: Add support for Microchip LAN969x SoC - -This adds support for the Microchip LAN969x ARMv8-based SoC switch family. - -Signed-off-by: Robert Marko -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - arch/arm64/Kconfig.platforms | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -166,6 +166,21 @@ menu "Microchip SoC support" - config ARCH_MICROCHIP - bool - -+config ARCH_LAN969X -+ bool "Microchip LAN969X SoC family" -+ select PINCTRL -+ select DW_APB_TIMER_OF -+ select ARCH_MICROCHIP -+ help -+ This enables support for the Microchip LAN969X ARMv8-based -+ SoC family of TSN-capable gigabit switches. -+ -+ The LAN969X Ethernet switch family provides a rich set of -+ switching features such as advanced TCAM-based VLAN and QoS -+ processing enabling delivery of differentiated services, and -+ security through TCAM-based frame processing using versatile -+ content aware processor (VCAP). -+ - config ARCH_SPARX5 - bool "Microchip Sparx5 SoC family" - select PINCTRL diff --git a/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch b/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch deleted file mode 100644 index 723bddfdf4..0000000000 --- a/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch +++ /dev/null @@ -1,348 +0,0 @@ -From bcf540500e1feb072cf7659f71a437a63f1735f9 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Tue, 17 Sep 2024 14:45:41 +0200 -Subject: [PATCH 03/25] pinctrl: ocelot: add support for lan969x SoC pinctrl - -This adds support for lan969x SoC pinctrl, reusing the existing ocelot -driver. There are 66 General Purpose I/O pins that are individually -configurable to multiple interfaces. - -Signed-off-by: Daniel Machon -Link: https://lore.kernel.org/20240917-lan969x-pinctrl-v2-2-ea02cbc56831@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-ocelot.c | 203 +++++++++++++++++++++++++++++++ - 1 file changed, 203 insertions(+) - ---- a/drivers/pinctrl/pinctrl-ocelot.c -+++ b/drivers/pinctrl/pinctrl-ocelot.c -@@ -57,6 +57,8 @@ enum { - FUNC_CAN1, - FUNC_CLKMON, - FUNC_NONE, -+ FUNC_FAN, -+ FUNC_FC, - FUNC_FC0_a, - FUNC_FC0_b, - FUNC_FC0_c, -@@ -71,6 +73,7 @@ enum { - FUNC_FC4_a, - FUNC_FC4_b, - FUNC_FC4_c, -+ FUNC_FC_SHRD, - FUNC_FC_SHRD0, - FUNC_FC_SHRD1, - FUNC_FC_SHRD2, -@@ -92,6 +95,7 @@ enum { - FUNC_FC_SHRD18, - FUNC_FC_SHRD19, - FUNC_FC_SHRD20, -+ FUNC_FUSA, - FUNC_GPIO, - FUNC_IB_TRG_a, - FUNC_IB_TRG_b, -@@ -108,6 +112,8 @@ enum { - FUNC_IRQ1, - FUNC_IRQ1_IN, - FUNC_IRQ1_OUT, -+ FUNC_IRQ3, -+ FUNC_IRQ4, - FUNC_EXT_IRQ, - FUNC_MIIM, - FUNC_MIIM_a, -@@ -115,12 +121,14 @@ enum { - FUNC_MIIM_c, - FUNC_MIIM_Sa, - FUNC_MIIM_Sb, -+ FUNC_MIIM_IRQ, - FUNC_OB_TRG, - FUNC_OB_TRG_a, - FUNC_OB_TRG_b, - FUNC_PHY_LED, - FUNC_PCI_WAKE, - FUNC_MD, -+ FUNC_PCIE_PERST, - FUNC_PTP0, - FUNC_PTP1, - FUNC_PTP2, -@@ -152,6 +160,7 @@ enum { - FUNC_SGPIO_b, - FUNC_SI, - FUNC_SI2, -+ FUNC_SYNCE, - FUNC_TACHO, - FUNC_TACHO_a, - FUNC_TACHO_b, -@@ -170,6 +179,10 @@ enum { - FUNC_USB_S_a, - FUNC_USB_S_b, - FUNC_USB_S_c, -+ FUNC_USB_POWER, -+ FUNC_USB2PHY_RST, -+ FUNC_USB_OVER_DETECT, -+ FUNC_USB_ULPI, - FUNC_PLL_STAT, - FUNC_EMMC, - FUNC_EMMC_SD, -@@ -184,6 +197,8 @@ static const char *const ocelot_function - [FUNC_CAN1] = "can1", - [FUNC_CLKMON] = "clkmon", - [FUNC_NONE] = "none", -+ [FUNC_FAN] = "fan", -+ [FUNC_FC] = "fc", - [FUNC_FC0_a] = "fc0_a", - [FUNC_FC0_b] = "fc0_b", - [FUNC_FC0_c] = "fc0_c", -@@ -198,6 +213,7 @@ static const char *const ocelot_function - [FUNC_FC4_a] = "fc4_a", - [FUNC_FC4_b] = "fc4_b", - [FUNC_FC4_c] = "fc4_c", -+ [FUNC_FC_SHRD] = "fc_shrd", - [FUNC_FC_SHRD0] = "fc_shrd0", - [FUNC_FC_SHRD1] = "fc_shrd1", - [FUNC_FC_SHRD2] = "fc_shrd2", -@@ -219,6 +235,7 @@ static const char *const ocelot_function - [FUNC_FC_SHRD18] = "fc_shrd18", - [FUNC_FC_SHRD19] = "fc_shrd19", - [FUNC_FC_SHRD20] = "fc_shrd20", -+ [FUNC_FUSA] = "fusa", - [FUNC_GPIO] = "gpio", - [FUNC_IB_TRG_a] = "ib_trig_a", - [FUNC_IB_TRG_b] = "ib_trig_b", -@@ -235,6 +252,8 @@ static const char *const ocelot_function - [FUNC_IRQ1] = "irq1", - [FUNC_IRQ1_IN] = "irq1_in", - [FUNC_IRQ1_OUT] = "irq1_out", -+ [FUNC_IRQ3] = "irq3", -+ [FUNC_IRQ4] = "irq4", - [FUNC_EXT_IRQ] = "ext_irq", - [FUNC_MIIM] = "miim", - [FUNC_MIIM_a] = "miim_a", -@@ -242,8 +261,10 @@ static const char *const ocelot_function - [FUNC_MIIM_c] = "miim_c", - [FUNC_MIIM_Sa] = "miim_slave_a", - [FUNC_MIIM_Sb] = "miim_slave_b", -+ [FUNC_MIIM_IRQ] = "miim_irq", - [FUNC_PHY_LED] = "phy_led", - [FUNC_PCI_WAKE] = "pci_wake", -+ [FUNC_PCIE_PERST] = "pcie_perst", - [FUNC_MD] = "md", - [FUNC_OB_TRG] = "ob_trig", - [FUNC_OB_TRG_a] = "ob_trig_a", -@@ -279,6 +300,7 @@ static const char *const ocelot_function - [FUNC_SGPIO_b] = "sgpio_b", - [FUNC_SI] = "si", - [FUNC_SI2] = "si2", -+ [FUNC_SYNCE] = "synce", - [FUNC_TACHO] = "tacho", - [FUNC_TACHO_a] = "tacho_a", - [FUNC_TACHO_b] = "tacho_b", -@@ -294,6 +316,10 @@ static const char *const ocelot_function - [FUNC_USB_S_a] = "usb_slave_a", - [FUNC_USB_S_b] = "usb_slave_b", - [FUNC_USB_S_c] = "usb_slave_c", -+ [FUNC_USB_POWER] = "usb_power", -+ [FUNC_USB2PHY_RST] = "usb2phy_rst", -+ [FUNC_USB_OVER_DETECT] = "usb_over_detect", -+ [FUNC_USB_ULPI] = "usb_ulpi", - [FUNC_UART] = "uart", - [FUNC_UART2] = "uart2", - [FUNC_UART3] = "uart3", -@@ -1136,6 +1162,165 @@ static const struct pinctrl_pin_desc lan - LAN966X_PIN(77), - }; - -+#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ -+static struct ocelot_pin_caps lan969x_pin_##p = { \ -+ .pin = p, \ -+ .functions = { \ -+ FUNC_##f0, FUNC_##f1, FUNC_##f2, \ -+ FUNC_##f3 \ -+ }, \ -+ .a_functions = { \ -+ FUNC_##f4, FUNC_##f5, FUNC_##f6, \ -+ FUNC_##f7 \ -+ }, \ -+} -+ -+/* Pinmuxing table taken from data sheet */ -+/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ -+LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R); -+LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R); -+LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); -+LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); -+LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); -+LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); -+LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R); -+LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R); -+LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); -+LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); -+LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); -+LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R); -+LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R); -+LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R); -+LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R); -+LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); -+LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); -+LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); -+LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); -+LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R); -+LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R); -+LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); -+LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); -+LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); -+LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R); -+LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); -+LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); -+LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); -+LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); -+LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R); -+LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R); -+LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R); -+LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); -+LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); -+LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); -+LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); -+LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R); -+LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R); -+LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R); -+LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R); -+LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); -+LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); -+LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R); -+LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); -+LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); -+LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); -+ -+#define LAN969X_PIN(n) { \ -+ .number = n, \ -+ .name = "GPIO_"#n, \ -+ .drv_data = &lan969x_pin_##n \ -+} -+ -+static const struct pinctrl_pin_desc lan969x_pins[] = { -+ LAN969X_PIN(0), -+ LAN969X_PIN(1), -+ LAN969X_PIN(2), -+ LAN969X_PIN(3), -+ LAN969X_PIN(4), -+ LAN969X_PIN(5), -+ LAN969X_PIN(6), -+ LAN969X_PIN(7), -+ LAN969X_PIN(8), -+ LAN969X_PIN(9), -+ LAN969X_PIN(10), -+ LAN969X_PIN(11), -+ LAN969X_PIN(12), -+ LAN969X_PIN(13), -+ LAN969X_PIN(14), -+ LAN969X_PIN(15), -+ LAN969X_PIN(16), -+ LAN969X_PIN(17), -+ LAN969X_PIN(18), -+ LAN969X_PIN(19), -+ LAN969X_PIN(20), -+ LAN969X_PIN(21), -+ LAN969X_PIN(22), -+ LAN969X_PIN(23), -+ LAN969X_PIN(24), -+ LAN969X_PIN(25), -+ LAN969X_PIN(26), -+ LAN969X_PIN(27), -+ LAN969X_PIN(28), -+ LAN969X_PIN(29), -+ LAN969X_PIN(30), -+ LAN969X_PIN(31), -+ LAN969X_PIN(32), -+ LAN969X_PIN(33), -+ LAN969X_PIN(34), -+ LAN969X_PIN(35), -+ LAN969X_PIN(36), -+ LAN969X_PIN(37), -+ LAN969X_PIN(38), -+ LAN969X_PIN(39), -+ LAN969X_PIN(40), -+ LAN969X_PIN(41), -+ LAN969X_PIN(42), -+ LAN969X_PIN(43), -+ LAN969X_PIN(44), -+ LAN969X_PIN(45), -+ LAN969X_PIN(46), -+ LAN969X_PIN(47), -+ LAN969X_PIN(48), -+ LAN969X_PIN(49), -+ LAN969X_PIN(50), -+ LAN969X_PIN(51), -+ LAN969X_PIN(52), -+ LAN969X_PIN(53), -+ LAN969X_PIN(54), -+ LAN969X_PIN(55), -+ LAN969X_PIN(56), -+ LAN969X_PIN(57), -+ LAN969X_PIN(58), -+ LAN969X_PIN(59), -+ LAN969X_PIN(60), -+ LAN969X_PIN(61), -+ LAN969X_PIN(62), -+ LAN969X_PIN(63), -+ LAN969X_PIN(64), -+ LAN969X_PIN(65), -+ LAN969X_PIN(66), -+}; -+ - static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) - { - return ARRAY_SIZE(ocelot_function_names); -@@ -1682,6 +1867,23 @@ static struct ocelot_match_data lan966x_ - }, - }; - -+static struct ocelot_match_data lan969x_desc = { -+ .desc = { -+ .name = "lan969x-pinctrl", -+ .pins = lan969x_pins, -+ .npins = ARRAY_SIZE(lan969x_pins), -+ .pctlops = &ocelot_pctl_ops, -+ .pmxops = &lan966x_pmx_ops, -+ .confops = &ocelot_confops, -+ .owner = THIS_MODULE, -+ }, -+ .pincfg_data = { -+ .pd_bit = BIT(3), -+ .pu_bit = BIT(2), -+ .drive_bits = GENMASK(1, 0), -+ }, -+}; -+ - static int ocelot_create_group_func_map(struct device *dev, - struct ocelot_pinctrl *info) - { -@@ -2014,6 +2216,7 @@ static const struct of_device_id ocelot_ - { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, - { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, - { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, -+ { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, - {}, - }; - MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); diff --git a/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch b/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch deleted file mode 100644 index f210904313..0000000000 --- a/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 60b15ad144394ef5da427160fd947af93affef72 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 16 Sep 2024 11:49:20 +0200 -Subject: [PATCH 04/25] clk: lan966x: make clk_names const char * const - -Change clk_names to const char * const to silence checkpatch in -subsequent patches. - -Signed-off-by: Daniel Machon -Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-2-0e150336074d@microchip.com -Signed-off-by: Claudiu Beznea ---- - drivers/clk/clk-lan966x.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/clk-lan966x.c -+++ b/drivers/clk/clk-lan966x.c -@@ -24,7 +24,7 @@ - - #define DIV_MAX 255 - --static const char *clk_names[N_CLOCKS] = { -+static const char * const clk_names[N_CLOCKS] = { - "qspi0", "qspi1", "qspi2", "sdmmc0", - "pi", "mcan0", "mcan1", "flexcom0", - "flexcom1", "flexcom2", "flexcom3", diff --git a/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch b/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch deleted file mode 100644 index 86c8504eff..0000000000 --- a/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 471d54facf2a1ee5740839e7870873a3f5965911 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 16 Sep 2024 11:49:21 +0200 -Subject: [PATCH 05/25] clk: lan966x: prepare driver for lan969x support - -In preparation for lan969x support, add private match data for lan966x -and add variables for: peripheral clock names, clock gate names, number -of total clocks and number of generic clocks. Use the variables -throughout. - -Signed-off-by: Daniel Machon -Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-3-0e150336074d@microchip.com -[claudiu.beznea: in lan966x_clk_probe(): keep struct_size() arguments on - a single line] -Signed-off-by: Claudiu Beznea ---- - drivers/clk/clk-lan966x.c | 55 +++++++++++++++++++++++++++------------ - 1 file changed, 39 insertions(+), 16 deletions(-) - ---- a/drivers/clk/clk-lan966x.c -+++ b/drivers/clk/clk-lan966x.c -@@ -24,7 +24,7 @@ - - #define DIV_MAX 255 - --static const char * const clk_names[N_CLOCKS] = { -+static const char * const lan966x_clk_names[] = { - "qspi0", "qspi1", "qspi2", "sdmmc0", - "pi", "mcan0", "mcan1", "flexcom0", - "flexcom1", "flexcom2", "flexcom3", -@@ -53,7 +53,7 @@ struct clk_gate_soc_desc { - int bit_idx; - }; - --static const struct clk_gate_soc_desc clk_gate_desc[] = { -+static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = { - { "uhphs", 11 }, - { "udphs", 10 }, - { "mcramc", 9 }, -@@ -61,6 +61,22 @@ static const struct clk_gate_soc_desc cl - { } - }; - -+struct lan966x_match_data { -+ char *name; -+ const char * const *clk_name; -+ const struct clk_gate_soc_desc *clk_gate_desc; -+ u8 num_generic_clks; -+ u8 num_total_clks; -+}; -+ -+static struct lan966x_match_data lan966x_desc = { -+ .name = "lan966x", -+ .clk_name = lan966x_clk_names, -+ .clk_gate_desc = lan966x_clk_gate_desc, -+ .num_total_clks = 18, -+ .num_generic_clks = 14, -+}; -+ - static DEFINE_SPINLOCK(clk_gate_lock); - static void __iomem *base; - -@@ -186,24 +202,26 @@ static struct clk_hw *lan966x_gck_clk_re - }; - - static int lan966x_gate_clk_register(struct device *dev, -+ const struct lan966x_match_data *data, - struct clk_hw_onecell_data *hw_data, - void __iomem *gate_base) - { -- int i; -+ for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) { -+ int idx = i - data->num_generic_clks; -+ const struct clk_gate_soc_desc *desc; - -- for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) { -- int idx = i - GCK_GATE_UHPHS; -+ desc = &data->clk_gate_desc[idx]; - - hw_data->hws[i] = -- devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, -- "lan966x", 0, gate_base, -- clk_gate_desc[idx].bit_idx, -+ devm_clk_hw_register_gate(dev, desc->name, -+ data->name, 0, gate_base, -+ desc->bit_idx, - 0, &clk_gate_lock); - - if (IS_ERR(hw_data->hws[i])) - return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]), - "failed to register %s clock\n", -- clk_gate_desc[idx].name); -+ desc->name); - } - - return 0; -@@ -211,13 +229,18 @@ static int lan966x_gate_clk_register(str - - static int lan966x_clk_probe(struct platform_device *pdev) - { -+ const struct lan966x_match_data *data; - struct clk_hw_onecell_data *hw_data; - struct device *dev = &pdev->dev; - void __iomem *gate_base; - struct resource *res; - int i, ret; - -- hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS), -+ data = device_get_match_data(dev); -+ if (!data) -+ return -EINVAL; -+ -+ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, data->num_total_clks), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; -@@ -228,10 +251,10 @@ static int lan966x_clk_probe(struct plat - - init.ops = &lan966x_gck_ops; - -- hw_data->num = GCK_GATE_UHPHS; -+ hw_data->num = data->num_generic_clks; - -- for (i = 0; i < GCK_GATE_UHPHS; i++) { -- init.name = clk_names[i]; -+ for (i = 0; i < data->num_generic_clks; i++) { -+ init.name = data->clk_name[i]; - hw_data->hws[i] = lan966x_gck_clk_register(dev, i); - if (IS_ERR(hw_data->hws[i])) { - dev_err(dev, "failed to register %s clock\n", -@@ -246,9 +269,9 @@ static int lan966x_clk_probe(struct plat - if (IS_ERR(gate_base)) - return PTR_ERR(gate_base); - -- hw_data->num = N_CLOCKS; -+ hw_data->num = data->num_total_clks; - -- ret = lan966x_gate_clk_register(dev, hw_data, gate_base); -+ ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base); - if (ret) - return ret; - } -@@ -257,7 +280,7 @@ static int lan966x_clk_probe(struct plat - } - - static const struct of_device_id lan966x_clk_dt_ids[] = { -- { .compatible = "microchip,lan966x-gck", }, -+ { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, - { } - }; - MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); diff --git a/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch b/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch deleted file mode 100644 index be6188584f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 5b89e2d7ec7afd2e2d92f90f90f232e17d70cfc0 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 16 Sep 2024 11:49:22 +0200 -Subject: [PATCH 06/25] clk: lan966x: add support for lan969x SoC clock driver - -Add support for the lan969x SoC clock driver in the existing lan966x -driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk -and sys_clk (same as lan966x) which generates and supplies the clock to -various peripherals within the SoC. - -Signed-off-by: Daniel Machon -Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-4-0e150336074d@microchip.com -Signed-off-by: Claudiu Beznea ---- - drivers/clk/clk-lan966x.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/clk/clk-lan966x.c -+++ b/drivers/clk/clk-lan966x.c -@@ -31,6 +31,13 @@ static const char * const lan966x_clk_na - "flexcom4", "timer1", "usb_refclk", - }; - -+static const char * const lan969x_clk_names[] = { -+ "qspi0", "qspi2", "sdmmc0", "sdmmc1", -+ "mcan0", "mcan1", "flexcom0", -+ "flexcom1", "flexcom2", "flexcom3", -+ "timer1", "usb_refclk", -+}; -+ - struct lan966x_gck { - struct clk_hw hw; - void __iomem *reg; -@@ -61,6 +68,13 @@ static const struct clk_gate_soc_desc la - { } - }; - -+static const struct clk_gate_soc_desc lan969x_clk_gate_desc[] = { -+ { "usb_drd", 10 }, -+ { "mcramc", 9 }, -+ { "hmatrix", 8 }, -+ { } -+}; -+ - struct lan966x_match_data { - char *name; - const char * const *clk_name; -@@ -77,6 +91,14 @@ static struct lan966x_match_data lan966x - .num_generic_clks = 14, - }; - -+static struct lan966x_match_data lan969x_desc = { -+ .name = "lan969x", -+ .clk_name = lan969x_clk_names, -+ .clk_gate_desc = lan969x_clk_gate_desc, -+ .num_total_clks = 15, -+ .num_generic_clks = 12, -+}; -+ - static DEFINE_SPINLOCK(clk_gate_lock); - static void __iomem *base; - -@@ -281,6 +303,7 @@ static int lan966x_clk_probe(struct plat - - static const struct of_device_id lan966x_clk_dt_ids[] = { - { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, -+ { .compatible = "microchip,lan9691-gck", .data = &lan969x_desc }, - { } - }; - MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); diff --git a/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch b/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch deleted file mode 100644 index 4e15737ef6..0000000000 --- a/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 6c18e8aba5313a930a72c5b2143e73e2cc437a14 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:41 +0200 -Subject: [PATCH 08/25] phy: sparx5-serdes: add support for private match data - -In order to reuse the existing Sparx5 SERDES driver for lan969x, we add -support for private match data, with initial fields for the iomap and -imap_size. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-1-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 16 +++++++++++++--- - drivers/phy/microchip/sparx5_serdes.h | 6 ++++++ - 2 files changed, 19 insertions(+), 3 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -2507,6 +2507,11 @@ static struct sparx5_serdes_io_resource - { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ - }; - -+static const struct sparx5_serdes_match_data sparx5_desc = { -+ .iomap = sparx5_serdes_iomap, -+ .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), -+}; -+ - /* Client lookup function, uses serdes index */ - static struct phy *sparx5_serdes_xlate(struct device *dev, - const struct of_phandle_args *args) -@@ -2555,6 +2560,10 @@ static int sparx5_serdes_probe(struct pl - platform_set_drvdata(pdev, priv); - priv->dev = &pdev->dev; - -+ priv->data = device_get_match_data(priv->dev); -+ if (!priv->data) -+ return -EINVAL; -+ - /* Get coreclock */ - clk = devm_clk_get(priv->dev, NULL); - if (IS_ERR(clk)) { -@@ -2579,8 +2588,9 @@ static int sparx5_serdes_probe(struct pl - iores->name); - return -ENOMEM; - } -- for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) { -- struct sparx5_serdes_io_resource *iomap = &sparx5_serdes_iomap[idx]; -+ for (idx = 0; idx < priv->data->iomap_size; idx++) { -+ const struct sparx5_serdes_io_resource *iomap = -+ &priv->data->iomap[idx]; - - priv->regs[iomap->id] = iomem + iomap->offset; - } -@@ -2599,7 +2609,7 @@ static int sparx5_serdes_probe(struct pl - } - - static const struct of_device_id sparx5_serdes_match[] = { -- { .compatible = "microchip,sparx5-serdes" }, -+ { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc }, - { } - }; - MODULE_DEVICE_TABLE(of, sparx5_serdes_match); ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -26,11 +26,17 @@ enum sparx5_serdes_mode { - SPX5_SD_MODE_SFI, - }; - -+struct sparx5_serdes_match_data { -+ const struct sparx5_serdes_io_resource *iomap; -+ int iomap_size; -+}; -+ - struct sparx5_serdes_private { - struct device *dev; - void __iomem *regs[NUM_TARGETS]; - struct phy *phys[SPX5_SERDES_MAX]; - unsigned long coreclock; -+ const struct sparx5_serdes_match_data *data; - }; - - struct sparx5_serdes_macro { diff --git a/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch deleted file mode 100644 index 18f97bc4bd..0000000000 --- a/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 484f940614857bfb2766c6a0dadd6f77485ba992 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:42 +0200 -Subject: [PATCH 09/25] phy: sparx5-serdes: add constants to match data - -We need to handle a few different constants that differ for Sparx5 and -lan969x. Add a new struct: sparx5_serdes_consts for this purpose. We -populate it with an initial field for the number of SERDES'es: sd_max. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-2-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 7 +++++-- - drivers/phy/microchip/sparx5_serdes.h | 5 +++++ - 2 files changed, 10 insertions(+), 2 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -2510,6 +2510,9 @@ static struct sparx5_serdes_io_resource - static const struct sparx5_serdes_match_data sparx5_desc = { - .iomap = sparx5_serdes_iomap, - .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), -+ .consts = { -+ .sd_max = 33, -+ }, - }; - - /* Client lookup function, uses serdes index */ -@@ -2526,7 +2529,7 @@ static struct phy *sparx5_serdes_xlate(s - sidx = args->args[0]; - - /* Check validity: ERR_PTR(-ENODEV) if not valid */ -- for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { -+ for (idx = 0; idx < priv->data->consts.sd_max; idx++) { - struct sparx5_serdes_macro *macro = - phy_get_drvdata(priv->phys[idx]); - -@@ -2594,7 +2597,7 @@ static int sparx5_serdes_probe(struct pl - - priv->regs[iomap->id] = iomem + iomap->offset; - } -- for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { -+ for (idx = 0; idx < priv->data->consts.sd_max; idx++) { - err = sparx5_phy_create(priv, idx, &priv->phys[idx]); - if (err) - return err; ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -26,7 +26,12 @@ enum sparx5_serdes_mode { - SPX5_SD_MODE_SFI, - }; - -+struct sparx5_serdes_consts { -+ int sd_max; -+}; -+ - struct sparx5_serdes_match_data { -+ const struct sparx5_serdes_consts consts; - const struct sparx5_serdes_io_resource *iomap; - int iomap_size; - }; diff --git a/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch b/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch deleted file mode 100644 index ad4a3afc40..0000000000 --- a/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 25fec35ac0e5bf3f9da0920055c278bb170983d2 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:43 +0200 -Subject: [PATCH 10/25] phy: sparx5-serdes: add constant for the number of - CMU's - -The number of CMU's differ for Sparx5 and lan969x, so add a new field: -cmu_max and use it throughout. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-3-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 5 ++--- - drivers/phy/microchip/sparx5_serdes.h | 1 + - 2 files changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -21,8 +21,6 @@ - - #include "sparx5_serdes.h" - --#define SPX5_CMU_MAX 14 -- - #define SPX5_SERDES_10G_START 13 - #define SPX5_SERDES_25G_START 25 - #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START -@@ -1101,7 +1099,7 @@ static void sparx5_serdes_cmu_power_off( - int i; - - /* Power down each CMU */ -- for (i = 0; i < SPX5_CMU_MAX; i++) { -+ for (i = 0; i < priv->data->consts.cmu_max; i++) { - cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i); - cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i); - -@@ -2512,6 +2510,7 @@ static const struct sparx5_serdes_match_ - .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), - .consts = { - .sd_max = 33, -+ .cmu_max = 14, - }, - }; - ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -28,6 +28,7 @@ enum sparx5_serdes_mode { - - struct sparx5_serdes_consts { - int sd_max; -+ int cmu_max; - }; - - struct sparx5_serdes_match_data { diff --git a/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch deleted file mode 100644 index 151710ad27..0000000000 --- a/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 06d4a10a636ef4c97680007abb4625b9eebbf169 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:44 +0200 -Subject: [PATCH 11/25] phy: sparx5-serdes: add ops to match data - -We need to handle code differently in a few places. Add a struct: -sparx5_serdes_ops for this purpose, and populate it a with function to -set the SERDES type. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-4-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 29 ++++++++++++++++++--------- - drivers/phy/microchip/sparx5_serdes.h | 27 +++++++++++++++---------- - 2 files changed, 35 insertions(+), 21 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -2373,6 +2373,20 @@ static const struct phy_ops sparx5_serde - .owner = THIS_MODULE, - }; - -+static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) -+{ -+ if (sidx < SPX5_SERDES_10G_START) { -+ macro->serdestype = SPX5_SDT_6G; -+ macro->stpidx = macro->sidx; -+ } else if (sidx < SPX5_SERDES_25G_START) { -+ macro->serdestype = SPX5_SDT_10G; -+ macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; -+ } else { -+ macro->serdestype = SPX5_SDT_25G; -+ macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; -+ } -+} -+ - static int sparx5_phy_create(struct sparx5_serdes_private *priv, - int idx, struct phy **phy) - { -@@ -2389,16 +2403,8 @@ static int sparx5_phy_create(struct spar - macro->sidx = idx; - macro->priv = priv; - macro->speed = SPEED_UNKNOWN; -- if (idx < SPX5_SERDES_10G_START) { -- macro->serdestype = SPX5_SDT_6G; -- macro->stpidx = macro->sidx; -- } else if (idx < SPX5_SERDES_25G_START) { -- macro->serdestype = SPX5_SDT_10G; -- macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; -- } else { -- macro->serdestype = SPX5_SDT_25G; -- macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; -- } -+ -+ priv->data->ops.serdes_type_set(macro, idx); - - phy_set_drvdata(*phy, macro); - -@@ -2512,6 +2518,9 @@ static const struct sparx5_serdes_match_ - .sd_max = 33, - .cmu_max = 14, - }, -+ .ops = { -+ .serdes_type_set = &sparx5_serdes_type_set, -+ }, - }; - - /* Client lookup function, uses serdes index */ ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -26,13 +26,29 @@ enum sparx5_serdes_mode { - SPX5_SD_MODE_SFI, - }; - -+struct sparx5_serdes_macro { -+ struct sparx5_serdes_private *priv; -+ u32 sidx; -+ u32 stpidx; -+ enum sparx5_serdes_type serdestype; -+ enum sparx5_serdes_mode serdesmode; -+ phy_interface_t portmode; -+ int speed; -+ enum phy_media media; -+}; -+ - struct sparx5_serdes_consts { - int sd_max; - int cmu_max; - }; - -+struct sparx5_serdes_ops { -+ void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx); -+}; -+ - struct sparx5_serdes_match_data { - const struct sparx5_serdes_consts consts; -+ const struct sparx5_serdes_ops ops; - const struct sparx5_serdes_io_resource *iomap; - int iomap_size; - }; -@@ -45,17 +61,6 @@ struct sparx5_serdes_private { - const struct sparx5_serdes_match_data *data; - }; - --struct sparx5_serdes_macro { -- struct sparx5_serdes_private *priv; -- u32 sidx; -- u32 stpidx; -- enum sparx5_serdes_type serdestype; -- enum sparx5_serdes_mode serdesmode; -- phy_interface_t portmode; -- int speed; -- enum phy_media media; --}; -- - /* Read, Write and modify registers content. - * The register definition macros start at the id - */ diff --git a/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch b/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch deleted file mode 100644 index 4807ba8b0b..0000000000 --- a/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch +++ /dev/null @@ -1,77 +0,0 @@ -From e072ab8d032cd89a6c5333652c2ea909a8942b8a Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:45 +0200 -Subject: [PATCH 12/25] phy: sparx5-serdes: add function for getting the CMU - index - -The SERDES to CMU mapping is different on Sparx5 and lan969x. Therefore -create a function for getting the CMU index on Sparx5. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-5-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 11 ++--------- - drivers/phy/microchip/sparx5_serdes.h | 9 +++++++++ - 2 files changed, 11 insertions(+), 9 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -28,14 +28,6 @@ - /* Optimal power settings from GUC */ - #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c - --enum sparx5_10g28cmu_mode { -- SPX5_SD10G28_CMU_MAIN = 0, -- SPX5_SD10G28_CMU_AUX1 = 1, -- SPX5_SD10G28_CMU_AUX2 = 3, -- SPX5_SD10G28_CMU_NONE = 4, -- SPX5_SD10G28_CMU_MAX, --}; -- - enum sparx5_sd25g28_mode_preset_type { - SPX5_SD25G28_MODE_PRESET_25000, - SPX5_SD25G28_MODE_PRESET_10000, -@@ -1648,7 +1640,7 @@ static int sparx5_sd10g28_apply_params(s - if (params->skip_cmu_cfg) - return 0; - -- cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); -+ cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx); - err = sparx5_cmu_cfg(priv, cmu_idx); - if (err) - return err; -@@ -2520,6 +2512,7 @@ static const struct sparx5_serdes_match_ - }, - .ops = { - .serdes_type_set = &sparx5_serdes_type_set, -+ .serdes_cmu_get = &sparx5_serdes_cmu_get, - }, - }; - ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -26,6 +26,14 @@ enum sparx5_serdes_mode { - SPX5_SD_MODE_SFI, - }; - -+enum sparx5_10g28cmu_mode { -+ SPX5_SD10G28_CMU_MAIN = 0, -+ SPX5_SD10G28_CMU_AUX1 = 1, -+ SPX5_SD10G28_CMU_AUX2 = 3, -+ SPX5_SD10G28_CMU_NONE = 4, -+ SPX5_SD10G28_CMU_MAX, -+}; -+ - struct sparx5_serdes_macro { - struct sparx5_serdes_private *priv; - u32 sidx; -@@ -44,6 +52,7 @@ struct sparx5_serdes_consts { - - struct sparx5_serdes_ops { - void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx); -+ int (*serdes_cmu_get)(enum sparx5_10g28cmu_mode mode, int sd_index); - }; - - struct sparx5_serdes_match_data { diff --git a/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch b/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch deleted file mode 100644 index d78fd26fac..0000000000 --- a/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch +++ /dev/null @@ -1,1708 +0,0 @@ -From e85358f6566d31441f580c33b6acde6a70589959 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:46 +0200 -Subject: [PATCH 13/25] phy: sparx5-serdes: add indirection layer to register - macros - -The register macros are used to read and write to the SERDES registers. -The registers are largely the same on Sparx5 and lan969x, however some -register target sizes differ. Therefore we introduce a new indirection -to the register macros. The target sizes are looked up, using a mapping -table (sparx5_serdes_tsize) that maps the register target to the -register target size. - -With this addition, we can reuse all the existing macros for lan969x. - -Also the autogenerated macros are now formatted slightly different, to -adhere to a 80 character limit. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-6-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 14 + - drivers/phy/microchip/sparx5_serdes.h | 1 + - drivers/phy/microchip/sparx5_serdes_regs.h | 746 ++++++++++++++------- - 3 files changed, 507 insertions(+), 254 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -28,6 +28,17 @@ - /* Optimal power settings from GUC */ - #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c - -+/* Register target sizes */ -+const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = { -+ [TC_SD10G_LANE] = 12, -+ [TC_SD_CMU] = 14, -+ [TC_SD_CMU_CFG] = 14, -+ [TC_SD_LANE] = 25, -+}; -+ -+/* Pointer to the register target size table */ -+const unsigned int *tsize; -+ - enum sparx5_sd25g28_mode_preset_type { - SPX5_SD25G28_MODE_PRESET_25000, - SPX5_SD25G28_MODE_PRESET_10000, -@@ -2506,6 +2517,7 @@ static struct sparx5_serdes_io_resource - static const struct sparx5_serdes_match_data sparx5_desc = { - .iomap = sparx5_serdes_iomap, - .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), -+ .tsize = sparx5_serdes_tsize, - .consts = { - .sd_max = 33, - .cmu_max = 14, -@@ -2568,6 +2580,8 @@ static int sparx5_serdes_probe(struct pl - if (!priv->data) - return -EINVAL; - -+ tsize = priv->data->tsize; -+ - /* Get coreclock */ - clk = devm_clk_get(priv->dev, NULL); - if (IS_ERR(clk)) { ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -60,6 +60,7 @@ struct sparx5_serdes_match_data { - const struct sparx5_serdes_ops ops; - const struct sparx5_serdes_io_resource *iomap; - int iomap_size; -+ const unsigned int *tsize; - }; - - struct sparx5_serdes_private { ---- a/drivers/phy/microchip/sparx5_serdes_regs.h -+++ b/drivers/phy/microchip/sparx5_serdes_regs.h -@@ -1,11 +1,11 @@ - /* SPDX-License-Identifier: GPL-2.0+ - * Microchip Sparx5 SerDes driver - * -- * Copyright (c) 2020 Microchip Technology Inc. -+ * Copyright (c) 2024 Microchip Technology Inc. - */ - --/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100. -- * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f -+/* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200. -+ * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 - */ - - #ifndef _SPARX5_SERDES_REGS_H_ -@@ -26,10 +26,25 @@ enum sparx5_serdes_target { - NUM_TARGETS = 332 - }; - -+enum sparx5_serdes_tsize_enum { -+ TC_SD10G_LANE, -+ TC_SD_CMU, -+ TC_SD_CMU_CFG, -+ TC_SD_LANE, -+ TSIZE_LAST, -+}; -+ -+/* sparx5_serdes.c */ -+extern const unsigned int *tsize; -+ -+#define TSIZE(o) tsize[o] -+ - #define __REG(...) __VA_ARGS__ - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ --#define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ -+#define SD10G_LANE_LANE_01(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ -@@ -49,8 +64,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ --#define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ -+#define SD10G_LANE_LANE_02(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0) - #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ -@@ -82,8 +99,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ --#define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ -+#define SD10G_LANE_LANE_03(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0) - #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ -@@ -91,8 +110,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ --#define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ -+#define SD10G_LANE_LANE_04(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0) - #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ -@@ -100,8 +121,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ --#define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ -+#define SD10G_LANE_LANE_06(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0) - #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ -@@ -139,8 +162,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ --#define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ -+#define SD10G_LANE_LANE_0B(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0) - #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ -@@ -172,8 +197,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ --#define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ -+#define SD10G_LANE_LANE_0C(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0) - #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ -@@ -223,8 +250,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ --#define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ -+#define SD10G_LANE_LANE_0D(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ -@@ -238,8 +267,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ --#define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ -+#define SD10G_LANE_LANE_0E(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0) - #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ -@@ -265,8 +296,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ --#define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ -+#define SD10G_LANE_LANE_0F(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0) - #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ -@@ -274,8 +307,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ --#define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ -+#define SD10G_LANE_LANE_13(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0) - #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ -@@ -295,8 +330,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ --#define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ -+#define SD10G_LANE_LANE_14(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0) - #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ -@@ -304,8 +341,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ --#define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ -+#define SD10G_LANE_LANE_15(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0) - #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ -@@ -313,8 +352,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ --#define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ -+#define SD10G_LANE_LANE_16(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0) - #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ -@@ -322,8 +363,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ --#define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ -+#define SD10G_LANE_LANE_1A(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0) - #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ -@@ -355,8 +398,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ --#define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ -+#define SD10G_LANE_LANE_22(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0) - #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ -@@ -364,8 +409,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ --#define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ -+#define SD10G_LANE_LANE_23(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0) - #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ -@@ -397,8 +444,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ --#define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ -+#define SD10G_LANE_LANE_24(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0) - #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ -@@ -412,8 +461,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ --#define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ -+#define SD10G_LANE_LANE_26(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0) - #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ -@@ -421,8 +472,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ --#define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ -+#define SD10G_LANE_LANE_2F(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ -@@ -436,8 +489,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ --#define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ -+#define SD10G_LANE_LANE_30(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0) - #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ -@@ -451,8 +506,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ --#define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ -+#define SD10G_LANE_LANE_31(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0) - #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ -@@ -490,8 +547,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ --#define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ -+#define SD10G_LANE_LANE_32(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ -@@ -505,8 +564,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ --#define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ -+#define SD10G_LANE_LANE_33(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ -@@ -520,8 +581,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ --#define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ -+#define SD10G_LANE_LANE_35(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ -@@ -535,8 +598,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ --#define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ -+#define SD10G_LANE_LANE_36(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ -@@ -568,8 +633,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ --#define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ -+#define SD10G_LANE_LANE_37(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0) - #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ -@@ -595,8 +662,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ --#define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ -+#define SD10G_LANE_LANE_39(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ -@@ -610,8 +679,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ --#define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ -+#define SD10G_LANE_LANE_3A(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0) - #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ -@@ -625,8 +696,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ --#define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ -+#define SD10G_LANE_LANE_3C(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0) - #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ -@@ -640,8 +713,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ --#define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ -+#define SD10G_LANE_LANE_40(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0) - #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ -@@ -649,8 +724,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ --#define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ -+#define SD10G_LANE_LANE_41(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0) - #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ -@@ -658,8 +735,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x) - --/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ --#define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ -+#define SD10G_LANE_LANE_42(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ -@@ -673,8 +752,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ --#define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ -+#define SD10G_LANE_LANE_48(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0) - #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ -@@ -694,8 +775,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x) - --/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ --#define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ -+#define SD10G_LANE_LANE_50(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ -@@ -727,8 +810,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ --#define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ -+#define SD10G_LANE_LANE_52(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \ -+ 1, 4) - - #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0) - #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ -@@ -736,8 +821,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ --#define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ -+#define SD10G_LANE_LANE_83(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60, \ -+ 0, 1, 4) - - #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0) - #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ -@@ -781,8 +868,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ --#define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ -+#define SD10G_LANE_LANE_93(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0) - #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ -@@ -832,8 +921,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x) - --/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ --#define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ -+#define SD10G_LANE_LANE_94(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0) - #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ -@@ -865,8 +956,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x) - --/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ --#define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ -+#define SD10G_LANE_LANE_9E(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0) - #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ -@@ -886,8 +979,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x) - --/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ --#define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ -+#define SD10G_LANE_LANE_A1(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0) - #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ -@@ -919,8 +1014,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x) - --/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ --#define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ -+#define SD10G_LANE_LANE_A2(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) - #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ -@@ -928,8 +1025,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x) - --/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ --#define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4) -+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ -+#define SD10G_LANE_LANE_DF(t) \ -+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\ -+ 1, 4) - - #define SD10G_LANE_LANE_DF_LOL_UDL BIT(0) - #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ -@@ -955,8 +1054,10 @@ enum sparx5_serdes_target { - #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ - FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_09 */ --#define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_09 */ -+#define SD25G_LANE_CMU_09(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) - - #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0) - #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ -@@ -988,8 +1089,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_0B */ --#define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_0B */ -+#define SD25G_LANE_CMU_0B(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) - - #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0) - #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ -@@ -1039,8 +1142,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_0C */ --#define SD25G_LANE_CMU_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_0C */ -+#define SD25G_LANE_CMU_0C(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) - - #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0) - #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ -@@ -1072,8 +1177,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_0D */ --#define SD25G_LANE_CMU_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_0D */ -+#define SD25G_LANE_CMU_0D(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) - - #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0) - #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ -@@ -1105,8 +1212,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_0E */ --#define SD25G_LANE_CMU_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_0E */ -+#define SD25G_LANE_CMU_0E(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) - - #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0) - #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ -@@ -1120,8 +1229,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_13 */ --#define SD25G_LANE_CMU_13(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_13 */ -+#define SD25G_LANE_CMU_13(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) - - #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0) - #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ -@@ -1135,8 +1246,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_18 */ --#define SD25G_LANE_CMU_18(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_18 */ -+#define SD25G_LANE_CMU_18(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) - - #define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0) - #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ -@@ -1162,8 +1275,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_19 */ --#define SD25G_LANE_CMU_19(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_19 */ -+#define SD25G_LANE_CMU_19(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) - - #define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0) - #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ -@@ -1177,8 +1292,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x) - --/* SD25G_TARGET:CMU_GRP_0:CMU_1A */ --#define SD25G_LANE_CMU_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_0:CMU_1A */ -+#define SD25G_LANE_CMU_1A(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) - - #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0) - #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ -@@ -1204,8 +1321,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x) - --/* SD25G_TARGET:CMU_GRP_1:CMU_2A */ --#define SD25G_LANE_CMU_2A(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_1:CMU_2A */ -+#define SD25G_LANE_CMU_2A(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) - - #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0) - #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ -@@ -1225,8 +1344,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x) - --/* SD25G_TARGET:CMU_GRP_1:CMU_30 */ --#define SD25G_LANE_CMU_30(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_1:CMU_30 */ -+#define SD25G_LANE_CMU_30(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) - - #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0) - #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ -@@ -1240,8 +1361,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x) - --/* SD25G_TARGET:CMU_GRP_1:CMU_31 */ --#define SD25G_LANE_CMU_31(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_1:CMU_31 */ -+#define SD25G_LANE_CMU_31(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) - - #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0) - #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ -@@ -1249,8 +1372,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x) - --/* SD25G_TARGET:CMU_GRP_2:CMU_40 */ --#define SD25G_LANE_CMU_40(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_2:CMU_40 */ -+#define SD25G_LANE_CMU_40(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) - - #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0) - #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ -@@ -1288,8 +1413,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x) - --/* SD25G_TARGET:CMU_GRP_2:CMU_45 */ --#define SD25G_LANE_CMU_45(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_2:CMU_45 */ -+#define SD25G_LANE_CMU_45(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) - - #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0) - #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ -@@ -1297,8 +1424,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x) - --/* SD25G_TARGET:CMU_GRP_2:CMU_46 */ --#define SD25G_LANE_CMU_46(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_2:CMU_46 */ -+#define SD25G_LANE_CMU_46(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) - - #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0) - #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ -@@ -1306,8 +1435,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x) - --/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ --#define SD25G_LANE_CMU_C0(t) __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ -+#define SD25G_LANE_CMU_C0(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) - - #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) - #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ -@@ -1321,8 +1452,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x) - --/* SD25G_TARGET:CMU_GRP_4:CMU_FF */ --#define SD25G_LANE_CMU_FF(t) __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:CMU_GRP_4:CMU_FF */ -+#define SD25G_LANE_CMU_FF(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) - - #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0) - #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ -@@ -1330,8 +1463,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ - FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_00 */ --#define SD25G_LANE_LANE_00(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_00 */ -+#define SD25G_LANE_LANE_00(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) - - #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0) - #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ -@@ -1345,8 +1480,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_01 */ --#define SD25G_LANE_LANE_01(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_01 */ -+#define SD25G_LANE_LANE_01(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) - - #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) - #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ -@@ -1360,8 +1497,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_03 */ --#define SD25G_LANE_LANE_03(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_03 */ -+#define SD25G_LANE_LANE_03(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) - - #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0) - #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ -@@ -1369,8 +1508,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_04 */ --#define SD25G_LANE_LANE_04(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_04 */ -+#define SD25G_LANE_LANE_04(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) - - #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0) - #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ -@@ -1408,8 +1549,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_05 */ --#define SD25G_LANE_LANE_05(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_05 */ -+#define SD25G_LANE_LANE_05(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) - - #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0) - #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ -@@ -1423,8 +1566,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_06 */ --#define SD25G_LANE_LANE_06(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_06 */ -+#define SD25G_LANE_LANE_06(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) - - #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0) - #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ -@@ -1438,8 +1583,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_07 */ --#define SD25G_LANE_LANE_07(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_07 */ -+#define SD25G_LANE_LANE_07(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) - - #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0) - #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ -@@ -1459,8 +1606,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_09 */ --#define SD25G_LANE_LANE_09(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_09 */ -+#define SD25G_LANE_LANE_09(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) - - #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0) - #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ -@@ -1468,8 +1617,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0A */ --#define SD25G_LANE_LANE_0A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0A */ -+#define SD25G_LANE_LANE_0A(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) - - #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0) - #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ -@@ -1477,8 +1628,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0B */ --#define SD25G_LANE_LANE_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0B */ -+#define SD25G_LANE_LANE_0B(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) - - #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0) - #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ -@@ -1498,8 +1651,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0C */ --#define SD25G_LANE_LANE_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0C */ -+#define SD25G_LANE_LANE_0C(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) - - #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) - #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ -@@ -1519,8 +1674,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0D */ --#define SD25G_LANE_LANE_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0D */ -+#define SD25G_LANE_LANE_0D(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) - - #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0) - #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ -@@ -1552,8 +1709,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0E */ --#define SD25G_LANE_LANE_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0E */ -+#define SD25G_LANE_LANE_0E(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) - - #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0) - #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ -@@ -1579,8 +1738,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_0F */ --#define SD25G_LANE_LANE_0F(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_0F */ -+#define SD25G_LANE_LANE_0F(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) - - #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0) - #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ -@@ -1588,8 +1749,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_18 */ --#define SD25G_LANE_LANE_18(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_18 */ -+#define SD25G_LANE_LANE_18(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) - - #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0) - #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ -@@ -1621,8 +1784,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_19 */ --#define SD25G_LANE_LANE_19(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_19 */ -+#define SD25G_LANE_LANE_19(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) - - #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0) - #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ -@@ -1672,8 +1837,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_1A */ --#define SD25G_LANE_LANE_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_1A */ -+#define SD25G_LANE_LANE_1A(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) - - #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0) - #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ -@@ -1687,8 +1854,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_1B */ --#define SD25G_LANE_LANE_1B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_1B */ -+#define SD25G_LANE_LANE_1B(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) - - #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0) - #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ -@@ -1696,8 +1865,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_1C */ --#define SD25G_LANE_LANE_1C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_1C */ -+#define SD25G_LANE_LANE_1C(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) - - #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0) - #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ -@@ -1723,8 +1894,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_1D */ --#define SD25G_LANE_LANE_1D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_1D */ -+#define SD25G_LANE_LANE_1D(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) - - #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0) - #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ -@@ -1774,8 +1947,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_1E */ --#define SD25G_LANE_LANE_1E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_1E */ -+#define SD25G_LANE_LANE_1E(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) - - #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0) - #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ -@@ -1807,8 +1982,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_21 */ --#define SD25G_LANE_LANE_21(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_21 */ -+#define SD25G_LANE_LANE_21(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) - - #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0) - #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ -@@ -1816,8 +1993,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_22 */ --#define SD25G_LANE_LANE_22(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_22 */ -+#define SD25G_LANE_LANE_22(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) - - #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0) - #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ -@@ -1825,8 +2004,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_25 */ --#define SD25G_LANE_LANE_25(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_25 */ -+#define SD25G_LANE_LANE_25(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) - - #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0) - #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ -@@ -1834,8 +2015,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_26 */ --#define SD25G_LANE_LANE_26(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_26 */ -+#define SD25G_LANE_LANE_26(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) - - #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0) - #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ -@@ -1843,8 +2026,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_28 */ --#define SD25G_LANE_LANE_28(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_28 */ -+#define SD25G_LANE_LANE_28(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) - - #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0) - #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ -@@ -1870,8 +2055,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_2B */ --#define SD25G_LANE_LANE_2B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_2B */ -+#define SD25G_LANE_LANE_2B(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) - - #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0) - #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ -@@ -1891,8 +2078,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_2C */ --#define SD25G_LANE_LANE_2C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_2C */ -+#define SD25G_LANE_LANE_2C(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) - - #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0) - #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ -@@ -1906,8 +2095,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_2D */ --#define SD25G_LANE_LANE_2D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_2D */ -+#define SD25G_LANE_LANE_2D(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) - - #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0) - #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ -@@ -1921,8 +2112,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_2E */ --#define SD25G_LANE_LANE_2E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_2E */ -+#define SD25G_LANE_LANE_2E(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) - - #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0) - #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ -@@ -1972,8 +2165,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_40 */ --#define SD25G_LANE_LANE_40(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_40 */ -+#define SD25G_LANE_LANE_40(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) - - #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0) - #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ -@@ -2017,8 +2212,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_42 */ --#define SD25G_LANE_LANE_42(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_42 */ -+#define SD25G_LANE_LANE_42(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) - - #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0) - #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ -@@ -2026,8 +2223,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_43 */ --#define SD25G_LANE_LANE_43(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_43 */ -+#define SD25G_LANE_LANE_43(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) - - #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0) - #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ -@@ -2035,8 +2234,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_44 */ --#define SD25G_LANE_LANE_44(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_44 */ -+#define SD25G_LANE_LANE_44(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) - - #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0) - #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ -@@ -2044,8 +2245,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x) - --/* SD25G_TARGET:LANE_GRP_0:LANE_45 */ --#define SD25G_LANE_LANE_45(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_0:LANE_45 */ -+#define SD25G_LANE_LANE_45(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) - - #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0) - #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ -@@ -2053,8 +2256,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x) - --/* SD25G_TARGET:LANE_GRP_1:LANE_DE */ --#define SD25G_LANE_LANE_DE(t) __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_TARGET:LANE_GRP_1:LANE_DE */ -+#define SD25G_LANE_LANE_DE(t) \ -+ __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) - - #define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0) - #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ -@@ -2080,8 +2285,10 @@ enum sparx5_serdes_target { - #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ - FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x) - --/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ --#define SD6G_LANE_LANE_DF(t) __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ -+#define SD6G_LANE_LANE_DF(t) \ -+ __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) - - #define SD6G_LANE_LANE_DF_LOL_UDL BIT(0) - #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ -@@ -2107,8 +2314,9 @@ enum sparx5_serdes_target { - #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ - FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x) - --/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ --#define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ -+#define SD_CMU_CMU_00(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4) - - #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0) - #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ -@@ -2134,8 +2342,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ - FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x) - --/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ --#define SD_CMU_CMU_05(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ -+#define SD_CMU_CMU_05(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4) - - #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0) - #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ -@@ -2149,9 +2358,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ - FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) - --/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ --#define SD_CMU_CMU_06(t) \ -- __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ -+#define SD_CMU_CMU_06(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4) - - #define SD_CMU_CMU_06_CFG_DISLOS BIT(0) - #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ -@@ -2201,9 +2410,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ - FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x) - --/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ --#define SD_CMU_CMU_08(t) \ -- __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ -+#define SD_CMU_CMU_08(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4) - - #define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0) - #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ -@@ -2235,8 +2444,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ - FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x) - --/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ --#define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ -+#define SD_CMU_CMU_09(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4) - - #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0) - #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ -@@ -2262,8 +2472,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ - FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x) - --/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ --#define SD_CMU_CMU_0D(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ -+#define SD_CMU_CMU_0D(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4) - - #define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0) - #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ -@@ -2295,8 +2506,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ - FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x) - --/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ --#define SD_CMU_CMU_1B(t) __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ -+#define SD_CMU_CMU_1B(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4) - - #define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0) - #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ -@@ -2304,8 +2516,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ - FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x) - --/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ --#define SD_CMU_CMU_1F(t) __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ -+#define SD_CMU_CMU_1F(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4) - - #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0) - #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ -@@ -2331,8 +2544,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ - FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x) - --/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ --#define SD_CMU_CMU_30(t) __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ -+#define SD_CMU_CMU_30(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4) - - #define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0) - #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ -@@ -2340,8 +2554,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ - FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x) - --/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ --#define SD_CMU_CMU_44(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ -+#define SD_CMU_CMU_44(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4) - - #define SD_CMU_CMU_44_R_PLL_RSTN BIT(0) - #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ -@@ -2355,8 +2570,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ - FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x) - --/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ --#define SD_CMU_CMU_45(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ -+#define SD_CMU_CMU_45(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4) - - #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0) - #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ -@@ -2406,8 +2622,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ - FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x) - --/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ --#define SD_CMU_CMU_47(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ -+#define SD_CMU_CMU_47(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4) - - #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) - #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ -@@ -2415,8 +2632,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ - FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x) - --/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ --#define SD_CMU_CMU_E0(t) __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4) -+/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ -+#define SD_CMU_CMU_E0(t) \ -+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4) - - #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) - #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ -@@ -2430,8 +2648,10 @@ enum sparx5_serdes_target { - #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ - FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x) - --/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ --#define SD_CMU_CFG_SD_CMU_CFG(t) __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4) -+/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ -+#define SD_CMU_CFG_SD_CMU_CFG(t) \ -+ __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \ -+ 4) - - #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0) - #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ -@@ -2445,8 +2665,9 @@ enum sparx5_serdes_target { - #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ - FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x) - --/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ --#define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4) -+/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ -+#define SD_LANE_SD_SER_RST(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4) - - #define SD_LANE_SD_SER_RST_SER_RST BIT(0) - #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ -@@ -2454,8 +2675,9 @@ enum sparx5_serdes_target { - #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ - FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x) - --/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ --#define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4) -+/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ -+#define SD_LANE_SD_DES_RST(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4) - - #define SD_LANE_SD_DES_RST_DES_RST BIT(0) - #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ -@@ -2463,8 +2685,9 @@ enum sparx5_serdes_target { - #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ - FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x) - --/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ --#define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4) -+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ -+#define SD_LANE_SD_LANE_CFG(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4) - - #define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0) - #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ -@@ -2508,8 +2731,9 @@ enum sparx5_serdes_target { - #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ - FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x) - --/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ --#define SD_LANE_SD_LANE_STAT(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4) -+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ -+#define SD_LANE_SD_LANE_STAT(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4) - - #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0) - #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ -@@ -2529,9 +2753,9 @@ enum sparx5_serdes_target { - #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ - FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x) - --/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ --#define SD_LANE_QUIET_MODE_6G(t) \ -- __REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4) -+/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ -+#define SD_LANE_QUIET_MODE_6G(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4) - - #define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) - #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ -@@ -2539,8 +2763,9 @@ enum sparx5_serdes_target { - #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ - FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x) - --/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ --#define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4) -+/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ -+#define SD_LANE_MISC(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4) - - #define SD_LANE_MISC_SD_125_RST_DIS BIT(0) - #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ -@@ -2560,14 +2785,16 @@ enum sparx5_serdes_target { - #define SD_LANE_MISC_MUX_ENA_GET(x)\ - FIELD_GET(SD_LANE_MISC_MUX_ENA, x) - -+/* SPARX5 ONLY */ - #define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4) - #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ - FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x) - #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ - FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x) - --/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ --#define SD_LANE_M_STAT_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4) -+/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ -+#define SD_LANE_M_STAT_MISC(t) \ -+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4) - - #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0) - #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ -@@ -2581,8 +2808,10 @@ enum sparx5_serdes_target { - #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ - FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x) - --/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ --#define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ -+#define SD_LANE_25G_SD_SER_RST(t) \ -+ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) - - #define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0) - #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ -@@ -2590,8 +2819,10 @@ enum sparx5_serdes_target { - #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ - FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x) - --/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ --#define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ -+#define SD_LANE_25G_SD_DES_RST(t) \ -+ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) - - #define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0) - #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ -@@ -2599,8 +2830,10 @@ enum sparx5_serdes_target { - #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ - FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x) - --/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ --#define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ -+#define SD_LANE_25G_SD_LANE_CFG(t) \ -+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) - - #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0) - #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ -@@ -2698,8 +2931,10 @@ enum sparx5_serdes_target { - #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ - FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x) - --/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ --#define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ -+#define SD_LANE_25G_SD_LANE_CFG2(t) \ -+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) - - #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0) - #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ -@@ -2767,8 +3002,10 @@ enum sparx5_serdes_target { - #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ - FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x) - --/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ --#define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ -+#define SD_LANE_25G_SD_LANE_STAT(t) \ -+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) - - #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0) - #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ -@@ -2788,8 +3025,9 @@ enum sparx5_serdes_target { - #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ - FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) - --/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ --#define SD_LANE_25G_QUIET_MODE_6G(t) \ -+/* SPARX5 ONLY */ -+/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ -+#define SD_LANE_25G_QUIET_MODE_6G(t) \ - __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4) - - #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) diff --git a/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch b/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch deleted file mode 100644 index daae2f40e1..0000000000 --- a/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch +++ /dev/null @@ -1,101 +0,0 @@ -From db156d900072423be739b1aaaa68a712d3fcb8e4 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:47 +0200 -Subject: [PATCH 14/25] phy: sparx5-serdes: add support for branching on chip - type - -In preparation for lan969x, add a way to branch out on code that is to -be executed on either Sparx5 or lan969x. Initially, this is required to -branch out when checking the SERDES types and SERDES speeds, since the -handling of these differ on the two platforms. This will also be used by -the lan969x driver introduced in a subsequent patch. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-7-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 29 +++++++++++++++++---------- - drivers/phy/microchip/sparx5_serdes.h | 5 +++++ - 2 files changed, 23 insertions(+), 11 deletions(-) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -2298,10 +2298,12 @@ static int sparx5_serdes_set_speed(struc - { - struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); - -- if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) -- return -EINVAL; -- if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) -- return -EINVAL; -+ if (macro->priv->data->type == SPX5_TARGET_SPARX5) { -+ if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) -+ return -EINVAL; -+ if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) -+ return -EINVAL; -+ } - if (speed != macro->speed) { - macro->speed = speed; - if (macro->serdesmode != SPX5_SD_MODE_NONE) -@@ -2338,11 +2340,14 @@ static int sparx5_serdes_validate(struct - if (macro->speed == 0) - return -EINVAL; - -- if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000) -- return -EINVAL; -- if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000) -- return -EINVAL; -- -+ if (macro->priv->data->type == SPX5_TARGET_SPARX5) { -+ if (macro->sidx < SPX5_SERDES_10G_START && -+ macro->speed > SPEED_5000) -+ return -EINVAL; -+ if (macro->sidx < SPX5_SERDES_25G_START && -+ macro->speed > SPEED_10000) -+ return -EINVAL; -+ } - switch (submode) { - case PHY_INTERFACE_MODE_1000BASEX: - if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ -@@ -2515,6 +2520,7 @@ static struct sparx5_serdes_io_resource - }; - - static const struct sparx5_serdes_match_data sparx5_desc = { -+ .type = SPX5_TARGET_SPARX5, - .iomap = sparx5_serdes_iomap, - .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), - .tsize = sparx5_serdes_tsize, -@@ -2618,8 +2624,9 @@ static int sparx5_serdes_probe(struct pl - return err; - } - -- /* Power down all CMUs by default */ -- sparx5_serdes_cmu_power_off(priv); -+ /* Power down all CMU's by default */ -+ if (priv->data->type == SPX5_TARGET_SPARX5) -+ sparx5_serdes_cmu_power_off(priv); - - provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); - ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -34,6 +34,10 @@ enum sparx5_10g28cmu_mode { - SPX5_SD10G28_CMU_MAX, - }; - -+enum sparx5_target { -+ SPX5_TARGET_SPARX5, -+}; -+ - struct sparx5_serdes_macro { - struct sparx5_serdes_private *priv; - u32 sidx; -@@ -56,6 +60,7 @@ struct sparx5_serdes_ops { - }; - - struct sparx5_serdes_match_data { -+ enum sparx5_target type; - const struct sparx5_serdes_consts consts; - const struct sparx5_serdes_ops ops; - const struct sparx5_serdes_io_resource *iomap; diff --git a/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch b/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch deleted file mode 100644 index 30b1375885..0000000000 --- a/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch +++ /dev/null @@ -1,175 +0,0 @@ -From ec933122868bb205d8cdecc2049c49f811d32397 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 9 Sep 2024 17:14:49 +0200 -Subject: [PATCH 15/25] phy: lan969x-serdes: add support for lan969x serdes - driver - -Add support for lan969x SERDES driver. Lan969x has ten 10G SERDES'es -which share the same features and data rates as the Sparx5 SERDES'es. - -Signed-off-by: Daniel Machon -Reviewed-by: Steen Hegelund -Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-9-d695bcb57b84@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/sparx5_serdes.c | 88 +++++++++++++++++++++++++++ - drivers/phy/microchip/sparx5_serdes.h | 2 + - 2 files changed, 90 insertions(+) - ---- a/drivers/phy/microchip/sparx5_serdes.c -+++ b/drivers/phy/microchip/sparx5_serdes.c -@@ -25,6 +25,8 @@ - #define SPX5_SERDES_25G_START 25 - #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START - -+#define LAN969X_SERDES_10G_CNT 10 -+ - /* Optimal power settings from GUC */ - #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c - -@@ -36,6 +38,13 @@ const unsigned int sparx5_serdes_tsize[T - [TC_SD_LANE] = 25, - }; - -+const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = { -+ [TC_SD10G_LANE] = 10, -+ [TC_SD_CMU] = 6, -+ [TC_SD_CMU_CFG] = 6, -+ [TC_SD_LANE] = 10, -+}; -+ - /* Pointer to the register target size table */ - const unsigned int *tsize; - -@@ -1096,6 +1105,24 @@ static int sparx5_serdes_cmu_get(enum sp - return sparx5_serdes_cmu_map[mode][sd_index]; - } - -+/* Map of 6G/10G serdes mode and index to CMU index. */ -+static const int -+lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][LAN969X_SERDES_10G_CNT] = { -+ [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2, -+ 2, 2, 2, 5, 5 }, -+ [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3, -+ 3, 3, 3, 3, 3 }, -+ [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4, -+ 4, 4, 4, 4, 4 }, -+ [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4, -+ 4, 4, 4, 4, 4 }, -+}; -+ -+static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index) -+{ -+ return lan969x_serdes_cmu_map[mode][sd_index]; -+} -+ - static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) - { - void __iomem *cmu_inst, *cmu_cfg_inst; -@@ -2184,6 +2211,10 @@ static int sparx5_serdes_clock_config(st - { - struct sparx5_serdes_private *priv = macro->priv; - -+ /* Clock is auto-detected in 100Base-FX mode on lan969x */ -+ if (priv->data->type == SPX5_TARGET_LAN969X) -+ return 0; -+ - if (macro->serdesmode == SPX5_SD_MODE_100FX) { - u32 freq = priv->coreclock == 250000000 ? 2 : - priv->coreclock == 500000000 ? 1 : 0; -@@ -2395,6 +2426,12 @@ static void sparx5_serdes_type_set(struc - } - } - -+static void lan969x_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) -+{ -+ macro->serdestype = SPX5_SDT_10G; -+ macro->stpidx = macro->sidx; -+} -+ - static int sparx5_phy_create(struct sparx5_serdes_private *priv, - int idx, struct phy **phy) - { -@@ -2519,6 +2556,41 @@ static struct sparx5_serdes_io_resource - { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ - }; - -+static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = { -+ { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */ -+ { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */ -+ { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */ -+ { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */ -+ { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */ -+ { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */ -+ { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */ -+ { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */ -+ { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */ -+ { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */ -+ { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */ -+ { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */ -+ { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */ -+ { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */ -+ { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */ -+ { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */ -+ { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */ -+ { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */ -+ { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */ -+ { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */ -+ { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */ -+ { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */ -+ { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */ -+ { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */ -+ { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */ -+ { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */ -+ { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */ -+ { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */ -+ { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */ -+ { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */ -+ { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */ -+ { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */ -+}; -+ - static const struct sparx5_serdes_match_data sparx5_desc = { - .type = SPX5_TARGET_SPARX5, - .iomap = sparx5_serdes_iomap, -@@ -2534,6 +2606,21 @@ static const struct sparx5_serdes_match_ - }, - }; - -+static const struct sparx5_serdes_match_data lan969x_desc = { -+ .type = SPX5_TARGET_LAN969X, -+ .iomap = lan969x_serdes_iomap, -+ .iomap_size = ARRAY_SIZE(lan969x_serdes_iomap), -+ .tsize = lan969x_serdes_tsize, -+ .consts = { -+ .sd_max = 10, -+ .cmu_max = 6, -+ }, -+ .ops = { -+ .serdes_type_set = &lan969x_serdes_type_set, -+ .serdes_cmu_get = &lan969x_serdes_cmu_get, -+ } -+}; -+ - /* Client lookup function, uses serdes index */ - static struct phy *sparx5_serdes_xlate(struct device *dev, - const struct of_phandle_args *args) -@@ -2635,6 +2722,7 @@ static int sparx5_serdes_probe(struct pl - - static const struct of_device_id sparx5_serdes_match[] = { - { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc }, -+ { .compatible = "microchip,lan9691-serdes", .data = &lan969x_desc }, - { } - }; - MODULE_DEVICE_TABLE(of, sparx5_serdes_match); ---- a/drivers/phy/microchip/sparx5_serdes.h -+++ b/drivers/phy/microchip/sparx5_serdes.h -@@ -36,6 +36,8 @@ enum sparx5_10g28cmu_mode { - - enum sparx5_target { - SPX5_TARGET_SPARX5, -+ SPX5_TARGET_LAN969X, -+ - }; - - struct sparx5_serdes_macro { diff --git a/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch deleted file mode 100644 index e9938a475f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 48a8c9defc691a038c1fa515b2b6c8edb6e55aa4 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 8 Jan 2025 14:09:28 +0100 -Subject: [PATCH 17/25] tty: serial: atmel: make it selectable for ARCH_LAN969X - -LAN969x uses the Atmel serial, so make it selectable for ARCH_LAN969X. - -Signed-off-by: Robert Marko -Acked-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20250108131045.40642-3-robert.marko@sartura.hr -Signed-off-by: Greg Kroah-Hartman ---- - drivers/tty/serial/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/Kconfig -+++ b/drivers/tty/serial/Kconfig -@@ -128,7 +128,7 @@ config SERIAL_SB1250_DUART_CONSOLE - config SERIAL_ATMEL - bool "AT91 on-chip serial port support" - depends on COMMON_CLK -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST - select SERIAL_CORE - select SERIAL_MCTRL_GPIO if GPIOLIB - select MFD_AT91_USART diff --git a/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch deleted file mode 100644 index 43bea8aca7..0000000000 --- a/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 04d0fbaff226d574e698ba1f6220be173b3b554d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 31 Jan 2025 18:14:10 +0100 -Subject: [PATCH 18/25] mfd: at91-usart: Make it selectable for ARCH_LAN969X - -LAN969x uses the AT91 USART IP so make it selectable for ARCH_LAN969X. - -Signed-off-by: Robert Marko -Acked-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20250131171739.1044701-2-robert.marko@sartura.hr -Signed-off-by: Lee Jones ---- - drivers/mfd/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -138,7 +138,7 @@ config MFD_AAT2870_CORE - config MFD_AT91_USART - tristate "AT91 USART Driver" - select MFD_CORE -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST - help - Select this to get support for AT91 USART IP. This is a wrapper - over at91-usart-serial driver and usart-spi-driver. Only one function diff --git a/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch b/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch deleted file mode 100644 index 511283225f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 823122980e18bf20eac1689ebccad488e828b33b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 2 Jul 2025 20:36:06 +0200 -Subject: [PATCH 19/25] dmaengine: xdmac: make it selectable for ARCH_MICROCHIP - -LAN969x uses the Atmel XDMAC, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20250702183856.1727275-9-robert.marko@sartura.hr -Signed-off-by: Vinod Koul ---- - drivers/dma/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/dma/Kconfig -+++ b/drivers/dma/Kconfig -@@ -103,7 +103,7 @@ config AT_HDMAC - - config AT_XDMAC - tristate "Atmel XDMA support" -- depends on ARCH_AT91 -+ depends on ARCH_MICROCHIP - select DMA_ENGINE - help - Support the Atmel XDMA controller. diff --git a/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch deleted file mode 100644 index 4631eebf8c..0000000000 --- a/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch +++ /dev/null @@ -1,28 +0,0 @@ -From a1166284ce7eecc7ff3b0611ba58cbbee2e3953a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:40 +0200 -Subject: [PATCH 20/25] mfd: at91-usart: Make it selectable for ARCH_MICROCHIP - -LAN969x uses the Atmel USART, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Acked-by: Daniel Machon -Acked-by: Lee Jones -Signed-off-by: Nicolas Ferre ---- - drivers/mfd/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -138,7 +138,7 @@ config MFD_AAT2870_CORE - config MFD_AT91_USART - tristate "AT91 USART Driver" - select MFD_CORE -- depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - help - Select this to get support for AT91 USART IP. This is a wrapper - over at91-usart-serial driver and usart-spi-driver. Only one function diff --git a/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch b/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch deleted file mode 100644 index aaa59ecdc7..0000000000 --- a/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 67a4c049056d6de07460d576e785c2fdbf64bc7c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:41 +0200 -Subject: [PATCH 21/25] tty: serial: atmel: make it selectable for - ARCH_MICROCHIP - -LAN969x uses the Atmel USART serial, so make it selectable for -ARCH_MICROCHIP to avoid needing to update depends in future if other -Microchip SoC-s use it as well. - -Signed-off-by: Robert Marko -Acked-by: Greg Kroah-Hartman -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - drivers/tty/serial/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/Kconfig -+++ b/drivers/tty/serial/Kconfig -@@ -128,7 +128,7 @@ config SERIAL_SB1250_DUART_CONSOLE - config SERIAL_ATMEL - bool "AT91 on-chip serial port support" - depends on COMMON_CLK -- depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - select SERIAL_CORE - select SERIAL_MCTRL_GPIO if GPIOLIB - select MFD_AT91_USART diff --git a/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch deleted file mode 100644 index 2049712ce4..0000000000 --- a/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e761a7b6753f3d4db9fde26dacab5ecff3b5d0e8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:42 +0200 -Subject: [PATCH 22/25] spi: atmel: make it selectable for ARCH_MICROCHIP - -LAN969x uses the Atmel SPI, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Acked-by: Mark Brown -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - drivers/spi/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -131,7 +131,7 @@ config SPI_ASPEED_SMC - - config SPI_ATMEL - tristate "Atmel SPI Controller" -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - depends on OF - help - This selects a driver for the Atmel SPI Controller, present on diff --git a/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch deleted file mode 100644 index c29745b9f6..0000000000 --- a/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0ee61e26871b1c039b905569cf74382c800c1e8b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:43 +0200 -Subject: [PATCH 23/25] i2c: at91: make it selectable for ARCH_MICROCHIP - -LAN969x uses the Atmel TWI I2C, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Acked-by: Wolfram Sang -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - drivers/i2c/busses/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -423,7 +423,7 @@ config I2C_ASPEED - - config I2C_AT91 - tristate "Atmel AT91 I2C Two-Wire interface (TWI)" -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - help - This supports the use of the I2C interface on Atmel AT91 - processors. diff --git a/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch b/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch deleted file mode 100644 index 717572e31e..0000000000 --- a/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 25e23abbc37484862c411b7317878d448b47fad5 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:44 +0200 -Subject: [PATCH 24/25] char: hw_random: atmel: make it selectable for - ARCH_MICROCHIP - -LAN969x uses the Atmel HWRNG, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - drivers/char/hw_random/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -64,7 +64,7 @@ config HW_RANDOM_AMD - - config HW_RANDOM_ATMEL - tristate "Atmel Random Number Generator support" -- depends on (ARCH_AT91 || COMPILE_TEST) -+ depends on (ARCH_MICROCHIP || COMPILE_TEST) - default HW_RANDOM - help - This driver provides kernel-side support for the Random Number diff --git a/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch b/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch deleted file mode 100644 index a4db1d2eba..0000000000 --- a/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 405fad723d71997ca9ad894ba7ac755a75fa5443 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 13 Aug 2025 19:44:45 +0200 -Subject: [PATCH 25/25] crypto: atmel-aes: make it selectable for - ARCH_MICROCHIP - -LAN969x uses the Atmel crypto, so make it selectable for ARCH_MICROCHIP to -avoid needing to update depends in future if other Microchip SoC-s use it -as well. - -Signed-off-by: Robert Marko -Acked-by: Herbert Xu -Acked-by: Daniel Machon -Signed-off-by: Nicolas Ferre ---- - drivers/crypto/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -421,7 +421,7 @@ config CRYPTO_DEV_ATMEL_AUTHENC - - config CRYPTO_DEV_ATMEL_AES - tristate "Support for Atmel AES hw accelerator" -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - select CRYPTO_AES - select CRYPTO_AEAD - select CRYPTO_SKCIPHER diff --git a/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch b/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch deleted file mode 100644 index ad21cb6240..0000000000 --- a/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 7b27e8e600e75b493c97a3fd5b764064fa61dd91 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:27 +0200 -Subject: [PATCH 29/82] net: sparx5: add support for private match data - -In preparation for lan969x, add support for private match data. This -will be needed for abstracting away differences between the Sparx5 and -lan969x platforms. We initially add values for: iomap, iomap size and -ioranges. Update the use of these throughout. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../ethernet/microchip/sparx5/sparx5_main.c | 36 +++++++++++-------- - .../ethernet/microchip/sparx5/sparx5_main.h | 13 +++++++ - 2 files changed, 34 insertions(+), 15 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -45,12 +45,6 @@ struct sparx5_ram_config { - u32 init_val; - }; - --struct sparx5_main_io_resource { -- enum sparx5_target id; -- phys_addr_t offset; -- int range; --}; -- - static const struct sparx5_main_io_resource sparx5_main_iomap[] = { - { TARGET_CPU, 0, 0 }, /* 0x600000000 */ - { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ -@@ -216,21 +210,24 @@ static const struct sparx5_main_io_resou - - static int sparx5_create_targets(struct sparx5 *sparx5) - { -+ const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; -+ int iomap_size = sparx5->data->iomap_size; -+ int ioranges = sparx5->data->ioranges; - struct resource *iores[IO_RANGES]; - void __iomem *iomem[IO_RANGES]; - void __iomem *begin[IO_RANGES]; - int range_id[IO_RANGES]; - int idx, jdx; - -- for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { -- const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; -+ for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { -+ const struct sparx5_main_io_resource *io = &iomap[jdx]; - -- if (idx == iomap->range) { -+ if (idx == io->range) { - range_id[idx] = jdx; - idx++; - } - } -- for (idx = 0; idx < IO_RANGES; idx++) { -+ for (idx = 0; idx < ioranges; idx++) { - iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, - idx); - if (!iores[idx]) { -@@ -245,12 +242,12 @@ static int sparx5_create_targets(struct - iores[idx]->name); - return -ENOMEM; - } -- begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; -+ begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; - } -- for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { -- const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; -+ for (jdx = 0; jdx < iomap_size; jdx++) { -+ const struct sparx5_main_io_resource *io = &iomap[jdx]; - -- sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; -+ sparx5->regs[io->id] = begin[io->range] + io->offset; - } - return 0; - } -@@ -758,6 +755,9 @@ static int mchp_sparx5_probe(struct plat - sparx5->dev = &pdev->dev; - spin_lock_init(&sparx5->tx_lock); - -+ sparx5->data = device_get_match_data(sparx5->dev); -+ if (!sparx5->data) -+ return -EINVAL; - /* Do switch core reset if available */ - reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); - if (IS_ERR(reset)) -@@ -936,8 +936,14 @@ static void mchp_sparx5_remove(struct pl - destroy_workqueue(sparx5->mact_queue); - } - -+static const struct sparx5_match_data sparx5_desc = { -+ .iomap = sparx5_main_iomap, -+ .iomap_size = ARRAY_SIZE(sparx5_main_iomap), -+ .ioranges = 3, -+}; -+ - static const struct of_device_id mchp_sparx5_match[] = { -- { .compatible = "microchip,sparx5-switch" }, -+ { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, - { } - }; - MODULE_DEVICE_TABLE(of, mchp_sparx5_match); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -226,6 +226,18 @@ struct sparx5_mall_entry { - #define SPARX5_SKB_CB(skb) \ - ((struct sparx5_skb_cb *)((skb)->cb)) - -+struct sparx5_main_io_resource { -+ enum sparx5_target id; -+ phys_addr_t offset; -+ int range; -+}; -+ -+struct sparx5_match_data { -+ const struct sparx5_main_io_resource *iomap; -+ int ioranges; -+ int iomap_size; -+}; -+ - struct sparx5 { - struct platform_device *pdev; - struct device *dev; -@@ -293,6 +305,7 @@ struct sparx5 { - struct list_head mall_entries; - /* Common root for debugfs */ - struct dentry *debugfs_root; -+ const struct sparx5_match_data *data; - }; - - /* sparx5_switchdev.c */ diff --git a/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch b/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch deleted file mode 100644 index 00fd6fb95f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch +++ /dev/null @@ -1,7398 +0,0 @@ -From 161b518a0b6af89f7fc883c78503cb9472ae8791 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:28 +0200 -Subject: [PATCH 30/82] net: sparx5: add indirection layer to register macros - -The register macros are used to read and write to the switch registers. -The registers are largely the same on Sparx5 and lan969x, however in some -cases they differ. The differences can be one or more of the following: -target size, register address, register count, group address, group -count, group size, field position, field size. - -In order to handle these differences, we introduce a new indirection -layer, that defines and maps them to corresponding values, based on the -platform. As the register macro arguments can now be non-constants, we -also add non-constant variants of FIELD_GET and FIELD_PREP. - -Since the indirection layer contributes to longer macros, we have -changed the formatting of them slightly, to adhere to a 80 character -limit, and added a comment if a macro is platform-specific. - -With these additions, we can reuse all the existing macros for -lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../net/ethernet/microchip/sparx5/Makefile | 2 +- - .../ethernet/microchip/sparx5/sparx5_main.c | 17 + - .../ethernet/microchip/sparx5/sparx5_main.h | 12 + - .../microchip/sparx5/sparx5_main_regs.h | 4469 ++++++++++------- - .../ethernet/microchip/sparx5/sparx5_regs.c | 219 + - .../ethernet/microchip/sparx5/sparx5_regs.h | 244 + - 6 files changed, 3009 insertions(+), 1954 deletions(-) - create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_regs.c - create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_regs.h - ---- a/drivers/net/ethernet/microchip/sparx5/Makefile -+++ b/drivers/net/ethernet/microchip/sparx5/Makefile -@@ -11,7 +11,7 @@ sparx5-switch-y := sparx5_main.o sparx5 - sparx5_ptp.o sparx5_pgid.o sparx5_tc.o sparx5_qos.o \ - sparx5_vcap_impl.o sparx5_vcap_ag_api.o sparx5_tc_flower.o \ - sparx5_tc_matchall.o sparx5_pool.o sparx5_sdlb.o sparx5_police.o \ -- sparx5_psfp.o sparx5_mirror.o -+ sparx5_psfp.o sparx5_mirror.o sparx5_regs.o - - sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o - sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -29,6 +29,8 @@ - #include "sparx5_port.h" - #include "sparx5_qos.h" - -+const struct sparx5_regs *regs; -+ - #define QLIM_WM(fraction) \ - ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) - #define IO_RANGES 3 -@@ -758,6 +760,9 @@ static int mchp_sparx5_probe(struct plat - sparx5->data = device_get_match_data(sparx5->dev); - if (!sparx5->data) - return -EINVAL; -+ -+ regs = sparx5->data->regs; -+ - /* Do switch core reset if available */ - reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); - if (IS_ERR(reset)) -@@ -936,10 +941,22 @@ static void mchp_sparx5_remove(struct pl - destroy_workqueue(sparx5->mact_queue); - } - -+static const struct sparx5_regs sparx5_regs = { -+ .tsize = sparx5_tsize, -+ .gaddr = sparx5_gaddr, -+ .gcnt = sparx5_gcnt, -+ .gsize = sparx5_gsize, -+ .raddr = sparx5_raddr, -+ .rcnt = sparx5_rcnt, -+ .fpos = sparx5_fpos, -+ .fsize = sparx5_fsize, -+}; -+ - static const struct sparx5_match_data sparx5_desc = { - .iomap = sparx5_main_iomap, - .iomap_size = ARRAY_SIZE(sparx5_main_iomap), - .ioranges = 3, -+ .regs = &sparx5_regs, - }; - - static const struct of_device_id mchp_sparx5_match[] = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -226,6 +226,17 @@ struct sparx5_mall_entry { - #define SPARX5_SKB_CB(skb) \ - ((struct sparx5_skb_cb *)((skb)->cb)) - -+struct sparx5_regs { -+ const unsigned int *tsize; -+ const unsigned int *gaddr; -+ const unsigned int *gcnt; -+ const unsigned int *gsize; -+ const unsigned int *raddr; -+ const unsigned int *rcnt; -+ const unsigned int *fpos; -+ const unsigned int *fsize; -+}; -+ - struct sparx5_main_io_resource { - enum sparx5_target id; - phys_addr_t offset; -@@ -233,6 +244,7 @@ struct sparx5_main_io_resource { - }; - - struct sparx5_match_data { -+ const struct sparx5_regs *regs; - const struct sparx5_main_io_resource *iomap; - int ioranges; - int iomap_size; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -@@ -1,11 +1,11 @@ - /* SPDX-License-Identifier: GPL-2.0+ - * Microchip Sparx5 Switch driver - * -- * Copyright (c) 2021 Microchip Technology Inc. -+ * Copyright (c) 2024 Microchip Technology Inc. - */ - --/* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100. -- * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada -+/* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200. -+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b - */ - - #ifndef _SPARX5_MAIN_REGS_H_ -@@ -15,6 +15,8 @@ - #include - #include - -+#include "sparx5_regs.h" -+ - enum sparx5_target { - TARGET_ANA_AC = 1, - TARGET_ANA_ACL = 2, -@@ -52,14 +54,27 @@ enum sparx5_target { - TARGET_VCAP_SUPER = 326, - TARGET_VOP = 327, - TARGET_XQS = 331, -- NUM_TARGETS = 332 -+ NUM_TARGETS = 517 - }; - -+/* sparx5_main.c -+ * -+ * This is used by the register macros to access chip differences (if any) in: -+ * target size, register address, register count, group address, group count, -+ * group size, field position and field size. -+ */ -+extern const struct sparx5_regs *regs; -+ -+/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -+ - #define __REG(...) __VA_ARGS__ - --/* ANA_AC:RAM_CTRL:RAM_INIT */ --#define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\ -- 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) -+/* ANA_AC:RAM_CTRL:RAM_INIT */ -+#define ANA_AC_RAM_INIT \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\ -+ 0, 1, 4) - - #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) - #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ -@@ -73,9 +88,10 @@ enum sparx5_target { - #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) - --/* ANA_AC:PS_COMMON:OWN_UPSID */ --#define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) -+/* ANA_AC:PS_COMMON:OWN_UPSID */ -+#define ANA_AC_OWN_UPSID(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\ -+ 52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4) - - #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) - #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ -@@ -83,75 +99,86 @@ enum sparx5_target { - #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ - FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) - --/* ANA_AC:MIRROR_PROBE:PROBE_CFG */ --#define ANA_AC_PROBE_CFG(g) \ -- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4) -+/* ANA_AC:MIRROR_PROBE:PROBE_CFG */ -+#define ANA_AC_PROBE_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ -+ 32, 0, 0, 1, 4) - --#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) -+#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) - #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) - #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) - --#define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) -+#define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) - #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) - #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) - --#define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) -+#define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) - #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) - #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) - --#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) -+#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) - #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) - #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) - --#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) -+#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) - #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) - #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) - --#define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) -+#define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) - #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) - #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ - FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) - --/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ --#define ANA_AC_PROBE_PORT_CFG(g) \ -- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4) -- --/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ --#define ANA_AC_PROBE_PORT_CFG1(g) \ -- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4) -- --/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ --#define ANA_AC_PROBE_PORT_CFG2(g) \ -- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4) -+/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ -+#define ANA_AC_PROBE_PORT_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ -+ 32, 8, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ -+#define ANA_AC_PROBE_PORT_CFG1(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ -+ 32, 12, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ -+#define ANA_AC_PROBE_PORT_CFG2(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ -+ 32, 16, 0, 1, 4) - --#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) -+#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) - #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ - FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) - #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ - FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) - --/* ANA_AC:SRC:SRC_CFG */ --#define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) -- --/* ANA_AC:SRC:SRC_CFG1 */ --#define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) -- --/* ANA_AC:SRC:SRC_CFG2 */ --#define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) -+/* ANA_AC:SRC:SRC_CFG */ -+#define ANA_AC_SRC_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ -+ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:SRC:SRC_CFG1 */ -+#define ANA_AC_SRC_CFG1(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ -+ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:SRC:SRC_CFG2 */ -+#define ANA_AC_SRC_CFG2(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ -+ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4) - - #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) - #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ -@@ -159,17 +186,22 @@ enum sparx5_target { - #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ - FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) - --/* ANA_AC:PGID:PGID_CFG */ --#define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) -- --/* ANA_AC:PGID:PGID_CFG1 */ --#define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) -- --/* ANA_AC:PGID:PGID_CFG2 */ --#define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) -+/* ANA_AC:PGID:PGID_CFG */ -+#define ANA_AC_PGID_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ -+ regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:PGID:PGID_CFG1 */ -+#define ANA_AC_PGID_CFG1(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ -+ regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_AC:PGID:PGID_CFG2 */ -+#define ANA_AC_PGID_CFG2(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ -+ regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4) - - #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) - #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ -@@ -177,9 +209,10 @@ enum sparx5_target { - #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ - FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) - --/* ANA_AC:PGID:PGID_MISC_CFG */ --#define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) -+/* ANA_AC:PGID:PGID_MISC_CFG */ -+#define ANA_AC_PGID_MISC_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ -+ regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4) - - #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) - #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ -@@ -199,9 +232,10 @@ enum sparx5_target { - #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ - FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) - --/* ANA_AC:TSN_SF:TSN_SF */ --#define ANA_AC_TSN_SF __REG(TARGET_ANA_AC,\ -- 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4) -+/* ANA_AC:TSN_SF:TSN_SF */ -+#define ANA_AC_TSN_SF \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \ -+ 0, 1, 4) - - #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) - #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ -@@ -209,21 +243,24 @@ enum sparx5_target { - #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ - FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) - --#define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0) -+#define ANA_AC_TSN_SF_PORT_NUM\ -+ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0) - #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ -- FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x) -+ spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x) - #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ -- FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x) -+ spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x) - --/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ --#define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ -- 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4) -+/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ -+#define ANA_AC_TSN_SF_CFG(g) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \ -+ regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4) - --#define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16) -+#define ANA_AC_TSN_SF_CFG_TSN_SGID\ -+ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16) - #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ -- FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x) -+ spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x) - #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ -- FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x) -+ spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x) - - #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) - #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ -@@ -243,9 +280,10 @@ enum sparx5_target { - #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ - FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) - --/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ --#define ANA_AC_TSN_SF_STATUS __REG(TARGET_ANA_AC,\ -- 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4) -+/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ -+#define ANA_AC_TSN_SF_STATUS \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \ -+ 16, 0, 0, 1, 4) - - #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) - #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ -@@ -259,11 +297,12 @@ enum sparx5_target { - #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ - FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) - --#define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1) -+#define ANA_AC_TSN_SF_STATUS_TSN_SFID\ -+ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1) - #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ -- FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) -+ spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) - #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ -- FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) -+ spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) - - #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) - #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ -@@ -271,15 +310,17 @@ enum sparx5_target { - #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ - FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) - --/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ --#define ANA_AC_SG_ACCESS_CTRL __REG(TARGET_ANA_AC,\ -- 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4) -+/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ -+#define ANA_AC_SG_ACCESS_CTRL \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ -+ 0, 0, 1, 4) - --#define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0) -+#define ANA_AC_SG_ACCESS_CTRL_SGID\ -+ GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0) - #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ -- FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x) -+ spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x) - #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ -- FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x) -+ spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x) - - #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) - #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ -@@ -287,9 +328,10 @@ enum sparx5_target { - #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ - FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) - --/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ --#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD __REG(TARGET_ANA_AC,\ -- 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4) -+/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ -+#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ -+ 8, 0, 1, 4) - - #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) - #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ -@@ -303,17 +345,20 @@ enum sparx5_target { - #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ - FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) - --/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ --#define ANA_AC_SG_CONFIG_REG_1 __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4) -- --/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ --#define ANA_AC_SG_CONFIG_REG_2 __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4) -- --/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ --#define ANA_AC_SG_CONFIG_REG_3 __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4) -+/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ -+#define ANA_AC_SG_CONFIG_REG_1 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 48, 0, 1, 4) -+ -+/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ -+#define ANA_AC_SG_CONFIG_REG_2 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 52, 0, 1, 4) -+ -+/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ -+#define ANA_AC_SG_CONFIG_REG_3 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 56, 0, 1, 4) - - #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) - #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ -@@ -369,17 +414,20 @@ enum sparx5_target { - #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ - FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) - --/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ --#define ANA_AC_SG_CONFIG_REG_4 __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4) -- --/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ --#define ANA_AC_SG_CONFIG_REG_5 __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4) -- --/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ --#define ANA_AC_SG_GCL_GS_CONFIG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 0, r, 4, 4) -+/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ -+#define ANA_AC_SG_CONFIG_REG_4 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 60, 0, 1, 4) -+ -+/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ -+#define ANA_AC_SG_CONFIG_REG_5 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 64, 0, 1, 4) -+ -+/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ -+#define ANA_AC_SG_GCL_GS_CONFIG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 0, r, 4, 4) - - #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) - #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ -@@ -393,25 +441,30 @@ enum sparx5_target { - #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ - FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) - --/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ --#define ANA_AC_SG_GCL_TI_CONFIG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 16, r, 4, 4) -- --/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ --#define ANA_AC_SG_GCL_OCT_CONFIG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 851584, 0, 1, 128, 32, r, 4, 4) -- --/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ --#define ANA_AC_SG_STATUS_REG_1 __REG(TARGET_ANA_AC,\ -- 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4) -- --/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ --#define ANA_AC_SG_STATUS_REG_2 __REG(TARGET_ANA_AC,\ -- 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4) -- --/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ --#define ANA_AC_SG_STATUS_REG_3 __REG(TARGET_ANA_AC,\ -- 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4) -+/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ -+#define ANA_AC_SG_GCL_TI_CONFIG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 16, r, 4, 4) -+ -+/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ -+#define ANA_AC_SG_GCL_OCT_CONFIG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ -+ 32, r, 4, 4) -+ -+/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ -+#define ANA_AC_SG_STATUS_REG_1 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ -+ 0, 0, 1, 4) -+ -+/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ -+#define ANA_AC_SG_STATUS_REG_2 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ -+ 4, 0, 1, 4) -+ -+/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ -+#define ANA_AC_SG_STATUS_REG_3 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ -+ 8, 0, 1, 4) - - #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) - #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ -@@ -443,23 +496,27 @@ enum sparx5_target { - #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ - FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) - --/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ --#define ANA_AC_SG_STATUS_REG_4 __REG(TARGET_ANA_AC,\ -- 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4) -- --/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ --#define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) -+/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ -+#define ANA_AC_SG_STATUS_REG_4 \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ -+ 12, 0, 1, 4) -+ -+/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ -+#define ANA_AC_PORT_SGE_CFG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ -+ 0, 1, 20, 0, r, 4, 4) - --#define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) -+#define ANA_AC_PORT_SGE_CFG_MASK\ -+ GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0) - #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ -- FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) -+ spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x) - #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ -- FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) -+ spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x) - --/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ --#define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC,\ -- 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) -+/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ -+#define ANA_AC_STAT_RESET \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ -+ 0, 1, 20, 16, 0, 1, 4) - - #define ANA_AC_STAT_RESET_RESET BIT(0) - #define ANA_AC_STAT_RESET_RESET_SET(x)\ -@@ -467,9 +524,10 @@ enum sparx5_target { - #define ANA_AC_STAT_RESET_RESET_GET(x)\ - FIELD_GET(ANA_AC_STAT_RESET_RESET, x) - --/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ --#define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ -- 0, 1, 843776, g, 70, 64, 4, r, 4, 4) -+/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ -+#define ANA_AC_PORT_STAT_CFG(g, r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ -+ regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4) - - #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) - #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ -@@ -489,13 +547,15 @@ enum sparx5_target { - #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ - FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) - --/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ --#define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ -- 0, 1, 843776, g, 70, 64, 20, r, 4, 4) -- --/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ --#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 893792, 0, 1, 24, 0, r, 2, 4) -+/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ -+#define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ -+ regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4) -+ -+/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ -+#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ -+ 0, 1, 24, 0, r, 2, 4) - - #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) - #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ -@@ -503,9 +563,10 @@ enum sparx5_target { - #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ - FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) - --/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ --#define ANA_AC_ACL_STAT_GLOBAL_CFG(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 893792, 0, 1, 24, 8, r, 2, 4) -+/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ -+#define ANA_AC_ACL_STAT_GLOBAL_CFG(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ -+ 0, 1, 24, 8, r, 2, 4) - - #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) - #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ -@@ -513,9 +574,10 @@ enum sparx5_target { - #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ - FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) - --/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ --#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) __REG(TARGET_ANA_AC,\ -- 0, 1, 893792, 0, 1, 24, 16, r, 2, 4) -+/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ -+#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) \ -+ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ -+ 0, 1, 24, 16, r, 2, 4) - - #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) - #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ -@@ -523,9 +585,10 @@ enum sparx5_target { - #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ - FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) - --/* ANA_ACL:COMMON:VCAP_S2_CFG */ --#define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL,\ -- 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) -+/* ANA_ACL:COMMON:VCAP_S2_CFG */ -+#define ANA_ACL_VCAP_S2_CFG(r) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ -+ 0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4) - - #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) - #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ -@@ -611,9 +674,10 @@ enum sparx5_target { - #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ - FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) - --/* ANA_ACL:COMMON:SWAP_IP_CTRL */ --#define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL,\ -- 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) -+/* ANA_ACL:COMMON:SWAP_IP_CTRL */ -+#define ANA_ACL_SWAP_IP_CTRL \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ -+ 412, 0, 1, 4) - - #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) - #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ -@@ -645,9 +709,10 @@ enum sparx5_target { - #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ - FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) - --/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ --#define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL,\ -- 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) -+/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ -+#define ANA_ACL_VCAP_S2_RLEG_STAT(r) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ -+ 424, r, 4, 4) - - #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) - #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ -@@ -661,9 +726,10 @@ enum sparx5_target { - #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ - FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) - --/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ --#define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL,\ -- 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) -+/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ -+#define ANA_ACL_VCAP_S2_FRAGMENT_CFG \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ -+ 440, 0, 1, 4) - - #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) - #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ -@@ -683,9 +749,10 @@ enum sparx5_target { - #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ - FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) - --/* ANA_ACL:COMMON:OWN_UPSID */ --#define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL,\ -- 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) -+/* ANA_ACL:COMMON:OWN_UPSID */ -+#define ANA_ACL_OWN_UPSID(r) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ -+ 580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4) - - #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) - #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ -@@ -693,9 +760,10 @@ enum sparx5_target { - #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ - FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) - --/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ --#define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ -- 0, 1, 34200, g, 134, 16, 0, r, 4, 4) -+/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ -+#define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \ -+ regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4) - - #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) - #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ -@@ -745,17 +813,20 @@ enum sparx5_target { - #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ - FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) - --/* ANA_ACL:CNT_A:CNT_A */ --#define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ -- 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) -- --/* ANA_ACL:CNT_B:CNT_B */ --#define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ -- 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) -- --/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ --#define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL,\ -- 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) -+/* ANA_ACL:CNT_A:CNT_A */ -+#define ANA_ACL_CNT_A(g) \ -+ __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \ -+ 0, 1, 4) -+ -+/* ANA_ACL:CNT_B:CNT_B */ -+#define ANA_ACL_CNT_B(g) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \ -+ regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4) -+ -+/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ -+#define ANA_ACL_SEC_LOOKUP_STICKY(r) \ -+ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \ -+ 0, r, 4, 4) - - #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) - #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ -@@ -865,9 +936,10 @@ enum sparx5_target { - #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ - FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) - --/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ --#define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL,\ -- 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) -+/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ -+#define ANA_AC_POL_POL_UPD_INT_CFG \ -+ __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \ -+ 0, 1, 1160, 1148, 0, 1, 4) - - #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) - #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ -@@ -875,9 +947,10 @@ enum sparx5_target { - #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ - FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) - --/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ --#define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ -- 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) -+/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ -+#define ANA_AC_POL_BDLB_DLB_CTRL \ -+ __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \ -+ 0, 1, 8, 0, 0, 1, 4) - - #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) - #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ -@@ -903,9 +976,10 @@ enum sparx5_target { - #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ - FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) - --/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ --#define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ -- 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) -+/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ -+#define ANA_AC_POL_SLB_DLB_CTRL \ -+ __REG(TARGET_ANA_AC_POL, 0, 1, \ -+ regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4) - - #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) - #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ -@@ -931,19 +1005,22 @@ enum sparx5_target { - #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ - FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) - --/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ --#define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 0, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ -+#define ANA_AC_SDLB_XLB_START(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4) - --#define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0) -+#define ANA_AC_SDLB_XLB_START_LBSET_START\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0) - #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x) -+ spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x) - #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x) -+ spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x) - --/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ --#define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 4, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ -+#define ANA_AC_SDLB_PUP_INTERVAL(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4) - - #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) - #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ -@@ -951,9 +1028,10 @@ enum sparx5_target { - #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ - FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) - --/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ --#define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 8, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ -+#define ANA_AC_SDLB_PUP_CTRL(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4) - - #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) - #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ -@@ -967,19 +1045,22 @@ enum sparx5_target { - #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ - FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) - --/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ --#define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 12, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ -+#define ANA_AC_SDLB_LBGRP_MISC(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4) - --#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8) -+#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8) - #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) -+ spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) - #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) -+ spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) - --/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ --#define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 16, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ -+#define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4) - - #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) - #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ -@@ -987,9 +1068,10 @@ enum sparx5_target { - #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ - FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) - --/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ --#define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 295468, g, 10, 24, 20, 0, 1, 4) -+/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ -+#define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ -+ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4) - - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ -@@ -1003,15 +1085,17 @@ enum sparx5_target { - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ - FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) - --#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16) -+#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16) - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) -+ spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) -+ spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) - --/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ --#define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 0, r, 2, 4) -+/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ -+#define ANA_AC_SDLB_PUP_TOKENS(g, r) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4) - - #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) - #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ -@@ -1019,9 +1103,10 @@ enum sparx5_target { - #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ - FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) - --/* ANA_AC_SDLB:LBSET_TBL:THRES */ --#define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 8, r, 2, 4) -+/* ANA_AC_SDLB:LBSET_TBL:THRES */ -+#define ANA_AC_SDLB_THRES(g, r) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4) - - #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) - #define ANA_AC_SDLB_THRES_THRES_SET(x)\ -@@ -1035,25 +1120,29 @@ enum sparx5_target { - #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ - FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) - --/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ --#define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 16, 0, 1, 4) -+/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ -+#define ANA_AC_SDLB_XLB_NEXT(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4) - --#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0) -+#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0) - #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) -+ spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) - #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) -+ spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) - --#define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24) -+#define ANA_AC_SDLB_XLB_NEXT_LBGRP\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24) - #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) -+ spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) - #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) -+ spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) - --/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ --#define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 20, r, 2, 4) -+/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ -+#define ANA_AC_SDLB_INH_CTRL(g, r) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4) - - #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) - #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ -@@ -1073,19 +1162,22 @@ enum sparx5_target { - #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ - FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) - --/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ --#define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 28, 0, 1, 4) -+/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ -+#define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4) - --#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0) -+#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\ -+ GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0) - #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ -- FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) -+ spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) - #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ -- FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) -+ spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) - --/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ --#define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 32, 0, 1, 4) -+/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ -+#define ANA_AC_SDLB_DLB_MISC(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4) - - #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) - #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ -@@ -1105,9 +1197,10 @@ enum sparx5_target { - #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ - FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) - --/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ --#define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ -- 0, 1, 0, g, 4616, 64, 36, 0, 1, 4) -+/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ -+#define ANA_AC_SDLB_DLB_CFG(g) \ -+ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ -+ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4) - - #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) - #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ -@@ -1157,9 +1250,10 @@ enum sparx5_target { - #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ - FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) - --/* ANA_CL:PORT:FILTER_CTRL */ --#define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) -+/* ANA_CL:PORT:FILTER_CTRL */ -+#define ANA_CL_FILTER_CTRL(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4) - - #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) - #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ -@@ -1179,9 +1273,10 @@ enum sparx5_target { - #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ - FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) - --/* ANA_CL:PORT:VLAN_FILTER_CTRL */ --#define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 8, r, 3, 4) -+/* ANA_CL:PORT:VLAN_FILTER_CTRL */ -+#define ANA_CL_VLAN_FILTER_CTRL(g, r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4) - - #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) - #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ -@@ -1249,9 +1344,10 @@ enum sparx5_target { - #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ - FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) - --/* ANA_CL:PORT:ETAG_FILTER_CTRL */ --#define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) -+/* ANA_CL:PORT:ETAG_FILTER_CTRL */ -+#define ANA_CL_ETAG_FILTER_CTRL(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4) - - #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) - #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ -@@ -1265,9 +1361,10 @@ enum sparx5_target { - #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ - FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) - --/* ANA_CL:PORT:VLAN_CTRL */ --#define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) -+/* ANA_CL:PORT:VLAN_CTRL */ -+#define ANA_CL_VLAN_CTRL(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4) - - #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) - #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ -@@ -1335,9 +1432,10 @@ enum sparx5_target { - #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ - FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) - --/* ANA_CL:PORT:VLAN_CTRL_2 */ --#define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) -+/* ANA_CL:PORT:VLAN_CTRL_2 */ -+#define ANA_CL_VLAN_CTRL_2(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4) - - #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) - #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ -@@ -1345,9 +1443,10 @@ enum sparx5_target { - #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ - FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) - --/* ANA_CL:PORT:PCP_DEI_MAP_CFG */ --#define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 108, r, 16, 4) -+/* ANA_CL:PORT:PCP_DEI_MAP_CFG */ -+#define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4) - - #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) - #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ -@@ -1361,9 +1460,10 @@ enum sparx5_target { - #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ - FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) - --/* ANA_CL:PORT:QOS_CFG */ --#define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) -+/* ANA_CL:PORT:QOS_CFG */ -+#define ANA_CL_QOS_CFG(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4) - - #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) - #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ -@@ -1437,13 +1537,15 @@ enum sparx5_target { - #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ - FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) - --/* ANA_CL:PORT:CAPTURE_BPDU_CFG */ --#define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) -- --/* ANA_CL:PORT:ADV_CL_CFG_2 */ --#define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 200, r, 6, 4) -+/* ANA_CL:PORT:CAPTURE_BPDU_CFG */ -+#define ANA_CL_CAPTURE_BPDU_CFG(g) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4) -+ -+/* ANA_CL:PORT:ADV_CL_CFG_2 */ -+#define ANA_CL_ADV_CL_CFG_2(g, r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4) - - #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) - #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ -@@ -1457,9 +1559,10 @@ enum sparx5_target { - #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ - FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) - --/* ANA_CL:PORT:ADV_CL_CFG */ --#define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ -- 0, 1, 131072, g, 70, 512, 224, r, 6, 4) -+/* ANA_CL:PORT:ADV_CL_CFG */ -+#define ANA_CL_ADV_CL_CFG(g, r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ -+ regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4) - - #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) - #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ -@@ -1503,9 +1606,10 @@ enum sparx5_target { - #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ - FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) - --/* ANA_CL:COMMON:OWN_UPSID */ --#define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL,\ -- 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) -+/* ANA_CL:COMMON:OWN_UPSID */ -+#define ANA_CL_OWN_UPSID(r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\ -+ r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4) - - #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) - #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ -@@ -1513,9 +1617,10 @@ enum sparx5_target { - #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ - FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) - --/* ANA_CL:COMMON:DSCP_CFG */ --#define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL,\ -- 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) -+/* ANA_CL:COMMON:DSCP_CFG */ -+#define ANA_CL_DSCP_CFG(r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ -+ 256, r, 64, 4) - - #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) - #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ -@@ -1547,9 +1652,10 @@ enum sparx5_target { - #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ - FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) - --/* ANA_CL:COMMON:QOS_MAP_CFG */ --#define ANA_CL_QOS_MAP_CFG(r) __REG(TARGET_ANA_CL,\ -- 0, 1, 166912, 0, 1, 756, 512, r, 32, 4) -+/* ANA_CL:COMMON:QOS_MAP_CFG */ -+#define ANA_CL_QOS_MAP_CFG(r) \ -+ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ -+ 512, r, 32, 4) - - #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) - #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ -@@ -1557,9 +1663,10 @@ enum sparx5_target { - #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ - FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) - --/* ANA_L2:COMMON:FWD_CFG */ --#define ANA_L2_FWD_CFG __REG(TARGET_ANA_L2,\ -- 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4) -+/* ANA_L2:COMMON:FWD_CFG */ -+#define ANA_L2_FWD_CFG \ -+ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ -+ regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4) - - #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) - #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ -@@ -1633,17 +1740,22 @@ enum sparx5_target { - #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ - FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) - --/* ANA_L2:COMMON:AUTO_LRN_CFG */ --#define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2,\ -- 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) -- --/* ANA_L2:COMMON:AUTO_LRN_CFG1 */ --#define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2,\ -- 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) -- --/* ANA_L2:COMMON:AUTO_LRN_CFG2 */ --#define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2,\ -- 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) -+/* ANA_L2:COMMON:AUTO_LRN_CFG */ -+#define ANA_L2_AUTO_LRN_CFG \ -+ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ -+ regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_L2:COMMON:AUTO_LRN_CFG1 */ -+#define ANA_L2_AUTO_LRN_CFG1 \ -+ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ -+ regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_L2:COMMON:AUTO_LRN_CFG2 */ -+#define ANA_L2_AUTO_LRN_CFG2 \ -+ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ -+ regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4) - - #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) - #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ -@@ -1651,9 +1763,11 @@ enum sparx5_target { - #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ - FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) - --/* ANA_L2:COMMON:OWN_UPSID */ --#define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2,\ -- 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) -+/* ANA_L2:COMMON:OWN_UPSID */ -+#define ANA_L2_OWN_UPSID(r) \ -+ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ -+ regs->gsize[GW_ANA_L2_COMMON], 672, r, \ -+ regs->rcnt[RC_ANA_L2_OWN_UPSID], 4) - - #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) - #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ -@@ -1661,29 +1775,34 @@ enum sparx5_target { - #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ - FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) - --/* ANA_L2:ISDX:DLB_CFG */ --#define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ -- 0, 1, 0, g, 4096, 128, 56, 0, 1, 4) -+/* ANA_L2:ISDX:DLB_CFG */ -+#define ANA_L2_DLB_CFG(g) \ -+ __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \ -+ 0, 1, 4) - --#define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0) -+#define ANA_L2_DLB_CFG_DLB_IDX\ -+ GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0) - #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ -- FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x) -+ spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x) - #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ -- FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x) -+ spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x) - --/* ANA_L2:ISDX:TSN_CFG */ --#define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ -- 0, 1, 0, g, 4096, 128, 100, 0, 1, 4) -+/* ANA_L2:ISDX:TSN_CFG */ -+#define ANA_L2_TSN_CFG(g) \ -+ __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \ -+ 0, 1, 4) - --#define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0) -+#define ANA_L2_TSN_CFG_TSN_SFID\ -+ GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0) - #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ -- FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x) -+ spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x) - #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ -- FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x) -+ spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x) - --/* ANA_L3:COMMON:VLAN_CTRL */ --#define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3,\ -- 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) -+/* ANA_L3:COMMON:VLAN_CTRL */ -+#define ANA_L3_VLAN_CTRL \ -+ __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\ -+ 0, 1, 4) - - #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) - #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ -@@ -1691,9 +1810,10 @@ enum sparx5_target { - #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ - FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) - --/* ANA_L3:VLAN:VLAN_CFG */ --#define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ -- 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) -+/* ANA_L3:VLAN:VLAN_CFG */ -+#define ANA_L3_VLAN_CFG(g) \ -+ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \ -+ 1, 4) - - #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) - #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ -@@ -1749,17 +1869,22 @@ enum sparx5_target { - #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ - FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) - --/* ANA_L3:VLAN:VLAN_MASK_CFG */ --#define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ -- 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) -- --/* ANA_L3:VLAN:VLAN_MASK_CFG1 */ --#define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ -- 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) -- --/* ANA_L3:VLAN:VLAN_MASK_CFG2 */ --#define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ -- 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) -+/* ANA_L3:VLAN:VLAN_MASK_CFG */ -+#define ANA_L3_VLAN_MASK_CFG(g) \ -+ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\ -+ 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_L3:VLAN:VLAN_MASK_CFG1 */ -+#define ANA_L3_VLAN_MASK_CFG1(g) \ -+ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\ -+ 1, 4) -+ -+/* SPARX5 ONLY */ -+/* ANA_L3:VLAN:VLAN_MASK_CFG2 */ -+#define ANA_L3_VLAN_MASK_CFG2(g) \ -+ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\ -+ 1, 4) - - #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) - #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ -@@ -1767,365 +1892,455 @@ enum sparx5_target { - #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ - FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) - --/* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ --#define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 0, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ --#define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 4, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ --#define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 8, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ --#define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 12, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ --#define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 16, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ --#define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 20, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_UC_CNT */ --#define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 24, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_MC_CNT */ --#define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 28, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_BC_CNT */ --#define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 32, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ --#define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 36, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ --#define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 40, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ --#define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 44, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ --#define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 48, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ --#define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 52, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ --#define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 56, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ --#define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 60, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ --#define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 64, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ --#define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 68, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ --#define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 72, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ --#define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 76, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ --#define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 80, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ --#define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 84, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ --#define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 88, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ --#define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 92, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ --#define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 96, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ --#define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 100, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ --#define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 104, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_UC_CNT */ --#define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 108, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_MC_CNT */ --#define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 112, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_BC_CNT */ --#define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 116, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ --#define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 120, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ --#define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 124, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ --#define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 128, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ --#define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 132, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ --#define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 136, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ --#define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 140, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ --#define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 144, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ --#define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 148, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ --#define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 152, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ --#define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 156, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ --#define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 160, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ --#define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 164, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ --#define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 168, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ --#define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 172, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ --#define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 176, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ --#define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 180, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ --#define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 184, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ --#define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 188, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ --#define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 192, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ --#define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 196, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ --#define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 200, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ --#define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 204, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ --#define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 208, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ --#define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 212, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ --#define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 216, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ --#define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 220, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ --#define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 224, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ --#define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 228, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ --#define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 232, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ --#define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 236, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ --#define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 240, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ --#define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 244, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ --#define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 248, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ --#define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 252, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ --#define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 256, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ --#define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 260, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ --#define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 264, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ --#define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 268, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ --#define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 272, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ --#define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 276, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ --#define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 280, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ --#define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 284, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ --#define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 288, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ --#define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 292, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ --#define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 296, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ --#define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 300, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ --#define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 304, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ --#define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 308, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ --#define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 312, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ --#define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 316, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ --#define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 320, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ --#define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 324, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ --#define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 328, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ --#define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 332, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ --#define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 336, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_DEFER_CNT */ --#define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 340, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ --#define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 344, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ --#define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 348, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ --#define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 352, 0, 1, 4) -- --/* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ --#define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 356, 0, 1, 4) -+/* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ -+#define ASM_RX_IN_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 0, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ -+#define ASM_RX_SYMBOL_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 4, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ -+#define ASM_RX_PAUSE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 8, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ -+#define ASM_RX_UNSUP_OPCODE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 12, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ -+#define ASM_RX_OK_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 16, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ -+#define ASM_RX_BAD_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 20, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_UC_CNT */ -+#define ASM_RX_UC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 24, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_MC_CNT */ -+#define ASM_RX_MC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 28, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_BC_CNT */ -+#define ASM_RX_BC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 32, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ -+#define ASM_RX_CRC_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 36, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ -+#define ASM_RX_UNDERSIZE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 40, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ -+#define ASM_RX_FRAGMENTS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 44, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ -+#define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 48, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ -+#define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 52, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ -+#define ASM_RX_OVERSIZE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 56, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ -+#define ASM_RX_JABBERS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 60, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ -+#define ASM_RX_SIZE64_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 64, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ -+#define ASM_RX_SIZE65TO127_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 68, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ -+#define ASM_RX_SIZE128TO255_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 72, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ -+#define ASM_RX_SIZE256TO511_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 76, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ -+#define ASM_RX_SIZE512TO1023_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 80, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ -+#define ASM_RX_SIZE1024TO1518_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 84, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ -+#define ASM_RX_SIZE1519TOMAX_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 88, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ -+#define ASM_RX_IPG_SHRINK_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 92, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ -+#define ASM_TX_OUT_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 96, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ -+#define ASM_TX_PAUSE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 100, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ -+#define ASM_TX_OK_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 104, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_UC_CNT */ -+#define ASM_TX_UC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 108, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_MC_CNT */ -+#define ASM_TX_MC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 112, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_BC_CNT */ -+#define ASM_TX_BC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 116, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ -+#define ASM_TX_SIZE64_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 120, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ -+#define ASM_TX_SIZE65TO127_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 124, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ -+#define ASM_TX_SIZE128TO255_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 128, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ -+#define ASM_TX_SIZE256TO511_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 132, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ -+#define ASM_TX_SIZE512TO1023_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 136, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ -+#define ASM_TX_SIZE1024TO1518_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 140, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ -+#define ASM_TX_SIZE1519TOMAX_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 144, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ -+#define ASM_RX_ALIGNMENT_LOST_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 148, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ -+#define ASM_RX_TAGGED_FRMS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 152, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ -+#define ASM_RX_UNTAGGED_FRMS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 156, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ -+#define ASM_TX_TAGGED_FRMS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 160, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ -+#define ASM_TX_UNTAGGED_FRMS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 164, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ -+#define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 168, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ -+#define ASM_PMAC_RX_PAUSE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 172, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ -+#define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 176, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ -+#define ASM_PMAC_RX_OK_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 180, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ -+#define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 184, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ -+#define ASM_PMAC_RX_UC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 188, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ -+#define ASM_PMAC_RX_MC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 192, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ -+#define ASM_PMAC_RX_BC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 196, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ -+#define ASM_PMAC_RX_CRC_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 200, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ -+#define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 204, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ -+#define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 208, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ -+#define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 212, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ -+#define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 216, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ -+#define ASM_PMAC_RX_OVERSIZE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 220, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ -+#define ASM_PMAC_RX_JABBERS_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 224, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ -+#define ASM_PMAC_RX_SIZE64_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 228, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ -+#define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 232, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ -+#define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 236, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ -+#define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 240, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ -+#define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 244, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ -+#define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 248, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ -+#define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 252, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ -+#define ASM_PMAC_TX_PAUSE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 256, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ -+#define ASM_PMAC_TX_OK_BYTES_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 260, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ -+#define ASM_PMAC_TX_UC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 264, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ -+#define ASM_PMAC_TX_MC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 268, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ -+#define ASM_PMAC_TX_BC_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 272, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ -+#define ASM_PMAC_TX_SIZE64_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 276, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ -+#define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 280, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ -+#define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 284, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ -+#define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 288, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ -+#define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 292, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ -+#define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 296, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ -+#define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 300, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ -+#define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 304, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ -+#define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 308, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ -+#define ASM_MM_RX_SMD_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 312, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ -+#define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 316, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ -+#define ASM_MM_RX_MERGE_FRAG_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 320, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ -+#define ASM_MM_TX_PFRAGMENT_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 324, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ -+#define ASM_TX_MULTI_COLL_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 328, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ -+#define ASM_TX_LATE_COLL_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 332, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ -+#define ASM_TX_XCOLL_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 336, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_DEFER_CNT */ -+#define ASM_TX_DEFER_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 340, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ -+#define ASM_TX_XDEFER_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 344, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ -+#define ASM_TX_BACKOFF1_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 348, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ -+#define ASM_TX_CSENSE_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 352, 0, 1, 4) -+ -+/* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ -+#define ASM_RX_IN_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 356, 0, 1, 4) - - #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ -@@ -2133,9 +2348,10 @@ enum sparx5_target { - #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ --#define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 360, 0, 1, 4) -+/* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ -+#define ASM_RX_OK_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 360, 0, 1, 4) - - #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -2143,9 +2359,10 @@ enum sparx5_target { - #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ --#define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 364, 0, 1, 4) -+/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ -+#define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 364, 0, 1, 4) - - #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -2153,9 +2370,10 @@ enum sparx5_target { - #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ --#define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 368, 0, 1, 4) -+/* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ -+#define ASM_RX_BAD_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 368, 0, 1, 4) - - #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ -@@ -2163,9 +2381,10 @@ enum sparx5_target { - #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ --#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 372, 0, 1, 4) -+/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ -+#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 372, 0, 1, 4) - - #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ -@@ -2173,9 +2392,10 @@ enum sparx5_target { - #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ --#define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 376, 0, 1, 4) -+/* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ -+#define ASM_TX_OUT_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 376, 0, 1, 4) - - #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ -@@ -2183,9 +2403,10 @@ enum sparx5_target { - #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ --#define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 380, 0, 1, 4) -+/* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ -+#define ASM_TX_OK_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 380, 0, 1, 4) - - #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -2193,9 +2414,10 @@ enum sparx5_target { - #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ --#define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 384, 0, 1, 4) -+/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ -+#define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 384, 0, 1, 4) - - #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) - #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -2203,13 +2425,15 @@ enum sparx5_target { - #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) - --/* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ --#define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ -- 0, 1, 0, g, 65, 512, 388, 0, 1, 4) -- --/* ASM:CFG:STAT_CFG */ --#define ASM_STAT_CFG __REG(TARGET_ASM,\ -- 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) -+/* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ -+#define ASM_RX_SYNC_LOST_ERR_CNT(g) \ -+ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ -+ 388, 0, 1, 4) -+ -+/* ASM:CFG:STAT_CFG */ -+#define ASM_STAT_CFG \ -+ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ -+ regs->gsize[GW_ASM_CFG], 0, 0, 1, 4) - - #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) - #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ -@@ -2217,9 +2441,10 @@ enum sparx5_target { - #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ - FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) - --/* ASM:CFG:PORT_CFG */ --#define ASM_PORT_CFG(r) __REG(TARGET_ASM,\ -- 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) -+/* ASM:CFG:PORT_CFG */ -+#define ASM_PORT_CFG(r) \ -+ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ -+ regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4) - - #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) - #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ -@@ -2287,9 +2512,10 @@ enum sparx5_target { - #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ - FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) - --/* ASM:RAM_CTRL:RAM_INIT */ --#define ASM_RAM_INIT __REG(TARGET_ASM,\ -- 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) -+/* ASM:RAM_CTRL:RAM_INIT */ -+#define ASM_RAM_INIT \ -+ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ -+ 4) - - #define ASM_RAM_INIT_RAM_INIT BIT(1) - #define ASM_RAM_INIT_RAM_INIT_SET(x)\ -@@ -2303,9 +2529,10 @@ enum sparx5_target { - #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) - --/* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ --#define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN,\ -- 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ -+#define CLKGEN_LCPLL1_CORE_CLK_CFG \ -+ __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) - - #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) - #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ -@@ -2343,91 +2570,106 @@ enum sparx5_target { - #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ - FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) - --/* CPU:CPU_REGS:PROC_CTRL */ --#define CPU_PROC_CTRL __REG(TARGET_CPU,\ -- 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) -+/* CPU:CPU_REGS:PROC_CTRL */ -+#define CPU_PROC_CTRL \ -+ __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \ -+ regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4) - --#define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) -+#define CPU_PROC_CTRL_AARCH64_MODE_ENA\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA]) - #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) -+ spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) - #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) -+ spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) - --#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) -+#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS]) - #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) -+ spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) - #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) -+ spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) - --#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) -+#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS]) - #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) -+ spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) - #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) -+ spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) - --#define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) -+#define CPU_PROC_CTRL_BE_EXCEP_MODE\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE]) - #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) -+ spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x) - #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) -+ spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x) - --#define CPU_PROC_CTRL_VINITHI BIT(8) -+#define CPU_PROC_CTRL_VINITHI\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI]) - #define CPU_PROC_CTRL_VINITHI_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) -+ spx5_field_prep(CPU_PROC_CTRL_VINITHI, x) - #define CPU_PROC_CTRL_VINITHI_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_VINITHI, x) -+ spx5_field_get(CPU_PROC_CTRL_VINITHI, x) - --#define CPU_PROC_CTRL_CFGTE BIT(7) -+#define CPU_PROC_CTRL_CFGTE\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE]) - #define CPU_PROC_CTRL_CFGTE_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) -+ spx5_field_prep(CPU_PROC_CTRL_CFGTE, x) - #define CPU_PROC_CTRL_CFGTE_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_CFGTE, x) -+ spx5_field_get(CPU_PROC_CTRL_CFGTE, x) - --#define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) -+#define CPU_PROC_CTRL_CP15S_DISABLE\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE]) - #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) -+ spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x) - #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) -+ spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x) - --#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) -+#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE]) - #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) -+ spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) - #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) -+ spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) - -+/* SPARX5 ONLY */ - #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) - #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ - FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) - #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ - FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) - -+/* SPARX5 ONLY */ - #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) - #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ - FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) - #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ - FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) - -+/* SPARX5 ONLY */ - #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) - #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ - FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) - #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ - FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) - --#define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) -+#define CPU_PROC_CTRL_L2_FLUSH_REQ\ -+ BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ]) - #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ -- FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) -+ spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x) - #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ -- FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) -+ spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x) - -+/* SPARX5 ONLY */ - #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) - #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ - FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) - #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ - FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ --#define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 0, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ -+#define DEV10G_MAC_ENA_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ -+ 4) - - #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) - #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ -@@ -2441,9 +2683,10 @@ enum sparx5_target { - #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ - FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ --#define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 8, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ -+#define DEV10G_MAC_MAXLEN_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \ -+ 4) - - #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) - #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ -@@ -2457,9 +2700,10 @@ enum sparx5_target { - #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ - FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ --#define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 12, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ -+#define DEV10G_MAC_NUM_TAGS_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \ -+ 4) - - #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) - #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ -@@ -2467,9 +2711,10 @@ enum sparx5_target { - #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ - FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ --#define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 16, r, 3, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ -+#define DEV10G_MAC_TAGS_CFG(t, r) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \ -+ 4) - - #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) - #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ -@@ -2483,9 +2728,10 @@ enum sparx5_target { - #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ - FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ --#define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 28, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ -+#define DEV10G_MAC_ADV_CHK_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \ -+ 4) - - #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) - #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ -@@ -2529,9 +2775,10 @@ enum sparx5_target { - #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ - FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ --#define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G,\ -- t, 12, 0, 0, 1, 60, 48, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ -+#define DEV10G_MAC_TX_MONITOR_STICKY(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \ -+ 4) - - #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) - #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ -@@ -2563,9 +2810,10 @@ enum sparx5_target { - #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ - FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) - --/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ --#define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G,\ -- t, 12, 436, 0, 1, 52, 0, 0, 1, 4) -+/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ -+#define DEV10G_DEV_RST_CTRL(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\ -+ 4) - - #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) - #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ -@@ -2621,9 +2869,10 @@ enum sparx5_target { - #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) - --/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ --#define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G,\ -- t, 12, 488, 0, 1, 32, 0, 0, 1, 4) -+/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ -+#define DEV10G_PCS25G_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ -+ 4) - - #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) - #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ -@@ -2631,9 +2880,10 @@ enum sparx5_target { - #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ - FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ --#define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G,\ -- t, 8, 0, 0, 1, 60, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ -+#define DEV25G_MAC_ENA_CFG(t) \ -+ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) - - #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) - #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ -@@ -2647,9 +2897,10 @@ enum sparx5_target { - #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ - FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ --#define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G,\ -- t, 8, 0, 0, 1, 60, 8, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ -+#define DEV25G_MAC_MAXLEN_CFG(t) \ -+ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) - - #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) - #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ -@@ -2663,9 +2914,10 @@ enum sparx5_target { - #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ - FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ --#define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G,\ -- t, 8, 0, 0, 1, 60, 28, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ -+#define DEV25G_MAC_ADV_CHK_CFG(t) \ -+ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) - - #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) - #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ -@@ -2709,9 +2961,10 @@ enum sparx5_target { - #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ - FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) - --/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ --#define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G,\ -- t, 8, 436, 0, 1, 52, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ -+#define DEV25G_DEV_RST_CTRL(t) \ -+ __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) - - #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) - #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ -@@ -2767,9 +3020,10 @@ enum sparx5_target { - #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) - --/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ --#define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G,\ -- t, 8, 488, 0, 1, 32, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ -+#define DEV25G_PCS25G_CFG(t) \ -+ __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) - - #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) - #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ -@@ -2777,9 +3031,10 @@ enum sparx5_target { - #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ - FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) - --/* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ --#define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G,\ -- t, 8, 488, 0, 1, 32, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ -+#define DEV25G_PCS25G_SD_CFG(t) \ -+ __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) - - #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) - #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ -@@ -2799,9 +3054,10 @@ enum sparx5_target { - #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ - FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) - --/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ --#define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5,\ -- t, 65, 0, 0, 1, 36, 0, 0, 1, 4) -+/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ -+#define DEV2G5_DEV_RST_CTRL(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \ -+ 4) - - #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) - #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ -@@ -2851,9 +3107,10 @@ enum sparx5_target { - #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ --#define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 0, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ -+#define DEV2G5_MAC_ENA_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \ -+ 4) - - #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) - #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ -@@ -2867,9 +3124,10 @@ enum sparx5_target { - #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ - FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ --#define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 4, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ -+#define DEV2G5_MAC_MODE_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \ -+ 4) - - #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) - #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ -@@ -2889,9 +3147,10 @@ enum sparx5_target { - #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ - FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ --#define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 8, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ -+#define DEV2G5_MAC_MAXLEN_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \ -+ 4) - - #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) - #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ -@@ -2899,9 +3158,10 @@ enum sparx5_target { - #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ - FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ --#define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 12, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ -+#define DEV2G5_MAC_TAGS_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\ -+ 4) - - #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) - #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ -@@ -2927,9 +3187,10 @@ enum sparx5_target { - #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ - FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ --#define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 16, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ -+#define DEV2G5_MAC_TAGS_CFG2(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\ -+ 4) - - #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) - #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ -@@ -2943,9 +3204,10 @@ enum sparx5_target { - #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ - FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ --#define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 20, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ -+#define DEV2G5_MAC_ADV_CHK_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\ -+ 4) - - #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) - #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ -@@ -2953,9 +3215,10 @@ enum sparx5_target { - #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ - FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ --#define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 24, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ -+#define DEV2G5_MAC_IFG_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\ -+ 4) - - #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) - #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ -@@ -2981,9 +3244,10 @@ enum sparx5_target { - #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ - FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) - --/* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ --#define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 52, 0, 1, 36, 28, 0, 1, 4) -+/* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ -+#define DEV2G5_MAC_HDX_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\ -+ 4) - - #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) - #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ -@@ -3015,9 +3279,10 @@ enum sparx5_target { - #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ - FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ --#define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 0, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ -+#define DEV2G5_PCS1G_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \ -+ 4) - - #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) - #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ -@@ -3037,9 +3302,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ --#define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 4, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ -+#define DEV2G5_PCS1G_MODE_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \ -+ 4) - - #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) - #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ -@@ -3059,9 +3325,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ --#define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 8, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ -+#define DEV2G5_PCS1G_SD_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \ -+ 4) - - #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) - #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ -@@ -3081,9 +3348,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ --#define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 12, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ -+#define DEV2G5_PCS1G_ANEG_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\ -+ 4) - - #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) - #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ -@@ -3109,9 +3377,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ --#define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 20, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ -+#define DEV2G5_PCS1G_LB_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\ -+ 4) - - #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) - #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ -@@ -3131,9 +3400,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ --#define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 32, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ -+#define DEV2G5_PCS1G_ANEG_STATUS(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\ -+ 4) - - #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) - #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ -@@ -3159,9 +3429,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ --#define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 40, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ -+#define DEV2G5_PCS1G_LINK_STATUS(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\ -+ 4) - - #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) - #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ -@@ -3187,9 +3458,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) - --/* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ --#define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5,\ -- t, 65, 88, 0, 1, 68, 48, 0, 1, 4) -+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ -+#define DEV2G5_PCS1G_STICKY(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\ -+ 4) - - #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) - #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ -@@ -3203,9 +3475,10 @@ enum sparx5_target { - #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ - FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) - --/* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ --#define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5,\ -- t, 65, 164, 0, 1, 4, 0, 0, 1, 4) -+/* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ -+#define DEV2G5_PCS_FX100_CFG(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \ -+ 4) - - #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) - #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ -@@ -3285,9 +3558,10 @@ enum sparx5_target { - #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ - FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) - --/* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ --#define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5,\ -- t, 65, 168, 0, 1, 4, 0, 0, 1, 4) -+/* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ -+#define DEV2G5_PCS_FX100_STATUS(t) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \ -+ 4) - - #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) - #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ -@@ -3337,9 +3611,9 @@ enum sparx5_target { - #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ - FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ --#define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G,\ -- t, 13, 0, 0, 1, 60, 0, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ -+#define DEV5G_MAC_ENA_CFG(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4) - - #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) - #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ -@@ -3353,9 +3627,9 @@ enum sparx5_target { - #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ - FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ --#define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G,\ -- t, 13, 0, 0, 1, 60, 8, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ -+#define DEV5G_MAC_MAXLEN_CFG(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4) - - #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) - #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ -@@ -3369,9 +3643,10 @@ enum sparx5_target { - #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ - FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) - --/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ --#define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G,\ -- t, 13, 0, 0, 1, 60, 28, 0, 1, 4) -+/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ -+#define DEV5G_MAC_ADV_CHK_CFG(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \ -+ 4) - - #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) - #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ -@@ -3415,325 +3690,405 @@ enum sparx5_target { - #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ - FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) - --/* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ --#define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 0, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ --#define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 4, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ --#define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 8, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ --#define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 12, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ --#define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 16, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ --#define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 20, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ --#define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 24, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ --#define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 28, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ --#define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 32, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ --#define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 36, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ --#define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 40, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ --#define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 44, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ --#define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 48, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ --#define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 52, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ --#define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 56, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ --#define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 60, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ --#define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 64, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ --#define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 68, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ --#define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 72, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ --#define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 76, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ --#define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 80, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ --#define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 84, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ --#define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 88, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ --#define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 92, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ --#define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 96, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ --#define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 100, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ --#define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 104, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ --#define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 108, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ --#define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 112, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ --#define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 116, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ --#define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 120, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ --#define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 124, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ --#define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 128, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ --#define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 132, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ --#define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 136, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ --#define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 140, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ --#define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 144, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ --#define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 148, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ --#define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 152, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ --#define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 156, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ --#define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 160, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ --#define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 164, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ --#define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 168, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ --#define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 172, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ --#define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 176, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ --#define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 180, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ --#define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 184, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ --#define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 188, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ --#define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 192, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ --#define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 196, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ --#define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 200, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ --#define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 204, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ --#define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 208, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ --#define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 212, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ --#define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 216, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ --#define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 220, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ --#define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 224, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ --#define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 228, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ --#define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 232, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ --#define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 236, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ --#define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 240, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ --#define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 244, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ --#define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 248, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ --#define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 252, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ --#define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 256, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ --#define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 260, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ --#define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 264, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ --#define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 268, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ --#define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 272, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ --#define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 276, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ --#define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 280, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ --#define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 284, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ --#define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 288, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ --#define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 292, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ --#define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 296, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ --#define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 300, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ --#define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 304, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ --#define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 60, 0, 1, 312, 308, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ --#define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 0, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ --#define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 4, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ -+#define DEV5G_RX_SYMBOL_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ -+#define DEV5G_RX_PAUSE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ -+#define DEV5G_RX_UNSUP_OPCODE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ -+#define DEV5G_RX_UC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ -+#define DEV5G_RX_MC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ -+#define DEV5G_RX_BC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ -+#define DEV5G_RX_CRC_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ -+#define DEV5G_RX_UNDERSIZE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ -+#define DEV5G_RX_FRAGMENTS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ -+#define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ -+#define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ -+#define DEV5G_RX_OVERSIZE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ -+#define DEV5G_RX_JABBERS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ -+#define DEV5G_RX_SIZE64_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ -+#define DEV5G_RX_SIZE65TO127_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ -+#define DEV5G_RX_SIZE128TO255_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ -+#define DEV5G_RX_SIZE256TO511_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ -+#define DEV5G_RX_SIZE512TO1023_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ -+#define DEV5G_RX_SIZE1024TO1518_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ -+#define DEV5G_RX_SIZE1519TOMAX_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ -+#define DEV5G_RX_IPG_SHRINK_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ -+#define DEV5G_TX_PAUSE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ -+#define DEV5G_TX_UC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ -+#define DEV5G_TX_MC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ -+#define DEV5G_TX_BC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ -+#define DEV5G_TX_SIZE64_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ -+#define DEV5G_TX_SIZE65TO127_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ -+#define DEV5G_TX_SIZE128TO255_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ -+#define DEV5G_TX_SIZE256TO511_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ -+#define DEV5G_TX_SIZE512TO1023_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ -+#define DEV5G_TX_SIZE1024TO1518_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ -+#define DEV5G_TX_SIZE1519TOMAX_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ -+#define DEV5G_RX_ALIGNMENT_LOST_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ -+#define DEV5G_RX_TAGGED_FRMS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ -+#define DEV5G_RX_UNTAGGED_FRMS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ -+#define DEV5G_TX_TAGGED_FRMS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ -+#define DEV5G_TX_UNTAGGED_FRMS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ -+#define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ -+#define DEV5G_PMAC_RX_PAUSE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ -+#define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ -+#define DEV5G_PMAC_RX_UC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ -+#define DEV5G_PMAC_RX_MC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ -+#define DEV5G_PMAC_RX_BC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ -+#define DEV5G_PMAC_RX_CRC_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ -+#define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ -+#define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ -+#define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ -+#define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ -+#define DEV5G_PMAC_RX_OVERSIZE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ -+#define DEV5G_PMAC_RX_JABBERS_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ -+#define DEV5G_PMAC_RX_SIZE64_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ -+#define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ -+#define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ -+#define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ -+#define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ -+#define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ -+#define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ -+#define DEV5G_PMAC_TX_PAUSE_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ -+#define DEV5G_PMAC_TX_UC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ -+#define DEV5G_PMAC_TX_MC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ -+#define DEV5G_PMAC_TX_BC_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ -+#define DEV5G_PMAC_TX_SIZE64_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ -+#define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ -+#define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ -+#define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ -+#define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ -+#define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ -+#define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ -+#define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ -+#define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ -+#define DEV5G_MM_RX_SMD_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ -+#define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ -+#define DEV5G_MM_RX_MERGE_FRAG_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ -+#define DEV5G_MM_TX_PFRAGMENT_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ -+#define DEV5G_RX_HIH_CKSM_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ -+#define DEV5G_RX_XGMII_PROT_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ -+#define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ -+#define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ -+#define DEV5G_RX_IN_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ -+#define DEV5G_RX_IN_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \ -+ 4) - - #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ -@@ -3741,13 +4096,15 @@ enum sparx5_target { - #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ --#define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 8, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ --#define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 12, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ -+#define DEV5G_RX_OK_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ -+#define DEV5G_RX_OK_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \ -+ 4) - - #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -3755,13 +4112,15 @@ enum sparx5_target { - #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ --#define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 16, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ --#define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 20, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ -+#define DEV5G_RX_BAD_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ -+#define DEV5G_RX_BAD_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \ -+ 4) - - #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ -@@ -3769,13 +4128,15 @@ enum sparx5_target { - #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ --#define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 24, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ --#define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 28, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ -+#define DEV5G_TX_OUT_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ -+#define DEV5G_TX_OUT_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \ -+ 4) - - #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ -@@ -3783,13 +4144,15 @@ enum sparx5_target { - #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ --#define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 32, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ --#define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 36, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ -+#define DEV5G_TX_OK_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ -+#define DEV5G_TX_OK_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \ -+ 4) - - #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -3797,13 +4160,15 @@ enum sparx5_target { - #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ --#define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 40, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ --#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 44, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ -+#define DEV5G_PMAC_RX_OK_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ -+#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \ -+ 4) - - #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -3811,13 +4176,15 @@ enum sparx5_target { - #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ --#define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 48, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ --#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 52, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ -+#define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ -+#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \ -+ 4) - - #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ -@@ -3825,13 +4192,15 @@ enum sparx5_target { - #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ --#define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 56, 0, 1, 4) -- --/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ --#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ -- t, 13, 372, 0, 1, 64, 60, 0, 1, 4) -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ -+#define DEV5G_PMAC_TX_OK_BYTES_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \ -+ 4) -+ -+/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ -+#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \ -+ 4) - - #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) - #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ -@@ -3839,9 +4208,10 @@ enum sparx5_target { - #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ - FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) - --/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ --#define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G,\ -- t, 13, 436, 0, 1, 52, 0, 0, 1, 4) -+/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ -+#define DEV5G_DEV_RST_CTRL(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \ -+ 4) - - #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) - #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ -@@ -3897,9 +4267,9 @@ enum sparx5_target { - #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) - --/* DSM:RAM_CTRL:RAM_INIT */ --#define DSM_RAM_INIT __REG(TARGET_DSM,\ -- 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) -+/* DSM:RAM_CTRL:RAM_INIT */ -+#define DSM_RAM_INIT \ -+ __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) - - #define DSM_RAM_INIT_RAM_INIT BIT(1) - #define DSM_RAM_INIT_RAM_INIT_SET(x)\ -@@ -3913,9 +4283,10 @@ enum sparx5_target { - #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) - --/* DSM:CFG:BUF_CFG */ --#define DSM_BUF_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) -+/* DSM:CFG:BUF_CFG */ -+#define DSM_BUF_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \ -+ regs->rcnt[RC_DSM_BUF_CFG], 4) - - #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) - #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ -@@ -3941,9 +4312,10 @@ enum sparx5_target { - #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ - FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) - --/* DSM:CFG:DEV_TX_STOP_WM_CFG */ --#define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) -+/* DSM:CFG:DEV_TX_STOP_WM_CFG */ -+#define DSM_DEV_TX_STOP_WM_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \ -+ regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4) - - #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) - #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ -@@ -3969,9 +4341,10 @@ enum sparx5_target { - #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ - FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) - --/* DSM:CFG:RX_PAUSE_CFG */ --#define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) -+/* DSM:CFG:RX_PAUSE_CFG */ -+#define DSM_RX_PAUSE_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \ -+ regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4) - - #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) - #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ -@@ -3985,9 +4358,10 @@ enum sparx5_target { - #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ - FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) - --/* DSM:CFG:MAC_CFG */ --#define DSM_MAC_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) -+/* DSM:CFG:MAC_CFG */ -+#define DSM_MAC_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \ -+ regs->rcnt[RC_DSM_MAC_CFG], 4) - - #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) - #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ -@@ -4013,9 +4387,10 @@ enum sparx5_target { - #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ - FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) - --/* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ --#define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) -+/* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ -+#define DSM_MAC_ADDR_BASE_HIGH_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \ -+ regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4) - - #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) - #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ -@@ -4023,9 +4398,10 @@ enum sparx5_target { - #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ - FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) - --/* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ --#define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) -+/* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ -+#define DSM_MAC_ADDR_BASE_LOW_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \ -+ regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4) - - #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) - #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ -@@ -4033,9 +4409,10 @@ enum sparx5_target { - #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ - FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) - --/* DSM:CFG:TAXI_CAL_CFG */ --#define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM,\ -- 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) -+/* DSM:CFG:TAXI_CAL_CFG */ -+#define DSM_TAXI_CAL_CFG(r) \ -+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \ -+ regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4) - - #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) - #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ -@@ -4067,9 +4444,10 @@ enum sparx5_target { - #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ - FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) - --/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ --#define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ -- 0, 1, 149504, g, 138, 8, 0, r, 2, 4) -+/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ -+#define EACL_VCAP_ES2_KEY_SEL(g, r) \ -+ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ -+ g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4) - - #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) - #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ -@@ -4095,13 +4473,15 @@ enum sparx5_target { - #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ - FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) - --/* EACL:CNT_TBL:ES2_CNT */ --#define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ -- 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4) -- --/* EACL:POL_CFG:POL_EACL_CFG */ --#define EACL_POL_EACL_CFG __REG(TARGET_EACL,\ -- 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) -+/* EACL:CNT_TBL:ES2_CNT */ -+#define EACL_ES2_CNT(g) \ -+ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \ -+ regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4) -+ -+/* EACL:POL_CFG:POL_EACL_CFG */ -+#define EACL_POL_EACL_CFG \ -+ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \ -+ 0, 1, 4) - - #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) - #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ -@@ -4139,9 +4519,10 @@ enum sparx5_target { - #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ - FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) - --/* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ --#define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL,\ -- 0, 1, 118696, 0, 1, 8, 0, r, 2, 4) -+/* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ -+#define EACL_SEC_LOOKUP_STICKY(r) \ -+ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \ -+ r, 2, 4) - - #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) - #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ -@@ -4191,9 +4572,10 @@ enum sparx5_target { - #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ - FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) - --/* EACL:RAM_CTRL:RAM_INIT */ --#define EACL_RAM_INIT __REG(TARGET_EACL,\ -- 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) -+/* EACL:RAM_CTRL:RAM_INIT */ -+#define EACL_RAM_INIT \ -+ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \ -+ 1, 4) - - #define EACL_RAM_INIT_RAM_INIT BIT(1) - #define EACL_RAM_INIT_RAM_INIT_SET(x)\ -@@ -4207,9 +4589,10 @@ enum sparx5_target { - #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) - --/* FDMA:FDMA:FDMA_CH_ACTIVATE */ --#define FDMA_CH_ACTIVATE __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) -+/* FDMA:FDMA:FDMA_CH_ACTIVATE */ -+#define FDMA_CH_ACTIVATE \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \ -+ 4) - - #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) - #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ -@@ -4217,9 +4600,10 @@ enum sparx5_target { - #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ - FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) - --/* FDMA:FDMA:FDMA_CH_RELOAD */ --#define FDMA_CH_RELOAD __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) -+/* FDMA:FDMA:FDMA_CH_RELOAD */ -+#define FDMA_CH_RELOAD \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \ -+ 4) - - #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) - #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ -@@ -4227,9 +4611,10 @@ enum sparx5_target { - #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ - FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) - --/* FDMA:FDMA:FDMA_CH_DISABLE */ --#define FDMA_CH_DISABLE __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) -+/* FDMA:FDMA:FDMA_CH_DISABLE */ -+#define FDMA_CH_DISABLE \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \ -+ 4) - - #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) - #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ -@@ -4237,49 +4622,58 @@ enum sparx5_target { - #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ - FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) - --/* FDMA:FDMA:FDMA_DCB_LLP */ --#define FDMA_DCB_LLP(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 52, r, 8, 4) -- --/* FDMA:FDMA:FDMA_DCB_LLP1 */ --#define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 84, r, 8, 4) -- --/* FDMA:FDMA:FDMA_DCB_LLP_PREV */ --#define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 116, r, 8, 4) -- --/* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ --#define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 148, r, 8, 4) -- --/* FDMA:FDMA:FDMA_CH_CFG */ --#define FDMA_CH_CFG(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 224, r, 8, 4) -+/* FDMA:FDMA:FDMA_DCB_LLP */ -+#define FDMA_DCB_LLP(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \ -+ 4) -+ -+/* FDMA:FDMA:FDMA_DCB_LLP1 */ -+#define FDMA_DCB_LLP1(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \ -+ 4) -+ -+/* FDMA:FDMA:FDMA_DCB_LLP_PREV */ -+#define FDMA_DCB_LLP_PREV(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\ -+ 4) -+ -+/* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ -+#define FDMA_DCB_LLP_PREV1(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\ -+ 4) -+ -+/* FDMA:FDMA:FDMA_CH_CFG */ -+#define FDMA_CH_CFG(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\ -+ 4) - --#define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) -+#define FDMA_CH_CFG_CH_XTR_STATUS_MODE\ -+ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE]) - #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ -- FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) -+ spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) - #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ -- FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) -+ spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) - --#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) -+#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\ -+ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY]) - #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ -- FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) -+ spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) - #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ -- FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) -+ spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) - --#define FDMA_CH_CFG_CH_INJ_PORT BIT(5) -+#define FDMA_CH_CFG_CH_INJ_PORT\ -+ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT]) - #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ -- FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) -+ spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x) - #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ -- FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) -+ spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x) - --#define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) -+#define FDMA_CH_CFG_CH_DCB_DB_CNT\ -+ GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1) - #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ -- FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) -+ spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x) - #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ -- FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) -+ spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x) - - #define FDMA_CH_CFG_CH_MEM BIT(0) - #define FDMA_CH_CFG_CH_MEM_SET(x)\ -@@ -4287,9 +4681,10 @@ enum sparx5_target { - #define FDMA_CH_CFG_CH_MEM_GET(x)\ - FIELD_GET(FDMA_CH_CFG_CH_MEM, x) - --/* FDMA:FDMA:FDMA_CH_TRANSLATE */ --#define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 256, r, 8, 4) -+/* FDMA:FDMA:FDMA_CH_TRANSLATE */ -+#define FDMA_CH_TRANSLATE(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\ -+ 4) - - #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) - #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ -@@ -4297,9 +4692,10 @@ enum sparx5_target { - #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ - FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) - --/* FDMA:FDMA:FDMA_XTR_CFG */ --#define FDMA_XTR_CFG __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) -+/* FDMA:FDMA:FDMA_XTR_CFG */ -+#define FDMA_XTR_CFG \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\ -+ 4) - - #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) - #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ -@@ -4313,9 +4709,10 @@ enum sparx5_target { - #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ - FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) - --/* FDMA:FDMA:FDMA_PORT_CTRL */ --#define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 376, r, 2, 4) -+/* FDMA:FDMA:FDMA_PORT_CTRL */ -+#define FDMA_PORT_CTRL(r) \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\ -+ 4) - - #define FDMA_PORT_CTRL_INJ_STOP BIT(4) - #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ -@@ -4347,9 +4744,10 @@ enum sparx5_target { - #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ - FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) - --/* FDMA:FDMA:FDMA_INTR_DCB */ --#define FDMA_INTR_DCB __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) -+/* FDMA:FDMA:FDMA_INTR_DCB */ -+#define FDMA_INTR_DCB \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\ -+ 4) - - #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) - #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ -@@ -4357,9 +4755,10 @@ enum sparx5_target { - #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ - FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) - --/* FDMA:FDMA:FDMA_INTR_DCB_ENA */ --#define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) -+/* FDMA:FDMA:FDMA_INTR_DCB_ENA */ -+#define FDMA_INTR_DCB_ENA \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\ -+ 4) - - #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) - #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ -@@ -4367,9 +4766,10 @@ enum sparx5_target { - #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ - FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) - --/* FDMA:FDMA:FDMA_INTR_DB */ --#define FDMA_INTR_DB __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) -+/* FDMA:FDMA:FDMA_INTR_DB */ -+#define FDMA_INTR_DB \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\ -+ 4) - - #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) - #define FDMA_INTR_DB_INTR_DB_SET(x)\ -@@ -4377,9 +4777,10 @@ enum sparx5_target { - #define FDMA_INTR_DB_INTR_DB_GET(x)\ - FIELD_GET(FDMA_INTR_DB_INTR_DB, x) - --/* FDMA:FDMA:FDMA_INTR_DB_ENA */ --#define FDMA_INTR_DB_ENA __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) -+/* FDMA:FDMA:FDMA_INTR_DB_ENA */ -+#define FDMA_INTR_DB_ENA \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\ -+ 4) - - #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) - #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ -@@ -4387,9 +4788,10 @@ enum sparx5_target { - #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ - FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) - --/* FDMA:FDMA:FDMA_INTR_ERR */ --#define FDMA_INTR_ERR __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) -+/* FDMA:FDMA:FDMA_INTR_ERR */ -+#define FDMA_INTR_ERR \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\ -+ 4) - - #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) - #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ -@@ -4403,9 +4805,10 @@ enum sparx5_target { - #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ - FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) - --/* FDMA:FDMA:FDMA_ERRORS */ --#define FDMA_ERRORS __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) -+/* FDMA:FDMA:FDMA_ERRORS */ -+#define FDMA_ERRORS \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\ -+ 4) - - #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) - #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ -@@ -4455,9 +4858,10 @@ enum sparx5_target { - #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ - FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) - --/* FDMA:FDMA:FDMA_ERRORS_2 */ --#define FDMA_ERRORS_2 __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) -+/* FDMA:FDMA:FDMA_ERRORS_2 */ -+#define FDMA_ERRORS_2 \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\ -+ 4) - - #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) - #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ -@@ -4465,9 +4869,10 @@ enum sparx5_target { - #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ - FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) - --/* FDMA:FDMA:FDMA_CTRL */ --#define FDMA_CTRL __REG(TARGET_FDMA,\ -- 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) -+/* FDMA:FDMA:FDMA_CTRL */ -+#define FDMA_CTRL \ -+ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\ -+ 4) - - #define FDMA_CTRL_NRESET BIT(0) - #define FDMA_CTRL_NRESET_SET(x)\ -@@ -4475,9 +4880,10 @@ enum sparx5_target { - #define FDMA_CTRL_NRESET_GET(x)\ - FIELD_GET(FDMA_CTRL_NRESET, x) - --/* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ --#define GCB_CHIP_ID __REG(TARGET_GCB,\ -- 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) -+/* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ -+#define GCB_CHIP_ID \ -+ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \ -+ 1, 4) - - #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) - #define GCB_CHIP_ID_REV_ID_SET(x)\ -@@ -4503,10 +4909,12 @@ enum sparx5_target { - #define GCB_CHIP_ID_ONE_GET(x)\ - FIELD_GET(GCB_CHIP_ID_ONE, x) - --/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ --#define GCB_SOFT_RST __REG(TARGET_GCB,\ -- 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) -+/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ -+#define GCB_SOFT_RST \ -+ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ -+ regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4) - -+/* SPARX5 ONLY */ - #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) - #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ - FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) -@@ -4525,9 +4933,11 @@ enum sparx5_target { - #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ - FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) - --/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ --#define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB,\ -- 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ -+#define GCB_HW_SGPIO_SD_CFG \ -+ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \ -+ 1, 4) - - #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) - #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ -@@ -4541,19 +4951,23 @@ enum sparx5_target { - #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ - FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) - --/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ --#define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB,\ -- 0, 1, 0, 0, 1, 424, 24, r, 65, 4) -+/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ -+#define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) \ -+ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ -+ regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r, \ -+ regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4) - --#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) -+#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\ -+ GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0) - #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ -- FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) -+ spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) - #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ -- FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) -+ spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) - --/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ --#define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ -- 0, 1, 876, g, 3, 280, 20, 0, 1, 4) -+/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ -+#define GCB_SIO_CLOCK(g) \ -+ __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \ -+ regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4) - - #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) - #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ -@@ -4567,9 +4981,10 @@ enum sparx5_target { - #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ - FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) - --/* HSCH:HSCH_CFG:CIR_CFG */ --#define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ -- 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) -+/* HSCH:HSCH_CFG:CIR_CFG */ -+#define HSCH_CIR_CFG(g) \ -+ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \ -+ 1, 4) - - #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) - #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ -@@ -4583,9 +4998,10 @@ enum sparx5_target { - #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ - FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) - --/* HSCH:HSCH_CFG:EIR_CFG */ --#define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ -- 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) -+/* HSCH:HSCH_CFG:EIR_CFG */ -+#define HSCH_EIR_CFG(g) \ -+ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \ -+ 1, 4) - - #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) - #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ -@@ -4599,15 +5015,17 @@ enum sparx5_target { - #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ - FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) - --/* HSCH:HSCH_CFG:SE_CFG */ --#define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ -- 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) -+/* HSCH:HSCH_CFG:SE_CFG */ -+#define HSCH_SE_CFG(g) \ -+ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \ -+ 1, 4) - --#define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) -+#define HSCH_SE_CFG_SE_DWRR_CNT\ -+ GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6) - #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ -- FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) -+ spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x) - #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ -- FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) -+ spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x) - - #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) - #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ -@@ -4633,19 +5051,22 @@ enum sparx5_target { - #define HSCH_SE_CFG_SE_STOP_GET(x)\ - FIELD_GET(HSCH_SE_CFG_SE_STOP, x) - --/* HSCH:HSCH_CFG:SE_CONNECT */ --#define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ -- 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) -+/* HSCH:HSCH_CFG:SE_CONNECT */ -+#define HSCH_SE_CONNECT(g) \ -+ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\ -+ 1, 4) - --#define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) -+#define HSCH_SE_CONNECT_SE_LEAK_LINK\ -+ GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0) - #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ -- FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) -+ spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x) - #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ -- FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) -+ spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x) - --/* HSCH:HSCH_CFG:SE_DLB_SENSE */ --#define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ -- 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) -+/* HSCH:HSCH_CFG:SE_DLB_SENSE */ -+#define HSCH_SE_DLB_SENSE(g) \ -+ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\ -+ 1, 4) - - #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) - #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ -@@ -4653,11 +5074,12 @@ enum sparx5_target { - #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ - FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) - --#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) -+#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\ -+ GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3) - #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ -- FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) -+ spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) - #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ -- FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) -+ spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) - - #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) - #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ -@@ -4677,9 +5099,10 @@ enum sparx5_target { - #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ - FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) - --/* HSCH:HSCH_DWRR:DWRR_ENTRY */ --#define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ -- 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) -+/* HSCH:HSCH_DWRR:DWRR_ENTRY */ -+#define HSCH_DWRR_ENTRY(g) \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \ -+ regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4) - - #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) - #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ -@@ -4693,15 +5116,17 @@ enum sparx5_target { - #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ - FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) - --/* HSCH:HSCH_MISC:HSCH_CFG_CFG */ --#define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH,\ -- 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) -+/* HSCH:HSCH_MISC:HSCH_CFG_CFG */ -+#define HSCH_HSCH_CFG_CFG \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ -+ 284, 0, 1, 4) - --#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) -+#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\ -+ GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14) - #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ -- FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) -+ spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) - #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ -- FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) -+ spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) - - #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) - #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ -@@ -4715,9 +5140,11 @@ enum sparx5_target { - #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ - FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) - --/* HSCH:HSCH_MISC:SYS_CLK_PER */ --#define HSCH_SYS_CLK_PER __REG(TARGET_HSCH,\ -- 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* HSCH:HSCH_MISC:SYS_CLK_PER */ -+#define HSCH_SYS_CLK_PER \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ -+ 640, 0, 1, 4) - - #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) - #define HSCH_SYS_CLK_PER_100PS_SET(x)\ -@@ -4725,9 +5152,10 @@ enum sparx5_target { - #define HSCH_SYS_CLK_PER_100PS_GET(x)\ - FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) - --/* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ --#define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ -- 0, 1, 161664, g, 4, 32, 0, r, 4, 4) -+/* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ -+#define HSCH_HSCH_TIMER_CFG(g, r) \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ -+ 32, 0, r, 4, 4) - - #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) - #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ -@@ -4735,15 +5163,17 @@ enum sparx5_target { - #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ - FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) - --/* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ --#define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ -- 0, 1, 161664, g, 4, 32, 16, r, 4, 4) -+/* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ -+#define HSCH_HSCH_LEAK_CFG(g, r) \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ -+ 32, 16, r, 4, 4) - --#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) -+#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\ -+ GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1) - #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ -- FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) -+ spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) - #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ -- FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) -+ spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) - - #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) - #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ -@@ -4751,9 +5181,10 @@ enum sparx5_target { - #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ - FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) - --/* HSCH:SYSTEM:FLUSH_CTRL */ --#define HSCH_FLUSH_CTRL __REG(TARGET_HSCH,\ -- 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) -+/* HSCH:SYSTEM:FLUSH_CTRL */ -+#define HSCH_FLUSH_CTRL \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \ -+ 1, 4) - - #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) - #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ -@@ -4773,11 +5204,12 @@ enum sparx5_target { - #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ - FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) - --#define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) -+#define HSCH_FLUSH_CTRL_FLUSH_PORT\ -+ GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18) - #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ -- FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) -+ spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x) - #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ -- FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) -+ spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x) - - #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) - #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ -@@ -4791,15 +5223,17 @@ enum sparx5_target { - #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ - FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) - --#define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) -+#define HSCH_FLUSH_CTRL_FLUSH_HIER\ -+ GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0) - #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ -- FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) -+ spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x) - #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ -- FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) -+ spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x) - --/* HSCH:SYSTEM:PORT_MODE */ --#define HSCH_PORT_MODE(r) __REG(TARGET_HSCH,\ -- 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) -+/* HSCH:SYSTEM:PORT_MODE */ -+#define HSCH_PORT_MODE(r) \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \ -+ regs->rcnt[RC_HSCH_PORT_MODE], 4) - - #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) - #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ -@@ -4831,9 +5265,10 @@ enum sparx5_target { - #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ - FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) - --/* HSCH:SYSTEM:OUTB_SHARE_ENA */ --#define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH,\ -- 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) -+/* HSCH:SYSTEM:OUTB_SHARE_ENA */ -+#define HSCH_OUTB_SHARE_ENA(r) \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \ -+ r, 5, 4) - - #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) - #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ -@@ -4841,9 +5276,10 @@ enum sparx5_target { - #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ - FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) - --/* HSCH:MMGT:RESET_CFG */ --#define HSCH_RESET_CFG __REG(TARGET_HSCH,\ -- 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) -+/* HSCH:MMGT:RESET_CFG */ -+#define HSCH_RESET_CFG \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \ -+ 4) - - #define HSCH_RESET_CFG_CORE_ENA BIT(0) - #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ -@@ -4851,9 +5287,10 @@ enum sparx5_target { - #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ - FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) - --/* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ --#define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH,\ -- 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) -+/* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ -+#define HSCH_TAS_STATEMACHINE_CFG \ -+ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \ -+ regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4) - - #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) - #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ -@@ -4861,9 +5298,9 @@ enum sparx5_target { - #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ - FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) - --/* LRN:COMMON:COMMON_ACCESS_CTRL */ --#define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) -+/* LRN:COMMON:COMMON_ACCESS_CTRL */ -+#define LRN_COMMON_ACCESS_CTRL \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) - - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ -@@ -4877,11 +5314,12 @@ enum sparx5_target { - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ - FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) - --#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) -+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\ -+ GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5) - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ -- FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) -+ spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ -- FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) -+ spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) - - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ -@@ -4895,9 +5333,9 @@ enum sparx5_target { - #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ - FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) - --/* LRN:COMMON:MAC_ACCESS_CFG_0 */ --#define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) -+/* LRN:COMMON:MAC_ACCESS_CFG_0 */ -+#define LRN_MAC_ACCESS_CFG_0 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) - - #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) - #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ -@@ -4911,13 +5349,13 @@ enum sparx5_target { - #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ - FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) - --/* LRN:COMMON:MAC_ACCESS_CFG_1 */ --#define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) -- --/* LRN:COMMON:MAC_ACCESS_CFG_2 */ --#define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) -+/* LRN:COMMON:MAC_ACCESS_CFG_1 */ -+#define LRN_MAC_ACCESS_CFG_1 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) -+ -+/* LRN:COMMON:MAC_ACCESS_CFG_2 */ -+#define LRN_MAC_ACCESS_CFG_2 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) - - #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) - #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ -@@ -4991,19 +5429,20 @@ enum sparx5_target { - #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ - FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) - --/* LRN:COMMON:MAC_ACCESS_CFG_3 */ --#define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) -+/* LRN:COMMON:MAC_ACCESS_CFG_3 */ -+#define LRN_MAC_ACCESS_CFG_3 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) - --#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) -+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\ -+ GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0) - #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ -- FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) -+ spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) - #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ -- FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) -+ spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) - --/* LRN:COMMON:SCAN_NEXT_CFG */ --#define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) -+/* LRN:COMMON:SCAN_NEXT_CFG */ -+#define LRN_SCAN_NEXT_CFG \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) - - #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) - #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ -@@ -5095,9 +5534,9 @@ enum sparx5_target { - #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ - FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) - --/* LRN:COMMON:SCAN_NEXT_CFG_1 */ --#define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) -+/* LRN:COMMON:SCAN_NEXT_CFG_1 */ -+#define LRN_SCAN_NEXT_CFG_1 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) - - #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) - #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ -@@ -5111,9 +5550,9 @@ enum sparx5_target { - #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ - FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) - --/* LRN:COMMON:AUTOAGE_CFG */ --#define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 36, r, 4, 4) -+/* LRN:COMMON:AUTOAGE_CFG */ -+#define LRN_AUTOAGE_CFG(r) \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) - - #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) - #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ -@@ -5127,9 +5566,9 @@ enum sparx5_target { - #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ - FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) - --/* LRN:COMMON:AUTOAGE_CFG_1 */ --#define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) -+/* LRN:COMMON:AUTOAGE_CFG_1 */ -+#define LRN_AUTOAGE_CFG_1 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) - - #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) - #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ -@@ -5173,15 +5612,16 @@ enum sparx5_target { - #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ - FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) - --/* LRN:COMMON:AUTOAGE_CFG_2 */ --#define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN,\ -- 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) -+/* LRN:COMMON:AUTOAGE_CFG_2 */ -+#define LRN_AUTOAGE_CFG_2 \ -+ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) - --#define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) -+#define LRN_AUTOAGE_CFG_2_NEXT_ROW\ -+ GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4) - #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ -- FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) -+ spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) - #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ -- FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) -+ spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) - - #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) - #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ -@@ -5189,9 +5629,10 @@ enum sparx5_target { - #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ - FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) - --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ --#define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ -+#define PCEP_RCTRL_2_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) - - #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) - #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ -@@ -5253,9 +5694,10 @@ enum sparx5_target { - #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ - FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) - --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_LWR_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) - - #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) - #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ -@@ -5269,13 +5711,15 @@ enum sparx5_target { - #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ - FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) - --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) -- --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_UPR_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_LIM_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) - - #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) - #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ -@@ -5289,17 +5733,20 @@ enum sparx5_target { - #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ - FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) - --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) -- --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) -- --/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ --#define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP,\ -- 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_LWR_TGT_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_UPR_TGT_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ -+#define PCEP_ADDR_UPR_LIM_OUT_0 \ -+ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) - - #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) - #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ -@@ -5313,9 +5760,10 @@ enum sparx5_target { - #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ - FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ --#define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR,\ -- t, 12, 0, 0, 1, 56, 0, 0, 1, 4) -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ -+#define PCS10G_BR_PCS_CFG(t) \ -+ __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \ -+ 0, 1, 4) - - #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) - #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ -@@ -5389,9 +5837,10 @@ enum sparx5_target { - #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ - FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ --#define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR,\ -- t, 12, 0, 0, 1, 56, 4, 0, 1, 4) -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ -+#define PCS10G_BR_PCS_SD_CFG(t) \ -+ __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \ -+ 0, 1, 4) - - #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) - #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ -@@ -5411,9 +5860,10 @@ enum sparx5_target { - #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ - FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ --#define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR,\ -- t, 8, 0, 0, 1, 56, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ -+#define PCS25G_BR_PCS_CFG(t) \ -+ __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) - - #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) - #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ -@@ -5487,9 +5937,10 @@ enum sparx5_target { - #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ - FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ --#define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR,\ -- t, 8, 0, 0, 1, 56, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ -+#define PCS25G_BR_PCS_SD_CFG(t) \ -+ __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) - - #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) - #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ -@@ -5509,9 +5960,10 @@ enum sparx5_target { - #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ - FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ --#define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR,\ -- t, 13, 0, 0, 1, 56, 0, 0, 1, 4) -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ -+#define PCS5G_BR_PCS_CFG(t) \ -+ __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \ -+ 1, 4) - - #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) - #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ -@@ -5585,9 +6037,10 @@ enum sparx5_target { - #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ - FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) - --/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ --#define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR,\ -- t, 13, 0, 0, 1, 56, 4, 0, 1, 4) -+/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ -+#define PCS5G_BR_PCS_SD_CFG(t) \ -+ __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \ -+ 1, 4) - - #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) - #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ -@@ -5607,58 +6060,67 @@ enum sparx5_target { - #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ - FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) - --/* PORT_CONF:HW_CFG:DEV5G_MODES */ --#define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF,\ -- 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) -+/* PORT_CONF:HW_CFG:DEV5G_MODES */ -+#define PORT_CONF_DEV5G_MODES \ -+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) - #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) - #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) - #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) - #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) - #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) - #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) - #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) - #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) - #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) -@@ -5671,27 +6133,30 @@ enum sparx5_target { - #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) - #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) - #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) - #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) - #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) - --/* PORT_CONF:HW_CFG:DEV10G_MODES */ --#define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF,\ -- 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) -+/* PORT_CONF:HW_CFG:DEV10G_MODES */ -+#define PORT_CONF_DEV10G_MODES \ -+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) - - #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) - #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ -@@ -5699,75 +6164,87 @@ enum sparx5_target { - #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) - #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) - #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) - #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) - #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) - #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) - #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) - #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) - #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) - #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) - #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) - #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ - FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) - #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) - --/* PORT_CONF:HW_CFG:DEV25G_MODES */ --#define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF,\ -- 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PORT_CONF:HW_CFG:DEV25G_MODES */ -+#define PORT_CONF_DEV25G_MODES \ -+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) - - #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) - #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ -@@ -5817,9 +6294,9 @@ enum sparx5_target { - #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ - FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) - --/* PORT_CONF:HW_CFG:QSGMII_ENA */ --#define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF,\ -- 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) -+/* PORT_CONF:HW_CFG:QSGMII_ENA */ -+#define PORT_CONF_QSGMII_ENA \ -+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) - - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ -@@ -5857,45 +6334,52 @@ enum sparx5_target { - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) - -+/* SPARX5 ONLY */ - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ - FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) - #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ - FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) - --/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ --#define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ -- 0, 1, 72, g, 6, 8, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ -+#define PORT_CONF_USGMII_CFG(g) \ -+ __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) - - #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) - #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ -@@ -5939,39 +6423,46 @@ enum sparx5_target { - #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ - FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) - --/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ --#define PTP_PTP_PIN_INTR __REG(TARGET_PTP,\ -- 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) -+/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ -+#define PTP_PTP_PIN_INTR \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\ -+ 4) - --#define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) -+#define PTP_PTP_PIN_INTR_INTR_PTP\ -+ GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0) - #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) -+ spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x) - #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) -+ spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x) - --/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ --#define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP,\ -- 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) -+/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ -+#define PTP_PTP_PIN_INTR_ENA \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\ -+ 4) - --#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) -+#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\ -+ GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0) - #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) -+ spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) - #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) -+ spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) - --/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ --#define PTP_PTP_INTR_IDENT __REG(TARGET_PTP,\ -- 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) -+/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ -+#define PTP_PTP_INTR_IDENT \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\ -+ 4) - --#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) -+#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\ -+ GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0) - #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ -- FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) -+ spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) - #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ -- FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) -+ spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) - --/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ --#define PTP_PTP_DOM_CFG __REG(TARGET_PTP,\ -- 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) -+/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ -+#define PTP_PTP_DOM_CFG \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \ -+ 1, 4) - - #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) - #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ -@@ -5997,13 +6488,15 @@ enum sparx5_target { - #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ - FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) - --/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ --#define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 0, r, 2, 4) -- --/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ --#define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 8, 0, 1, 4) -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ -+#define PTP_CLK_PER_CFG(g, r) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 0, r, 2, 4) -+ -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ -+#define PTP_PTP_CUR_NSEC(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 8, 0, 1, 4) - - #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) - #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ -@@ -6011,9 +6504,10 @@ enum sparx5_target { - #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ - FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) - --/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ --#define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 12, 0, 1, 4) -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ -+#define PTP_PTP_CUR_NSEC_FRAC(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 12, 0, 1, 4) - - #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) - #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ -@@ -6021,13 +6515,15 @@ enum sparx5_target { - #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ - FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) - --/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ --#define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 16, 0, 1, 4) -- --/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ --#define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 20, 0, 1, 4) -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ -+#define PTP_PTP_CUR_SEC_LSB(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 16, 0, 1, 4) -+ -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ -+#define PTP_PTP_CUR_SEC_MSB(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 20, 0, 1, 4) - - #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) - #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ -@@ -6035,37 +6531,43 @@ enum sparx5_target { - #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ - FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) - --/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ --#define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ -- 0, 1, 336, g, 3, 28, 24, 0, 1, 4) -- --/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ --#define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 0, 0, 1, 4) -+/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ -+#define PTP_NTP_CUR_NSEC(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ -+ 24, 0, 1, 4) -+ -+/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ -+#define PTP_PTP_PIN_CFG(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\ -+ 4) - --#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) -+#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\ -+ GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION]) - #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) -+ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) - #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) -+ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) - --#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) -+#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\ -+ GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC]) - #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) -+ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) - #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) -+ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) - --#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) -+#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\ -+ BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL]) - #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) -+ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) - #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) -+ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) - --#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) -+#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\ -+ GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21) - #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ -- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) -+ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) - #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ -- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) -+ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) - - #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) - #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ -@@ -6097,9 +6599,10 @@ enum sparx5_target { - #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ - FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) - --/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ --#define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 4, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ -+#define PTP_PTP_TOD_SEC_MSB(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\ -+ 4) - - #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) - #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ -@@ -6107,13 +6610,15 @@ enum sparx5_target { - #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ - FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) - --/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ --#define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 8, 0, 1, 4) -- --/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ --#define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 12, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ -+#define PTP_PTP_TOD_SEC_LSB(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\ -+ 4) -+ -+/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ -+#define PTP_PTP_TOD_NSEC(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \ -+ 1, 4) - - #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) - #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ -@@ -6121,9 +6626,10 @@ enum sparx5_target { - #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ - FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) - --/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ --#define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 16, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ -+#define PTP_PTP_TOD_NSEC_FRAC(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \ -+ 1, 4) - - #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) - #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ -@@ -6131,13 +6637,15 @@ enum sparx5_target { - #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ - FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) - --/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ --#define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 20, 0, 1, 4) -- --/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ --#define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 24, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ -+#define PTP_NTP_NSEC(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \ -+ 1, 4) -+ -+/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ -+#define PTP_PIN_WF_HIGH_PERIOD(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \ -+ 1, 4) - - #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) - #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ -@@ -6145,9 +6653,10 @@ enum sparx5_target { - #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ - FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) - --/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ --#define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 28, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ -+#define PTP_PIN_WF_LOW_PERIOD(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \ -+ 1, 4) - - #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) - #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ -@@ -6155,9 +6664,10 @@ enum sparx5_target { - #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ - FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) - --/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ --#define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ -- 0, 1, 0, g, 5, 64, 32, 0, 1, 4) -+/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ -+#define PTP_PIN_IOBOUNCH_DELAY(g) \ -+ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \ -+ 1, 4) - - #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) - #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ -@@ -6171,22 +6681,27 @@ enum sparx5_target { - #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ - FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) - --/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ --#define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ -- 0, 1, 420, g, 5, 8, 0, 0, 1, 4) -+/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ -+#define PTP_PHAD_CTRL(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ -+ regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ -+ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) - --#define PTP_PHAD_CTRL_PHAD_ENA BIT(7) -+#define PTP_PHAD_CTRL_PHAD_ENA\ -+ BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA]) - #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ -- FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) -+ spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x) - #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ -- FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) -+ spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x) - --#define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) -+#define PTP_PHAD_CTRL_PHAD_FAILED\ -+ BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED]) - #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ -- FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) -+ spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x) - #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ -- FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) -+ spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x) - -+/* SPARX5 ONLY */ - #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) - #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ - FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) -@@ -6199,13 +6714,16 @@ enum sparx5_target { - #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ - FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) - --/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ --#define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ -- 0, 1, 420, g, 5, 8, 4, 0, 1, 4) -- --/* QFWD:SYSTEM:SWITCH_PORT_MODE */ --#define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD,\ -- 0, 1, 0, 0, 1, 340, 0, r, 70, 4) -+/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ -+#define PTP_PHAD_CYC_STAT(g) \ -+ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ -+ regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ -+ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) -+ -+/* QFWD:SYSTEM:SWITCH_PORT_MODE */ -+#define QFWD_SWITCH_PORT_MODE(r) \ -+ __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ -+ regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4) - - #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) - #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ -@@ -6261,49 +6779,53 @@ enum sparx5_target { - #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ - FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) - --/* QFWD:SYSTEM:FRAME_COPY_CFG */ --#define QFWD_FRAME_COPY_CFG(r)\ -+/* QFWD:SYSTEM:FRAME_COPY_CFG */ -+#define QFWD_FRAME_COPY_CFG(r) \ - __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) - --#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL GENMASK(12, 6) -+#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\ -+ GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6) - #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ -- FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) -+ spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) - #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ -- FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) -+ spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) - --/* QRES:RES_CTRL:RES_CFG */ --#define QRES_RES_CFG(g) __REG(TARGET_QRES,\ -- 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) -+/* QRES:RES_CTRL:RES_CFG */ -+#define QRES_RES_CFG(g) \ -+ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) - --#define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) -+#define QRES_RES_CFG_WM_HIGH\ -+ GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0) - #define QRES_RES_CFG_WM_HIGH_SET(x)\ -- FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) -+ spx5_field_prep(QRES_RES_CFG_WM_HIGH, x) - #define QRES_RES_CFG_WM_HIGH_GET(x)\ -- FIELD_GET(QRES_RES_CFG_WM_HIGH, x) -+ spx5_field_get(QRES_RES_CFG_WM_HIGH, x) - --/* QRES:RES_CTRL:RES_STAT */ --#define QRES_RES_STAT(g) __REG(TARGET_QRES,\ -- 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) -+/* QRES:RES_CTRL:RES_STAT */ -+#define QRES_RES_STAT(g) \ -+ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) - --#define QRES_RES_STAT_MAXUSE GENMASK(20, 0) -+#define QRES_RES_STAT_MAXUSE\ -+ GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0) - #define QRES_RES_STAT_MAXUSE_SET(x)\ -- FIELD_PREP(QRES_RES_STAT_MAXUSE, x) -+ spx5_field_prep(QRES_RES_STAT_MAXUSE, x) - #define QRES_RES_STAT_MAXUSE_GET(x)\ -- FIELD_GET(QRES_RES_STAT_MAXUSE, x) -+ spx5_field_get(QRES_RES_STAT_MAXUSE, x) - --/* QRES:RES_CTRL:RES_STAT_CUR */ --#define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ -- 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) -+/* QRES:RES_CTRL:RES_STAT_CUR */ -+#define QRES_RES_STAT_CUR(g) \ -+ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) - --#define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) -+#define QRES_RES_STAT_CUR_INUSE\ -+ GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0) - #define QRES_RES_STAT_CUR_INUSE_SET(x)\ -- FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) -+ spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x) - #define QRES_RES_STAT_CUR_INUSE_GET(x)\ -- FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) -+ spx5_field_get(QRES_RES_STAT_CUR_INUSE, x) - --/* DEVCPU_QS:XTR:XTR_GRP_CFG */ --#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\ -- 0, 1, 0, 0, 1, 36, 0, r, 2, 4) -+/* DEVCPU_QS:XTR:XTR_GRP_CFG */ -+#define QS_XTR_GRP_CFG(r) \ -+ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) - - #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) - #define QS_XTR_GRP_CFG_MODE_SET(x)\ -@@ -6323,13 +6845,13 @@ enum sparx5_target { - #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ - FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) - --/* DEVCPU_QS:XTR:XTR_RD */ --#define QS_XTR_RD(r) __REG(TARGET_QS,\ -- 0, 1, 0, 0, 1, 36, 8, r, 2, 4) -- --/* DEVCPU_QS:XTR:XTR_FLUSH */ --#define QS_XTR_FLUSH __REG(TARGET_QS,\ -- 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) -+/* DEVCPU_QS:XTR:XTR_RD */ -+#define QS_XTR_RD(r) \ -+ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) -+ -+/* DEVCPU_QS:XTR:XTR_FLUSH */ -+#define QS_XTR_FLUSH \ -+ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) - - #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) - #define QS_XTR_FLUSH_FLUSH_SET(x)\ -@@ -6337,9 +6859,9 @@ enum sparx5_target { - #define QS_XTR_FLUSH_FLUSH_GET(x)\ - FIELD_GET(QS_XTR_FLUSH_FLUSH, x) - --/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ --#define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\ -- 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) -+/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ -+#define QS_XTR_DATA_PRESENT \ -+ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) - - #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) - #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ -@@ -6347,9 +6869,9 @@ enum sparx5_target { - #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ - FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) - --/* DEVCPU_QS:INJ:INJ_GRP_CFG */ --#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\ -- 0, 1, 36, 0, 1, 40, 0, r, 2, 4) -+/* DEVCPU_QS:INJ:INJ_GRP_CFG */ -+#define QS_INJ_GRP_CFG(r) \ -+ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) - - #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) - #define QS_INJ_GRP_CFG_MODE_SET(x)\ -@@ -6363,13 +6885,13 @@ enum sparx5_target { - #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ - FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) - --/* DEVCPU_QS:INJ:INJ_WR */ --#define QS_INJ_WR(r) __REG(TARGET_QS,\ -- 0, 1, 36, 0, 1, 40, 8, r, 2, 4) -- --/* DEVCPU_QS:INJ:INJ_CTRL */ --#define QS_INJ_CTRL(r) __REG(TARGET_QS,\ -- 0, 1, 36, 0, 1, 40, 16, r, 2, 4) -+/* DEVCPU_QS:INJ:INJ_WR */ -+#define QS_INJ_WR(r) \ -+ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) -+ -+/* DEVCPU_QS:INJ:INJ_CTRL */ -+#define QS_INJ_CTRL(r) \ -+ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) - - #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) - #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ -@@ -6401,9 +6923,9 @@ enum sparx5_target { - #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ - FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) - --/* DEVCPU_QS:INJ:INJ_STATUS */ --#define QS_INJ_STATUS __REG(TARGET_QS,\ -- 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) -+/* DEVCPU_QS:INJ:INJ_STATUS */ -+#define QS_INJ_STATUS \ -+ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) - - #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) - #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ -@@ -6423,21 +6945,24 @@ enum sparx5_target { - #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ - FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) - --/* QSYS:PAUSE_CFG:PAUSE_CFG */ --#define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\ -- 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) -+/* QSYS:PAUSE_CFG:PAUSE_CFG */ -+#define QSYS_PAUSE_CFG(r) \ -+ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \ -+ r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4) - --#define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) -+#define QSYS_PAUSE_CFG_PAUSE_START\ -+ GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14) - #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ -- FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) -+ spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x) - #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ -- FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) -+ spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x) - --#define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) -+#define QSYS_PAUSE_CFG_PAUSE_STOP\ -+ GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2) - #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ -- FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) -+ spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x) - #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ -- FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) -+ spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x) - - #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) - #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ -@@ -6451,19 +6976,22 @@ enum sparx5_target { - #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ - FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) - --/* QSYS:PAUSE_CFG:ATOP */ --#define QSYS_ATOP(r) __REG(TARGET_QSYS,\ -- 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) -+/* QSYS:PAUSE_CFG:ATOP */ -+#define QSYS_ATOP(r) \ -+ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ -+ 284, r, regs->rcnt[RC_QSYS_ATOP], 4) - --#define QSYS_ATOP_ATOP GENMASK(11, 0) -+#define QSYS_ATOP_ATOP\ -+ GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0) - #define QSYS_ATOP_ATOP_SET(x)\ -- FIELD_PREP(QSYS_ATOP_ATOP, x) -+ spx5_field_prep(QSYS_ATOP_ATOP, x) - #define QSYS_ATOP_ATOP_GET(x)\ -- FIELD_GET(QSYS_ATOP_ATOP, x) -+ spx5_field_get(QSYS_ATOP_ATOP, x) - --/* QSYS:PAUSE_CFG:FWD_PRESSURE */ --#define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\ -- 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) -+/* QSYS:PAUSE_CFG:FWD_PRESSURE */ -+#define QSYS_FWD_PRESSURE(r) \ -+ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ -+ 564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4) - - #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) - #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ -@@ -6477,19 +7005,22 @@ enum sparx5_target { - #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ - FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) - --/* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ --#define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\ -- 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) -+/* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ -+#define QSYS_ATOP_TOT_CFG \ -+ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ -+ 844, 0, 1, 4) - --#define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) -+#define QSYS_ATOP_TOT_CFG_ATOP_TOT\ -+ GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0) - #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ -- FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) -+ spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) - #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ -- FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) -+ spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) - --/* QSYS:CALCFG:CAL_AUTO */ --#define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\ -- 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) -+/* QSYS:CALCFG:CAL_AUTO */ -+#define QSYS_CAL_AUTO(r) \ -+ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \ -+ regs->rcnt[RC_QSYS_CAL_AUTO], 4) - - #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) - #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ -@@ -6497,9 +7028,10 @@ enum sparx5_target { - #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ - FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) - --/* QSYS:CALCFG:CAL_CTRL */ --#define QSYS_CAL_CTRL __REG(TARGET_QSYS,\ -- 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) -+/* QSYS:CALCFG:CAL_CTRL */ -+#define QSYS_CAL_CTRL \ -+ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \ -+ 1, 4) - - #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) - #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ -@@ -6519,9 +7051,10 @@ enum sparx5_target { - #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ - FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) - --/* QSYS:RAM_CTRL:RAM_INIT */ --#define QSYS_RAM_INIT __REG(TARGET_QSYS,\ -- 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) -+/* QSYS:RAM_CTRL:RAM_INIT */ -+#define QSYS_RAM_INIT \ -+ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \ -+ 1, 4) - - #define QSYS_RAM_INIT_RAM_INIT BIT(1) - #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ -@@ -6535,9 +7068,10 @@ enum sparx5_target { - #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) - --/* REW:COMMON:OWN_UPSID */ --#define REW_OWN_UPSID(r) __REG(TARGET_REW,\ -- 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) -+/* REW:COMMON:OWN_UPSID */ -+#define REW_OWN_UPSID(r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \ -+ regs->rcnt[RC_REW_OWN_UPSID], 4) - - #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) - #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ -@@ -6545,15 +7079,17 @@ enum sparx5_target { - #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ - FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) - --/* REW:COMMON:RTAG_ETAG_CTRL */ --#define REW_RTAG_ETAG_CTRL(r) __REG(TARGET_REW,\ -- 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4) -+/* REW:COMMON:RTAG_ETAG_CTRL */ -+#define REW_RTAG_ETAG_CTRL(r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\ -+ regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4) - --#define REW_RTAG_ETAG_CTRL_IPE_TBL GENMASK(9, 3) -+#define REW_RTAG_ETAG_CTRL_IPE_TBL\ -+ GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3) - #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ -- FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x) -+ spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x) - #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ -- FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x) -+ spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x) - - #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) - #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ -@@ -6567,9 +7103,10 @@ enum sparx5_target { - #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ - FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) - --/* REW:COMMON:ES0_CTRL */ --#define REW_ES0_CTRL __REG(TARGET_REW,\ -- 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4) -+/* REW:COMMON:ES0_CTRL */ -+#define REW_ES0_CTRL \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\ -+ 1, 4) - - #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) - #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ -@@ -6607,9 +7144,10 @@ enum sparx5_target { - #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ - FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) - --/* REW:PORT:PORT_VLAN_CFG */ --#define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) -+/* REW:PORT:PORT_VLAN_CFG */ -+#define REW_PORT_VLAN_CFG(g) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4) - - #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) - #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ -@@ -6629,9 +7167,10 @@ enum sparx5_target { - #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ - FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) - --/* REW:PORT:PCP_MAP_DE0 */ --#define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 4, r, 8, 4) -+/* REW:PORT:PCP_MAP_DE0 */ -+#define REW_PCP_MAP_DE0(g, r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4) - - #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) - #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ -@@ -6639,9 +7178,10 @@ enum sparx5_target { - #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ - FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) - --/* REW:PORT:PCP_MAP_DE1 */ --#define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 36, r, 8, 4) -+/* REW:PORT:PCP_MAP_DE1 */ -+#define REW_PCP_MAP_DE1(g, r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4) - - #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) - #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ -@@ -6649,9 +7189,10 @@ enum sparx5_target { - #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ - FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) - --/* REW:PORT:DEI_MAP_DE0 */ --#define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 68, r, 8, 4) -+/* REW:PORT:DEI_MAP_DE0 */ -+#define REW_DEI_MAP_DE0(g, r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4) - - #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) - #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ -@@ -6659,9 +7200,10 @@ enum sparx5_target { - #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ - FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) - --/* REW:PORT:DEI_MAP_DE1 */ --#define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 100, r, 8, 4) -+/* REW:PORT:DEI_MAP_DE1 */ -+#define REW_DEI_MAP_DE1(g, r) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4) - - #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) - #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ -@@ -6669,9 +7211,10 @@ enum sparx5_target { - #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ - FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) - --/* REW:PORT:TAG_CTRL */ --#define REW_TAG_CTRL(g) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) -+/* REW:PORT:TAG_CTRL */ -+#define REW_TAG_CTRL(g) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4) - - #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) - #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ -@@ -6709,9 +7252,10 @@ enum sparx5_target { - #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ - FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) - --/* REW:PORT:DSCP_MAP */ --#define REW_DSCP_MAP(g) __REG(TARGET_REW,\ -- 0, 1, 360448, g, 70, 256, 136, 0, 1, 4) -+/* REW:PORT:DSCP_MAP */ -+#define REW_DSCP_MAP(g) \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ -+ regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4) - - #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) - #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ -@@ -6725,9 +7269,10 @@ enum sparx5_target { - #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ - FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) - --/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ --#define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ -+#define REW_PTP_TWOSTEP_CTRL \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) - - #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) - #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ -@@ -6765,9 +7310,10 @@ enum sparx5_target { - #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ - FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) - --/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ --#define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ -+#define REW_PTP_TWOSTEP_STAMP \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) - - #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) - #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ -@@ -6775,9 +7321,10 @@ enum sparx5_target { - #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ - FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) - --/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ --#define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ -+#define REW_PTP_TWOSTEP_STAMP_SUBNS \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) - - #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) - #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ -@@ -6785,17 +7332,20 @@ enum sparx5_target { - #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ - FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) - --/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ --#define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) -- --/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ --#define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) -- --/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ --#define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ -+#define REW_PTP_RSRV_NOT_ZERO \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ -+#define REW_PTP_RSRV_NOT_ZERO1 \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) -+ -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ -+#define REW_PTP_RSRV_NOT_ZERO2 \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) - - #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) - #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ -@@ -6803,9 +7353,10 @@ enum sparx5_target { - #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ - FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) - --/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ --#define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW,\ -- 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) -+/* SPARX5 ONLY */ -+/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ -+#define REW_PTP_GEN_STAMP_FMT(r) \ -+ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) - - #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) - #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ -@@ -6819,9 +7370,10 @@ enum sparx5_target { - #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ - FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) - --/* REW:RAM_CTRL:RAM_INIT */ --#define REW_RAM_INIT __REG(TARGET_REW,\ -- 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) -+/* REW:RAM_CTRL:RAM_INIT */ -+#define REW_RAM_INIT \ -+ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ -+ 4) - - #define REW_RAM_INIT_RAM_INIT BIT(1) - #define REW_RAM_INIT_RAM_INIT_SET(x)\ -@@ -6835,9 +7387,9 @@ enum sparx5_target { - #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) - --/* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ --#define VCAP_ES0_CTRL __REG(TARGET_VCAP_ES0,\ -- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ -+#define VCAP_ES0_CTRL \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) - #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ -@@ -6887,9 +7439,9 @@ enum sparx5_target { - #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ - FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) - --/* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ --#define VCAP_ES0_CFG __REG(TARGET_VCAP_ES0,\ -- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ -+#define VCAP_ES0_CFG \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) - #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ -@@ -6903,33 +7455,33 @@ enum sparx5_target { - #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ - FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) - --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ --#define VCAP_ES0_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -- --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ --#define VCAP_ES0_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -- --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ --#define VCAP_ES0_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -- --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ --#define VCAP_ES0_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -- --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ --#define VCAP_ES0_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ --#define VCAP_ES0_VCAP_TG_DAT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ --#define VCAP_ES0_IDX __REG(TARGET_VCAP_ES0,\ -- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ -+#define VCAP_ES0_VCAP_ENTRY_DAT(r) \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -+ -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ -+#define VCAP_ES0_VCAP_MASK_DAT(r) \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -+ -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ -+#define VCAP_ES0_VCAP_ACTION_DAT(r) \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -+ -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ -+#define VCAP_ES0_VCAP_CNT_DAT(r) \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -+ -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ -+#define VCAP_ES0_VCAP_CNT_FW_DAT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ -+#define VCAP_ES0_VCAP_TG_DAT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ -+#define VCAP_ES0_IDX \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) - #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ -@@ -6937,9 +7489,9 @@ enum sparx5_target { - #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ - FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) - --/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ --#define VCAP_ES0_MAP __REG(TARGET_VCAP_ES0,\ -- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ -+#define VCAP_ES0_MAP \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) - #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ -@@ -6947,9 +7499,9 @@ enum sparx5_target { - #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ - FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) - --/* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ --#define VCAP_ES0_VCAP_STICKY __REG(TARGET_VCAP_ES0,\ -- 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) -+/* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ -+#define VCAP_ES0_VCAP_STICKY \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) - - #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) - #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ -@@ -6957,49 +7509,49 @@ enum sparx5_target { - #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ - FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) - --/* VCAP_ES0:VCAP_CONST:VCAP_VER */ --#define VCAP_ES0_VCAP_VER __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ --#define VCAP_ES0_ENTRY_WIDTH __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ --#define VCAP_ES0_ENTRY_CNT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ --#define VCAP_ES0_ENTRY_SWCNT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ --#define VCAP_ES0_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ --#define VCAP_ES0_ACTION_DEF_CNT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ --#define VCAP_ES0_ACTION_WIDTH __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ --#define VCAP_ES0_CNT_WIDTH __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:CORE_CNT */ --#define VCAP_ES0_CORE_CNT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -- --/* VCAP_ES0:VCAP_CONST:IF_CNT */ --#define VCAP_ES0_IF_CNT __REG(TARGET_VCAP_ES0,\ -- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ --#define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2,\ -- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_ES0:VCAP_CONST:VCAP_VER */ -+#define VCAP_ES0_VCAP_VER \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ -+#define VCAP_ES0_ENTRY_WIDTH \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ -+#define VCAP_ES0_ENTRY_CNT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ -+#define VCAP_ES0_ENTRY_SWCNT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ -+#define VCAP_ES0_ENTRY_TG_WIDTH \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ -+#define VCAP_ES0_ACTION_DEF_CNT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ -+#define VCAP_ES0_ACTION_WIDTH \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ -+#define VCAP_ES0_CNT_WIDTH \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:CORE_CNT */ -+#define VCAP_ES0_CORE_CNT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -+ -+/* VCAP_ES0:VCAP_CONST:IF_CNT */ -+#define VCAP_ES0_IF_CNT \ -+ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ -+#define VCAP_ES2_CTRL \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) - #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ -@@ -7049,9 +7601,9 @@ enum sparx5_target { - #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ - FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) - --/* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ --#define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2,\ -- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ -+#define VCAP_ES2_CFG \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) - #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ -@@ -7065,33 +7617,33 @@ enum sparx5_target { - #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ - FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) - --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ --#define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -- --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ --#define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -- --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ --#define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -- --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ --#define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -- --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ --#define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ --#define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ --#define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2,\ -- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ -+#define VCAP_ES2_VCAP_ENTRY_DAT(r) \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ -+#define VCAP_ES2_VCAP_MASK_DAT(r) \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ -+#define VCAP_ES2_VCAP_ACTION_DAT(r) \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ -+#define VCAP_ES2_VCAP_CNT_DAT(r) \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ -+#define VCAP_ES2_VCAP_CNT_FW_DAT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ -+#define VCAP_ES2_VCAP_TG_DAT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ -+#define VCAP_ES2_IDX \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) - #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ -@@ -7099,9 +7651,9 @@ enum sparx5_target { - #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ - FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) - --/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ --#define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2,\ -- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ -+#define VCAP_ES2_MAP \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) - #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ -@@ -7109,9 +7661,9 @@ enum sparx5_target { - #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ - FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) - --/* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ --#define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2,\ -- 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) -+/* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ -+#define VCAP_ES2_VCAP_STICKY \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) - - #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) - #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ -@@ -7119,49 +7671,49 @@ enum sparx5_target { - #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ - FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) - --/* VCAP_ES2:VCAP_CONST:VCAP_VER */ --#define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ --#define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ --#define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ --#define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ --#define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ --#define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ --#define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ --#define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:CORE_CNT */ --#define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -- --/* VCAP_ES2:VCAP_CONST:IF_CNT */ --#define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2,\ -- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ --#define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_ES2:VCAP_CONST:VCAP_VER */ -+#define VCAP_ES2_VCAP_VER \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ -+#define VCAP_ES2_ENTRY_WIDTH \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ -+#define VCAP_ES2_ENTRY_CNT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ -+#define VCAP_ES2_ENTRY_SWCNT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ -+#define VCAP_ES2_ENTRY_TG_WIDTH \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ -+#define VCAP_ES2_ACTION_DEF_CNT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ -+#define VCAP_ES2_ACTION_WIDTH \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ -+#define VCAP_ES2_CNT_WIDTH \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:CORE_CNT */ -+#define VCAP_ES2_CORE_CNT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -+ -+/* VCAP_ES2:VCAP_CONST:IF_CNT */ -+#define VCAP_ES2_IF_CNT \ -+ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ -+#define VCAP_SUPER_CTRL \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) - #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ -@@ -7211,9 +7763,9 @@ enum sparx5_target { - #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ - FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) - --/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ --#define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ -+#define VCAP_SUPER_CFG \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) - #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ -@@ -7227,33 +7779,33 @@ enum sparx5_target { - #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ - FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) - --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ --#define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -- --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ --#define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -- --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ --#define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -- --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ --#define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -- --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ --#define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ --#define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ --#define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ -+#define VCAP_SUPER_VCAP_ENTRY_DAT(r) \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ -+#define VCAP_SUPER_VCAP_MASK_DAT(r) \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ -+#define VCAP_SUPER_VCAP_ACTION_DAT(r) \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ -+#define VCAP_SUPER_VCAP_CNT_DAT(r) \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ -+#define VCAP_SUPER_VCAP_CNT_FW_DAT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ -+#define VCAP_SUPER_VCAP_TG_DAT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ -+#define VCAP_SUPER_IDX \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) - - #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) - #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ -@@ -7261,9 +7813,9 @@ enum sparx5_target { - #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ - FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) - --/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ --#define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) -+/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ -+#define VCAP_SUPER_MAP \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) - - #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) - #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ -@@ -7271,49 +7823,49 @@ enum sparx5_target { - #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ - FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) - --/* VCAP_SUPER:VCAP_CONST:VCAP_VER */ --#define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ --#define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ --#define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ --#define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ --#define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ --#define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ --#define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ --#define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:CORE_CNT */ --#define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -- --/* VCAP_SUPER:VCAP_CONST:IF_CNT */ --#define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -- --/* VCAP_SUPER:RAM_CTRL:RAM_INIT */ --#define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER,\ -- 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) -+/* VCAP_SUPER:VCAP_CONST:VCAP_VER */ -+#define VCAP_SUPER_VCAP_VER \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ -+#define VCAP_SUPER_ENTRY_WIDTH \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ -+#define VCAP_SUPER_ENTRY_CNT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ -+#define VCAP_SUPER_ENTRY_SWCNT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ -+#define VCAP_SUPER_ENTRY_TG_WIDTH \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ -+#define VCAP_SUPER_ACTION_DEF_CNT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ -+#define VCAP_SUPER_ACTION_WIDTH \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ -+#define VCAP_SUPER_CNT_WIDTH \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:CORE_CNT */ -+#define VCAP_SUPER_CORE_CNT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) -+ -+/* VCAP_SUPER:VCAP_CONST:IF_CNT */ -+#define VCAP_SUPER_IF_CNT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) -+ -+/* VCAP_SUPER:RAM_CTRL:RAM_INIT */ -+#define VCAP_SUPER_RAM_INIT \ -+ __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) - - #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) - #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ -@@ -7327,9 +7879,10 @@ enum sparx5_target { - #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) - --/* VOP:RAM_CTRL:RAM_INIT */ --#define VOP_RAM_INIT __REG(TARGET_VOP,\ -- 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) -+/* VOP:RAM_CTRL:RAM_INIT */ -+#define VOP_RAM_INIT \ -+ __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ -+ 4) - - #define VOP_RAM_INIT_RAM_INIT BIT(1) - #define VOP_RAM_INIT_RAM_INIT_SET(x)\ -@@ -7343,9 +7896,10 @@ enum sparx5_target { - #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ - FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) - --/* XQS:SYSTEM:STAT_CFG */ --#define XQS_STAT_CFG __REG(TARGET_XQS,\ -- 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) -+/* XQS:SYSTEM:STAT_CFG */ -+#define XQS_STAT_CFG \ -+ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \ -+ 1, 4) - - #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) - #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ -@@ -7353,11 +7907,12 @@ enum sparx5_target { - #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ - FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) - --#define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) -+#define XQS_STAT_CFG_STAT_VIEW\ -+ GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5) - #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ -- FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) -+ spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x) - #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ -- FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) -+ spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x) - - #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) - #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ -@@ -7371,48 +7926,56 @@ enum sparx5_target { - #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ - FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) - --/* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ --#define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ -- 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) -+/* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ -+#define XQS_QLIMIT_SHR_TOP_CFG(g) \ -+ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\ -+ 1, 4) - --#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) -+#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\ -+ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0) - #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ -- FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) -+ spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) - #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ -- FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) -+ spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) - --/* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ --#define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ -- 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) -+/* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ -+#define XQS_QLIMIT_SHR_ATOP_CFG(g) \ -+ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\ -+ 1, 4) - --#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) -+#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\ -+ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0) - #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ -- FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) -+ spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) - #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ -- FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) -+ spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) - --/* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ --#define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ -- 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) -+/* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ -+#define XQS_QLIMIT_SHR_CTOP_CFG(g) \ -+ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\ -+ 1, 4) - --#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) -+#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\ -+ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0) - #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ -- FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) -+ spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) - #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ -- FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) -+ spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) - --/* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ --#define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ -- 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) -+/* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ -+#define XQS_QLIMIT_SHR_QLIM_CFG(g) \ -+ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \ -+ 0, 1, 4) - --#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) -+#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\ -+ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0) - #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ -- FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) -+ spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) - #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ -- FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) -+ spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) - --/* XQS:STAT:CNT */ --#define XQS_CNT(g) __REG(TARGET_XQS,\ -- 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) -+/* XQS:STAT:CNT */ -+#define XQS_CNT(g) \ -+ __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) - - #endif /* _SPARX5_MAIN_REGS_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c -@@ -0,0 +1,219 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip Sparx5 Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. -+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b -+ */ -+ -+#include "sparx5_regs.h" -+ -+const unsigned int sparx5_tsize[TSIZE_LAST] = { -+ [TC_DEV10G] = 12, -+ [TC_DEV2G5] = 65, -+ [TC_DEV5G] = 13, -+ [TC_PCS10G_BR] = 12, -+ [TC_PCS5G_BR] = 13, -+}; -+ -+const unsigned int sparx5_raddr[RADDR_LAST] = { -+ [RA_CPU_PROC_CTRL] = 176, -+ [RA_GCB_SOFT_RST] = 8, -+ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24, -+}; -+ -+const unsigned int sparx5_rcnt[RCNT_LAST] = { -+ [RC_ANA_AC_OWN_UPSID] = 3, -+ [RC_ANA_ACL_VCAP_S2_CFG] = 70, -+ [RC_ANA_ACL_OWN_UPSID] = 3, -+ [RC_ANA_CL_OWN_UPSID] = 3, -+ [RC_ANA_L2_OWN_UPSID] = 3, -+ [RC_ASM_PORT_CFG] = 67, -+ [RC_DSM_BUF_CFG] = 67, -+ [RC_DSM_DEV_TX_STOP_WM_CFG] = 67, -+ [RC_DSM_RX_PAUSE_CFG] = 67, -+ [RC_DSM_MAC_CFG] = 67, -+ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65, -+ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65, -+ [RC_DSM_TAXI_CAL_CFG] = 9, -+ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65, -+ [RC_HSCH_PORT_MODE] = 70, -+ [RC_QFWD_SWITCH_PORT_MODE] = 70, -+ [RC_QSYS_PAUSE_CFG] = 70, -+ [RC_QSYS_ATOP] = 70, -+ [RC_QSYS_FWD_PRESSURE] = 70, -+ [RC_QSYS_CAL_AUTO] = 7, -+ [RC_REW_OWN_UPSID] = 3, -+ [RC_REW_RTAG_ETAG_CTRL] = 70, -+}; -+ -+const unsigned int sparx5_gaddr[GADDR_LAST] = { -+ [GA_ANA_AC_RAM_CTRL] = 839108, -+ [GA_ANA_AC_PS_COMMON] = 894472, -+ [GA_ANA_AC_MIRROR_PROBE] = 893696, -+ [GA_ANA_AC_SRC] = 849920, -+ [GA_ANA_AC_PGID] = 786432, -+ [GA_ANA_AC_TSN_SF] = 839136, -+ [GA_ANA_AC_TSN_SF_CFG] = 839680, -+ [GA_ANA_AC_TSN_SF_STATUS] = 839072, -+ [GA_ANA_AC_SG_ACCESS] = 839140, -+ [GA_ANA_AC_SG_CONFIG] = 851584, -+ [GA_ANA_AC_SG_STATUS] = 839088, -+ [GA_ANA_AC_SG_STATUS_STICKY] = 839152, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552, -+ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792, -+ [GA_ANA_ACL_COMMON] = 32768, -+ [GA_ANA_ACL_KEY_SEL] = 34200, -+ [GA_ANA_ACL_CNT_B] = 16384, -+ [GA_ANA_ACL_STICKY] = 36408, -+ [GA_ANA_AC_POL_POL_ALL_CFG] = 75968, -+ [GA_ANA_AC_POL_COMMON_BDLB] = 79048, -+ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056, -+ [GA_ANA_AC_SDLB_LBGRP_TBL] = 295468, -+ [GA_ANA_CL_PORT] = 131072, -+ [GA_ANA_CL_COMMON] = 166912, -+ [GA_ANA_L2_COMMON] = 566024, -+ [GA_ANA_L3_COMMON] = 493632, -+ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460, -+ [GA_ASM_CFG] = 33280, -+ [GA_ASM_PFC_TIMER_CFG] = 34716, -+ [GA_ASM_LBK_WM_CFG] = 34744, -+ [GA_ASM_LBK_MISC_CFG] = 34756, -+ [GA_ASM_RAM_CTRL] = 34832, -+ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504, -+ [GA_EACL_CNT_TBL] = 122880, -+ [GA_EACL_POL_CFG] = 150608, -+ [GA_EACL_ES2_STICKY] = 118696, -+ [GA_EACL_RAM_CTRL] = 118736, -+ [GA_GCB_SIO_CTRL] = 876, -+ [GA_HSCH_HSCH_DWRR] = 162816, -+ [GA_HSCH_HSCH_MISC] = 163104, -+ [GA_HSCH_HSCH_LEAK_LISTS] = 161664, -+ [GA_HSCH_SYSTEM] = 184000, -+ [GA_HSCH_MMGT] = 162368, -+ [GA_HSCH_TAS_CONFIG] = 162384, -+ [GA_PTP_PTP_CFG] = 320, -+ [GA_PTP_PTP_TOD_DOMAINS] = 336, -+ [GA_PTP_PHASE_DETECTOR_CTRL] = 420, -+ [GA_QSYS_CALCFG] = 2304, -+ [GA_QSYS_RAM_CTRL] = 2344, -+ [GA_REW_COMMON] = 387264, -+ [GA_REW_PORT] = 360448, -+ [GA_REW_VOE_PORT_LM_CNT] = 393216, -+ [GA_REW_RAM_CTRL] = 378696, -+ [GA_VOP_RAM_CTRL] = 279176, -+ [GA_XQS_SYSTEM] = 6768, -+ [GA_XQS_QLIMIT_SHR] = 7936, -+}; -+ -+const unsigned int sparx5_gcnt[GCNT_LAST] = { -+ [GC_ANA_AC_SRC] = 102, -+ [GC_ANA_AC_PGID] = 3290, -+ [GC_ANA_AC_TSN_SF_CFG] = 1024, -+ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 70, -+ [GC_ANA_ACL_KEY_SEL] = 134, -+ [GC_ANA_ACL_CNT_A] = 4096, -+ [GC_ANA_ACL_CNT_B] = 4096, -+ [GC_ANA_AC_SDLB_LBGRP_TBL] = 10, -+ [GC_ANA_AC_SDLB_LBSET_TBL] = 4616, -+ [GC_ANA_CL_PORT] = 70, -+ [GC_ANA_L2_ISDX_LIMIT] = 1536, -+ [GC_ANA_L2_ISDX] = 4096, -+ [GC_ANA_L3_VLAN] = 5120, -+ [GC_ASM_DEV_STATISTICS] = 65, -+ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 138, -+ [GC_EACL_CNT_TBL] = 2048, -+ [GC_GCB_SIO_CTRL] = 3, -+ [GC_HSCH_HSCH_CFG] = 5040, -+ [GC_HSCH_HSCH_DWRR] = 72, -+ [GC_PTP_PTP_PINS] = 5, -+ [GC_PTP_PHASE_DETECTOR_CTRL] = 5, -+ [GC_REW_PORT] = 70, -+ [GC_REW_VOE_PORT_LM_CNT] = 520, -+}; -+ -+const unsigned int sparx5_gsize[GSIZE_LAST] = { -+ [GW_ANA_AC_SRC] = 16, -+ [GW_ANA_L2_COMMON] = 700, -+ [GW_ASM_CFG] = 1088, -+ [GW_CPU_CPU_REGS] = 204, -+ [GW_FDMA_FDMA] = 428, -+ [GW_GCB_CHIP_REGS] = 424, -+ [GW_HSCH_TAS_CONFIG] = 12, -+ [GW_PTP_PHASE_DETECTOR_CTRL] = 8, -+ [GW_QSYS_PAUSE_CFG] = 1128, -+}; -+ -+const unsigned int sparx5_fpos[FPOS_LAST] = { -+ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 12, -+ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 11, -+ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 10, -+ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 9, -+ [FP_CPU_PROC_CTRL_VINITHI] = 8, -+ [FP_CPU_PROC_CTRL_CFGTE] = 7, -+ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, -+ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, -+ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, -+ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, -+ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, -+ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 26, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 24, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 23, -+ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 7, -+ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 6, -+}; -+ -+const unsigned int sparx5_fsize[FSIZE_LAST] = { -+ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 32, -+ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 32, -+ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 32, -+ [FW_ANA_AC_TSN_SF_PORT_NUM] = 9, -+ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 10, -+ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 10, -+ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 10, -+ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 16, -+ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 13, -+ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 5, -+ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 13, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 13, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 4, -+ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 13, -+ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 32, -+ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 13, -+ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 10, -+ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 32, -+ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 4, -+ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 9, -+ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 7, -+ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 16, -+ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 7, -+ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 13, -+ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 16, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 7, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 16, -+ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 14, -+ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 11, -+ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 14, -+ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 5, -+ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 5, -+ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 5, -+ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 2, -+ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 7, -+ [FW_QRES_RES_CFG_WM_HIGH] = 12, -+ [FW_QRES_RES_STAT_MAXUSE] = 21, -+ [FW_QRES_RES_STAT_CUR_INUSE] = 21, -+ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 12, -+ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 12, -+ [FW_QSYS_ATOP_ATOP] = 12, -+ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 12, -+ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 7, -+ [FW_XQS_STAT_CFG_STAT_VIEW] = 13, -+ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 15, -+ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 15, -+ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 15, -+ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 15, -+}; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h -@@ -0,0 +1,244 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* Microchip Sparx5 Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. -+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b -+ */ -+ -+#ifndef _SPARX5_REGS_H_ -+#define _SPARX5_REGS_H_ -+ -+/* These enumerated values are used to index the platform specific structs -+ * containing the addresses, counts, size and positions, of register groups, -+ * registers and fields. -+ */ -+ -+enum sparx5_tsize_enum { -+ TC_DEV10G, -+ TC_DEV2G5, -+ TC_DEV5G, -+ TC_PCS10G_BR, -+ TC_PCS5G_BR, -+ TSIZE_LAST, -+}; -+ -+enum sparx5_raddr_enum { -+ RA_CPU_PROC_CTRL, -+ RA_GCB_SOFT_RST, -+ RA_GCB_HW_SGPIO_TO_SD_MAP_CFG, -+ RADDR_LAST, -+}; -+ -+enum sparx5_rcnt_enum { -+ RC_ANA_AC_OWN_UPSID, -+ RC_ANA_ACL_VCAP_S2_CFG, -+ RC_ANA_ACL_OWN_UPSID, -+ RC_ANA_CL_OWN_UPSID, -+ RC_ANA_L2_OWN_UPSID, -+ RC_ASM_PORT_CFG, -+ RC_DSM_BUF_CFG, -+ RC_DSM_DEV_TX_STOP_WM_CFG, -+ RC_DSM_RX_PAUSE_CFG, -+ RC_DSM_MAC_CFG, -+ RC_DSM_MAC_ADDR_BASE_HIGH_CFG, -+ RC_DSM_MAC_ADDR_BASE_LOW_CFG, -+ RC_DSM_TAXI_CAL_CFG, -+ RC_GCB_HW_SGPIO_TO_SD_MAP_CFG, -+ RC_HSCH_PORT_MODE, -+ RC_QFWD_SWITCH_PORT_MODE, -+ RC_QSYS_PAUSE_CFG, -+ RC_QSYS_ATOP, -+ RC_QSYS_FWD_PRESSURE, -+ RC_QSYS_CAL_AUTO, -+ RC_REW_OWN_UPSID, -+ RC_REW_RTAG_ETAG_CTRL, -+ RCNT_LAST, -+}; -+ -+enum sparx5_gaddr_enum { -+ GA_ANA_AC_RAM_CTRL, -+ GA_ANA_AC_PS_COMMON, -+ GA_ANA_AC_MIRROR_PROBE, -+ GA_ANA_AC_SRC, -+ GA_ANA_AC_PGID, -+ GA_ANA_AC_TSN_SF, -+ GA_ANA_AC_TSN_SF_CFG, -+ GA_ANA_AC_TSN_SF_STATUS, -+ GA_ANA_AC_SG_ACCESS, -+ GA_ANA_AC_SG_CONFIG, -+ GA_ANA_AC_SG_STATUS, -+ GA_ANA_AC_SG_STATUS_STICKY, -+ GA_ANA_AC_STAT_GLOBAL_CFG_PORT, -+ GA_ANA_AC_STAT_CNT_CFG_PORT, -+ GA_ANA_AC_STAT_GLOBAL_CFG_ACL, -+ GA_ANA_ACL_COMMON, -+ GA_ANA_ACL_KEY_SEL, -+ GA_ANA_ACL_CNT_B, -+ GA_ANA_ACL_STICKY, -+ GA_ANA_AC_POL_POL_ALL_CFG, -+ GA_ANA_AC_POL_COMMON_BDLB, -+ GA_ANA_AC_POL_COMMON_BUM_SLB, -+ GA_ANA_AC_SDLB_LBGRP_TBL, -+ GA_ANA_CL_PORT, -+ GA_ANA_CL_COMMON, -+ GA_ANA_L2_COMMON, -+ GA_ANA_L3_COMMON, -+ GA_ANA_L3_VLAN_ARP_L3MC_STICKY, -+ GA_ASM_CFG, -+ GA_ASM_PFC_TIMER_CFG, -+ GA_ASM_LBK_WM_CFG, -+ GA_ASM_LBK_MISC_CFG, -+ GA_ASM_RAM_CTRL, -+ GA_EACL_ES2_KEY_SELECT_PROFILE, -+ GA_EACL_CNT_TBL, -+ GA_EACL_POL_CFG, -+ GA_EACL_ES2_STICKY, -+ GA_EACL_RAM_CTRL, -+ GA_GCB_SIO_CTRL, -+ GA_HSCH_HSCH_DWRR, -+ GA_HSCH_HSCH_MISC, -+ GA_HSCH_HSCH_LEAK_LISTS, -+ GA_HSCH_SYSTEM, -+ GA_HSCH_MMGT, -+ GA_HSCH_TAS_CONFIG, -+ GA_PTP_PTP_CFG, -+ GA_PTP_PTP_TOD_DOMAINS, -+ GA_PTP_PHASE_DETECTOR_CTRL, -+ GA_QSYS_CALCFG, -+ GA_QSYS_RAM_CTRL, -+ GA_REW_COMMON, -+ GA_REW_PORT, -+ GA_REW_VOE_PORT_LM_CNT, -+ GA_REW_RAM_CTRL, -+ GA_VOP_RAM_CTRL, -+ GA_XQS_SYSTEM, -+ GA_XQS_QLIMIT_SHR, -+ GADDR_LAST, -+}; -+ -+enum sparx5_gcnt_enum { -+ GC_ANA_AC_SRC, -+ GC_ANA_AC_PGID, -+ GC_ANA_AC_TSN_SF_CFG, -+ GC_ANA_AC_STAT_CNT_CFG_PORT, -+ GC_ANA_ACL_KEY_SEL, -+ GC_ANA_ACL_CNT_A, -+ GC_ANA_ACL_CNT_B, -+ GC_ANA_AC_SDLB_LBGRP_TBL, -+ GC_ANA_AC_SDLB_LBSET_TBL, -+ GC_ANA_CL_PORT, -+ GC_ANA_L2_ISDX_LIMIT, -+ GC_ANA_L2_ISDX, -+ GC_ANA_L3_VLAN, -+ GC_ASM_DEV_STATISTICS, -+ GC_EACL_ES2_KEY_SELECT_PROFILE, -+ GC_EACL_CNT_TBL, -+ GC_GCB_SIO_CTRL, -+ GC_HSCH_HSCH_CFG, -+ GC_HSCH_HSCH_DWRR, -+ GC_PTP_PTP_PINS, -+ GC_PTP_PHASE_DETECTOR_CTRL, -+ GC_REW_PORT, -+ GC_REW_VOE_PORT_LM_CNT, -+ GCNT_LAST, -+}; -+ -+enum sparx5_gsize_enum { -+ GW_ANA_AC_SRC, -+ GW_ANA_L2_COMMON, -+ GW_ASM_CFG, -+ GW_CPU_CPU_REGS, -+ GW_FDMA_FDMA, -+ GW_GCB_CHIP_REGS, -+ GW_HSCH_TAS_CONFIG, -+ GW_PTP_PHASE_DETECTOR_CTRL, -+ GW_QSYS_PAUSE_CFG, -+ GSIZE_LAST, -+}; -+ -+enum sparx5_fpos_enum { -+ FP_CPU_PROC_CTRL_AARCH64_MODE_ENA, -+ FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, -+ FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, -+ FP_CPU_PROC_CTRL_BE_EXCEP_MODE, -+ FP_CPU_PROC_CTRL_VINITHI, -+ FP_CPU_PROC_CTRL_CFGTE, -+ FP_CPU_PROC_CTRL_CP15S_DISABLE, -+ FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, -+ FP_CPU_PROC_CTRL_L2_FLUSH_REQ, -+ FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, -+ FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, -+ FP_FDMA_CH_CFG_CH_INJ_PORT, -+ FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION, -+ FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -+ FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, -+ FP_PTP_PHAD_CTRL_PHAD_ENA, -+ FP_PTP_PHAD_CTRL_PHAD_FAILED, -+ FPOS_LAST, -+}; -+ -+enum sparx5_fsize_enum { -+ FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK, -+ FW_ANA_AC_SRC_CFG_PORT_MASK, -+ FW_ANA_AC_PGID_CFG_PORT_MASK, -+ FW_ANA_AC_TSN_SF_PORT_NUM, -+ FW_ANA_AC_TSN_SF_CFG_TSN_SGID, -+ FW_ANA_AC_TSN_SF_STATUS_TSN_SFID, -+ FW_ANA_AC_SG_ACCESS_CTRL_SGID, -+ FW_ANA_AC_PORT_SGE_CFG_MASK, -+ FW_ANA_AC_SDLB_XLB_START_LBSET_START, -+ FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, -+ FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, -+ FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, -+ FW_ANA_AC_SDLB_XLB_NEXT_LBGRP, -+ FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, -+ FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA, -+ FW_ANA_L2_DLB_CFG_DLB_IDX, -+ FW_ANA_L2_TSN_CFG_TSN_SFID, -+ FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK, -+ FW_FDMA_CH_CFG_CH_DCB_DB_CNT, -+ FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, -+ FW_HSCH_SE_CFG_SE_DWRR_CNT, -+ FW_HSCH_SE_CONNECT_SE_LEAK_LINK, -+ FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT, -+ FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX, -+ FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST, -+ FW_HSCH_FLUSH_CTRL_FLUSH_PORT, -+ FW_HSCH_FLUSH_CTRL_FLUSH_HIER, -+ FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, -+ FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, -+ FW_LRN_AUTOAGE_CFG_2_NEXT_ROW, -+ FW_PTP_PTP_PIN_INTR_INTR_PTP, -+ FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, -+ FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, -+ FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT, -+ FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, -+ FW_QRES_RES_CFG_WM_HIGH, -+ FW_QRES_RES_STAT_MAXUSE, -+ FW_QRES_RES_STAT_CUR_INUSE, -+ FW_QSYS_PAUSE_CFG_PAUSE_START, -+ FW_QSYS_PAUSE_CFG_PAUSE_STOP, -+ FW_QSYS_ATOP_ATOP, -+ FW_QSYS_ATOP_TOT_CFG_ATOP_TOT, -+ FW_REW_RTAG_ETAG_CTRL_IPE_TBL, -+ FW_XQS_STAT_CFG_STAT_VIEW, -+ FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, -+ FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, -+ FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, -+ FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, -+ FSIZE_LAST, -+}; -+ -+extern const unsigned int sparx5_tsize[TSIZE_LAST]; -+extern const unsigned int sparx5_raddr[RADDR_LAST]; -+extern const unsigned int sparx5_rcnt[RCNT_LAST]; -+extern const unsigned int sparx5_gaddr[GADDR_LAST]; -+extern const unsigned int sparx5_gcnt[GCNT_LAST]; -+extern const unsigned int sparx5_gsize[GSIZE_LAST]; -+extern const unsigned int sparx5_fpos[FPOS_LAST]; -+extern const unsigned int sparx5_fsize[FSIZE_LAST]; -+ -+#endif /* _SPARX5_REGS_H_ */ diff --git a/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch b/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch deleted file mode 100644 index 226e52435a..0000000000 --- a/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 9f4b9996e892cd721bf1f6664c3ba95a7592924c Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:29 +0200 -Subject: [PATCH 31/82] net: sparx5: modify SPX5_PORTS_ALL macro - -In preparation for lan969x, we need to define the SPX5_PORTS_ALL macro -as 70 (65 front ports + 5 internal ports). This is required as the -SPX5_PORT_CPU will be redefined as an offset to the number of front -ports, in a subsequent patch. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -52,13 +52,14 @@ enum sparx5_vlan_port_type { - }; - - #define SPX5_PORTS 65 -+#define SPX5_PORTS_ALL 70 /* Total number of ports */ -+ - #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ - #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ - #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ - #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ - #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ - #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ --#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ - - #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ - #define PGID_UC_FLOOD (PGID_BASE + 0) diff --git a/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch b/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch deleted file mode 100644 index 556c0c8945..0000000000 --- a/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch +++ /dev/null @@ -1,355 +0,0 @@ -From fc875dc858249c8c2c2eac758c3f89b3a7719f74 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:30 +0200 -Subject: [PATCH 32/82] net: sparx5: add *sparx5 argument to a few functions - -The *sparx5 context pointer is required in functions that need to access -platform constants (which will be added in a subsequent patch). Prepare -for this by updating the prototype and use of such functions. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_ethtool.c | 24 ++++++++-------- - .../ethernet/microchip/sparx5/sparx5_main.h | 2 +- - .../ethernet/microchip/sparx5/sparx5_netdev.c | 2 +- - .../ethernet/microchip/sparx5/sparx5_packet.c | 2 +- - .../ethernet/microchip/sparx5/sparx5_port.c | 28 +++++++++---------- - .../ethernet/microchip/sparx5/sparx5_port.h | 6 ++-- - .../ethernet/microchip/sparx5/sparx5_psfp.c | 24 ++++++++-------- - .../net/ethernet/microchip/sparx5/sparx5_tc.c | 8 +++--- - 8 files changed, 48 insertions(+), 48 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -@@ -505,8 +505,8 @@ static void sparx5_get_dev_misc_stats(u6 - static void sparx5_get_device_stats(struct sparx5 *sparx5, int portno) - { - u64 *portstats = &sparx5->stats[portno * sparx5->num_stats]; -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - void __iomem *inst; - - inst = spx5_inst_get(sparx5, dev, tinst); -@@ -819,8 +819,8 @@ static void sparx5_get_eth_phy_stats(str - - portstats = &sparx5->stats[portno * sparx5->num_stats]; - if (sparx5_is_baser(port->conf.portmode)) { -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - - inst = spx5_inst_get(sparx5, dev, tinst); - sparx5_get_dev_phy_stats(portstats, inst, tinst); -@@ -844,8 +844,8 @@ static void sparx5_get_eth_mac_stats(str - - portstats = &sparx5->stats[portno * sparx5->num_stats]; - if (sparx5_is_baser(port->conf.portmode)) { -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - - inst = spx5_inst_get(sparx5, dev, tinst); - sparx5_get_dev_mac_stats(portstats, inst, tinst); -@@ -912,8 +912,8 @@ static void sparx5_get_eth_mac_ctrl_stat - - portstats = &sparx5->stats[portno * sparx5->num_stats]; - if (sparx5_is_baser(port->conf.portmode)) { -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - - inst = spx5_inst_get(sparx5, dev, tinst); - sparx5_get_dev_mac_ctrl_stats(portstats, inst, tinst); -@@ -944,8 +944,8 @@ static void sparx5_get_eth_rmon_stats(st - - portstats = &sparx5->stats[portno * sparx5->num_stats]; - if (sparx5_is_baser(port->conf.portmode)) { -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - - inst = spx5_inst_get(sparx5, dev, tinst); - sparx5_get_dev_rmon_stats(portstats, inst, tinst); -@@ -1027,8 +1027,8 @@ static void sparx5_get_sset_data(struct - - portstats = &sparx5->stats[portno * sparx5->num_stats]; - if (sparx5_is_baser(port->conf.portmode)) { -- u32 tinst = sparx5_port_dev_index(portno); -- u32 dev = sparx5_to_high_dev(portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, portno); -+ u32 dev = sparx5_to_high_dev(sparx5, portno); - - inst = spx5_inst_get(sparx5, dev, tinst); - sparx5_get_dev_misc_stats(portstats, inst, tinst); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -401,7 +401,7 @@ void sparx5_set_port_ifh_timestamp(void - void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); - void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); - void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); --void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); -+void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); - bool sparx5_netdevice_check(const struct net_device *dev); - struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); - int sparx5_register_netdevs(struct sparx5 *sparx5); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -55,7 +55,7 @@ static void __ifh_encode_bitfield(void * - ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); - } - --void sparx5_set_port_ifh(void *ifh_hdr, u16 portno) -+void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) - { - /* VSTAX.RSV = 1. MSBit must be 1 */ - ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -235,7 +235,7 @@ netdev_tx_t sparx5_port_xmit_impl(struct - netdev_tx_t ret; - - memset(ifh, 0, IFH_LEN * 4); -- sparx5_set_port_ifh(ifh, port->portno); -+ sparx5_set_port_ifh(sparx5, ifh, port->portno); - - if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { - if (sparx5_ptp_txtstamp_request(port, skb) < 0) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -132,8 +132,8 @@ static int sparx5_get_sfi_status(struct - return -EINVAL; - } - -- dev = sparx5_to_high_dev(portno); -- tinst = sparx5_port_dev_index(portno); -+ dev = sparx5_to_high_dev(sparx5, portno); -+ tinst = sparx5_port_dev_index(sparx5, portno); - inst = spx5_inst_get(sparx5, dev, tinst); - - value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0)); -@@ -316,9 +316,9 @@ static int sparx5_port_flush_poll(struct - static int sparx5_port_disable(struct sparx5 *sparx5, struct sparx5_port *port, bool high_spd_dev) - { - u32 tinst = high_spd_dev ? -- sparx5_port_dev_index(port->portno) : port->portno; -+ sparx5_port_dev_index(sparx5, port->portno) : port->portno; - u32 dev = high_spd_dev ? -- sparx5_to_high_dev(port->portno) : TARGET_DEV2G5; -+ sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; - void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); - u32 spd = port->conf.speed; - u32 spd_prm; -@@ -427,7 +427,7 @@ static int sparx5_port_disable(struct sp - HSCH_FLUSH_CTRL); - - if (high_spd_dev) { -- u32 pcs = sparx5_to_pcs_dev(port->portno); -+ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); - void __iomem *pcsinst = spx5_inst_get(sparx5, pcs, tinst); - - /* 12: Disable 5G/10G/25 BaseR PCS */ -@@ -558,8 +558,8 @@ static int sparx5_port_max_tags_set(stru - bool dtag = max_tags == SPX5_PORT_MAX_TAGS_TWO; - enum sparx5_vlan_port_type vlan_type = port->vlan_type; - bool dotag = max_tags != SPX5_PORT_MAX_TAGS_NONE; -- u32 dev = sparx5_to_high_dev(port->portno); -- u32 tinst = sparx5_port_dev_index(port->portno); -+ u32 dev = sparx5_to_high_dev(sparx5, port->portno); -+ u32 tinst = sparx5_port_dev_index(sparx5, port->portno); - void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); - u32 etype; - -@@ -789,9 +789,9 @@ static int sparx5_port_pcs_high_set(stru - struct sparx5_port_config *conf) - { - u32 clk_spd = conf->portmode == PHY_INTERFACE_MODE_5GBASER ? 1 : 0; -- u32 pix = sparx5_port_dev_index(port->portno); -- u32 dev = sparx5_to_high_dev(port->portno); -- u32 pcs = sparx5_to_pcs_dev(port->portno); -+ u32 pix = sparx5_port_dev_index(sparx5, port->portno); -+ u32 dev = sparx5_to_high_dev(sparx5, port->portno); -+ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); - void __iomem *devinst; - void __iomem *pcsinst; - int err; -@@ -843,7 +843,7 @@ static int sparx5_port_pcs_high_set(stru - /* Switch between 1G/2500 and 5G/10G/25G devices */ - static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) - { -- int bt_indx = BIT(sparx5_port_dev_index(port)); -+ int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); - - if (sparx5_port_is_5g(port)) { - spx5_rmw(hsd ? 0 : bt_indx, -@@ -1016,9 +1016,9 @@ int sparx5_port_init(struct sparx5 *spar - { - u32 pause_start = sparx5_wm_enc(6 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); - u32 atop = sparx5_wm_enc(20 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); -- u32 devhigh = sparx5_to_high_dev(port->portno); -- u32 pix = sparx5_port_dev_index(port->portno); -- u32 pcs = sparx5_to_pcs_dev(port->portno); -+ u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); -+ u32 pix = sparx5_port_dev_index(sparx5, port->portno); -+ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); - bool sd_pol = port->signd_active_high; - bool sd_sel = !port->signd_internal; - bool sd_ena = port->signd_enable; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -@@ -40,7 +40,7 @@ static inline bool sparx5_port_is_25g(in - return portno >= 56 && portno <= 63; - } - --static inline u32 sparx5_to_high_dev(int port) -+static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) - { - if (sparx5_port_is_5g(port)) - return TARGET_DEV5G; -@@ -49,7 +49,7 @@ static inline u32 sparx5_to_high_dev(int - return TARGET_DEV25G; - } - --static inline u32 sparx5_to_pcs_dev(int port) -+static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) - { - if (sparx5_port_is_5g(port)) - return TARGET_PCS5G_BR; -@@ -58,7 +58,7 @@ static inline u32 sparx5_to_pcs_dev(int - return TARGET_PCS25G_BR; - } - --static inline int sparx5_port_dev_index(int port) -+static inline int sparx5_port_dev_index(struct sparx5 *sparx5, int port) - { - if (sparx5_port_is_2g5(port)) - return port; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -@@ -20,34 +20,34 @@ static struct sparx5_pool_entry sparx5_p - /* Pool of available stream filters */ - static struct sparx5_pool_entry sparx5_psfp_sf_pool[SPX5_PSFP_SF_CNT]; - --static int sparx5_psfp_sf_get(u32 *id) -+static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) - { - return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); - } - --static int sparx5_psfp_sf_put(u32 id) -+static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) - { - return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); - } - --static int sparx5_psfp_sg_get(u32 idx, u32 *id) -+static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) - { - return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, - idx, id); - } - --static int sparx5_psfp_sg_put(u32 id) -+static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) - { - return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); - } - --static int sparx5_psfp_fm_get(u32 idx, u32 *id) -+static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) - { - return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, - id); - } - --static int sparx5_psfp_fm_put(u32 id) -+static int sparx5_psfp_fm_put(struct sparx5 *sparx5, u32 id) - { - return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); - } -@@ -205,7 +205,7 @@ int sparx5_psfp_sf_add(struct sparx5 *sp - { - int ret; - -- ret = sparx5_psfp_sf_get(id); -+ ret = sparx5_psfp_sf_get(sparx5, id); - if (ret < 0) - return ret; - -@@ -220,7 +220,7 @@ int sparx5_psfp_sf_del(struct sparx5 *sp - - sparx5_psfp_sf_set(sparx5, id, &sf); - -- return sparx5_psfp_sf_put(id); -+ return sparx5_psfp_sf_put(sparx5, id); - } - - int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, -@@ -229,7 +229,7 @@ int sparx5_psfp_sg_add(struct sparx5 *sp - ktime_t basetime; - int ret; - -- ret = sparx5_psfp_sg_get(uidx, id); -+ ret = sparx5_psfp_sg_get(sparx5, uidx, id); - if (ret < 0) - return ret; - /* Was already in use, no need to reconfigure */ -@@ -253,7 +253,7 @@ int sparx5_psfp_sg_del(struct sparx5 *sp - const struct sparx5_psfp_sg sg = { 0 }; - int ret; - -- ret = sparx5_psfp_sg_put(id); -+ ret = sparx5_psfp_sg_put(sparx5, id); - if (ret < 0) - return ret; - /* Stream gate still in use ? */ -@@ -270,7 +270,7 @@ int sparx5_psfp_fm_add(struct sparx5 *sp - int ret; - - /* Get flow meter */ -- ret = sparx5_psfp_fm_get(uidx, &fm->pol.idx); -+ ret = sparx5_psfp_fm_get(sparx5, uidx, &fm->pol.idx); - if (ret < 0) - return ret; - /* Was already in use, no need to reconfigure */ -@@ -303,7 +303,7 @@ int sparx5_psfp_fm_del(struct sparx5 *sp - if (ret < 0) - return ret; - -- ret = sparx5_psfp_fm_put(id); -+ ret = sparx5_psfp_fm_put(sparx5, id); - if (ret < 0) - return ret; - /* Do not reset flow-meter if still in use. */ ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc.c -@@ -60,8 +60,8 @@ static int sparx5_tc_setup_block(struct - cb, ndev, ndev, false); - } - --static void sparx5_tc_get_layer_and_idx(u32 parent, u32 portno, u32 *layer, -- u32 *idx) -+static void sparx5_tc_get_layer_and_idx(struct sparx5 *sparx5, u32 parent, -+ u32 portno, u32 *layer, u32 *idx) - { - if (parent == TC_H_ROOT) { - *layer = 2; -@@ -90,8 +90,8 @@ static int sparx5_tc_setup_qdisc_tbf(str - struct sparx5_port *port = netdev_priv(ndev); - u32 layer, se_idx; - -- sparx5_tc_get_layer_and_idx(qopt->parent, port->portno, &layer, -- &se_idx); -+ sparx5_tc_get_layer_and_idx(port->sparx5, qopt->parent, port->portno, -+ &layer, &se_idx); - - switch (qopt->command) { - case TC_TBF_REPLACE: diff --git a/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch deleted file mode 100644 index 219d1e8d34..0000000000 --- a/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch +++ /dev/null @@ -1,88 +0,0 @@ -From e263a2c741eef417e769075e11d32318b8b2b8ab Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:31 +0200 -Subject: [PATCH 33/82] net: sparx5: add constants to match data - -Add new struct sparx5_consts, containing all the chip constants that are -known to be different for Sparx5 and lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_main.h | 21 +++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -952,11 +952,32 @@ static const struct sparx5_regs sparx5_r - .fsize = sparx5_fsize, - }; - -+static const struct sparx5_consts sparx5_consts = { -+ .n_ports = 65, -+ .n_ports_all = 70, -+ .n_hsch_l1_elems = 64, -+ .n_hsch_queues = 8, -+ .n_lb_groups = 10, -+ .n_pgids = 2113, /* (2048 + n_ports) */ -+ .n_sio_clks = 3, -+ .n_own_upsids = 3, -+ .n_auto_cals = 7, -+ .n_filters = 1024, -+ .n_gates = 1024, -+ .n_sdlbs = 4096, -+ .n_dsm_cal_taxis = 8, -+ .buf_size = 4194280, -+ .qres_max_prio_idx = 630, -+ .qres_max_colour_idx = 638, -+ .tod_pin = 4, -+}; -+ - static const struct sparx5_match_data sparx5_desc = { - .iomap = sparx5_main_iomap, - .iomap_size = ARRAY_SIZE(sparx5_main_iomap), - .ioranges = 3, - .regs = &sparx5_regs, -+ .consts = &sparx5_consts, - }; - - static const struct of_device_id mchp_sparx5_match[] = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -238,6 +238,26 @@ struct sparx5_regs { - const unsigned int *fsize; - }; - -+struct sparx5_consts { -+ u32 n_ports; /* Number of front ports */ -+ u32 n_ports_all; /* Number of front ports + internal ports */ -+ u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */ -+ u32 n_hsch_queues; /* Number of HSCH queues */ -+ u32 n_lb_groups; /* Number of leacky bucket groupd */ -+ u32 n_pgids; /* Number of PGID's */ -+ u32 n_sio_clks; /* Number of serial IO clocks */ -+ u32 n_own_upsids; /* Number of own UPSID's */ -+ u32 n_auto_cals; /* Number of auto calendars */ -+ u32 n_filters; /* Number of PSFP filters */ -+ u32 n_gates; /* Number of PSFP gates */ -+ u32 n_sdlbs; /* Number of service dual leaky buckets */ -+ u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */ -+ u32 buf_size; /* Amount of QLIM watermark memory */ -+ u32 qres_max_prio_idx; /* Maximum QRES prio index */ -+ u32 qres_max_colour_idx; /* Maximum QRES colour index */ -+ u32 tod_pin; /* PTP TOD pin */ -+}; -+ - struct sparx5_main_io_resource { - enum sparx5_target id; - phys_addr_t offset; -@@ -246,6 +266,7 @@ struct sparx5_main_io_resource { - - struct sparx5_match_data { - const struct sparx5_regs *regs; -+ const struct sparx5_consts *consts; - const struct sparx5_main_io_resource *iomap; - int ioranges; - int iomap_size; diff --git a/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch b/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch deleted file mode 100644 index a0832128b8..0000000000 --- a/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch +++ /dev/null @@ -1,600 +0,0 @@ -From 27584455298c4d27246bfcb7ac6c570128648847 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:32 +0200 -Subject: [PATCH 34/82] net: sparx5: use SPX5_CONST for constants which already - have a symbol - -Now that we have indentified all the chip constants, update the use of -them where a symbol is already defined for the constant. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_calendar.c | 13 +++--- - .../ethernet/microchip/sparx5/sparx5_dcb.c | 5 ++- - .../microchip/sparx5/sparx5_ethtool.c | 8 ++-- - .../ethernet/microchip/sparx5/sparx5_fdma.c | 6 ++- - .../microchip/sparx5/sparx5_mactable.c | 7 +-- - .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++---- - .../ethernet/microchip/sparx5/sparx5_netdev.c | 7 ++- - .../ethernet/microchip/sparx5/sparx5_packet.c | 2 +- - .../ethernet/microchip/sparx5/sparx5_pgid.c | 6 +-- - .../ethernet/microchip/sparx5/sparx5_psfp.c | 22 ++++++---- - .../ethernet/microchip/sparx5/sparx5_ptp.c | 44 ++++++++++++------- - .../ethernet/microchip/sparx5/sparx5_sdlb.c | 4 +- - .../microchip/sparx5/sparx5_switchdev.c | 2 +- - .../microchip/sparx5/sparx5_tc_flower.c | 4 +- - .../ethernet/microchip/sparx5/sparx5_vlan.c | 2 +- - 15 files changed, 90 insertions(+), 63 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -131,7 +131,7 @@ static enum sparx5_cal_bw sparx5_get_por - { - struct sparx5_port *port; - -- if (portno >= SPX5_PORTS) { -+ if (portno >= sparx5->data->consts->n_ports) { - /* Internal ports */ - if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) { - /* Equals 1.25G */ -@@ -159,6 +159,7 @@ static enum sparx5_cal_bw sparx5_get_por - /* Auto configure the QSYS calendar based on port configuration */ - int sparx5_config_auto_calendar(struct sparx5 *sparx5) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - u32 cal[7], value, idx, portno; - u32 max_core_bw; - u32 total_bw = 0, used_port_bw = 0; -@@ -174,7 +175,7 @@ int sparx5_config_auto_calendar(struct s - } - - /* Setup the calendar with the bandwidth to each port */ -- for (portno = 0; portno < SPX5_PORTS_ALL; portno++) { -+ for (portno = 0; portno < consts->n_ports_all; portno++) { - u64 reg, offset, this_bw; - - spd = sparx5_get_port_cal_speed(sparx5, portno); -@@ -182,7 +183,7 @@ int sparx5_config_auto_calendar(struct s - continue; - - this_bw = sparx5_cal_speed_to_value(spd); -- if (portno < SPX5_PORTS) -+ if (portno < consts->n_ports) - used_port_bw += this_bw; - else - /* Internal ports are granted half the value */ -@@ -213,7 +214,7 @@ int sparx5_config_auto_calendar(struct s - sparx5, QSYS_CAL_CTRL); - - /* Assign port bandwidth to auto calendar */ -- for (idx = 0; idx < ARRAY_SIZE(cal); idx++) -+ for (idx = 0; idx < consts->n_auto_cals; idx++) - spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); - - /* Increase grant rate of all ports to account for -@@ -304,7 +305,7 @@ static int sparx5_dsm_calendar_calc(stru - for (idx = 0; idx < SPX5_DSM_CAL_MAX_DEVS_PER_TAXI; idx++) { - u32 portno = data->taxi_ports[idx]; - -- if (portno < SPX5_TAXI_PORT_MAX) { -+ if (portno < sparx5->data->consts->n_ports_all) { - data->taxi_speeds[idx] = sparx5_cal_speed_to_value - (sparx5_get_port_cal_speed(sparx5, portno)); - } else { -@@ -573,7 +574,7 @@ int sparx5_config_dsm_calendar(struct sp - if (!data) - return -ENOMEM; - -- for (taxi = 0; taxi < SPX5_DSM_CAL_TAXIS; ++taxi) { -+ for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) { - err = sparx5_dsm_calendar_calc(sparx5, taxi, data); - if (err) { - dev_err(sparx5->dev, "DSM calendar calculation failed\n"); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c -@@ -234,10 +234,11 @@ static int sparx5_dcb_ieee_dscp_setdel(s - struct dcb_app *)) - { - struct sparx5_port *port = netdev_priv(dev); -+ struct sparx5 *sparx5 = port->sparx5; - struct sparx5_port *port_itr; - int err, i; - -- for (i = 0; i < SPX5_PORTS; i++) { -+ for (i = 0; i < sparx5->data->consts->n_ports; i++) { - port_itr = port->sparx5->ports[i]; - if (!port_itr) - continue; -@@ -386,7 +387,7 @@ int sparx5_dcb_init(struct sparx5 *sparx - struct sparx5_port *port; - int i; - -- for (i = 0; i < SPX5_PORTS; i++) { -+ for (i = 0; i < sparx5->data->consts->n_ports; i++) { - port = sparx5->ports[i]; - if (!port) - continue; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -@@ -1122,7 +1122,7 @@ static void sparx5_update_stats(struct s - { - int idx; - -- for (idx = 0; idx < SPX5_PORTS; idx++) -+ for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) - if (sparx5->ports[idx]) - sparx5_update_port_stats(sparx5, idx); - } -@@ -1228,6 +1228,7 @@ const struct ethtool_ops sparx5_ethtool_ - - int sparx_stats_init(struct sparx5 *sparx5) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - char queue_name[32]; - int portno; - -@@ -1235,14 +1236,15 @@ int sparx_stats_init(struct sparx5 *spar - sparx5->num_stats = spx5_stats_count; - sparx5->num_ethtool_stats = ARRAY_SIZE(sparx5_stats_layout); - sparx5->stats = devm_kcalloc(sparx5->dev, -- SPX5_PORTS_ALL * sparx5->num_stats, -+ consts->n_ports_all * -+ sparx5->num_stats, - sizeof(u64), GFP_KERNEL); - if (!sparx5->stats) - return -ENOMEM; - - mutex_init(&sparx5->queue_stats_lock); - sparx5_config_stats(sparx5); -- for (portno = 0; portno < SPX5_PORTS; portno++) -+ for (portno = 0; portno < consts->n_ports; portno++) - if (sparx5->ports[portno]) - sparx5_config_port_stats(sparx5, portno); - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -156,7 +156,9 @@ static bool sparx5_fdma_rx_get_frame(str - /* Now do the normal processing of the skb */ - sparx5_ifh_parse((u32 *)skb->data, &fi); - /* Map to port netdev */ -- port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL; -+ port = fi.src_port < sparx5->data->consts->n_ports ? -+ sparx5->ports[fi.src_port] : -+ NULL; - if (!port || !port->ndev) { - dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); - sparx5_xtr_flush(sparx5, XTR_QUEUE); -@@ -296,7 +298,7 @@ static void sparx5_fdma_rx_init(struct s - fdma->ops.dataptr_cb = &sparx5_fdma_rx_dataptr_cb; - fdma->ops.nextptr_cb = &fdma_nextptr_cb; - /* Fetch a netdev for SKB and NAPI use, any will do */ -- for (idx = 0; idx < SPX5_PORTS; ++idx) { -+ for (idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { - struct sparx5_port *port = sparx5->ports[idx]; - - if (port && port->ndev) { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c -@@ -80,15 +80,16 @@ static void sparx5_mact_select(struct sp - int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, - const unsigned char mac[ETH_ALEN], u16 vid) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int addr, type, ret; - -- if (pgid < SPX5_PORTS) { -+ if (pgid < consts->n_ports) { - type = MAC_ENTRY_ADDR_TYPE_UPSID_PN; - addr = pgid % 32; - addr += (pgid / 32) << 5; /* Add upsid */ - } else { - type = MAC_ENTRY_ADDR_TYPE_MC_IDX; -- addr = pgid - SPX5_PORTS; -+ addr = pgid - consts->n_ports; - } - - mutex_lock(&sparx5->lock); -@@ -371,7 +372,7 @@ static void sparx5_mact_handle_entry(str - return; - - port = LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(cfg2); -- if (port >= SPX5_PORTS) -+ if (port >= sparx5->data->consts->n_ports) - return; - - if (!test_bit(port, sparx5->bridge_mask)) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -31,8 +31,6 @@ - - const struct sparx5_regs *regs; - --#define QLIM_WM(fraction) \ -- ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) - #define IO_RANGES 3 - - struct initial_port_config { -@@ -544,6 +542,12 @@ static int sparx5_init_coreclock(struct - return 0; - } - -+static u32 qlim_wm(struct sparx5 *sparx5, int fraction) -+{ -+ return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * -+ fraction / 100; -+} -+ - static int sparx5_qlim_set(struct sparx5 *sparx5) - { - u32 res, dp, prio; -@@ -559,10 +563,10 @@ static int sparx5_qlim_set(struct sparx5 - } - - /* Set 80,90,95,100% of memory size for top watermarks */ -- spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); -- spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); -- spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); -- spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); -+ spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); -+ spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); -+ spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); -+ spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); - - return 0; - } -@@ -584,7 +588,7 @@ static void sparx5_board_init(struct spa - GCB_HW_SGPIO_SD_CFG); - - /* Refer to LOS SGPIO */ -- for (idx = 0; idx < SPX5_PORTS; idx++) -+ for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) - if (sparx5->ports[idx]) - if (sparx5->ports[idx]->conf.sd_sgpio != ~0) - spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, -@@ -595,6 +599,7 @@ static void sparx5_board_init(struct spa - static int sparx5_start(struct sparx5 *sparx5) - { - u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; -+ const struct sparx5_consts *consts = sparx5->data->consts; - char queue_name[32]; - u32 idx; - int err; -@@ -608,7 +613,7 @@ static int sparx5_start(struct sparx5 *s - } - - /* Enable CPU ports */ -- for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) -+ for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) - spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), - QFWD_SWITCH_PORT_MODE_PORT_ENA, - sparx5, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -290,7 +290,7 @@ int sparx5_register_netdevs(struct sparx - int portno; - int err; - -- for (portno = 0; portno < SPX5_PORTS; portno++) -+ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) - if (sparx5->ports[portno]) { - err = register_netdev(sparx5->ports[portno]->ndev); - if (err) { -@@ -309,7 +309,7 @@ void sparx5_destroy_netdevs(struct sparx - struct sparx5_port *port; - int portno; - -- for (portno = 0; portno < SPX5_PORTS; portno++) { -+ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) { - port = sparx5->ports[portno]; - if (port && port->phylink) { - /* Disconnect the phy */ -@@ -327,8 +327,7 @@ void sparx5_unregister_netdevs(struct sp - { - int portno; - -- for (portno = 0; portno < SPX5_PORTS; portno++) -+ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) - if (sparx5->ports[portno]) - unregister_netdev(sparx5->ports[portno]->ndev); - } -- ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -75,7 +75,7 @@ static void sparx5_xtr_grp(struct sparx5 - sparx5_ifh_parse(ifh, &fi); - - /* Map to port netdev */ -- port = fi.src_port < SPX5_PORTS ? -+ port = fi.src_port < sparx5->data->consts->n_ports ? - sparx5->ports[fi.src_port] : NULL; - if (!port || !port->ndev) { - dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c -@@ -5,7 +5,7 @@ void sparx5_pgid_init(struct sparx5 *spx - { - int i; - -- for (i = 0; i < PGID_TABLE_SIZE; i++) -+ for (i = 0; i < spx5->data->consts->n_pgids; i++) - spx5->pgid_map[i] = SPX5_PGID_FREE; - - /* Reserved for unicast, flood control, broadcast, and CPU. -@@ -22,7 +22,7 @@ int sparx5_pgid_alloc_mcast(struct sparx - /* The multicast area starts at index 65, but the first 7 - * are reserved for flood masks and CPU. Start alloc after that. - */ -- for (i = PGID_MCAST_START; i < PGID_TABLE_SIZE; i++) { -+ for (i = PGID_MCAST_START; i < spx5->data->consts->n_pgids; i++) { - if (spx5->pgid_map[i] == SPX5_PGID_FREE) { - spx5->pgid_map[i] = SPX5_PGID_MULTICAST; - *idx = i; -@@ -35,7 +35,7 @@ int sparx5_pgid_alloc_mcast(struct sparx - - int sparx5_pgid_free(struct sparx5 *spx5, u16 idx) - { -- if (idx <= PGID_CPU || idx >= PGID_TABLE_SIZE) -+ if (idx <= PGID_CPU || idx >= spx5->data->consts->n_pgids) - return -EINVAL; - - if (spx5->pgid_map[idx] == SPX5_PGID_FREE) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -@@ -22,34 +22,38 @@ static struct sparx5_pool_entry sparx5_p - - static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) - { -- return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); -+ return sparx5_pool_get(sparx5_psfp_sf_pool, -+ sparx5->data->consts->n_filters, id); - } - - static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) - { -- return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); -+ return sparx5_pool_put(sparx5_psfp_sf_pool, -+ sparx5->data->consts->n_filters, id); - } - - static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) - { -- return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, -- idx, id); -+ return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, -+ sparx5->data->consts->n_gates, idx, id); - } - - static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) - { -- return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); -+ return sparx5_pool_put(sparx5_psfp_sg_pool, -+ sparx5->data->consts->n_gates, id); - } - - static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) - { -- return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, -- id); -+ return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, -+ sparx5->data->consts->n_sdlbs, idx, id); - } - - static int sparx5_psfp_fm_put(struct sparx5 *sparx5, u32 id) - { -- return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); -+ return sparx5_pool_put(sparx5_psfp_fm_pool, -+ sparx5->data->consts->n_sdlbs, id); - } - - u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) -@@ -318,7 +322,7 @@ void sparx5_psfp_init(struct sparx5 *spa - const struct sparx5_sdlb_group *group; - int i; - -- for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { -+ for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { - group = &sdlb_groups[i]; - sparx5_sdlb_group_init(sparx5, group->max_rate, - group->min_burst, group->frame_size, i); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -@@ -274,6 +274,7 @@ static void sparx5_get_hwtimestamp(struc - u32 nsec) - { - /* Read current PTP time to get seconds */ -+ const struct sparx5_consts *consts = sparx5->data->consts; - unsigned long flags; - u32 curr_nsec; - -@@ -285,10 +286,10 @@ static void sparx5_get_hwtimestamp(struc - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - -- ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); -- curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); -+ ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); -+ curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); - - ts->tv_nsec = nsec; - -@@ -440,8 +441,11 @@ static int sparx5_ptp_settime64(struct p - { - struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); - struct sparx5 *sparx5 = phc->sparx5; -+ const struct sparx5_consts *consts; - unsigned long flags; - -+ consts = sparx5->data->consts; -+ - spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); - - /* Must be in IDLE mode before the time can be loaded */ -@@ -451,14 +455,14 @@ static int sparx5_ptp_settime64(struct p - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - - /* Set new value */ - spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), -- sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); - spx5_wr(lower_32_bits(ts->tv_sec), -- sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); -- spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); -+ spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); - - /* Apply new values */ - spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | -@@ -467,7 +471,7 @@ static int sparx5_ptp_settime64(struct p - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - - spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); - -@@ -478,10 +482,13 @@ int sparx5_ptp_gettime64(struct ptp_cloc - { - struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); - struct sparx5 *sparx5 = phc->sparx5; -+ const struct sparx5_consts *consts; - unsigned long flags; - time64_t s; - s64 ns; - -+ consts = sparx5->data->consts; -+ - spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); - - spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | -@@ -490,12 +497,12 @@ int sparx5_ptp_gettime64(struct ptp_cloc - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - -- s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); -+ s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); - s <<= 32; -- s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); -- ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); -+ s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); -+ ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); - ns &= PTP_PTP_TOD_NSEC_PTP_TOD_NSEC; - - spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); -@@ -515,6 +522,9 @@ static int sparx5_ptp_adjtime(struct ptp - { - struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); - struct sparx5 *sparx5 = phc->sparx5; -+ const struct sparx5_consts *consts; -+ -+ consts = sparx5->data->consts; - - if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { - unsigned long flags; -@@ -528,10 +538,10 @@ static int sparx5_ptp_adjtime(struct ptp - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - - spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), -- sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); - - /* Adjust time with the value of PTP_TOD_NSEC */ - spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) | -@@ -540,7 +550,7 @@ static int sparx5_ptp_adjtime(struct ptp - PTP_PTP_PIN_CFG_PTP_PIN_ACTION | - PTP_PTP_PIN_CFG_PTP_PIN_DOM | - PTP_PTP_PIN_CFG_PTP_PIN_SYNC, -- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); -+ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); - - spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); - } else { -@@ -630,7 +640,7 @@ int sparx5_ptp_init(struct sparx5 *sparx - /* Enable master counters */ - spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); - -- for (i = 0; i < SPX5_PORTS; i++) { -+ for (i = 0; i < sparx5->data->consts->n_ports; i++) { - port = sparx5->ports[i]; - if (!port) - continue; -@@ -646,7 +656,7 @@ void sparx5_ptp_deinit(struct sparx5 *sp - struct sparx5_port *port; - int i; - -- for (i = 0; i < SPX5_PORTS; i++) { -+ for (i = 0; i < sparx5->data->consts->n_ports; i++) { - port = sparx5->ports[i]; - if (!port) - continue; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -@@ -184,7 +184,7 @@ int sparx5_sdlb_group_get_by_rate(struct - - rate_bps = rate * 1000; - -- for (i = SPX5_SDLB_GROUP_CNT - 1; i >= 0; i--) { -+ for (i = sparx5->data->consts->n_lb_groups - 1; i >= 0; i--) { - group = &sdlb_groups[i]; - - count = sparx5_sdlb_group_get_count(sparx5, i); -@@ -208,7 +208,7 @@ int sparx5_sdlb_group_get_by_index(struc - u32 itr, next; - int i; - -- for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { -+ for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { - if (sparx5_sdlb_group_is_empty(sparx5, i)) - continue; - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -@@ -547,7 +547,7 @@ static int sparx5_handle_port_mdb_add(st - - /* Add any mrouter ports to the new entry */ - if (is_new && ether_addr_is_ip_mcast(v->addr)) -- for (i = 0; i < SPX5_PORTS; i++) -+ for (i = 0; i < spx5->data->consts->n_ports; i++) - if (spx5->ports[i] && spx5->ports[i]->is_mrouter) - sparx5_pgid_update_mask(spx5->ports[i], - entry->pgid_idx, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c -@@ -785,7 +785,9 @@ static int sparx5_tc_flower_psfp_setup(s - * allocate a stream gate that is always open. - */ - if (sg_idx < 0) { -- sg_idx = sparx5_pool_idx_to_id(SPX5_PSFP_SG_OPEN); -+ /* Always-open stream gate is always the last */ -+ sg_idx = sparx5_pool_idx_to_id(sparx5->data->consts->n_gates - -+ 1); - sg->ipv = 0; /* Disabled */ - sg->cycletime = SPX5_PSFP_SG_CYCLE_TIME_DEFAULT; - sg->num_entries = 1; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -@@ -169,7 +169,7 @@ void sparx5_update_fwd(struct sparx5 *sp - } - - /* Update SRC masks */ -- for (port = 0; port < SPX5_PORTS; port++) { -+ for (port = 0; port < sparx5->data->consts->n_ports; port++) { - if (test_bit(port, sparx5->bridge_fwd_mask)) { - /* Allow to send to all bridged but self */ - bitmap_copy(workmask, sparx5->bridge_fwd_mask, SPX5_PORTS); diff --git a/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch b/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch deleted file mode 100644 index f311745f39..0000000000 --- a/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch +++ /dev/null @@ -1,60 +0,0 @@ -From efdc2c3094cc2e8aca09c3a16f7a0f3a10d9a097 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:33 +0200 -Subject: [PATCH 35/82] net: sparx5: use SPX5_CONST for constants which do not - have a symbol - -Now that we have indentified all the chip constants, update the use of -them where a symbol is not defined for the constant. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -522,7 +522,7 @@ static int sparx5_init_coreclock(struct - sparx5, - LRN_AUTOAGE_CFG_1); - -- for (idx = 0; idx < 3; idx++) -+ for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) - spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), - GCB_SIO_CLOCK_SYS_CLK_PERIOD, - sparx5, -@@ -550,16 +550,21 @@ static u32 qlim_wm(struct sparx5 *sparx5 - - static int sparx5_qlim_set(struct sparx5 *sparx5) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - u32 res, dp, prio; - - for (res = 0; res < 2; res++) { - for (prio = 0; prio < 8; prio++) - spx5_wr(0xFFF, sparx5, -- QRES_RES_CFG(prio + 630 + res * 1024)); -+ QRES_RES_CFG(prio + -+ consts->qres_max_prio_idx + -+ res * 1024)); - - for (dp = 0; dp < 4; dp++) - spx5_wr(0xFFF, sparx5, -- QRES_RES_CFG(dp + 638 + res * 1024)); -+ QRES_RES_CFG(dp + -+ consts->qres_max_colour_idx + -+ res * 1024)); - } - - /* Set 80,90,95,100% of memory size for top watermarks */ -@@ -605,7 +610,7 @@ static int sparx5_start(struct sparx5 *s - int err; - - /* Setup own UPSIDs */ -- for (idx = 0; idx < 3; idx++) { -+ for (idx = 0; idx < consts->n_own_upsids; idx++) { - spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); - spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); - spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); diff --git a/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch deleted file mode 100644 index 0f213c8367..0000000000 --- a/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch +++ /dev/null @@ -1,227 +0,0 @@ -From 9a6d927f8d9386fcabe4b93aa1bf16a0796e69fb Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:34 +0200 -Subject: [PATCH 36/82] net: sparx5: add ops to match data - -Add new struct sparx5_ops, containing functions that needs to be -different as the implementation differs on Sparx5 and lan969x. Initially -we add functions for checking the port type (2g5, 5g, 10g or 25g) based -on the port number. Update the code to use the ops instead of the -platform specific functions. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../ethernet/microchip/sparx5/sparx5_main.c | 8 +++++ - .../ethernet/microchip/sparx5/sparx5_main.h | 8 +++++ - .../ethernet/microchip/sparx5/sparx5_port.c | 34 +++++++++++-------- - .../ethernet/microchip/sparx5/sparx5_port.h | 12 ++++--- - 4 files changed, 44 insertions(+), 18 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -982,12 +982,20 @@ static const struct sparx5_consts sparx5 - .tod_pin = 4, - }; - -+static const struct sparx5_ops sparx5_ops = { -+ .is_port_2g5 = &sparx5_port_is_2g5, -+ .is_port_5g = &sparx5_port_is_5g, -+ .is_port_10g = &sparx5_port_is_10g, -+ .is_port_25g = &sparx5_port_is_25g, -+}; -+ - static const struct sparx5_match_data sparx5_desc = { - .iomap = sparx5_main_iomap, - .iomap_size = ARRAY_SIZE(sparx5_main_iomap), - .ioranges = 3, - .regs = &sparx5_regs, - .consts = &sparx5_consts, -+ .ops = &sparx5_ops, - }; - - static const struct of_device_id mchp_sparx5_match[] = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -258,6 +258,13 @@ struct sparx5_consts { - u32 tod_pin; /* PTP TOD pin */ - }; - -+struct sparx5_ops { -+ bool (*is_port_2g5)(int portno); -+ bool (*is_port_5g)(int portno); -+ bool (*is_port_10g)(int portno); -+ bool (*is_port_25g)(int portno); -+}; -+ - struct sparx5_main_io_resource { - enum sparx5_target id; - phys_addr_t offset; -@@ -267,6 +274,7 @@ struct sparx5_main_io_resource { - struct sparx5_match_data { - const struct sparx5_regs *regs; - const struct sparx5_consts *consts; -+ const struct sparx5_ops *ops; - const struct sparx5_main_io_resource *iomap; - int ioranges; - int iomap_size; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -213,11 +213,13 @@ static int sparx5_port_verify_speed(stru - struct sparx5_port *port, - struct sparx5_port_config *conf) - { -- if ((sparx5_port_is_2g5(port->portno) && -+ const struct sparx5_ops *ops = sparx5->data->ops; -+ -+ if ((ops->is_port_2g5(port->portno) && - conf->speed > SPEED_2500) || -- (sparx5_port_is_5g(port->portno) && -+ (ops->is_port_5g(port->portno) && - conf->speed > SPEED_5000) || -- (sparx5_port_is_10g(port->portno) && -+ (ops->is_port_10g(port->portno) && - conf->speed > SPEED_10000)) - return sparx5_port_error(port, conf, SPX5_PERR_SPEED); - -@@ -226,14 +228,14 @@ static int sparx5_port_verify_speed(stru - return -EINVAL; - case PHY_INTERFACE_MODE_1000BASEX: - if (conf->speed != SPEED_1000 || -- sparx5_port_is_2g5(port->portno)) -+ ops->is_port_2g5(port->portno)) - return sparx5_port_error(port, conf, SPX5_PERR_SPEED); -- if (sparx5_port_is_2g5(port->portno)) -+ if (ops->is_port_2g5(port->portno)) - return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); - break; - case PHY_INTERFACE_MODE_2500BASEX: - if (conf->speed != SPEED_2500 || -- sparx5_port_is_2g5(port->portno)) -+ ops->is_port_2g5(port->portno)) - return sparx5_port_error(port, conf, SPX5_PERR_SPEED); - break; - case PHY_INTERFACE_MODE_QSGMII: -@@ -320,6 +322,7 @@ static int sparx5_port_disable(struct sp - u32 dev = high_spd_dev ? - sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; - void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); -+ const struct sparx5_ops *ops = sparx5->data->ops; - u32 spd = port->conf.speed; - u32 spd_prm; - int err; -@@ -436,7 +439,7 @@ static int sparx5_port_disable(struct sp - pcsinst, - PCS10G_BR_PCS_CFG(0)); - -- if (sparx5_port_is_25g(port->portno)) -+ if (ops->is_port_25g(port->portno)) - /* Disable 25G PCS */ - spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0), - DEV25G_PCS25G_CFG_PCS25G_ENA, -@@ -561,6 +564,7 @@ static int sparx5_port_max_tags_set(stru - u32 dev = sparx5_to_high_dev(sparx5, port->portno); - u32 tinst = sparx5_port_dev_index(sparx5, port->portno); - void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); -+ const struct sparx5_ops *ops = sparx5->data->ops; - u32 etype; - - etype = (vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? -@@ -575,7 +579,7 @@ static int sparx5_port_max_tags_set(stru - sparx5, - DEV2G5_MAC_TAGS_CFG(port->portno)); - -- if (sparx5_port_is_2g5(port->portno)) -+ if (ops->is_port_2g5(port->portno)) - return 0; - - spx5_inst_rmw(DEV10G_MAC_TAGS_CFG_TAG_ID_SET(etype) | -@@ -844,18 +848,19 @@ static int sparx5_port_pcs_high_set(stru - static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) - { - int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); -+ const struct sparx5_ops *ops = sparx5->data->ops; - -- if (sparx5_port_is_5g(port)) { -+ if (ops->is_port_5g(port)) { - spx5_rmw(hsd ? 0 : bt_indx, - bt_indx, - sparx5, - PORT_CONF_DEV5G_MODES); -- } else if (sparx5_port_is_10g(port)) { -+ } else if (ops->is_port_10g(port)) { - spx5_rmw(hsd ? 0 : bt_indx, - bt_indx, - sparx5, - PORT_CONF_DEV10G_MODES); -- } else if (sparx5_port_is_25g(port)) { -+ } else if (ops->is_port_25g(port)) { - spx5_rmw(hsd ? 0 : bt_indx, - bt_indx, - sparx5, -@@ -1016,6 +1021,7 @@ int sparx5_port_init(struct sparx5 *spar - { - u32 pause_start = sparx5_wm_enc(6 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); - u32 atop = sparx5_wm_enc(20 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); -+ const struct sparx5_ops *ops = sparx5->data->ops; - u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); - u32 pix = sparx5_port_dev_index(sparx5, port->portno); - u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); -@@ -1082,7 +1088,7 @@ int sparx5_port_init(struct sparx5 *spar - if (err) - return err; - -- if (!sparx5_port_is_2g5(port->portno)) -+ if (!ops->is_port_2g5(port->portno)) - /* Enable shadow device */ - spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), - DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, -@@ -1105,7 +1111,7 @@ int sparx5_port_init(struct sparx5 *spar - sparx5, - DEV2G5_MAC_IFG_CFG(port->portno)); - -- if (sparx5_port_is_2g5(port->portno)) -+ if (ops->is_port_2g5(port->portno)) - return 0; /* Low speed device only - return */ - - /* Now setup the high speed device */ -@@ -1128,7 +1134,7 @@ int sparx5_port_init(struct sparx5 *spar - pcsinst, - PCS10G_BR_PCS_SD_CFG(0)); - -- if (sparx5_port_is_25g(port->portno)) { -+ if (ops->is_port_25g(port->portno)) { - /* Handle Signal Detect in 25G PCS */ - spx5_wr(DEV25G_PCS25G_SD_CFG_SD_POL_SET(sd_pol) | - DEV25G_PCS25G_SD_CFG_SD_SEL_SET(sd_sel) | ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -@@ -42,18 +42,22 @@ static inline bool sparx5_port_is_25g(in - - static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) - { -- if (sparx5_port_is_5g(port)) -+ const struct sparx5_ops *ops = sparx5->data->ops; -+ -+ if (ops->is_port_5g(port)) - return TARGET_DEV5G; -- if (sparx5_port_is_10g(port)) -+ if (ops->is_port_10g(port)) - return TARGET_DEV10G; - return TARGET_DEV25G; - } - - static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) - { -- if (sparx5_port_is_5g(port)) -+ const struct sparx5_ops *ops = sparx5->data->ops; -+ -+ if (ops->is_port_5g(port)) - return TARGET_PCS5G_BR; -- if (sparx5_port_is_10g(port)) -+ if (ops->is_port_10g(port)) - return TARGET_PCS10G_BR; - return TARGET_PCS25G_BR; - } diff --git a/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch b/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch deleted file mode 100644 index 5a201dedb2..0000000000 --- a/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch +++ /dev/null @@ -1,80 +0,0 @@ -From cc1814ae3a2cd34a345c7d638f5da991d8d22d33 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:35 +0200 -Subject: [PATCH 37/82] net: sparx5: ops out chip port to device index/bit - functions - -The chip port device index and mode bit can be obtained using the port -number. However the mapping of port number to chip device index and -mode bit differs on Sparx5 and lan969x. Therefore ops out the function. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 ++ - drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 4 +++- - drivers/net/ethernet/microchip/sparx5/sparx5_port.h | 7 ++++++- - 4 files changed, 13 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -987,6 +987,8 @@ static const struct sparx5_ops sparx5_op - .is_port_5g = &sparx5_port_is_5g, - .is_port_10g = &sparx5_port_is_10g, - .is_port_25g = &sparx5_port_is_25g, -+ .get_port_dev_index = &sparx5_port_dev_mapping, -+ .get_port_dev_bit = &sparx5_port_dev_mapping, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -263,6 +263,8 @@ struct sparx5_ops { - bool (*is_port_5g)(int portno); - bool (*is_port_10g)(int portno); - bool (*is_port_25g)(int portno); -+ u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); -+ u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); - }; - - struct sparx5_main_io_resource { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -847,8 +847,10 @@ static int sparx5_port_pcs_high_set(stru - /* Switch between 1G/2500 and 5G/10G/25G devices */ - static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) - { -- int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); - const struct sparx5_ops *ops = sparx5->data->ops; -+ int bt_indx; -+ -+ bt_indx = BIT(ops->get_port_dev_bit(sparx5, port)); - - if (ops->is_port_5g(port)) { - spx5_rmw(hsd ? 0 : bt_indx, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -@@ -62,7 +62,7 @@ static inline u32 sparx5_to_pcs_dev(stru - return TARGET_PCS25G_BR; - } - --static inline int sparx5_port_dev_index(struct sparx5 *sparx5, int port) -+static inline u32 sparx5_port_dev_mapping(struct sparx5 *sparx5, int port) - { - if (sparx5_port_is_2g5(port)) - return port; -@@ -74,6 +74,11 @@ static inline int sparx5_port_dev_index( - return (port - 56); - } - -+static inline u32 sparx5_port_dev_index(struct sparx5 *sparx5, int port) -+{ -+ return sparx5->data->ops->get_port_dev_index(sparx5, port); -+} -+ - int sparx5_port_init(struct sparx5 *sparx5, - struct sparx5_port *spx5_port, - struct sparx5_port_config *conf); diff --git a/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch b/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch deleted file mode 100644 index 71fff9c8db..0000000000 --- a/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 54a152e60ab7b7fb64211ee6a3defec095fb796e Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:36 +0200 -Subject: [PATCH 38/82] net: sparx5: ops out functions for getting certain - array values - -Add getters for getting values in arrays: sdlb_groups and -sparx5_hsch_max_group_rate and ops out the getters, as these arrays will -differ on lan969x. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 +++ - drivers/net/ethernet/microchip/sparx5/sparx5_police.c | 3 ++- - drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c | 3 ++- - drivers/net/ethernet/microchip/sparx5/sparx5_qos.c | 8 +++++++- - drivers/net/ethernet/microchip/sparx5/sparx5_qos.h | 2 ++ - drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 11 +++++++++-- - 7 files changed, 27 insertions(+), 5 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -989,6 +989,8 @@ static const struct sparx5_ops sparx5_op - .is_port_25g = &sparx5_port_is_25g, - .get_port_dev_index = &sparx5_port_dev_mapping, - .get_port_dev_bit = &sparx5_port_dev_mapping, -+ .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, -+ .get_sdlb_group = &sparx5_get_sdlb_group, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -265,6 +265,8 @@ struct sparx5_ops { - bool (*is_port_25g)(int portno); - u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); - u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); -+ u32 (*get_hsch_max_group_rate)(int grp); -+ struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); - }; - - struct sparx5_main_io_resource { -@@ -501,6 +503,7 @@ struct sparx5_sdlb_group { - }; - - extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; -+struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); - int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, - u64 rate); - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_police.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_police.c -@@ -11,10 +11,11 @@ static int sparx5_policer_service_conf_s - struct sparx5_policer *pol) - { - u32 idx, pup_tokens, max_pup_tokens, burst, thres; -+ const struct sparx5_ops *ops = sparx5->data->ops; - struct sparx5_sdlb_group *g; - u64 rate; - -- g = &sdlb_groups[pol->group]; -+ g = ops->get_sdlb_group(pol->group); - idx = pol->idx; - - rate = pol->rate * 1000; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c -@@ -319,11 +319,12 @@ int sparx5_psfp_fm_del(struct sparx5 *sp - - void sparx5_psfp_init(struct sparx5 *sparx5) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - const struct sparx5_sdlb_group *group; - int i; - - for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { -- group = &sdlb_groups[i]; -+ group = ops->get_sdlb_group(i); - sparx5_sdlb_group_init(sparx5, group->max_rate, - group->min_burst, group->frame_size, i); - } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c -@@ -74,6 +74,11 @@ static const u32 spx5_hsch_max_group_rat - 26214200 /* 26.214 Gbps */ - }; - -+u32 sparx5_get_hsch_max_group_rate(int grp) -+{ -+ return spx5_hsch_max_group_rate[grp]; -+} -+ - static struct sparx5_layer layers[SPX5_HSCH_LAYER_CNT]; - - static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) -@@ -385,6 +390,7 @@ static int sparx5_dwrr_conf_set(struct s - - static int sparx5_leak_groups_init(struct sparx5 *sparx5) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - struct sparx5_layer *layer; - u32 sys_clk_per_100ps; - struct sparx5_lg *lg; -@@ -397,7 +403,7 @@ static int sparx5_leak_groups_init(struc - layer = &layers[i]; - for (ii = 0; ii < SPX5_HSCH_LEAK_GRP_CNT; ii++) { - lg = &layer->leak_groups[ii]; -- lg->max_rate = spx5_hsch_max_group_rate[ii]; -+ lg->max_rate = ops->get_hsch_max_group_rate(i); - - /* Calculate the leak time in us, to serve a maximum - * rate of 'max_rate' for this group ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h -@@ -79,4 +79,6 @@ int sparx5_tc_ets_add(struct sparx5_port - - int sparx5_tc_ets_del(struct sparx5_port *port); - -+u32 sparx5_get_hsch_max_group_rate(int grp); -+ - #endif /* __SPARX5_QOS_H__ */ ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -@@ -20,6 +20,11 @@ struct sparx5_sdlb_group sdlb_groups[SPX - { 5000000ULL, 8192 / 8, 64 } /* 5 M */ - }; - -+struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) -+{ -+ return &sdlb_groups[idx]; -+} -+ - int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) - { - u32 clk_per_100ps; -@@ -178,6 +183,7 @@ static int sparx5_sdlb_group_get_count(s - - int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - const struct sparx5_sdlb_group *group; - u64 rate_bps; - int i, count; -@@ -185,7 +191,7 @@ int sparx5_sdlb_group_get_by_rate(struct - rate_bps = rate * 1000; - - for (i = sparx5->data->consts->n_lb_groups - 1; i >= 0; i--) { -- group = &sdlb_groups[i]; -+ group = ops->get_sdlb_group(i); - - count = sparx5_sdlb_group_get_count(sparx5, i); - -@@ -303,11 +309,12 @@ int sparx5_sdlb_group_del(struct sparx5 - void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, - u32 frame_size, u32 idx) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - u32 thres_shift, mask = 0x01, power = 0; - struct sparx5_sdlb_group *group; - u64 max_token; - -- group = &sdlb_groups[idx]; -+ group = ops->get_sdlb_group(idx); - - /* Number of positions to right-shift LB's threshold value. */ - while ((min_burst & mask) == 0) { diff --git a/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch b/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch deleted file mode 100644 index 44443b8e2d..0000000000 --- a/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch +++ /dev/null @@ -1,74 +0,0 @@ -From def4582837fa546a00860649a253c47107123060 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:37 +0200 -Subject: [PATCH 39/82] net: sparx5: ops out function for setting the port mux - -Port muxing is configured based on the supported port modes. As these -modes can differ on Sparx5 and lan969x we ops out the port muxing -function. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 1 + - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 6 ++++++ - drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 7 +++---- - 3 files changed, 10 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -991,6 +991,7 @@ static const struct sparx5_ops sparx5_op - .get_port_dev_bit = &sparx5_port_dev_mapping, - .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, - .get_sdlb_group = &sparx5_get_sdlb_group, -+ .set_port_mux = &sparx5_port_mux_set, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -267,6 +267,8 @@ struct sparx5_ops { - u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); - u32 (*get_hsch_max_group_rate)(int grp); - struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); -+ int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, -+ struct sparx5_port_config *conf); - }; - - struct sparx5_main_io_resource { -@@ -485,6 +487,10 @@ int sparx5_pool_get(struct sparx5_pool_e - int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, - u32 *id); - -+/* sparx5_port.c */ -+int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, -+ struct sparx5_port_config *conf); -+ - /* sparx5_sdlb.c */ - #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF - #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -516,9 +516,8 @@ static int sparx5_port_fifo_sz(struct sp - /* Configure port muxing: - * QSGMII: 4x2G5 devices - */ --static int sparx5_port_mux_set(struct sparx5 *sparx5, -- struct sparx5_port *port, -- struct sparx5_port_config *conf) -+int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, -+ struct sparx5_port_config *conf) - { - u32 portno = port->portno; - u32 inst; -@@ -1039,7 +1038,7 @@ int sparx5_port_init(struct sparx5 *spar - pcsinst = spx5_inst_get(sparx5, pcs, pix); - - /* Set the mux port mode */ -- err = sparx5_port_mux_set(sparx5, port, conf); -+ err = ops->set_port_mux(sparx5, port, conf); - if (err) - return err; - diff --git a/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch b/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch deleted file mode 100644 index 455c332bc2..0000000000 --- a/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 6802dd4ba13b3487fb4e57dce38c53edf2ba63a2 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:38 +0200 -Subject: [PATCH 40/82] net: sparx5: ops out PTP IRQ handler - -The PTP registers are located in two different register targets on -Sparx5 and lan969x. We can't handle this with the register macros, so -ops out the handler. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 4 +++- - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 ++ - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -605,6 +605,7 @@ static int sparx5_start(struct sparx5 *s - { - u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - const struct sparx5_consts *consts = sparx5->data->consts; -+ const struct sparx5_ops *ops = sparx5->data->ops; - char queue_name[32]; - u32 idx; - int err; -@@ -728,7 +729,7 @@ static int sparx5_start(struct sparx5 *s - - if (sparx5->ptp_irq >= 0) { - err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, -- NULL, sparx5_ptp_irq_handler, -+ NULL, ops->ptp_irq_handler, - IRQF_ONESHOT, "sparx5-ptp", - sparx5); - if (err) -@@ -992,6 +993,7 @@ static const struct sparx5_ops sparx5_op - .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, - .get_sdlb_group = &sparx5_get_sdlb_group, - .set_port_mux = &sparx5_port_mux_set, -+ .ptp_irq_handler = &sparx5_ptp_irq_handler, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -269,6 +269,8 @@ struct sparx5_ops { - struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); - int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, - struct sparx5_port_config *conf); -+ -+ irqreturn_t (*ptp_irq_handler)(int irq, void *args); - }; - - struct sparx5_main_io_resource { diff --git a/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch b/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch deleted file mode 100644 index 44523d9011..0000000000 --- a/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch +++ /dev/null @@ -1,137 +0,0 @@ -From e8df6924d6e793aca572b8fa766779354d20adae Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:39 +0200 -Subject: [PATCH 41/82] net: sparx5: ops out function for DSM calendar - calculation - -The DSM (Disassembler) calendar grants each port access to internal -busses. The configuration of the calendar is done differently on Sparx5 -and lan969x. Therefore ops out the function that calculates the -calendar. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_calendar.c | 22 ++++--------------- - .../ethernet/microchip/sparx5/sparx5_main.c | 1 + - .../ethernet/microchip/sparx5/sparx5_main.h | 21 ++++++++++++++++++ - 3 files changed, 26 insertions(+), 18 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -15,9 +15,7 @@ - #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ - - /* DSM calendar information */ --#define SPX5_DSM_CAL_LEN 64 - #define SPX5_DSM_CAL_EMPTY 0xFFFF --#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 - #define SPX5_DSM_CAL_TAXIS 8 - #define SPX5_DSM_CAL_BW_LOSS 553 - -@@ -37,19 +35,6 @@ static u32 sparx5_taxi_ports[SPX5_DSM_CA - {64, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99}, - }; - --struct sparx5_calendar_data { -- u32 schedule[SPX5_DSM_CAL_LEN]; -- u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -- u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -- u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -- u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -- u32 new_slots[SPX5_DSM_CAL_LEN]; -- u32 temp_sched[SPX5_DSM_CAL_LEN]; -- u32 indices[SPX5_DSM_CAL_LEN]; -- u32 short_list[SPX5_DSM_CAL_LEN]; -- u32 long_list[SPX5_DSM_CAL_LEN]; --}; -- - static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) - { - switch (sparx5->target_ct) { -@@ -279,8 +264,8 @@ static u32 sparx5_dsm_cp_cal(u32 *sched) - return SPX5_DSM_CAL_EMPTY; - } - --static int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -- struct sparx5_calendar_data *data) -+int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data) - { - bool slow_mode; - u32 gcd, idx, sum, min, factor; -@@ -566,6 +551,7 @@ update_err: - /* Configure the DSM calendar based on port configuration */ - int sparx5_config_dsm_calendar(struct sparx5 *sparx5) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - int taxi; - struct sparx5_calendar_data *data; - int err = 0; -@@ -575,7 +561,7 @@ int sparx5_config_dsm_calendar(struct sp - return -ENOMEM; - - for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) { -- err = sparx5_dsm_calendar_calc(sparx5, taxi, data); -+ err = ops->dsm_calendar_calc(sparx5, taxi, data); - if (err) { - dev_err(sparx5->dev, "DSM calendar calculation failed\n"); - goto cal_out; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -994,6 +994,7 @@ static const struct sparx5_ops sparx5_op - .get_sdlb_group = &sparx5_get_sdlb_group, - .set_port_mux = &sparx5_port_mux_set, - .ptp_irq_handler = &sparx5_ptp_irq_handler, -+ .dsm_calendar_calc = &sparx5_dsm_calendar_calc, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -101,8 +101,24 @@ enum sparx5_vlan_port_type { - #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 - #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 - -+#define SPX5_DSM_CAL_LEN 64 -+#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 -+ - struct sparx5; - -+struct sparx5_calendar_data { -+ u32 schedule[SPX5_DSM_CAL_LEN]; -+ u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -+ u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -+ u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -+ u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; -+ u32 new_slots[SPX5_DSM_CAL_LEN]; -+ u32 temp_sched[SPX5_DSM_CAL_LEN]; -+ u32 indices[SPX5_DSM_CAL_LEN]; -+ u32 short_list[SPX5_DSM_CAL_LEN]; -+ u32 long_list[SPX5_DSM_CAL_LEN]; -+}; -+ - /* Frame DMA receive state: - * For each DB, there is a SKB, and the skb data pointer is mapped in - * the DB. Once a frame is received the skb is given to the upper layers -@@ -271,6 +287,8 @@ struct sparx5_ops { - struct sparx5_port_config *conf); - - irqreturn_t (*ptp_irq_handler)(int irq, void *args); -+ int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data); - }; - - struct sparx5_main_io_resource { -@@ -418,6 +436,9 @@ void sparx5_vlan_port_apply(struct sparx - /* sparx5_calendar.c */ - int sparx5_config_auto_calendar(struct sparx5 *sparx5); - int sparx5_config_dsm_calendar(struct sparx5 *sparx5); -+int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data); -+ - - /* sparx5_ethtool.c */ - void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); diff --git a/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch b/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch deleted file mode 100644 index ab475ed860..0000000000 --- a/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch +++ /dev/null @@ -1,267 +0,0 @@ -From 234d82beadb5fdf26dd9f469764e048f1ca4dd60 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:40 +0200 -Subject: [PATCH 42/82] net: sparx5: add is_sparx5 macro and use it throughout - -We dont want to ops out each time a function needs to do some platform -specifics. In particular we have a few places, where it would be -convenient to just branch out on the platform type. Add the function -is_sparx5() and, initially, use it for: - - - register writes that should only be done on Sparx5 (QSYS_CAL_CTRL, - CLKGEN_LCPLL1_CORE_CLK). - - - function calls that should only be done on Sparx5 - (ethtool_op_get_ts_info()) - - - register writes that are chip-exclusive (MASK_CFG1/2, PGID_CFG1/2, - these are replicated for n_ports >32 on Sparx5). - -The is_sparx5() function simply checks the target chip type, to -determine if this is a Sparx5 SKU or not. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jacob Keller -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_calendar.c | 7 +- - .../microchip/sparx5/sparx5_ethtool.c | 2 +- - .../ethernet/microchip/sparx5/sparx5_main.c | 88 ++++++++++++------- - .../ethernet/microchip/sparx5/sparx5_main.h | 3 + - .../ethernet/microchip/sparx5/sparx5_vlan.c | 42 ++++++--- - 5 files changed, 90 insertions(+), 52 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -194,9 +194,10 @@ int sparx5_config_auto_calendar(struct s - } - - /* Halt the calendar while changing it */ -- spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), -- QSYS_CAL_CTRL_CAL_MODE, -- sparx5, QSYS_CAL_CTRL); -+ if (is_sparx5(sparx5)) -+ spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), -+ QSYS_CAL_CTRL_CAL_MODE, -+ sparx5, QSYS_CAL_CTRL); - - /* Assign port bandwidth to auto calendar */ - for (idx = 0; idx < consts->n_auto_cals; idx++) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -@@ -1189,7 +1189,7 @@ static int sparx5_get_ts_info(struct net - struct sparx5 *sparx5 = port->sparx5; - struct sparx5_phc *phc; - -- if (!sparx5->ptp) -+ if (!sparx5->ptp && is_sparx5(sparx5)) - return ethtool_op_get_ts_info(dev, info); - - phc = &sparx5->phc[SPARX5_PHC_PORT]; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -208,6 +208,25 @@ static const struct sparx5_main_io_resou - { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ - }; - -+bool is_sparx5(struct sparx5 *sparx5) -+{ -+ switch (sparx5->target_ct) { -+ case SPX5_TARGET_CT_7546: -+ case SPX5_TARGET_CT_7549: -+ case SPX5_TARGET_CT_7552: -+ case SPX5_TARGET_CT_7556: -+ case SPX5_TARGET_CT_7558: -+ case SPX5_TARGET_CT_7546TSN: -+ case SPX5_TARGET_CT_7549TSN: -+ case SPX5_TARGET_CT_7552TSN: -+ case SPX5_TARGET_CT_7556TSN: -+ case SPX5_TARGET_CT_7558TSN: -+ return true; -+ default: -+ return false; -+ } -+} -+ - static int sparx5_create_targets(struct sparx5 *sparx5) - { - const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; -@@ -462,44 +481,45 @@ static int sparx5_init_coreclock(struct - return -ENODEV; - } - -- switch (freq) { -- case SPX5_CORE_CLOCK_250MHZ: -- clk_div = 10; -- pol_upd_int = 312; -- break; -- case SPX5_CORE_CLOCK_500MHZ: -- clk_div = 5; -- pol_upd_int = 624; -- break; -- case SPX5_CORE_CLOCK_625MHZ: -- clk_div = 4; -- pol_upd_int = 780; -- break; -- default: -- dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", -- sparx5->coreclock, sparx5->target_ct); -- return -EINVAL; -+ if (is_sparx5(sparx5)) { -+ switch (freq) { -+ case SPX5_CORE_CLOCK_250MHZ: -+ clk_div = 10; -+ pol_upd_int = 312; -+ break; -+ case SPX5_CORE_CLOCK_500MHZ: -+ clk_div = 5; -+ pol_upd_int = 624; -+ break; -+ case SPX5_CORE_CLOCK_625MHZ: -+ clk_div = 4; -+ pol_upd_int = 780; -+ break; -+ default: -+ dev_err(sparx5->dev, -+ "%d coreclock not supported on (%#04x)\n", -+ sparx5->coreclock, sparx5->target_ct); -+ return -EINVAL; -+ } -+ -+ /* Configure the LCPLL */ -+ spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | -+ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, -+ sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); - } - - /* Update state with chosen frequency */ - sparx5->coreclock = freq; -- -- /* Configure the LCPLL */ -- spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | -- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, -- sparx5, -- CLKGEN_LCPLL1_CORE_CLK_CFG); -- - clk_period = sparx5_clk_period(freq); - - spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -376,6 +376,9 @@ struct sparx5 { - const struct sparx5_match_data *data; - }; - -+/* sparx5_main.c */ -+bool is_sparx5(struct sparx5 *sparx5); -+ - /* sparx5_switchdev.c */ - int sparx5_register_notifier_blocks(struct sparx5 *sparx5); - void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -@@ -16,8 +16,10 @@ static int sparx5_vlant_set_mask(struct - - /* Output mask to respective registers */ - spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); -- spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); -- spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); -+ if (is_sparx5(sparx5)) { -+ spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); -+ spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); -+ } - - return 0; - } -@@ -141,15 +143,19 @@ void sparx5_pgid_update_mask(struct spar - void sparx5_pgid_clear(struct sparx5 *spx5, int pgid) - { - spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); -- spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); -- spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); -+ if (is_sparx5(spx5)) { -+ spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); -+ spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); -+ } - } - - void sparx5_pgid_read_mask(struct sparx5 *spx5, int pgid, u32 portmask[3]) - { - portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid)); -- portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); -- portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); -+ if (is_sparx5(spx5)) { -+ portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); -+ portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); -+ } - } - - void sparx5_update_fwd(struct sparx5 *sparx5) -@@ -164,8 +170,10 @@ void sparx5_update_fwd(struct sparx5 *sp - /* Update flood masks */ - for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) { - spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); -- spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); -- spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); -+ if (is_sparx5(sparx5)) { -+ spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); -+ spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); -+ } - } - - /* Update SRC masks */ -@@ -176,12 +184,16 @@ void sparx5_update_fwd(struct sparx5 *sp - clear_bit(port, workmask); - bitmap_to_arr32(mask, workmask, SPX5_PORTS); - spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); -- spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); -- spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); -+ if (is_sparx5(sparx5)) { -+ spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); -+ spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); -+ } - } else { - spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); -- spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); -- spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); -+ if (is_sparx5(sparx5)) { -+ spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); -+ spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); -+ } - } - } - -@@ -192,8 +204,10 @@ void sparx5_update_fwd(struct sparx5 *sp - - /* Apply learning mask */ - spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG); -- spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); -- spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); -+ if (is_sparx5(sparx5)) { -+ spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); -+ spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); -+ } - } - - void sparx5_vlan_port_apply(struct sparx5 *sparx5, diff --git a/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch b/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch deleted file mode 100644 index 3e0337237f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch +++ /dev/null @@ -1,351 +0,0 @@ -From 976b85797451b92683f78af10334ceda13d5f1e0 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 4 Oct 2024 15:19:41 +0200 -Subject: [PATCH 43/82] net: sparx5: redefine internal ports and PGID's as - offsets - -Internal ports and PGID's are both defined relative to the number of -front ports on Sparx5. This will not work on lan969x. Instead make them -offsets to the number of front ports and add two helpers to retrieve -them. Use the helpers throughout. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_calendar.c | 14 +++++--- - .../ethernet/microchip/sparx5/sparx5_fdma.c | 4 ++- - .../microchip/sparx5/sparx5_mactable.c | 3 +- - .../ethernet/microchip/sparx5/sparx5_main.c | 14 ++++---- - .../ethernet/microchip/sparx5/sparx5_main.h | 34 +++++++++---------- - .../ethernet/microchip/sparx5/sparx5_netdev.c | 6 ++-- - .../ethernet/microchip/sparx5/sparx5_packet.c | 4 ++- - .../ethernet/microchip/sparx5/sparx5_pgid.c | 13 +++++-- - .../ethernet/microchip/sparx5/sparx5_port.c | 5 +++ - .../microchip/sparx5/sparx5_switchdev.c | 31 ++++++++++++----- - .../ethernet/microchip/sparx5/sparx5_vlan.c | 3 +- - 11 files changed, 86 insertions(+), 45 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -118,16 +118,22 @@ static enum sparx5_cal_bw sparx5_get_por - - if (portno >= sparx5->data->consts->n_ports) { - /* Internal ports */ -- if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) { -+ if (portno == -+ sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || -+ portno == -+ sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) { - /* Equals 1.25G */ - return SPX5_CAL_SPEED_2G5; -- } else if (portno == SPX5_PORT_VD0) { -+ } else if (portno == -+ sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) { - /* IPMC only idle BW */ - return SPX5_CAL_SPEED_NONE; -- } else if (portno == SPX5_PORT_VD1) { -+ } else if (portno == -+ sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) { - /* OAM only idle BW */ - return SPX5_CAL_SPEED_NONE; -- } else if (portno == SPX5_PORT_VD2) { -+ } else if (portno == -+ sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) { - /* IPinIP gets only idle BW */ - return SPX5_CAL_SPEED_NONE; - } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -364,7 +364,9 @@ static void sparx5_fdma_injection_mode(s - sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); - - /* CPU ports capture setup */ -- for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { -+ for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); -+ portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); -+ portno++) { - /* ASM CPU port: No preamble, IFH, enable padding */ - spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | - ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) | ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c -@@ -129,7 +129,8 @@ int sparx5_mc_sync(struct net_device *de - struct sparx5_port *port = netdev_priv(dev); - struct sparx5 *sparx5 = port->sparx5; - -- return sparx5_mact_learn(sparx5, PGID_CPU, addr, port->pvid); -+ return sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), -+ addr, port->pvid); - } - - static int sparx5_mact_get(struct sparx5 *sparx5, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -649,13 +649,14 @@ static int sparx5_start(struct sparx5 *s - sparx5_update_fwd(sparx5); - - /* CPU copy CPU pgids */ -- spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), -- sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); -- spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), -- sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); -+ spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, -+ ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); -+ spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, -+ ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); - - /* Recalc injected frame FCS */ -- for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) -+ for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); -+ idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) - spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), - ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, - sparx5, ANA_CL_FILTER_CTRL(idx)); -@@ -670,7 +671,8 @@ static int sparx5_start(struct sparx5 *s - sparx5_vlan_init(sparx5); - - /* Add host mode BC address (points only to CPU) */ -- sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); -+ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, -+ NULL_VID); - - /* Enable queue limitation watermarks */ - sparx5_qlim_set(sparx5); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -54,23 +54,21 @@ enum sparx5_vlan_port_type { - #define SPX5_PORTS 65 - #define SPX5_PORTS_ALL 70 /* Total number of ports */ - --#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ --#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ --#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ --#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ --#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ --#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ -- --#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ --#define PGID_UC_FLOOD (PGID_BASE + 0) --#define PGID_MC_FLOOD (PGID_BASE + 1) --#define PGID_IPV4_MC_DATA (PGID_BASE + 2) --#define PGID_IPV4_MC_CTRL (PGID_BASE + 3) --#define PGID_IPV6_MC_DATA (PGID_BASE + 4) --#define PGID_IPV6_MC_CTRL (PGID_BASE + 5) --#define PGID_BCAST (PGID_BASE + 6) --#define PGID_CPU (PGID_BASE + 7) --#define PGID_MCAST_START (PGID_BASE + 8) -+#define SPX5_PORT_CPU_0 0 /* CPU Port 0 */ -+#define SPX5_PORT_CPU_1 1 /* CPU Port 1 */ -+#define SPX5_PORT_VD0 2 /* VD0/Port used for IPMC */ -+#define SPX5_PORT_VD1 3 /* VD1/Port used for AFI/OAM */ -+#define SPX5_PORT_VD2 4 /* VD2/Port used for IPinIP*/ -+ -+#define PGID_UC_FLOOD 0 -+#define PGID_MC_FLOOD 1 -+#define PGID_IPV4_MC_DATA 2 -+#define PGID_IPV4_MC_CTRL 3 -+#define PGID_IPV6_MC_DATA 4 -+#define PGID_IPV6_MC_CTRL 5 -+#define PGID_BCAST 6 -+#define PGID_CPU 7 -+#define PGID_MCAST_START 8 - - #define PGID_TABLE_SIZE 3290 - -@@ -500,6 +498,7 @@ enum sparx5_pgid_type { - void sparx5_pgid_init(struct sparx5 *spx5); - int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); - int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); -+int sparx5_get_pgid(struct sparx5 *sparx5, int pgid); - - /* sparx5_pool.c */ - struct sparx5_pool_entry { -@@ -516,6 +515,7 @@ int sparx5_pool_get_with_idx(struct spar - /* sparx5_port.c */ - int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, - struct sparx5_port_config *conf); -+int sparx5_get_internal_port(struct sparx5 *sparx5, int port); - - /* sparx5_sdlb.c */ - #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -68,7 +68,8 @@ void sparx5_set_port_ifh(struct sparx5 * - /* MISC.PIPELINE_ACT */ - ifh_encode_bitfield(ifh_hdr, 1, 42, 3); - /* FWD.SRC_PORT = CPU */ -- ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7); -+ ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), -+ 46, 7); - /* FWD.SFLOW_ID (disable SFlow sampling) */ - ifh_encode_bitfield(ifh_hdr, 124, 57, 7); - /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ -@@ -190,7 +191,8 @@ static int sparx5_set_mac_address(struct - sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); - - /* Add new */ -- sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); -+ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), -+ addr->sa_data, port->pvid); - - /* Record the address */ - eth_hw_addr_set(dev, addr->sa_data); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -317,7 +317,9 @@ int sparx5_manual_injection_mode(struct - sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); - - /* CPU ports capture setup */ -- for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { -+ for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); -+ portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); -+ portno++) { - /* ASM CPU port: No preamble, IFH, enable padding */ - spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | - ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) | ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c -@@ -11,7 +11,7 @@ void sparx5_pgid_init(struct sparx5 *spx - /* Reserved for unicast, flood control, broadcast, and CPU. - * These cannot be freed. - */ -- for (i = 0; i <= PGID_CPU; i++) -+ for (i = 0; i <= sparx5_get_pgid(spx5, PGID_CPU); i++) - spx5->pgid_map[i] = SPX5_PGID_RESERVED; - } - -@@ -22,7 +22,8 @@ int sparx5_pgid_alloc_mcast(struct sparx - /* The multicast area starts at index 65, but the first 7 - * are reserved for flood masks and CPU. Start alloc after that. - */ -- for (i = PGID_MCAST_START; i < spx5->data->consts->n_pgids; i++) { -+ for (i = sparx5_get_pgid(spx5, PGID_MCAST_START); -+ i < spx5->data->consts->n_pgids; i++) { - if (spx5->pgid_map[i] == SPX5_PGID_FREE) { - spx5->pgid_map[i] = SPX5_PGID_MULTICAST; - *idx = i; -@@ -35,7 +36,8 @@ int sparx5_pgid_alloc_mcast(struct sparx - - int sparx5_pgid_free(struct sparx5 *spx5, u16 idx) - { -- if (idx <= PGID_CPU || idx >= spx5->data->consts->n_pgids) -+ if (idx <= sparx5_get_pgid(spx5, PGID_CPU) || -+ idx >= spx5->data->consts->n_pgids) - return -EINVAL; - - if (spx5->pgid_map[idx] == SPX5_PGID_FREE) -@@ -44,3 +46,8 @@ int sparx5_pgid_free(struct sparx5 *spx5 - spx5->pgid_map[idx] = SPX5_PGID_FREE; - return 0; - } -+ -+int sparx5_get_pgid(struct sparx5 *sparx5, int pgid) -+{ -+ return sparx5->data->consts->n_ports + pgid; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -1352,3 +1352,8 @@ int sparx5_port_qos_default_set(const st - - return 0; - } -+ -+int sparx5_get_internal_port(struct sparx5 *sparx5, int port) -+{ -+ return sparx5->data->consts->n_ports + port; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -@@ -32,24 +32,34 @@ static int sparx5_port_attr_pre_bridge_f - static void sparx5_port_update_mcast_ip_flood(struct sparx5_port *port, bool flood_flag) - { - bool should_flood = flood_flag || port->is_mrouter; -+ struct sparx5 *sparx5 = port->sparx5; - int pgid; - -- for (pgid = PGID_IPV4_MC_DATA; pgid <= PGID_IPV6_MC_CTRL; pgid++) -+ for (pgid = sparx5_get_pgid(sparx5, PGID_IPV4_MC_DATA); -+ pgid <= sparx5_get_pgid(sparx5, PGID_IPV6_MC_CTRL); pgid++) - sparx5_pgid_update_mask(port, pgid, should_flood); - } - - static void sparx5_port_attr_bridge_flags(struct sparx5_port *port, - struct switchdev_brport_flags flags) - { -+ struct sparx5 *sparx5 = port->sparx5; -+ - if (flags.mask & BR_MCAST_FLOOD) { -- sparx5_pgid_update_mask(port, PGID_MC_FLOOD, !!(flags.val & BR_MCAST_FLOOD)); -+ sparx5_pgid_update_mask(port, -+ sparx5_get_pgid(sparx5, PGID_MC_FLOOD), -+ !!(flags.val & BR_MCAST_FLOOD)); - sparx5_port_update_mcast_ip_flood(port, !!(flags.val & BR_MCAST_FLOOD)); - } - - if (flags.mask & BR_FLOOD) -- sparx5_pgid_update_mask(port, PGID_UC_FLOOD, !!(flags.val & BR_FLOOD)); -+ sparx5_pgid_update_mask(port, -+ sparx5_get_pgid(sparx5, PGID_UC_FLOOD), -+ !!(flags.val & BR_FLOOD)); - if (flags.mask & BR_BCAST_FLOOD) -- sparx5_pgid_update_mask(port, PGID_BCAST, !!(flags.val & BR_BCAST_FLOOD)); -+ sparx5_pgid_update_mask(port, -+ sparx5_get_pgid(sparx5, PGID_BCAST), -+ !!(flags.val & BR_BCAST_FLOOD)); - } - - static void sparx5_attr_stp_state_set(struct sparx5_port *port, -@@ -219,7 +229,8 @@ static void sparx5_port_bridge_leave(str - port->vid = NULL_VID; - - /* Forward frames to CPU */ -- sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, 0); -+ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), -+ port->ndev->dev_addr, 0); - - /* Port enters in host more therefore restore mc list */ - __dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync); -@@ -254,7 +265,8 @@ static int sparx5_port_add_addr(struct n - u16 vid = port->pvid; - - if (up) -- sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, vid); -+ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), -+ port->ndev->dev_addr, vid); - else - sparx5_mact_forget(sparx5, port->ndev->dev_addr, vid); - -@@ -330,7 +342,8 @@ static void sparx5_switchdev_bridge_fdb_ - switch (switchdev_work->event) { - case SWITCHDEV_FDB_ADD_TO_DEVICE: - if (host_addr) -- sparx5_add_mact_entry(sparx5, dev, PGID_CPU, -+ sparx5_add_mact_entry(sparx5, dev, -+ sparx5_get_pgid(sparx5, PGID_CPU), - fdb_info->addr, vid); - else - sparx5_add_mact_entry(sparx5, port->ndev, port->portno, -@@ -418,8 +431,8 @@ static int sparx5_handle_port_vlan_add(s - switchdev_blocking_nb); - - /* Flood broadcast to CPU */ -- sparx5_mact_learn(sparx5, PGID_BCAST, dev->broadcast, -- v->vid); -+ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_BCAST), -+ dev->broadcast, v->vid); - return 0; - } - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -@@ -168,7 +168,8 @@ void sparx5_update_fwd(struct sparx5 *sp - bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS); - - /* Update flood masks */ -- for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) { -+ for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); -+ port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) { - spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); - if (is_sparx5(sparx5)) { - spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); diff --git a/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch b/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch deleted file mode 100644 index be9c440c6f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch +++ /dev/null @@ -1,169 +0,0 @@ -From 3ba2228de3c42509cddd592fd7e61e1f2738b95e Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:20 +0200 -Subject: [PATCH 44/82] net: sparx5: add support for lan969x targets and core - clock - -In preparation for lan969x, add lan969x targets to -sparx5_target_chiptype and set the core clock frequency for these -throughout. Lan969x only supports a core clock frequency of 328MHz. - -Also, set the policer update internal (pol_upd_int) matching the 328 MHz -frequency of the lan969x targets. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-1-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../microchip/sparx5/sparx5_calendar.c | 17 +++++++++ - .../ethernet/microchip/sparx5/sparx5_main.c | 16 +++++++++ - .../ethernet/microchip/sparx5/sparx5_main.h | 35 +++++++++++++------ - .../ethernet/microchip/sparx5/sparx5_ptp.c | 6 ++++ - 4 files changed, 64 insertions(+), 10 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -53,6 +53,22 @@ static u32 sparx5_target_bandwidth(struc - case SPX5_TARGET_CT_7558: - case SPX5_TARGET_CT_7558TSN: - return 201000; -+ case SPX5_TARGET_CT_LAN9691VAO: -+ return 46000; -+ case SPX5_TARGET_CT_LAN9694RED: -+ case SPX5_TARGET_CT_LAN9694TSN: -+ case SPX5_TARGET_CT_LAN9694: -+ return 68000; -+ case SPX5_TARGET_CT_LAN9696RED: -+ case SPX5_TARGET_CT_LAN9696TSN: -+ case SPX5_TARGET_CT_LAN9692VAO: -+ case SPX5_TARGET_CT_LAN9696: -+ return 88000; -+ case SPX5_TARGET_CT_LAN9698RED: -+ case SPX5_TARGET_CT_LAN9698TSN: -+ case SPX5_TARGET_CT_LAN9693VAO: -+ case SPX5_TARGET_CT_LAN9698: -+ return 101000; - default: - return 0; - } -@@ -74,6 +90,7 @@ static u32 sparx5_clk_to_bandwidth(enum - { - switch (cclock) { - case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */ -+ case SPX5_CORE_CLOCK_328MHZ: return 109375; /* 328000 / 3 */ - case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */ - case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */ - default: return 0; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -475,6 +475,20 @@ static int sparx5_init_coreclock(struct - else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) - freq = 0; /* Not supported */ - break; -+ case SPX5_TARGET_CT_LAN9694: -+ case SPX5_TARGET_CT_LAN9691VAO: -+ case SPX5_TARGET_CT_LAN9694TSN: -+ case SPX5_TARGET_CT_LAN9694RED: -+ case SPX5_TARGET_CT_LAN9696: -+ case SPX5_TARGET_CT_LAN9692VAO: -+ case SPX5_TARGET_CT_LAN9696TSN: -+ case SPX5_TARGET_CT_LAN9696RED: -+ case SPX5_TARGET_CT_LAN9698: -+ case SPX5_TARGET_CT_LAN9693VAO: -+ case SPX5_TARGET_CT_LAN9698TSN: -+ case SPX5_TARGET_CT_LAN9698RED: -+ freq = SPX5_CORE_CLOCK_328MHZ; -+ break; - default: - dev_err(sparx5->dev, "Target (%#04x) not supported\n", - sparx5->target_ct); -@@ -516,6 +530,8 @@ static int sparx5_init_coreclock(struct - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, - sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); -+ } else { -+ pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ - } - - /* Update state with chosen frequency */ ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -26,16 +26,28 @@ - - /* Target chip type */ - enum spx5_target_chiptype { -- SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ -- SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ -- SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ -- SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ -- SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ -- SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ -- SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ -- SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ -- SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ -- SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ -+ SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ -+ SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ -+ SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ -+ SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ -+ SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ -+ SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ -+ SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ -+ SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ -+ SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ -+ SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ -+ SPX5_TARGET_CT_LAN9694 = 0x9694, /* lan969x-40 */ -+ SPX5_TARGET_CT_LAN9691VAO = 0x9691, /* lan969x-40-VAO */ -+ SPX5_TARGET_CT_LAN9694TSN = 0x9695, /* lan969x-40-TSN */ -+ SPX5_TARGET_CT_LAN9694RED = 0x969A, /* lan969x-40-RED */ -+ SPX5_TARGET_CT_LAN9696 = 0x9696, /* lan969x-60 */ -+ SPX5_TARGET_CT_LAN9692VAO = 0x9692, /* lan969x-65-VAO */ -+ SPX5_TARGET_CT_LAN9696TSN = 0x9697, /* lan969x-60-TSN */ -+ SPX5_TARGET_CT_LAN9696RED = 0x969B, /* lan969x-60-RED */ -+ SPX5_TARGET_CT_LAN9698 = 0x9698, /* lan969x-100 */ -+ SPX5_TARGET_CT_LAN9693VAO = 0x9693, /* lan969x-100-VAO */ -+ SPX5_TARGET_CT_LAN9698TSN = 0x9699, /* lan969x-100-TSN */ -+ SPX5_TARGET_CT_LAN9698RED = 0x969C, /* lan969x-100-RED */ - }; - - enum sparx5_port_max_tags { -@@ -192,6 +204,7 @@ struct sparx5_port { - enum sparx5_core_clockfreq { - SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ - SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ -+ SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */ - SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ - SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ - }; -@@ -641,6 +654,8 @@ static inline u32 sparx5_clk_period(enum - switch (cclock) { - case SPX5_CORE_CLOCK_250MHZ: - return 4000; -+ case SPX5_CORE_CLOCK_328MHZ: -+ return 3048; - case SPX5_CORE_CLOCK_500MHZ: - return 2000; - case SPX5_CORE_CLOCK_625MHZ: ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -@@ -38,6 +38,9 @@ static u64 sparx5_ptp_get_1ppm(struct sp - case SPX5_CORE_CLOCK_250MHZ: - res = 2301339409586; - break; -+ case SPX5_CORE_CLOCK_328MHZ: -+ res = 1756832768924; -+ break; - case SPX5_CORE_CLOCK_500MHZ: - res = 1150669704793; - break; -@@ -60,6 +63,9 @@ static u64 sparx5_ptp_get_nominal_value( - case SPX5_CORE_CLOCK_250MHZ: - res = 0x1FF0000000000000; - break; -+ case SPX5_CORE_CLOCK_328MHZ: -+ res = 0x18604697DD0F9B5B; -+ break; - case SPX5_CORE_CLOCK_500MHZ: - res = 0x0FF8000000000000; - break; diff --git a/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch b/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch deleted file mode 100644 index e000abdaa2..0000000000 --- a/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 4feb1d4bb1cc58d86ef8c19091ba4b2785784e08 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:21 +0200 -Subject: [PATCH 45/82] net: sparx5: change spx5_wr to spx5_rmw in cal update() - -In preparation for lan969x, use spx5_rmw() for enabling the update of -the calendar. This is required to not overwrite the DSM_TAXI_CAL_CFG -register, as an additional write will be added before this one, in a -subsequent patch. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-2-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_calendar.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -546,9 +546,10 @@ static int sparx5_dsm_calendar_update(st - u32 idx; - u32 cal_len = sparx5_dsm_cal_len(data->schedule), len; - -- spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), -- sparx5, -- DSM_TAXI_CAL_CFG(taxi)); -+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), -+ DSM_TAXI_CAL_CFG_CAL_PGM_ENA, -+ sparx5, -+ DSM_TAXI_CAL_CFG(taxi)); - for (idx = 0; idx < cal_len; idx++) { - spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), - DSM_TAXI_CAL_CFG_CAL_IDX, -@@ -559,9 +560,10 @@ static int sparx5_dsm_calendar_update(st - sparx5, - DSM_TAXI_CAL_CFG(taxi)); - } -- spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), -- sparx5, -- DSM_TAXI_CAL_CFG(taxi)); -+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), -+ DSM_TAXI_CAL_CFG_CAL_PGM_ENA, -+ sparx5, -+ DSM_TAXI_CAL_CFG(taxi)); - len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5, - DSM_TAXI_CAL_CFG(taxi))); - if (len != cal_len - 1) diff --git a/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch b/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch deleted file mode 100644 index adc46b6c12..0000000000 --- a/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6e50593002ad4886e2d74e99b67e735cbab0c606 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:22 +0200 -Subject: [PATCH 46/82] net: sparx5: change frequency calculation for SDLB's - -In preparation for lan969x, rework the function that calculates the SDLB -(Service Dual Leacky Bucket) clock. This is required, as the -HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock -from the core clock, using the sparx5_clk_period() function. The clock -stays the same before and after this patch, only now, -sparx5_sdlb_clk_hz_get() can be used for lan969x too. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 +- - drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 10 +++------- - 2 files changed, 4 insertions(+), 8 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdl - int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, - u64 rate); - --int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); -+u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); - int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); - int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c -@@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdl - return &sdlb_groups[idx]; - } - --int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) -+u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) - { -- u32 clk_per_100ps; - u64 clk_hz; - -- clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, -- HSCH_SYS_CLK_PER)); -- if (!clk_per_100ps) -- clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT; -+ clk_hz = (10 * 1000 * 1000) / -+ (sparx5_clk_period(sparx5->coreclock) / 100); - -- clk_hz = (10 * 1000 * 1000) / clk_per_100ps; - return clk_hz *= 1000; - } - diff --git a/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch b/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch deleted file mode 100644 index 2ea8da484c..0000000000 --- a/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 6e84c752630600be74db11feae869d333c55fe1c Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:23 +0200 -Subject: [PATCH 47/82] net: sparx5: add sparx5 context pointer to a few - functions - -In preparation for lan969x, add the sparx5 context pointer to certain -IFH (Internal Frame Header) functions. This is required, as the -is_sparx5() function will be used here in a subsequent patch. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-4-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 2 +- - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 11 +++++++---- - .../net/ethernet/microchip/sparx5/sparx5_netdev.c | 9 ++++++--- - .../net/ethernet/microchip/sparx5/sparx5_packet.c | 13 ++++++++----- - 4 files changed, 22 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -154,7 +154,7 @@ static bool sparx5_fdma_rx_get_frame(str - skb = rx->skb[fdma->dcb_index][fdma->db_index]; - skb_put(skb, fdma_db_len_get(db_hw)); - /* Now do the normal processing of the skb */ -- sparx5_ifh_parse((u32 *)skb->data, &fi); -+ sparx5_ifh_parse(sparx5, (u32 *)skb->data, &fi); - /* Map to port netdev */ - port = fi.src_port < sparx5->data->consts->n_ports ? - sparx5->ports[fi.src_port] : ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -401,7 +401,7 @@ struct frame_info { - }; - - void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); --void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); -+void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info); - irqreturn_t sparx5_xtr_handler(int irq, void *_priv); - netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); - int sparx5_manual_injection_mode(struct sparx5 *sparx5); -@@ -469,10 +469,13 @@ static inline int sparx5_dcb_init(struct - #endif - - /* sparx5_netdev.c */ --void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); -+void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, -+ u64 timestamp); - void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); --void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); --void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); -+void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, -+ u32 pdu_type); -+void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, -+ u32 pdu_w16_offset); - void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); - bool sparx5_netdevice_check(const struct net_device *dev); - struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -81,17 +81,20 @@ void sparx5_set_port_ifh_rew_op(void *if - ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10); - } - --void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type) -+void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, -+ u32 pdu_type) - { - ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); - } - --void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset) -+void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, -+ u32 pdu_w16_offset) - { - ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); - } - --void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp) -+void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, -+ u64 timestamp) - { - ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); - } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -32,7 +32,7 @@ void sparx5_xtr_flush(struct sparx5 *spa - spx5_wr(0, sparx5, QS_XTR_FLUSH); - } - --void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) -+void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) - { - u8 *xtr_hdr = (u8 *)ifh; - -@@ -72,7 +72,7 @@ static void sparx5_xtr_grp(struct sparx5 - ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); - - /* Decode IFH (what's needed) */ -- sparx5_ifh_parse(ifh, &fi); -+ sparx5_ifh_parse(sparx5, ifh, &fi); - - /* Map to port netdev */ - port = fi.src_port < sparx5->data->consts->n_ports ? -@@ -242,9 +242,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct - return NETDEV_TX_BUSY; - - sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op); -- sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type); -- sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offset); -- sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id); -+ sparx5_set_port_ifh_pdu_type(sparx5, ifh, -+ SPARX5_SKB_CB(skb)->pdu_type); -+ sparx5_set_port_ifh_pdu_w16_offset(sparx5, ifh, -+ SPARX5_SKB_CB(skb)->pdu_w16_offset); -+ sparx5_set_port_ifh_timestamp(sparx5, ifh, -+ SPARX5_SKB_CB(skb)->ts_id); - } - - skb_tx_timestamp(skb); diff --git a/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch b/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch deleted file mode 100644 index 58df536635..0000000000 --- a/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 79009c7ee726a104e4d67c99ef5b53db31a39549 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:24 +0200 -Subject: [PATCH 48/82] net: sparx5: add registers required by lan969x - -Lan969x will require a few additional registers for certain operations. -Some are shared, some are not. Add these. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-5-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../microchip/sparx5/sparx5_main_regs.h | 132 ++++++++++++++++++ - 1 file changed, 132 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -@@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs; - #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ - FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) - -+/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ -+#define DEV2G5_PHAD_CTRL(t, g) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ -+ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) -+ -+#define DEV2G5_PHAD_CTRL_PHAD_ENA\ -+ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) -+#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ -+ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) -+#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ -+ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) -+ -+/* LAN969X ONLY */ -+#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) -+#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ -+ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) -+#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ -+ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) -+ -+/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ -+#define DEV2G5_PHAD_CTRL(t, g) \ -+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ -+ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) -+ -+#define DEV2G5_PHAD_CTRL_PHAD_ENA\ -+ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) -+#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ -+ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) -+#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ -+ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) -+ -+/* LAN969X ONLY */ -+#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) -+#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ -+ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) -+#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ -+ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) -+ - /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ - #define DEV10G_MAC_ENA_CFG(t) \ - __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ -@@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs; - #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) - -+/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ -+#define DEV10G_PTP_STAMPER_CFG(t) \ -+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \ -+ 1, 4) -+ - /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ - #define DEV10G_PCS25G_CFG(t) \ - __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ -@@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs; - #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ - FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) - -+/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ -+#define DEV5G_PTP_STAMPER_CFG(t) \ -+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \ -+ 4) -+ - /* DSM:RAM_CTRL:RAM_INIT */ - #define DSM_RAM_INIT \ - __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) -@@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs; - #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ - FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) - -+/* LAN969X ONLY */ -+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23) -+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\ -+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) -+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\ -+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) -+ -+/* LAN969X ONLY */ -+#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22) -+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\ -+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) -+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\ -+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) -+ -+/* LAN969X ONLY */ -+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21) -+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\ -+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) -+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\ -+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) -+ - /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ - #define EACL_VCAP_ES2_KEY_SEL(g, r) \ - __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ -@@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs; - regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ - regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) - -+/* LAN969X ONLY */ -+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ -+#define PTP_TWOSTEP_CTRL \ -+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4) -+ -+#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) -+#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) -+#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) -+ -+#define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) -+#define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x) -+#define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x) -+ -+#define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) -+#define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x) -+#define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x) -+ -+#define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) -+#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) -+#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) -+ -+#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) -+#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) -+#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) -+ -+#define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) -+#define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x) -+#define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x) -+ -+/* LAN969X ONLY */ -+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */ -+#define PTP_TWOSTEP_STAMP_NSEC \ -+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4) -+ -+#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0) -+#define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x) -+#define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x) -+ -+/* LAN969X ONLY */ -+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */ -+#define PTP_TWOSTEP_STAMP_SUBNS \ -+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4) -+ -+#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0) -+#define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\ -+ FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x) -+#define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\ -+ FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x) -+ - /* QFWD:SYSTEM:SWITCH_PORT_MODE */ - #define QFWD_SWITCH_PORT_MODE(r) \ - __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ diff --git a/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch b/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch deleted file mode 100644 index b3a9355e47..0000000000 --- a/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch +++ /dev/null @@ -1,216 +0,0 @@ -From 033defe6fd3cc5b5b90c31d7bf0effe27772adbd Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:25 +0200 -Subject: [PATCH 49/82] net: lan969x: add match data for lan969x - -Add match data for lan969x, with initial fields for iomap, iomap_size -and ioranges. Add new Kconfig symbol CONFIG_LAN969X_CONFIG for compiling -the lan969x driver. - -It has been decided to give lan969x its own Kconfig symbol, as a -considerable amount of code is needed, beside the Sparx5 code, to add -full chip support (and more will be added in future series). Also this -makes it possible to compile Sparx5 without lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-6-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - MAINTAINERS | 7 ++ - drivers/net/ethernet/microchip/Kconfig | 1 + - drivers/net/ethernet/microchip/Makefile | 1 + - .../net/ethernet/microchip/lan969x/Kconfig | 5 + - .../net/ethernet/microchip/lan969x/Makefile | 12 ++ - .../net/ethernet/microchip/lan969x/lan969x.c | 104 ++++++++++++++++++ - .../net/ethernet/microchip/lan969x/lan969x.h | 15 +++ - 7 files changed, 145 insertions(+) - create mode 100644 drivers/net/ethernet/microchip/lan969x/Kconfig - create mode 100644 drivers/net/ethernet/microchip/lan969x/Makefile - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x.c - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x.h - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -15160,6 +15160,13 @@ S: Maintained - F: Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml - F: drivers/irqchip/irq-lan966x-oic.c - -+MICROCHIP LAN969X ETHERNET DRIVER -+M: Daniel Machon -+M: UNGLinuxDriver@microchip.com -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/ethernet/microchip/lan969x/* -+ - MICROCHIP LCDFB DRIVER - M: Nicolas Ferre - L: linux-fbdev@vger.kernel.org ---- a/drivers/net/ethernet/microchip/Kconfig -+++ b/drivers/net/ethernet/microchip/Kconfig -@@ -59,6 +59,7 @@ config LAN743X - - source "drivers/net/ethernet/microchip/lan865x/Kconfig" - source "drivers/net/ethernet/microchip/lan966x/Kconfig" -+source "drivers/net/ethernet/microchip/lan969x/Kconfig" - source "drivers/net/ethernet/microchip/sparx5/Kconfig" - source "drivers/net/ethernet/microchip/vcap/Kconfig" - source "drivers/net/ethernet/microchip/fdma/Kconfig" ---- a/drivers/net/ethernet/microchip/Makefile -+++ b/drivers/net/ethernet/microchip/Makefile -@@ -11,6 +11,7 @@ lan743x-objs := lan743x_main.o lan743x_e - - obj-$(CONFIG_LAN865X) += lan865x/ - obj-$(CONFIG_LAN966X_SWITCH) += lan966x/ -+obj-$(CONFIG_LAN969X_SWITCH) += lan969x/ - obj-$(CONFIG_SPARX5_SWITCH) += sparx5/ - obj-$(CONFIG_VCAP) += vcap/ - obj-$(CONFIG_FDMA) += fdma/ ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/Kconfig -@@ -0,0 +1,5 @@ -+config LAN969X_SWITCH -+ tristate "Lan969x switch driver" -+ depends on SPARX5_SWITCH -+ help -+ This driver supports the lan969x family of network switch devices. ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -0,0 +1,12 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+# -+# Makefile for the Microchip lan969x network device drivers. -+# -+ -+obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o -+ -+lan969x-switch-y := lan969x.o -+ -+# Provide include files -+ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma -+ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -0,0 +1,104 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "lan969x.h" -+ -+static const struct sparx5_main_io_resource lan969x_main_iomap[] = { -+ { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ -+ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ -+ { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ -+ { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ -+ { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ -+ { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ -+ { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ -+ { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ -+ { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ -+ { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ -+ { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ -+ { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ -+ { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ -+ { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ -+ { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ -+ { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ -+ { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ -+ { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ -+ { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ -+ { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ -+ { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ -+ { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ -+ { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ -+ { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ -+ { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ -+ { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ -+ { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ -+ { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ -+ { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ -+ { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ -+ { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ -+ { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ -+ { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ -+ { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ -+ { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ -+ { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ -+ { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ -+ { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ -+ { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ -+ { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ -+ { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ -+ { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ -+ { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ -+ { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ -+ { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ -+ { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ -+ { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ -+ { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ -+ { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ -+ { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ -+ { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ -+ { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ -+ { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ -+ { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ -+ { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ -+ { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ -+ { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ -+ { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ -+ { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ -+ { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ -+ { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ -+ { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ -+ { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ -+ { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ -+ { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ -+ { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ -+ { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ -+ { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ -+ { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ -+ { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ -+ { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ -+ { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ -+ { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ -+ { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ -+ { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ -+ { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ -+ { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ -+ { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ -+ { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ -+ { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ -+ { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ -+ { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ -+ { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ -+}; -+ -+const struct sparx5_match_data lan969x_desc = { -+ .iomap = lan969x_main_iomap, -+ .iomap_size = ARRAY_SIZE(lan969x_main_iomap), -+ .ioranges = 2, -+}; -+EXPORT_SYMBOL_GPL(lan969x_desc); -+ -+MODULE_DESCRIPTION("Microchip lan969x switch driver"); -+MODULE_AUTHOR("Daniel Machon "); -+MODULE_LICENSE("Dual MIT/GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#ifndef __LAN969X_H__ -+#define __LAN969X_H__ -+ -+#include "../sparx5/sparx5_main.h" -+ -+/* lan969x.c */ -+extern const struct sparx5_match_data lan969x_desc; -+ -+#endif diff --git a/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch deleted file mode 100644 index 059faf0f04..0000000000 --- a/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch +++ /dev/null @@ -1,365 +0,0 @@ -From d68c6bbfd6ba14f5c2987a59f1d6fb4a4688204e Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:26 +0200 -Subject: [PATCH 50/82] net: lan969x: add register diffs to match data - -Add new file lan969x_regs.c that defines all the register differences -for lan969x, and add it to the lan969x match data. - -GW_DEV2G5_PHASE_DETECTOR_CTRL, FP_DEV2G5_PHAD_CTRL_PHAD_ENA and -FP_DEV2G5_PHAD_CTRL_PHAD_FAILED are required by the new register macros -which was introduced earlier. Add these for Sparx5 also. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-7-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/lan969x/Makefile | 2 +- - .../net/ethernet/microchip/lan969x/lan969x.c | 12 + - .../net/ethernet/microchip/lan969x/lan969x.h | 11 + - .../ethernet/microchip/lan969x/lan969x_regs.c | 222 ++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_regs.c | 5 +- - .../ethernet/microchip/sparx5/sparx5_regs.h | 5 +- - 6 files changed, 254 insertions(+), 3 deletions(-) - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_regs.c - ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -5,7 +5,7 @@ - - obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o - --lan969x-switch-y := lan969x.o -+lan969x-switch-y := lan969x_regs.o lan969x.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -92,10 +92,22 @@ static const struct sparx5_main_io_resou - { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ - }; - -+static const struct sparx5_regs lan969x_regs = { -+ .tsize = lan969x_tsize, -+ .gaddr = lan969x_gaddr, -+ .gcnt = lan969x_gcnt, -+ .gsize = lan969x_gsize, -+ .raddr = lan969x_raddr, -+ .rcnt = lan969x_rcnt, -+ .fpos = lan969x_fpos, -+ .fsize = lan969x_fsize, -+}; -+ - const struct sparx5_match_data lan969x_desc = { - .iomap = lan969x_main_iomap, - .iomap_size = ARRAY_SIZE(lan969x_main_iomap), - .ioranges = 2, -+ .regs = &lan969x_regs, - }; - EXPORT_SYMBOL_GPL(lan969x_desc); - ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -8,8 +8,19 @@ - #define __LAN969X_H__ - - #include "../sparx5/sparx5_main.h" -+#include "../sparx5/sparx5_regs.h" - - /* lan969x.c */ - extern const struct sparx5_match_data lan969x_desc; - -+/* lan969x_regs.c */ -+extern const unsigned int lan969x_tsize[TSIZE_LAST]; -+extern const unsigned int lan969x_raddr[RADDR_LAST]; -+extern const unsigned int lan969x_rcnt[RCNT_LAST]; -+extern const unsigned int lan969x_gaddr[GADDR_LAST]; -+extern const unsigned int lan969x_gcnt[GCNT_LAST]; -+extern const unsigned int lan969x_gsize[GSIZE_LAST]; -+extern const unsigned int lan969x_fpos[FPOS_LAST]; -+extern const unsigned int lan969x_fsize[FSIZE_LAST]; -+ - #endif ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c -@@ -0,0 +1,222 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. -+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b -+ */ -+ -+#include "lan969x.h" -+ -+const unsigned int lan969x_tsize[TSIZE_LAST] = { -+ [TC_DEV10G] = 10, -+ [TC_DEV2G5] = 28, -+ [TC_DEV5G] = 4, -+ [TC_PCS10G_BR] = 10, -+ [TC_PCS5G_BR] = 4, -+}; -+ -+const unsigned int lan969x_raddr[RADDR_LAST] = { -+ [RA_CPU_PROC_CTRL] = 160, -+ [RA_GCB_SOFT_RST] = 12, -+ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, -+}; -+ -+const unsigned int lan969x_rcnt[RCNT_LAST] = { -+ [RC_ANA_AC_OWN_UPSID] = 1, -+ [RC_ANA_ACL_VCAP_S2_CFG] = 35, -+ [RC_ANA_ACL_OWN_UPSID] = 1, -+ [RC_ANA_CL_OWN_UPSID] = 1, -+ [RC_ANA_L2_OWN_UPSID] = 1, -+ [RC_ASM_PORT_CFG] = 32, -+ [RC_DSM_BUF_CFG] = 32, -+ [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, -+ [RC_DSM_RX_PAUSE_CFG] = 32, -+ [RC_DSM_MAC_CFG] = 32, -+ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, -+ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, -+ [RC_DSM_TAXI_CAL_CFG] = 6, -+ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, -+ [RC_HSCH_PORT_MODE] = 35, -+ [RC_QFWD_SWITCH_PORT_MODE] = 35, -+ [RC_QSYS_PAUSE_CFG] = 35, -+ [RC_QSYS_ATOP] = 35, -+ [RC_QSYS_FWD_PRESSURE] = 35, -+ [RC_QSYS_CAL_AUTO] = 4, -+ [RC_REW_OWN_UPSID] = 1, -+ [RC_REW_RTAG_ETAG_CTRL] = 35, -+}; -+ -+const unsigned int lan969x_gaddr[GADDR_LAST] = { -+ [GA_ANA_AC_RAM_CTRL] = 202000, -+ [GA_ANA_AC_PS_COMMON] = 202880, -+ [GA_ANA_AC_MIRROR_PROBE] = 203232, -+ [GA_ANA_AC_SRC] = 201728, -+ [GA_ANA_AC_PGID] = 131072, -+ [GA_ANA_AC_TSN_SF] = 202028, -+ [GA_ANA_AC_TSN_SF_CFG] = 148480, -+ [GA_ANA_AC_TSN_SF_STATUS] = 147936, -+ [GA_ANA_AC_SG_ACCESS] = 202032, -+ [GA_ANA_AC_SG_CONFIG] = 202752, -+ [GA_ANA_AC_SG_STATUS] = 147952, -+ [GA_ANA_AC_SG_STATUS_STICKY] = 202044, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, -+ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, -+ [GA_ANA_ACL_COMMON] = 8192, -+ [GA_ANA_ACL_KEY_SEL] = 9204, -+ [GA_ANA_ACL_CNT_B] = 4096, -+ [GA_ANA_ACL_STICKY] = 10852, -+ [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, -+ [GA_ANA_AC_POL_COMMON_BDLB] = 19464, -+ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, -+ [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, -+ [GA_ANA_CL_PORT] = 65536, -+ [GA_ANA_CL_COMMON] = 87040, -+ [GA_ANA_L2_COMMON] = 561928, -+ [GA_ANA_L3_COMMON] = 370752, -+ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, -+ [GA_ASM_CFG] = 18304, -+ [GA_ASM_PFC_TIMER_CFG] = 15568, -+ [GA_ASM_LBK_WM_CFG] = 15596, -+ [GA_ASM_LBK_MISC_CFG] = 15608, -+ [GA_ASM_RAM_CTRL] = 15684, -+ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, -+ [GA_EACL_CNT_TBL] = 30720, -+ [GA_EACL_POL_CFG] = 38400, -+ [GA_EACL_ES2_STICKY] = 29072, -+ [GA_EACL_RAM_CTRL] = 29112, -+ [GA_GCB_SIO_CTRL] = 560, -+ [GA_HSCH_HSCH_DWRR] = 36480, -+ [GA_HSCH_HSCH_MISC] = 36608, -+ [GA_HSCH_HSCH_LEAK_LISTS] = 37256, -+ [GA_HSCH_SYSTEM] = 37384, -+ [GA_HSCH_MMGT] = 36260, -+ [GA_HSCH_TAS_CONFIG] = 37696, -+ [GA_PTP_PTP_CFG] = 512, -+ [GA_PTP_PTP_TOD_DOMAINS] = 528, -+ [GA_PTP_PHASE_DETECTOR_CTRL] = 628, -+ [GA_QSYS_CALCFG] = 2164, -+ [GA_QSYS_RAM_CTRL] = 2204, -+ [GA_REW_COMMON] = 98304, -+ [GA_REW_PORT] = 49152, -+ [GA_REW_VOE_PORT_LM_CNT] = 90112, -+ [GA_REW_RAM_CTRL] = 93992, -+ [GA_VOP_RAM_CTRL] = 16368, -+ [GA_XQS_SYSTEM] = 5744, -+ [GA_XQS_QLIMIT_SHR] = 6912, -+}; -+ -+const unsigned int lan969x_gcnt[GCNT_LAST] = { -+ [GC_ANA_AC_SRC] = 67, -+ [GC_ANA_AC_PGID] = 1054, -+ [GC_ANA_AC_TSN_SF_CFG] = 256, -+ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, -+ [GC_ANA_ACL_KEY_SEL] = 99, -+ [GC_ANA_ACL_CNT_A] = 1024, -+ [GC_ANA_ACL_CNT_B] = 1024, -+ [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, -+ [GC_ANA_AC_SDLB_LBSET_TBL] = 496, -+ [GC_ANA_CL_PORT] = 35, -+ [GC_ANA_L2_ISDX_LIMIT] = 256, -+ [GC_ANA_L2_ISDX] = 1024, -+ [GC_ANA_L3_VLAN] = 4608, -+ [GC_ASM_DEV_STATISTICS] = 30, -+ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, -+ [GC_EACL_CNT_TBL] = 512, -+ [GC_GCB_SIO_CTRL] = 1, -+ [GC_HSCH_HSCH_CFG] = 1120, -+ [GC_HSCH_HSCH_DWRR] = 32, -+ [GC_PTP_PTP_PINS] = 8, -+ [GC_PTP_PHASE_DETECTOR_CTRL] = 8, -+ [GC_REW_PORT] = 35, -+ [GC_REW_VOE_PORT_LM_CNT] = 240, -+}; -+ -+const unsigned int lan969x_gsize[GSIZE_LAST] = { -+ [GW_ANA_AC_SRC] = 4, -+ [GW_ANA_L2_COMMON] = 712, -+ [GW_ASM_CFG] = 1092, -+ [GW_CPU_CPU_REGS] = 180, -+ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, -+ [GW_FDMA_FDMA] = 448, -+ [GW_GCB_CHIP_REGS] = 180, -+ [GW_HSCH_TAS_CONFIG] = 16, -+ [GW_PTP_PHASE_DETECTOR_CTRL] = 12, -+ [GW_QSYS_PAUSE_CFG] = 988, -+}; -+ -+const unsigned int lan969x_fpos[FPOS_LAST] = { -+ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, -+ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, -+ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, -+ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, -+ [FP_CPU_PROC_CTRL_VINITHI] = 3, -+ [FP_CPU_PROC_CTRL_CFGTE] = 2, -+ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, -+ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, -+ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, -+ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, -+ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, -+ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, -+ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, -+ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, -+}; -+ -+const unsigned int lan969x_fsize[FSIZE_LAST] = { -+ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, -+ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, -+ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, -+ [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, -+ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, -+ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, -+ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, -+ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, -+ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, -+ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, -+ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, -+ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, -+ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, -+ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, -+ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, -+ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, -+ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, -+ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, -+ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, -+ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, -+ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, -+ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, -+ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, -+ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, -+ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, -+ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, -+ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, -+ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, -+ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, -+ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, -+ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, -+ [FW_QRES_RES_CFG_WM_HIGH] = 11, -+ [FW_QRES_RES_STAT_MAXUSE] = 19, -+ [FW_QRES_RES_STAT_CUR_INUSE] = 19, -+ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, -+ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, -+ [FW_QSYS_ATOP_ATOP] = 11, -+ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, -+ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, -+ [FW_XQS_STAT_CFG_STAT_VIEW] = 10, -+ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, -+ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, -+ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, -+ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, -+}; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c -@@ -4,7 +4,7 @@ - * Copyright (c) 2024 Microchip Technology Inc. - */ - --/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. -+/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. - * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b - */ - -@@ -140,6 +140,7 @@ const unsigned int sparx5_gsize[GSIZE_LA - [GW_ANA_L2_COMMON] = 700, - [GW_ASM_CFG] = 1088, - [GW_CPU_CPU_REGS] = 204, -+ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 8, - [GW_FDMA_FDMA] = 428, - [GW_GCB_CHIP_REGS] = 424, - [GW_HSCH_TAS_CONFIG] = 12, -@@ -157,6 +158,8 @@ const unsigned int sparx5_fpos[FPOS_LAST - [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, - [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, - [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 7, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 6, - [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, - [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, - [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h -@@ -4,7 +4,7 @@ - * Copyright (c) 2024 Microchip Technology Inc. - */ - --/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. -+/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. - * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b - */ - -@@ -151,6 +151,7 @@ enum sparx5_gsize_enum { - GW_ANA_L2_COMMON, - GW_ASM_CFG, - GW_CPU_CPU_REGS, -+ GW_DEV2G5_PHASE_DETECTOR_CTRL, - GW_FDMA_FDMA, - GW_GCB_CHIP_REGS, - GW_HSCH_TAS_CONFIG, -@@ -169,6 +170,8 @@ enum sparx5_fpos_enum { - FP_CPU_PROC_CTRL_CP15S_DISABLE, - FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, - FP_CPU_PROC_CTRL_L2_FLUSH_REQ, -+ FP_DEV2G5_PHAD_CTRL_PHAD_ENA, -+ FP_DEV2G5_PHAD_CTRL_PHAD_FAILED, - FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, - FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, - FP_FDMA_CH_CFG_CH_INJ_PORT, diff --git a/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch deleted file mode 100644 index eb9b597aa7..0000000000 --- a/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch +++ /dev/null @@ -1,54 +0,0 @@ -From df0ae12e09264cb432472c707ccb33ececc65935 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:27 +0200 -Subject: [PATCH 51/82] net: lan969x: add constants to match data - -Add the lan969x constants to match data. These are already used -throughout the Sparx5 code (introduced in earlier series [1]), so no -need to update any code use. - -[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-0-d3290f581663@microchip.com/ - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-8-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/lan969x/lan969x.c | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -103,11 +103,32 @@ static const struct sparx5_regs lan969x_ - .fsize = lan969x_fsize, - }; - -+static const struct sparx5_consts lan969x_consts = { -+ .n_ports = 30, -+ .n_ports_all = 35, -+ .n_hsch_l1_elems = 32, -+ .n_hsch_queues = 4, -+ .n_lb_groups = 5, -+ .n_pgids = 1054, /* (1024 + n_ports) */ -+ .n_sio_clks = 1, -+ .n_own_upsids = 1, -+ .n_auto_cals = 4, -+ .n_filters = 256, -+ .n_gates = 256, -+ .n_sdlbs = 496, -+ .n_dsm_cal_taxis = 5, -+ .buf_size = 1572864, -+ .qres_max_prio_idx = 315, -+ .qres_max_colour_idx = 323, -+ .tod_pin = 4, -+}; -+ - const struct sparx5_match_data lan969x_desc = { - .iomap = lan969x_main_iomap, - .iomap_size = ARRAY_SIZE(lan969x_main_iomap), - .ioranges = 2, - .regs = &lan969x_regs, -+ .consts = &lan969x_consts, - }; - EXPORT_SYMBOL_GPL(lan969x_desc); - diff --git a/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch deleted file mode 100644 index 7cabd2ca39..0000000000 --- a/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 487d962349a2be3de1c3dc556b9d2a3529837f3a Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:28 +0200 -Subject: [PATCH 52/82] net: lan969x: add lan969x ops to match data - -Add a bunch of small lan969x ops in bulk. These ops are explained in -detail in a previous series [1]. - -[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-8-d3290f581663@microchip.com/ - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-9-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/lan969x/lan969x.c | 122 ++++++++++++++++++ - .../net/ethernet/microchip/lan969x/lan969x.h | 28 ++++ - 2 files changed, 150 insertions(+) - ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -6,6 +6,9 @@ - - #include "lan969x.h" - -+#define LAN969X_SDLB_GRP_CNT 5 -+#define LAN969X_HSCH_LEAK_GRP_CNT 4 -+ - static const struct sparx5_main_io_resource lan969x_main_iomap[] = { - { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ - { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ -@@ -92,6 +95,112 @@ static const struct sparx5_main_io_resou - { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ - }; - -+static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { -+ { 1000000000, 8192 / 2, 64 }, /* 1 G */ -+ { 500000000, 8192 / 2, 64 }, /* 500 M */ -+ { 100000000, 8192 / 4, 64 }, /* 100 M */ -+ { 50000000, 8192 / 4, 64 }, /* 50 M */ -+ { 5000000, 8192 / 8, 64 }, /* 10 M */ -+}; -+ -+static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { -+ 655355, 1048568, 6553550, 10485680 -+}; -+ -+static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) -+{ -+ return &lan969x_sdlb_groups[idx]; -+} -+ -+static u32 lan969x_get_hsch_max_group_rate(int grp) -+{ -+ return lan969x_hsch_max_group_rate[grp]; -+} -+ -+static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) -+{ -+ if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) -+ return port; -+ -+ /* 10G */ -+ switch (port) { -+ case 0: -+ return 12; -+ case 4: -+ return 13; -+ case 8: -+ return 14; -+ case 12: -+ return 0; -+ default: -+ return port; -+ } -+} -+ -+static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) -+{ -+ if (lan969x_port_is_5g(port)) { -+ switch (port) { -+ case 9: -+ return 0; -+ case 13: -+ return 1; -+ case 17: -+ return 2; -+ case 21: -+ return 3; -+ } -+ } -+ -+ if (lan969x_port_is_10g(port)) { -+ switch (port) { -+ case 0: -+ return 0; -+ case 4: -+ return 1; -+ case 8: -+ return 2; -+ case 12: -+ return 3; -+ case 16: -+ return 4; -+ case 20: -+ return 5; -+ case 24: -+ return 6; -+ case 25: -+ return 7; -+ case 26: -+ return 8; -+ case 27: -+ return 9; -+ } -+ } -+ -+ /* 2g5 port */ -+ return port; -+} -+ -+static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ u32 portno = port->portno; -+ u32 inst; -+ -+ if (port->conf.portmode == conf->portmode) -+ return 0; /* Nothing to do */ -+ -+ switch (conf->portmode) { -+ case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ -+ inst = (portno - portno % 4) / 4; -+ spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); -+ break; -+ default: -+ break; -+ } -+ return 0; -+} -+ - static const struct sparx5_regs lan969x_regs = { - .tsize = lan969x_tsize, - .gaddr = lan969x_gaddr, -@@ -123,12 +232,25 @@ static const struct sparx5_consts lan969 - .tod_pin = 4, - }; - -+static const struct sparx5_ops lan969x_ops = { -+ .is_port_2g5 = &lan969x_port_is_2g5, -+ .is_port_5g = &lan969x_port_is_5g, -+ .is_port_10g = &lan969x_port_is_10g, -+ .is_port_25g = &lan969x_port_is_25g, -+ .get_port_dev_index = &lan969x_port_dev_mapping, -+ .get_port_dev_bit = &lan969x_get_dev_mode_bit, -+ .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, -+ .get_sdlb_group = &lan969x_get_sdlb_group, -+ .set_port_mux = &lan969x_port_mux_set, -+}; -+ - const struct sparx5_match_data lan969x_desc = { - .iomap = lan969x_main_iomap, - .iomap_size = ARRAY_SIZE(lan969x_main_iomap), - .ioranges = 2, - .regs = &lan969x_regs, - .consts = &lan969x_consts, -+ .ops = &lan969x_ops, - }; - EXPORT_SYMBOL_GPL(lan969x_desc); - ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -23,4 +23,32 @@ extern const unsigned int lan969x_gsize[ - extern const unsigned int lan969x_fpos[FPOS_LAST]; - extern const unsigned int lan969x_fsize[FSIZE_LAST]; - -+static inline bool lan969x_port_is_2g5(int portno) -+{ -+ return portno == 1 || portno == 2 || portno == 3 || -+ portno == 5 || portno == 6 || portno == 7 || -+ portno == 10 || portno == 11 || portno == 14 || -+ portno == 15 || portno == 18 || portno == 19 || -+ portno == 22 || portno == 23; -+} -+ -+static inline bool lan969x_port_is_5g(int portno) -+{ -+ return portno == 9 || portno == 13 || portno == 17 || -+ portno == 21; -+} -+ -+static inline bool lan969x_port_is_10g(int portno) -+{ -+ return portno == 0 || portno == 4 || portno == 8 || -+ portno == 12 || portno == 16 || portno == 20 || -+ portno == 24 || portno == 25 || portno == 26 || -+ portno == 27; -+} -+ -+static inline bool lan969x_port_is_25g(int portno) -+{ -+ return false; -+} -+ - #endif diff --git a/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch b/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch deleted file mode 100644 index c93431f891..0000000000 --- a/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch +++ /dev/null @@ -1,180 +0,0 @@ -From a84b19eaf3ede71d2e4075dddffc71a529ccbdd9 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:29 +0200 -Subject: [PATCH 53/82] net: lan969x: add PTP handler function - -Add PTP IRQ handler for lan969x. This is required, as the PTP registers -are placed in two different targets on Sparx5 and lan969x. The -implementation is otherwise the same as on Sparx5. - -Also, expose sparx5_get_hwtimestamp() for use by lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-10-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/lan969x/lan969x.c | 90 +++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_main.h | 5 ++ - .../ethernet/microchip/sparx5/sparx5_ptp.c | 9 +- - 3 files changed, 99 insertions(+), 5 deletions(-) - ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -201,6 +201,95 @@ static int lan969x_port_mux_set(struct s - return 0; - } - -+static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) -+{ -+ int budget = SPARX5_MAX_PTP_ID; -+ struct sparx5 *sparx5 = args; -+ -+ while (budget--) { -+ struct sk_buff *skb, *skb_tmp, *skb_match = NULL; -+ struct skb_shared_hwtstamps shhwtstamps; -+ struct sparx5_port *port; -+ struct timespec64 ts; -+ unsigned long flags; -+ u32 val, id, txport; -+ u32 delay; -+ -+ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -+ -+ /* Check if a timestamp can be retrieved */ -+ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -+ break; -+ -+ WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); -+ -+ if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) -+ continue; -+ -+ /* Retrieve the ts Tx port */ -+ txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); -+ -+ /* Retrieve its associated skb */ -+ port = sparx5->ports[txport]; -+ -+ /* Retrieve the delay */ -+ delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -+ delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); -+ -+ /* Get next timestamp from fifo, which needs to be the -+ * rx timestamp which represents the id of the frame -+ */ -+ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -+ PTP_TWOSTEP_CTRL_PTP_NXT, -+ sparx5, PTP_TWOSTEP_CTRL); -+ -+ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -+ -+ /* Check if a timestamp can be retrieved */ -+ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -+ break; -+ -+ /* Read RX timestamping to get the ID */ -+ id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -+ id <<= 8; -+ id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); -+ -+ spin_lock_irqsave(&port->tx_skbs.lock, flags); -+ skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { -+ if (SPARX5_SKB_CB(skb)->ts_id != id) -+ continue; -+ -+ __skb_unlink(skb, &port->tx_skbs); -+ skb_match = skb; -+ break; -+ } -+ spin_unlock_irqrestore(&port->tx_skbs.lock, flags); -+ -+ /* Next ts */ -+ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -+ PTP_TWOSTEP_CTRL_PTP_NXT, -+ sparx5, PTP_TWOSTEP_CTRL); -+ -+ if (WARN_ON(!skb_match)) -+ continue; -+ -+ spin_lock(&sparx5->ptp_ts_id_lock); -+ sparx5->ptp_skbs--; -+ spin_unlock(&sparx5->ptp_ts_id_lock); -+ -+ /* Get the h/w timestamp */ -+ sparx5_get_hwtimestamp(sparx5, &ts, delay); -+ -+ /* Set the timestamp in the skb */ -+ shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); -+ skb_tstamp_tx(skb_match, &shhwtstamps); -+ -+ dev_kfree_skb_any(skb_match); -+ } -+ -+ return IRQ_HANDLED; -+} -+ - static const struct sparx5_regs lan969x_regs = { - .tsize = lan969x_tsize, - .gaddr = lan969x_gaddr, -@@ -242,6 +331,7 @@ static const struct sparx5_ops lan969x_o - .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, - .get_sdlb_group = &lan969x_get_sdlb_group, - .set_port_mux = &lan969x_port_mux_set, -+ .ptp_irq_handler = &lan969x_ptp_irq_handler, - }; - - const struct sparx5_match_data lan969x_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -114,6 +114,8 @@ enum sparx5_vlan_port_type { - #define SPX5_DSM_CAL_LEN 64 - #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 - -+#define SPARX5_MAX_PTP_ID 512 -+ - struct sparx5; - - struct sparx5_calendar_data { -@@ -499,6 +501,9 @@ void sparx5_ptp_txtstamp_release(struct - struct sk_buff *skb); - irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); - int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); -+void sparx5_get_hwtimestamp(struct sparx5 *sparx5, -+ struct timespec64 *ts, -+ u32 nsec); - - /* sparx5_vcap_impl.c */ - int sparx5_vcap_init(struct sparx5 *sparx5); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -@@ -11,8 +11,6 @@ - #include "sparx5_main_regs.h" - #include "sparx5_main.h" - --#define SPARX5_MAX_PTP_ID 512 -- - #define TOD_ACC_PIN 0x4 - - enum { -@@ -275,9 +273,9 @@ void sparx5_ptp_txtstamp_release(struct - spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); - } - --static void sparx5_get_hwtimestamp(struct sparx5 *sparx5, -- struct timespec64 *ts, -- u32 nsec) -+void sparx5_get_hwtimestamp(struct sparx5 *sparx5, -+ struct timespec64 *ts, -+ u32 nsec) - { - /* Read current PTP time to get seconds */ - const struct sparx5_consts *consts = sparx5->data->consts; -@@ -305,6 +303,7 @@ static void sparx5_get_hwtimestamp(struc - - spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); - } -+EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp); - - irqreturn_t sparx5_ptp_irq_handler(int irq, void *args) - { diff --git a/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch b/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch deleted file mode 100644 index ebfc1fc4e6..0000000000 --- a/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch +++ /dev/null @@ -1,359 +0,0 @@ -From bb44231712c296fa992cf7e0f7206b0798a1b84c Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:30 +0200 -Subject: [PATCH 54/82] net: lan969x: add function for calculating the DSM - calendar - -Lan969x has support for RedBox / HSR / PRP (not implemented yet). In -order to accommodate for this in the future, we need to give lan969x it's -own function for calculating the DSM calendar. - -The function calculates the calendar for each taxi bus. The calendar is -used for bandwidth allocation towards the ports attached to the taxi -bus. A calendar configuration consists of up-to 64 slots, which may be -allocated to ports or left unused. Each slot accounts for 1 clock cycle. - -Also expose sparx5_cal_speed_to_value(), sparx5_get_port_cal_speed, -sparx5_cal_bw and SPX5_DSM_CAL_EMPTY for use by lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-11-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/lan969x/Makefile | 2 +- - .../net/ethernet/microchip/lan969x/lan969x.c | 1 + - .../net/ethernet/microchip/lan969x/lan969x.h | 3 + - .../microchip/lan969x/lan969x_calendar.c | 191 ++++++++++++++++++ - .../microchip/sparx5/sparx5_calendar.c | 20 +- - .../ethernet/microchip/sparx5/sparx5_main.h | 15 ++ - 6 files changed, 215 insertions(+), 17 deletions(-) - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c - ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -5,7 +5,7 @@ - - obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o - --lan969x-switch-y := lan969x_regs.o lan969x.o -+lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -332,6 +332,7 @@ static const struct sparx5_ops lan969x_o - .get_sdlb_group = &lan969x_get_sdlb_group, - .set_port_mux = &lan969x_port_mux_set, - .ptp_irq_handler = &lan969x_ptp_irq_handler, -+ .dsm_calendar_calc = &lan969x_dsm_calendar_calc, - }; - - const struct sparx5_match_data lan969x_desc = { ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -51,4 +51,7 @@ static inline bool lan969x_port_is_25g(i - return false; - } - -+/* lan969x_calendar.c */ -+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data); - #endif ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "lan969x.h" -+ -+#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 -+#define LAN969X_DSM_CAL_TAXIS 5 -+ -+enum lan969x_dsm_cal_dev { -+ DSM_CAL_DEV_2G5, -+ DSM_CAL_DEV_5G, -+ DSM_CAL_DEV_10G, -+ DSM_CAL_DEV_OTHER, /* 1G or less */ -+ DSM_CAL_DEV_MAX -+}; -+ -+/* Each entry in the following struct defines properties for a given speed -+ * (10G, 5G, 2.5G, or 1G or less). -+ */ -+struct lan969x_dsm_cal_dev_speed { -+ /* Number of devices that requires this speed. */ -+ u32 n_devs; -+ -+ /* Array of devices that requires this speed. */ -+ u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; -+ -+ /* Number of slots required for one device running this speed. */ -+ u32 n_slots; -+ -+ /* Gap between two slots for one device running this speed. */ -+ u32 gap; -+}; -+ -+static u32 -+lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { -+ { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, -+ { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, -+ { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, -+ { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, -+ { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } -+}; -+ -+static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) -+{ -+ if (*cal_idx >= cal_len) -+ return -EINVAL; -+ -+ do { -+ if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) -+ return 0; -+ -+ (*cal_idx)++; -+ } while (*cal_idx < cal_len); -+ -+ return -ENOENT; -+} -+ -+static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) -+{ -+ return (speed == 10000 ? DSM_CAL_DEV_10G : -+ speed == 5000 ? DSM_CAL_DEV_5G : -+ speed == 2500 ? DSM_CAL_DEV_2G5 : -+ DSM_CAL_DEV_OTHER); -+} -+ -+static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) -+{ -+ return (dev == DSM_CAL_DEV_10G ? 10000 : -+ dev == DSM_CAL_DEV_5G ? 5000 : -+ dev == DSM_CAL_DEV_2G5 ? 2500 : -+ 1000); -+} -+ -+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data) -+{ -+ struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; -+ u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; -+ struct lan969x_dsm_cal_dev_speed *speed; -+ int err; -+ -+ /* Maximum bandwidth for this taxi */ -+ taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); -+ -+ memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], -+ LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); -+ -+ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -+ u32 portno = data->taxi_ports[i]; -+ enum sparx5_cal_bw bw; -+ -+ bw = sparx5_get_port_cal_speed(sparx5, portno); -+ -+ if (portno < sparx5->data->consts->n_ports_all) -+ data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); -+ else -+ data->taxi_speeds[i] = 0; -+ } -+ -+ /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the -+ * this taxi map. -+ */ -+ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -+ u32 taxi_speed = data->taxi_speeds[i]; -+ enum lan969x_dsm_cal_dev dev; -+ -+ if (taxi_speed == 0) -+ continue; -+ -+ required_bw += taxi_speed; -+ -+ dev = lan969x_dsm_cal_get_dev(taxi_speed); -+ speed = &dev_speeds[dev]; -+ speed->devs[speed->n_devs++] = i; -+ n_devs++; -+ } -+ -+ if (required_bw > taxi_bw) { -+ pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", -+ required_bw, taxi_bw); -+ return -EINVAL; -+ } -+ -+ if (n_devs == 0) { -+ data->schedule[0] = SPX5_DSM_CAL_EMPTY; -+ return 0; -+ } -+ -+ cal_len = n_devs; -+ -+ /* Search for a calendar length that fits all active devices. */ -+ while (cal_len < SPX5_DSM_CAL_LEN) { -+ u32 bw_per_slot = taxi_bw / cal_len; -+ -+ n_slots = 0; -+ -+ for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { -+ speed = &dev_speeds[i]; -+ -+ if (speed->n_devs == 0) -+ continue; -+ -+ required_bw = lan969x_dsm_cal_get_speed(i); -+ speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); -+ -+ if (speed->n_slots) -+ speed->gap = DIV_ROUND_UP(cal_len, -+ speed->n_slots); -+ else -+ speed->gap = 0; -+ -+ n_slots += speed->n_slots * speed->n_devs; -+ } -+ -+ if (n_slots <= cal_len) -+ break; /* Found a suitable calendar length. */ -+ -+ /* Not good enough yet. */ -+ cal_len = n_slots; -+ } -+ -+ if (cal_len > SPX5_DSM_CAL_LEN) { -+ pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); -+ return -EINVAL; -+ } -+ -+ for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) -+ data->schedule[i] = SPX5_DSM_CAL_EMPTY; -+ -+ /* Place the remaining devices */ -+ for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { -+ speed = &dev_speeds[i]; -+ for (u32 dev = 0; dev < speed->n_devs; dev++) { -+ u32 idx = 0; -+ -+ for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { -+ err = lan969x_dsm_cal_idx_get(data->schedule, -+ cal_len, &idx); -+ if (err) -+ return err; -+ data->schedule[idx] = speed->devs[dev]; -+ idx += speed->gap; -+ } -+ } -+ } -+ -+ return 0; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -15,7 +15,6 @@ - #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ - - /* DSM calendar information */ --#define SPX5_DSM_CAL_EMPTY 0xFFFF - #define SPX5_DSM_CAL_TAXIS 8 - #define SPX5_DSM_CAL_BW_LOSS 553 - -@@ -74,18 +73,6 @@ static u32 sparx5_target_bandwidth(struc - } - } - --/* This is used in calendar configuration */ --enum sparx5_cal_bw { -- SPX5_CAL_SPEED_NONE = 0, -- SPX5_CAL_SPEED_1G = 1, -- SPX5_CAL_SPEED_2G5 = 2, -- SPX5_CAL_SPEED_5G = 3, -- SPX5_CAL_SPEED_10G = 4, -- SPX5_CAL_SPEED_25G = 5, -- SPX5_CAL_SPEED_0G5 = 6, -- SPX5_CAL_SPEED_12G5 = 7 --}; -- - static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock) - { - switch (cclock) { -@@ -98,7 +85,7 @@ static u32 sparx5_clk_to_bandwidth(enum - return 0; - } - --static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) -+u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) - { - switch (speed) { - case SPX5_CAL_SPEED_1G: return 1000; -@@ -111,6 +98,7 @@ static u32 sparx5_cal_speed_to_value(enu - default: return 0; - } - } -+EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); - - static u32 sparx5_bandwidth_to_calendar(u32 bw) - { -@@ -128,8 +116,7 @@ static u32 sparx5_bandwidth_to_calendar( - } - } - --static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, -- u32 portno) -+enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) - { - struct sparx5_port *port; - -@@ -163,6 +150,7 @@ static enum sparx5_cal_bw sparx5_get_por - return SPX5_CAL_SPEED_NONE; - return sparx5_bandwidth_to_calendar(port->conf.bandwidth); - } -+EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); - - /* Auto configure the QSYS calendar based on port configuration */ - int sparx5_config_auto_calendar(struct sparx5 *sparx5) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -63,6 +63,18 @@ enum sparx5_vlan_port_type { - SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ - }; - -+/* This is used in calendar configuration */ -+enum sparx5_cal_bw { -+ SPX5_CAL_SPEED_NONE = 0, -+ SPX5_CAL_SPEED_1G = 1, -+ SPX5_CAL_SPEED_2G5 = 2, -+ SPX5_CAL_SPEED_5G = 3, -+ SPX5_CAL_SPEED_10G = 4, -+ SPX5_CAL_SPEED_25G = 5, -+ SPX5_CAL_SPEED_0G5 = 6, -+ SPX5_CAL_SPEED_12G5 = 7 -+}; -+ - #define SPX5_PORTS 65 - #define SPX5_PORTS_ALL 70 /* Total number of ports */ - -@@ -113,6 +125,7 @@ enum sparx5_vlan_port_type { - - #define SPX5_DSM_CAL_LEN 64 - #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 -+#define SPX5_DSM_CAL_EMPTY 0xFFFF - - #define SPARX5_MAX_PTP_ID 512 - -@@ -454,6 +467,8 @@ int sparx5_config_auto_calendar(struct s - int sparx5_config_dsm_calendar(struct sparx5 *sparx5); - int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data); -+u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed); -+enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno); - - - /* sparx5_ethtool.c */ diff --git a/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch b/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch deleted file mode 100644 index ab2c53a165..0000000000 --- a/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch +++ /dev/null @@ -1,306 +0,0 @@ -From ad3d33e6ac44359d2414f11bcaf1ebb8ba64346d Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:31 +0200 -Subject: [PATCH 55/82] net: sparx5: use is_sparx5() macro throughout - -Use the is_sparx5() macro (introduced in earlier series [1]), in places -where we need to handle things a bit differently on lan969x. - -These places are: - - - in sparx5_dsm_calendar_update() we need to switch the calendar - from a to b on lan969x. - - - in sparx5_start() we need to make sure the HSCH_SYS_CLK_PER - register is only touched on Sparx5. - - - in sparx5_start() we need to disable VCAP and FDMA for lan969x - (will come in later series). - - - in sparx5_mirror_port_get() we must make sure the - ANA_AC_PROBE_PORT_CFG1 register is only read on Sparx5. - - - sparx5_netdev.c and sparx5_packet.c we need to use different IFH - (Internal Frame Header) offsets for lan969x. - - - in sparx5_port_fifo_sz() we must bail out on lan969x. - - - in sparx5_port_config_low_set() we must configure the phase - detection registers. - - - in sparx5_port_config() and sparx5_port_init() we must do some - additional configuration of the port devices. - - - in sparx5_dwrr_conf_set() we must derive the scheduling layer - -[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-8-d3290f581663@microchip.com/ - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-12-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../microchip/sparx5/sparx5_calendar.c | 21 ++++++++- - .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++---- - .../ethernet/microchip/sparx5/sparx5_mirror.c | 10 +++- - .../ethernet/microchip/sparx5/sparx5_netdev.c | 17 ++++--- - .../ethernet/microchip/sparx5/sparx5_packet.c | 3 +- - .../ethernet/microchip/sparx5/sparx5_port.c | 46 +++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_qos.c | 3 +- - 7 files changed, 99 insertions(+), 22 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -531,8 +531,18 @@ check_err: - static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data) - { -- u32 idx; -- u32 cal_len = sparx5_dsm_cal_len(data->schedule), len; -+ u32 cal_len = sparx5_dsm_cal_len(data->schedule), len, idx; -+ -+ if (!is_sparx5(sparx5)) { -+ u32 val, act; -+ -+ val = spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi)); -+ act = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val); -+ -+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), -+ DSM_TAXI_CAL_CFG_CAL_PGM_SEL, -+ sparx5, DSM_TAXI_CAL_CFG(taxi)); -+ } - - spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), - DSM_TAXI_CAL_CFG_CAL_PGM_ENA, -@@ -556,6 +566,13 @@ static int sparx5_dsm_calendar_update(st - DSM_TAXI_CAL_CFG(taxi))); - if (len != cal_len - 1) - goto update_err; -+ -+ if (!is_sparx5(sparx5)) { -+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), -+ DSM_TAXI_CAL_CFG_CAL_SWITCH, -+ sparx5, DSM_TAXI_CAL_CFG(taxi)); -+ } -+ - return 0; - update_err: - dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -538,10 +538,11 @@ static int sparx5_init_coreclock(struct - sparx5->coreclock = freq; - clk_period = sparx5_clk_period(freq); - -- spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), -- HSCH_SYS_CLK_PER_100PS, -- sparx5, -- HSCH_SYS_CLK_PER); -+ if (is_sparx5(sparx5)) -+ spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), -+ HSCH_SYS_CLK_PER_100PS, -+ sparx5, -+ HSCH_SYS_CLK_PER); - - spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), - ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, -@@ -731,15 +732,17 @@ static int sparx5_start(struct sparx5 *s - if (err) - return err; - -- err = sparx5_vcap_init(sparx5); -- if (err) { -- sparx5_unregister_notifier_blocks(sparx5); -- return err; -+ if (is_sparx5(sparx5)) { -+ err = sparx5_vcap_init(sparx5); -+ if (err) { -+ sparx5_unregister_notifier_blocks(sparx5); -+ return err; -+ } - } - - /* Start Frame DMA with fallback to register based INJ/XTR */ - err = -ENXIO; -- if (sparx5->fdma_irq >= 0) { -+ if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { - if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) - err = devm_request_irq(sparx5->dev, - sparx5->fdma_irq, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c -@@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ing - /* Get ports belonging to this mirror */ - static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) - { -- return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | -- spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); -+ u64 val; -+ -+ val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); -+ -+ if (is_sparx5(sparx5)) -+ val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; -+ -+ return val; - } - - /* Add port to mirror (only front ports) */ ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 * - /* MISC.CPU_MASK/DPORT = Destination port */ - ifh_encode_bitfield(ifh_hdr, portno, 29, 8); - /* MISC.PIPELINE_PT */ -- ifh_encode_bitfield(ifh_hdr, 16, 37, 5); -+ ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); - /* MISC.PIPELINE_ACT */ - ifh_encode_bitfield(ifh_hdr, 1, 42, 3); - /* FWD.SRC_PORT = CPU */ - ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), -- 46, 7); -+ 46, is_sparx5(sparx5) ? 7 : 6); - /* FWD.SFLOW_ID (disable SFlow sampling) */ -- ifh_encode_bitfield(ifh_hdr, 124, 57, 7); -+ ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); - /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ -- ifh_encode_bitfield(ifh_hdr, 1, 67, 1); -+ ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); - } - - void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) -@@ -84,19 +84,22 @@ void sparx5_set_port_ifh_rew_op(void *if - void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, - u32 pdu_type) - { -- ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); -+ ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, -+ 4); - } - - void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, - u32 pdu_w16_offset) - { -- ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); -+ ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, -+ is_sparx5(sparx5) ? 195 : 194, 6); - } - - void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, - u64 timestamp) - { -- ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); -+ ifh_encode_bitfield(ifh_hdr, timestamp, 232, -+ is_sparx5(sparx5) ? 40 : 38); - } - - static int sparx5_port_open(struct net_device *ndev) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -43,7 +43,8 @@ void sparx5_ifh_parse(struct sparx5 *spa - ((u32)xtr_hdr[29] << 8) | - ((u32)xtr_hdr[30] << 0); - fwd = (fwd >> 5); -- info->src_port = FIELD_GET(GENMASK(7, 1), fwd); -+ info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), -+ fwd); - - /* - * Bit 270-271 are occasionally unexpectedly set by the hardware, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -476,6 +476,9 @@ static int sparx5_port_fifo_sz(struct sp - u32 mac_width = 8; - u32 addition = 0; - -+ if (!is_sparx5(sparx5)) -+ return 0; -+ - switch (speed) { - case SPEED_25000: - return 0; -@@ -921,6 +924,20 @@ static int sparx5_port_config_low_set(st - sparx5, - DEV2G5_DEV_RST_CTRL(port->portno)); - -+ /* Enable PHAD_CTRL for better timestamping */ -+ if (!is_sparx5(sparx5)) { -+ for (int i = 0; i < 2; ++i) { -+ /* Divide the port clock by three for the two -+ * phase detection registers. -+ */ -+ spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) | -+ DEV2G5_PHAD_CTRL_PHAD_ENA_SET(1), -+ DEV2G5_PHAD_CTRL_DIV_CFG | -+ DEV2G5_PHAD_CTRL_PHAD_ENA, -+ sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); -+ } -+ } -+ - return 0; - } - -@@ -978,6 +995,7 @@ int sparx5_port_config(struct sparx5 *sp - struct sparx5_port_config *conf) - { - bool high_speed_dev = sparx5_is_baser(conf->portmode); -+ const struct sparx5_ops *ops = sparx5->data->ops; - int err, urgency, stop_wm; - - err = sparx5_port_verify_speed(sparx5, port, conf); -@@ -993,6 +1011,13 @@ int sparx5_port_config(struct sparx5 *sp - if (err) - return err; - -+ if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && -+ conf->speed < SPEED_10000) -+ spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), -+ DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, -+ sparx5, -+ DSM_DEV_TX_STOP_WM_CFG(port->portno)); -+ - /* Set the DSM stop watermark */ - stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); - spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm), -@@ -1144,6 +1169,27 @@ int sparx5_port_init(struct sparx5 *spar - DEV25G_PCS25G_SD_CFG(pix)); - } - -+ if (!is_sparx5(sparx5)) { -+ void __iomem *inst; -+ u32 dev, tinst; -+ -+ if (ops->is_port_10g(port->portno)) { -+ dev = sparx5_to_high_dev(sparx5, port->portno); -+ tinst = sparx5_port_dev_index(sparx5, port->portno); -+ inst = spx5_inst_get(sparx5, dev, tinst); -+ -+ spx5_inst_wr(5, inst, -+ DEV10G_PTP_STAMPER_CFG(port->portno)); -+ } else if (ops->is_port_5g(port->portno)) { -+ dev = sparx5_to_high_dev(sparx5, port->portno); -+ tinst = sparx5_port_dev_index(sparx5, port->portno); -+ inst = spx5_inst_get(sparx5, dev, tinst); -+ -+ spx5_inst_wr(5, inst, -+ DEV5G_PTP_STAMPER_CFG(port->portno)); -+ } -+ } -+ - return 0; - } - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c -@@ -367,9 +367,10 @@ static u32 sparx5_weight_to_hw_cost(u32 - static int sparx5_dwrr_conf_set(struct sparx5_port *port, - struct sparx5_dwrr *dwrr) - { -+ u32 layer = is_sparx5(port->sparx5) ? 2 : 1; - int i; - -- spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | -+ spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) | - HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(port->portno), - HSCH_HSCH_CFG_CFG_HSCH_LAYER | HSCH_HSCH_CFG_CFG_CFG_SE_IDX, - port->sparx5, HSCH_HSCH_CFG_CFG); diff --git a/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch b/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch deleted file mode 100644 index a8416226fd..0000000000 --- a/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a02276501dbc5ae015e56aad0176e9f40703aac9 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:33 +0200 -Subject: [PATCH 56/82] net: sparx5: add compatible string for lan969x - -Add lan9691-switch compatible string to mchp_sparx5_match. Guard it with -IS_ENABLED(CONFIG_LAN969X_SWITCH) to make sure Sparx5 can be compiled on -its own. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-14-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -24,6 +24,8 @@ - #include - #include - -+#include "../lan969x/lan969x.h" /* for lan969x match data */ -+ - #include "sparx5_main_regs.h" - #include "sparx5_main.h" - #include "sparx5_port.h" -@@ -1049,6 +1051,9 @@ static const struct sparx5_match_data sp - - static const struct of_device_id mchp_sparx5_match[] = { - { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, -+#if IS_ENABLED(CONFIG_LAN969X_SWITCH) -+ { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, -+#endif - { } - }; - MODULE_DEVICE_TABLE(of, mchp_sparx5_match); diff --git a/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch b/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch deleted file mode 100644 index 4601a14948..0000000000 --- a/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch +++ /dev/null @@ -1,130 +0,0 @@ -From 77520fd6b40f129f2b8d6d81d27bd311d30c3250 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 24 Oct 2024 00:01:34 +0200 -Subject: [PATCH 57/82] net: sparx5: add feature support - -Lan969x supports a number of different features, depending on the -target. Add new field sparx5->features and initialize the features based -on the target. Also add the function sparx5_has_feature() and use it -throughout. For now, we only need to handle features: PSFP and PTP - -more will come in the future. - -[1] https://www.microchip.com/en-us/product/lan9698 - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-15-a0b5fae88a0f@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_main.c | 40 ++++++++++++++++++- - .../ethernet/microchip/sparx5/sparx5_main.h | 7 ++++ - .../microchip/sparx5/sparx5_tc_flower.c | 5 +++ - 3 files changed, 51 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -229,6 +229,40 @@ bool is_sparx5(struct sparx5 *sparx5) - } - } - -+static void sparx5_init_features(struct sparx5 *sparx5) -+{ -+ switch (sparx5->target_ct) { -+ case SPX5_TARGET_CT_7546: -+ case SPX5_TARGET_CT_7549: -+ case SPX5_TARGET_CT_7552: -+ case SPX5_TARGET_CT_7556: -+ case SPX5_TARGET_CT_7558: -+ case SPX5_TARGET_CT_7546TSN: -+ case SPX5_TARGET_CT_7549TSN: -+ case SPX5_TARGET_CT_7552TSN: -+ case SPX5_TARGET_CT_7556TSN: -+ case SPX5_TARGET_CT_7558TSN: -+ case SPX5_TARGET_CT_LAN9691VAO: -+ case SPX5_TARGET_CT_LAN9694TSN: -+ case SPX5_TARGET_CT_LAN9694RED: -+ case SPX5_TARGET_CT_LAN9692VAO: -+ case SPX5_TARGET_CT_LAN9696TSN: -+ case SPX5_TARGET_CT_LAN9696RED: -+ case SPX5_TARGET_CT_LAN9693VAO: -+ case SPX5_TARGET_CT_LAN9698TSN: -+ case SPX5_TARGET_CT_LAN9698RED: -+ sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); -+ break; -+ default: -+ break; -+ } -+} -+ -+bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) -+{ -+ return sparx5->features & feature; -+} -+ - static int sparx5_create_targets(struct sparx5 *sparx5) - { - const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; -@@ -770,7 +804,8 @@ static int sparx5_start(struct sparx5 *s - sparx5->xtr_irq = -ENXIO; - } - -- if (sparx5->ptp_irq >= 0) { -+ if (sparx5->ptp_irq >= 0 && -+ sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { - err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, - NULL, ops->ptp_irq_handler, - IRQF_ONESHOT, "sparx5-ptp", -@@ -914,6 +949,9 @@ static int mchp_sparx5_probe(struct plat - sparx5->target_ct = (enum spx5_target_chiptype) - GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); - -+ /* Initialize the features based on the target */ -+ sparx5_init_features(sparx5); -+ - /* Initialize Switchcore and internal RAMs */ - err = sparx5_init_switchcore(sparx5); - if (err) { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -75,6 +75,11 @@ enum sparx5_cal_bw { - SPX5_CAL_SPEED_12G5 = 7 - }; - -+enum sparx5_feature { -+ SPX5_FEATURE_PSFP = BIT(0), -+ SPX5_FEATURE_PTP = BIT(1), -+}; -+ - #define SPX5_PORTS 65 - #define SPX5_PORTS_ALL 70 /* Total number of ports */ - -@@ -337,6 +342,7 @@ struct sparx5 { - struct device *dev; - u32 chip_id; - enum spx5_target_chiptype target_ct; -+ u32 features; - void __iomem *regs[NUM_TARGETS]; - int port_count; - struct mutex lock; /* MAC reg lock */ -@@ -404,6 +410,7 @@ struct sparx5 { - - /* sparx5_main.c */ - bool is_sparx5(struct sparx5 *sparx5); -+bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature); - - /* sparx5_switchdev.c */ - int sparx5_register_notifier_blocks(struct sparx5 *sparx5); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c -@@ -1284,6 +1284,11 @@ static int sparx5_tc_flower_replace(stru - - /* Setup PSFP */ - if (tc_sg_idx >= 0 || tc_pol_idx >= 0) { -+ if (!sparx5_has_feature(sparx5, SPX5_FEATURE_PSFP)) { -+ err = -EOPNOTSUPP; -+ goto out; -+ } -+ - err = sparx5_tc_flower_psfp_setup(sparx5, vrule, tc_sg_idx, - tc_pol_idx, &sg, &fm, &sf); - if (err) diff --git a/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch b/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch deleted file mode 100644 index de7804c61b..0000000000 --- a/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch +++ /dev/null @@ -1,116 +0,0 @@ -From c7a8ba9eec856c3a1d134a09387df04a13efb163 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:07 +0100 -Subject: [PATCH 58/82] net: sparx5: expose some sparx5 VCAP symbols -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In preparation for lan969x VCAP support, expose the following symbols for -use by the lan969x VCAP implementation: - -- The symbols SPARX5_*_LOOKUPS defines the number of lookups in each - VCAP instance. These are the same for lan969x. Move them to the - header file. - -- The struct sparx5_vcap_inst encapsulates information about a single - VCAP instance. Move this struct to the header file and declare the - sparx5_vcap_inst_cfg as extern. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_vcap_impl.c | 18 +--------------- - .../microchip/sparx5/sparx5_vcap_impl.h | 21 +++++++++++++++++++ - 2 files changed, 22 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -@@ -17,7 +17,6 @@ - #define SUPER_VCAP_BLK_SIZE 3072 /* addresses per Super VCAP block */ - #define STREAMSIZE (64 * 4) /* bytes in the VCAP cache area */ - --#define SPARX5_IS2_LOOKUPS 4 - #define VCAP_IS2_KEYSEL(_ena, _noneth, _v4_mc, _v4_uc, _v6_mc, _v6_uc, _arp) \ - (ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(_ena) | \ - ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(_noneth) | \ -@@ -27,7 +26,6 @@ - ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(_v6_uc) | \ - ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(_arp)) - --#define SPARX5_IS0_LOOKUPS 6 - #define VCAP_IS0_KEYSEL(_ena, _etype, _ipv4, _ipv6, _mpls_uc, _mpls_mc, _mlbs) \ - (ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(_ena) | \ - ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(_etype) | \ -@@ -37,31 +35,17 @@ - ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(_mpls_mc) | \ - ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(_mlbs)) - --#define SPARX5_ES0_LOOKUPS 1 - #define VCAP_ES0_KEYSEL(_key) (REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(_key)) - #define SPARX5_STAT_ESDX_GRN_PKTS 0x300 - #define SPARX5_STAT_ESDX_YEL_PKTS 0x301 - --#define SPARX5_ES2_LOOKUPS 2 - #define VCAP_ES2_KEYSEL(_ena, _arp, _ipv4, _ipv6) \ - (EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(_ena) | \ - EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(_arp) | \ - EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(_ipv4) | \ - EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(_ipv6)) - --static struct sparx5_vcap_inst { -- enum vcap_type vtype; /* type of vcap */ -- int vinst; /* instance number within the same type */ -- int lookups; /* number of lookups in this vcap type */ -- int lookups_per_instance; /* number of lookups in this instance */ -- int first_cid; /* first chain id in this vcap */ -- int last_cid; /* last chain id in this vcap */ -- int count; /* number of available addresses, not in super vcap */ -- int map_id; /* id in the super vcap block mapping (if applicable) */ -- int blockno; /* starting block in super vcap (if applicable) */ -- int blocks; /* number of blocks in super vcap (if applicable) */ -- bool ingress; /* is vcap in the ingress path */ --} sparx5_vcap_inst_cfg[] = { -+const struct sparx5_vcap_inst sparx5_vcap_inst_cfg[] = { - { - .vtype = VCAP_TYPE_IS0, /* CLM-0 */ - .vinst = 0, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.h -@@ -16,6 +16,11 @@ - #include "vcap_api.h" - #include "vcap_api_client.h" - -+#define SPARX5_IS2_LOOKUPS 4 -+#define SPARX5_IS0_LOOKUPS 6 -+#define SPARX5_ES0_LOOKUPS 1 -+#define SPARX5_ES2_LOOKUPS 2 -+ - #define SPARX5_VCAP_CID_IS0_L0 VCAP_CID_INGRESS_L0 /* IS0/CLM lookup 0 */ - #define SPARX5_VCAP_CID_IS0_L1 VCAP_CID_INGRESS_L1 /* IS0/CLM lookup 1 */ - #define SPARX5_VCAP_CID_IS0_L2 VCAP_CID_INGRESS_L2 /* IS0/CLM lookup 2 */ -@@ -40,6 +45,22 @@ - #define SPARX5_VCAP_CID_ES2_MAX \ - (VCAP_CID_EGRESS_STAGE2_L1 + VCAP_CID_LOOKUP_SIZE - 1) /* ES2 Max */ - -+struct sparx5_vcap_inst { -+ enum vcap_type vtype; /* type of vcap */ -+ int vinst; /* instance number within the same type */ -+ int lookups; /* number of lookups in this vcap type */ -+ int lookups_per_instance; /* number of lookups in this instance */ -+ int first_cid; /* first chain id in this vcap */ -+ int last_cid; /* last chain id in this vcap */ -+ int count; /* number of available addresses, not in super vcap */ -+ int map_id; /* id in the super vcap block mapping (if applicable) */ -+ int blockno; /* starting block in super vcap (if applicable) */ -+ int blocks; /* number of blocks in super vcap (if applicable) */ -+ bool ingress; /* is vcap in the ingress path */ -+}; -+ -+extern const struct sparx5_vcap_inst sparx5_vcap_inst_cfg[]; -+ - /* IS0 port keyset selection control */ - - /* IS0 ethernet, IPv4, IPv6 traffic type keyset generation */ diff --git a/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch b/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch deleted file mode 100644 index 039fc7e8a2..0000000000 --- a/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 847d70a1d4583e2a5c00faf48e54d8880d248310 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:08 +0100 -Subject: [PATCH 59/82] net: sparx5: replace SPX5_PORTS with n_ports -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Sparx5 VCAP implementation uses the SPX5_PORTS symbol to iterate over -the 65 front ports of Sparx5. Replace the use with the n_ports constant -from the match data, which translates to 65 of Sparx5 and 30 on lan969x. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../microchip/sparx5/sparx5_vcap_impl.c | 24 ++++++++++++------- - 1 file changed, 15 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -@@ -1777,6 +1777,7 @@ void sparx5_vcap_set_port_keyset(struct - static void sparx5_vcap_is0_port_key_selection(struct sparx5 *sparx5, - struct vcap_admin *admin) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int portno, lookup; - u32 keysel; - -@@ -1788,7 +1789,7 @@ static void sparx5_vcap_is0_port_key_sel - VCAP_IS0_PS_MPLS_FOLLOW_ETYPE, - VCAP_IS0_PS_MLBS_FOLLOW_ETYPE); - for (lookup = 0; lookup < admin->lookups; ++lookup) { -- for (portno = 0; portno < SPX5_PORTS; ++portno) { -+ for (portno = 0; portno < consts->n_ports; ++portno) { - spx5_wr(keysel, sparx5, - ANA_CL_ADV_CL_CFG(portno, lookup)); - spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, -@@ -1803,6 +1804,7 @@ static void sparx5_vcap_is0_port_key_sel - static void sparx5_vcap_is2_port_key_selection(struct sparx5 *sparx5, - struct vcap_admin *admin) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int portno, lookup; - u32 keysel; - -@@ -1813,13 +1815,13 @@ static void sparx5_vcap_is2_port_key_sel - VCAP_IS2_PS_IPV6_UC_IP_7TUPLE, - VCAP_IS2_PS_ARP_ARP); - for (lookup = 0; lookup < admin->lookups; ++lookup) { -- for (portno = 0; portno < SPX5_PORTS; ++portno) { -+ for (portno = 0; portno < consts->n_ports; ++portno) { - spx5_wr(keysel, sparx5, - ANA_ACL_VCAP_S2_KEY_SEL(portno, lookup)); - } - } - /* IS2 lookups are in bit 0:3 */ -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0xf), - ANA_ACL_VCAP_S2_CFG_SEC_ENA, - sparx5, -@@ -1830,11 +1832,12 @@ static void sparx5_vcap_is2_port_key_sel - static void sparx5_vcap_es0_port_key_selection(struct sparx5 *sparx5, - struct vcap_admin *admin) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int portno; - u32 keysel; - - keysel = VCAP_ES0_KEYSEL(VCAP_ES0_PS_FORCE_ISDX_LOOKUPS); -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_rmw(keysel, REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, - sparx5, REW_RTAG_ETAG_CTRL(portno)); - -@@ -1846,6 +1849,7 @@ static void sparx5_vcap_es0_port_key_sel - static void sparx5_vcap_es2_port_key_selection(struct sparx5 *sparx5, - struct vcap_admin *admin) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int portno, lookup; - u32 keysel; - -@@ -1853,7 +1857,7 @@ static void sparx5_vcap_es2_port_key_sel - VCAP_ES2_PS_IPV4_IP4_TCP_UDP_OTHER, - VCAP_ES2_PS_IPV6_IP_7TUPLE); - for (lookup = 0; lookup < admin->lookups; ++lookup) -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_wr(keysel, sparx5, - EACL_VCAP_ES2_KEY_SEL(portno, lookup)); - } -@@ -1885,19 +1889,20 @@ static void sparx5_vcap_port_key_selecti - static void sparx5_vcap_port_key_deselection(struct sparx5 *sparx5, - struct vcap_admin *admin) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - int portno, lookup; - - switch (admin->vtype) { - case VCAP_TYPE_IS0: - for (lookup = 0; lookup < admin->lookups; ++lookup) -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(0), - ANA_CL_ADV_CL_CFG_LOOKUP_ENA, - sparx5, - ANA_CL_ADV_CL_CFG(portno, lookup)); - break; - case VCAP_TYPE_IS2: -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0), - ANA_ACL_VCAP_S2_CFG_SEC_ENA, - sparx5, -@@ -1909,7 +1914,7 @@ static void sparx5_vcap_port_key_deselec - break; - case VCAP_TYPE_ES2: - for (lookup = 0; lookup < admin->lookups; ++lookup) -- for (portno = 0; portno < SPX5_PORTS; ++portno) -+ for (portno = 0; portno < consts->n_ports; ++portno) - spx5_rmw(EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(0), - EACL_VCAP_ES2_KEY_SEL_KEY_ENA, - sparx5, -@@ -2026,6 +2031,7 @@ static void sparx5_vcap_block_alloc(stru - /* Allocate a vcap control and vcap instances and configure the system */ - int sparx5_vcap_init(struct sparx5 *sparx5) - { -+ const struct sparx5_consts *consts = sparx5->data->consts; - const struct sparx5_vcap_inst *cfg; - struct vcap_control *ctrl; - struct vcap_admin *admin; -@@ -2069,7 +2075,7 @@ int sparx5_vcap_init(struct sparx5 *spar - list_add_tail(&admin->list, &ctrl->list); - } - dir = vcap_debugfs(sparx5->dev, sparx5->debugfs_root, ctrl); -- for (idx = 0; idx < SPX5_PORTS; ++idx) -+ for (idx = 0; idx < consts->n_ports; ++idx) - if (sparx5->ports[idx]) - vcap_port_debugfs(sparx5->dev, dir, ctrl, - sparx5->ports[idx]->ndev); diff --git a/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch deleted file mode 100644 index 1d5dbd437e..0000000000 --- a/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 6deea25857672a2ae9742499634b07f83508b35a Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:09 +0100 -Subject: [PATCH 60/82] net: sparx5: add new VCAP constants to match data -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In preparation for lan969x VCAP support, add the following three new -VCAP constants to match data: - - - vcaps_cfg (contains configuration data for each VCAP). - - - vcaps (contains auto-generated information about VCAP keys and - actions). - - - vcap_stats: (contains auto-generated string names of all the keys - and actions) - -Add these constants to the Sparx5 match data constants and use them to -initialize the VCAP's in sparx5_vcap_init(). - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 +++ - drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h | 2 ++ - drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c | 6 +++--- - 4 files changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -30,6 +30,8 @@ - #include "sparx5_main.h" - #include "sparx5_port.h" - #include "sparx5_qos.h" -+#include "sparx5_vcap_ag_api.h" -+#include "sparx5_vcap_impl.h" - - const struct sparx5_regs *regs; - -@@ -1062,6 +1064,9 @@ static const struct sparx5_consts sparx5 - .qres_max_prio_idx = 630, - .qres_max_colour_idx = 638, - .tod_pin = 4, -+ .vcaps = sparx5_vcaps, -+ .vcaps_cfg = sparx5_vcap_inst_cfg, -+ .vcap_stats = &sparx5_vcap_stats, - }; - - static const struct sparx5_ops sparx5_ops = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -303,6 +303,9 @@ struct sparx5_consts { - u32 qres_max_prio_idx; /* Maximum QRES prio index */ - u32 qres_max_colour_idx; /* Maximum QRES colour index */ - u32 tod_pin; /* PTP TOD pin */ -+ const struct sparx5_vcap_inst *vcaps_cfg; -+ const struct vcap_info *vcaps; -+ const struct vcap_statistics *vcap_stats; - }; - - struct sparx5_ops { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h -@@ -10,6 +10,8 @@ - #ifndef __SPARX5_VCAP_AG_API_H__ - #define __SPARX5_VCAP_AG_API_H__ - -+#include "vcap_api.h" -+ - /* VCAPs */ - extern const struct vcap_info sparx5_vcaps[]; - extern const struct vcap_statistics sparx5_vcap_stats; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c -@@ -2053,14 +2053,14 @@ int sparx5_vcap_init(struct sparx5 *spar - - sparx5->vcap_ctrl = ctrl; - /* select the sparx5 VCAP model */ -- ctrl->vcaps = sparx5_vcaps; -- ctrl->stats = &sparx5_vcap_stats; -+ ctrl->vcaps = consts->vcaps; -+ ctrl->stats = consts->vcap_stats; - /* Setup callbacks to allow the API to use the VCAP HW */ - ctrl->ops = &sparx5_vcap_ops; - - INIT_LIST_HEAD(&ctrl->list); - for (idx = 0; idx < ARRAY_SIZE(sparx5_vcap_inst_cfg); ++idx) { -- cfg = &sparx5_vcap_inst_cfg[idx]; -+ cfg = &consts->vcaps_cfg[idx]; - admin = sparx5_vcap_admin_alloc(sparx5, ctrl, cfg); - if (IS_ERR(admin)) { - err = PTR_ERR(admin); diff --git a/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch b/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch deleted file mode 100644 index 6df0092689..0000000000 --- a/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 41742f746f4860ad7658484ec24a2971476a9d05 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:10 +0100 -Subject: [PATCH 61/82] net: sparx5: execute sparx5_vcap_init() on lan969x -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The is_sparx5() check was introduced in an earlier series, to make sure -the sparx5_vcap_init() was not executed on lan969x, as it was not -implemented there yet. Now that it is, remove that check. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -770,12 +770,10 @@ static int sparx5_start(struct sparx5 *s - if (err) - return err; - -- if (is_sparx5(sparx5)) { -- err = sparx5_vcap_init(sparx5); -- if (err) { -- sparx5_unregister_notifier_blocks(sparx5); -- return err; -- } -+ err = sparx5_vcap_init(sparx5); -+ if (err) { -+ sparx5_unregister_notifier_blocks(sparx5); -+ return err; - } - - /* Start Frame DMA with fallback to register based INJ/XTR */ diff --git a/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch b/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch deleted file mode 100644 index 50eccb4af3..0000000000 --- a/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch +++ /dev/null @@ -1,3916 +0,0 @@ -From 1a3175837f88ce0d121bcaa4c8947872eb201a22 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:11 +0100 -Subject: [PATCH 62/82] net: lan969x: add autogenerated VCAP information -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Platform VCAP data for each VCAP instance is auto-generated using an -internal Microchip tool. The generated VCAP data contains information -about keyfields, keyfield sets, actionfields, actionfield sets and -typegroups, which in combination are used to encode and decode rules in -the VCAP. - -Add the auto-generated VCAP file lan969x_vcap_ag_api.c and assign the -two structs: lan969x_vcaps and lan969x_vcap_stats to the match data. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../net/ethernet/microchip/lan969x/Makefile | 3 +- - .../net/ethernet/microchip/lan969x/lan969x.c | 2 + - .../net/ethernet/microchip/lan969x/lan969x.h | 5 + - .../microchip/lan969x/lan969x_vcap_ag_api.c | 3843 +++++++++++++++++ - 4 files changed, 3852 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c - ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -5,7 +5,8 @@ - - obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o - --lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o -+lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ -+ lan969x_vcap_ag_api.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -319,6 +319,8 @@ static const struct sparx5_consts lan969 - .qres_max_prio_idx = 315, - .qres_max_colour_idx = 323, - .tod_pin = 4, -+ .vcaps = lan969x_vcaps, -+ .vcap_stats = &lan969x_vcap_stats, - }; - - static const struct sparx5_ops lan969x_ops = { ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -9,10 +9,15 @@ - - #include "../sparx5/sparx5_main.h" - #include "../sparx5/sparx5_regs.h" -+#include "../sparx5/sparx5_vcap_impl.h" - - /* lan969x.c */ - extern const struct sparx5_match_data lan969x_desc; - -+/* lan969x_vcap_ag_api.c */ -+extern const struct vcap_statistics lan969x_vcap_stats; -+extern const struct vcap_info lan969x_vcaps[]; -+ - /* lan969x_regs.c */ - extern const unsigned int lan969x_tsize[TSIZE_LAST]; - extern const unsigned int lan969x_raddr[RADDR_LAST]; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c -@@ -0,0 +1,3843 @@ -+// SPDX-License-Identifier: BSD-3-Clause -+/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. -+ * Microchip VCAP API -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. -+ * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 -+ */ -+ -+#include -+#include -+ -+#include "lan969x.h" -+ -+/* keyfields */ -+static const struct vcap_field is0_normal_7tuple_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 4, -+ .width = 10, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 16, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 81, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 82, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 83, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 86, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 89, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 93, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 105, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 108, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI1] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 111, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 112, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 124, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 127, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI2] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 130, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 131, -+ .width = 12, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 144, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 192, -+ .width = 48, -+ }, -+ [VCAP_KF_IP_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 240, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 241, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 242, -+ .width = 16, -+ }, -+ [VCAP_KF_IP_SNAP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 258, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 259, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 260, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 262, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 263, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DSCP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 264, -+ .width = 6, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 270, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 398, -+ .width = 128, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 526, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 527, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 528, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 544, -+ .width = 8, -+ }, -+}; -+ -+static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 10, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 15, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 17, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 82, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 83, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 87, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 94, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 106, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI1] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 112, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 113, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 125, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 128, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI2] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 131, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 132, -+ .width = 12, -+ }, -+ [VCAP_KF_IP_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 145, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 146, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 147, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 149, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 150, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DSCP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 151, -+ .width = 6, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 157, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 189, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 221, -+ .width = 8, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 229, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 230, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 231, -+ .width = 8, -+ }, -+ [VCAP_KF_IP_PAYLOAD_5TUPLE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 239, -+ .width = 32, -+ }, -+}; -+ -+static const struct vcap_field is2_mac_etype_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 89, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 137, -+ .width = 48, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 185, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 186, -+ .width = 16, -+ }, -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 202, -+ .width = 64, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 266, -+ .width = 16, -+ }, -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 282, -+ .width = 1, -+ }, -+ [VCAP_KF_OAM_Y1731_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 283, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field is2_arp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 85, -+ .width = 48, -+ }, -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 133, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 134, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_LEN_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 135, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_TGT_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 136, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 137, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 138, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 139, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 173, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 205, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 206, -+ .width = 16, -+ }, -+}; -+ -+static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 94, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 95, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 103, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 135, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 167, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 168, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 169, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 185, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 201, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 217, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 219, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 220, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 221, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 222, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 223, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 224, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 225, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field is2_ip4_other_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 94, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 95, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 103, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 135, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 167, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 168, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 176, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U112, -+ .offset = 192, -+ .width = 96, -+ }, -+}; -+ -+static const struct vcap_field is2_ip6_std_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 90, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 219, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 227, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 243, -+ .width = 40, -+ }, -+}; -+ -+static const struct vcap_field is2_ip_7tuple_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 18, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 83, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 85, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 98, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 111, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 112, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 115, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 118, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 119, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 120, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 168, -+ .width = 48, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 219, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 220, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 228, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 356, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 484, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 485, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 486, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 487, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 503, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 519, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 535, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 536, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 537, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 538, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 539, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 540, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 541, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 542, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 543, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es0_isdx_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_EGR_PORT_NO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 1, -+ .width = 6, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 7, -+ .width = 13, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 23, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 27, -+ .width = 1, -+ }, -+ [VCAP_KF_PROT_ACTIVE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 28, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 38, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field es2_mac_etype_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 96, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 144, -+ .width = 48, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 192, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 193, -+ .width = 16, -+ }, -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 209, -+ .width = 64, -+ }, -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 273, -+ .width = 1, -+ }, -+ [VCAP_KF_OAM_Y1731_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 274, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_arp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 95, -+ .width = 48, -+ }, -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 143, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 144, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_LEN_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 145, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_TGT_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 146, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 147, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 148, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 149, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 151, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 183, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 215, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 97, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 99, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 100, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 101, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 173, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 174, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 175, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 191, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 207, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 223, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 224, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 225, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 226, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 227, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 228, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 229, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 230, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 231, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es2_ip4_other_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 97, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 99, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 100, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 101, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 173, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 174, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U112, -+ .offset = 182, -+ .width = 96, -+ }, -+}; -+ -+static const struct vcap_field es2_ip_7tuple_keyfield[] = { -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 10, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 12, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 13, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 23, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 38, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 73, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 74, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 85, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 93, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 141, -+ .width = 48, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 191, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 192, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 193, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 201, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 329, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 457, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 458, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 459, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 460, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 476, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 492, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 508, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 509, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 510, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 511, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 512, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 513, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 514, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 515, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 516, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es2_ip6_std_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 97, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 225, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 226, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 234, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 250, -+ .width = 40, -+ }, -+}; -+ -+/* keyfield_set */ -+static const struct vcap_set is0_keyfield_set[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = { -+ .type_id = 0, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = { -+ .type_id = 2, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+}; -+ -+static const struct vcap_set is2_keyfield_set[] = { -+ [VCAP_KFS_MAC_ETYPE] = { -+ .type_id = 0, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_ARP] = { -+ .type_id = 3, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_TCP_UDP] = { -+ .type_id = 4, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_OTHER] = { -+ .type_id = 5, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP6_STD] = { -+ .type_id = 6, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP_7TUPLE] = { -+ .type_id = 1, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es0_keyfield_set[] = { -+ [VCAP_KFS_ISDX] = { -+ .type_id = 0, -+ .sw_per_item = 1, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es2_keyfield_set[] = { -+ [VCAP_KFS_MAC_ETYPE] = { -+ .type_id = 0, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_ARP] = { -+ .type_id = 1, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_TCP_UDP] = { -+ .type_id = 2, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_OTHER] = { -+ .type_id = 3, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP_7TUPLE] = { -+ .type_id = -1, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+ [VCAP_KFS_IP6_STD] = { -+ .type_id = 4, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+}; -+ -+/* keyfield_set map */ -+static const struct vcap_field *is0_keyfield_set_map[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, -+}; -+ -+static const struct vcap_field *is2_keyfield_set_map[] = { -+ [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, -+ [VCAP_KFS_ARP] = is2_arp_keyfield, -+ [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, -+ [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, -+ [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, -+ [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, -+}; -+ -+static const struct vcap_field *es0_keyfield_set_map[] = { -+ [VCAP_KFS_ISDX] = es0_isdx_keyfield, -+}; -+ -+static const struct vcap_field *es2_keyfield_set_map[] = { -+ [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, -+ [VCAP_KFS_ARP] = es2_arp_keyfield, -+ [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, -+ [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, -+ [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, -+ [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, -+}; -+ -+/* keyfield_set map sizes */ -+static int is0_keyfield_set_map_size[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), -+}; -+ -+static int is2_keyfield_set_map_size[] = { -+ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), -+ [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), -+ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), -+ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), -+ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), -+ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), -+}; -+ -+static int es0_keyfield_set_map_size[] = { -+ [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), -+}; -+ -+static int es2_keyfield_set_map_size[] = { -+ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), -+ [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), -+ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), -+ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), -+ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), -+ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), -+}; -+ -+/* actionfields */ -+static const struct vcap_field is0_classification_actionfield[] = { -+ [VCAP_AF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 6, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 12, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 13, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 16, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 2, -+ }, -+ [VCAP_AF_DEI_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 19, -+ .width = 1, -+ }, -+ [VCAP_AF_DEI_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 20, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 21, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 22, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 30, -+ .width = 7, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 37, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 43, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 66, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 10, -+ }, -+ [VCAP_AF_PAG_OVERRIDE_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 107, -+ .width = 8, -+ }, -+ [VCAP_AF_PAG_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 115, -+ .width = 8, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 167, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 170, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is0_full_actionfield[] = { -+ [VCAP_AF_DSCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 1, -+ .width = 6, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 2, -+ }, -+ [VCAP_AF_DEI_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 18, -+ .width = 1, -+ }, -+ [VCAP_AF_DEI_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 19, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 20, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 21, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 24, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 26, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 29, -+ .width = 7, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 36, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 42, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 65, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 66, -+ .width = 10, -+ }, -+ [VCAP_AF_MASK_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 76, -+ .width = 3, -+ }, -+ [VCAP_AF_PORT_MASK] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 79, -+ .width = 37, -+ }, -+ [VCAP_AF_PAG_OVERRIDE_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 174, -+ .width = 8, -+ }, -+ [VCAP_AF_PAG_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 182, -+ .width = 8, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 266, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 269, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is0_class_reduced_actionfield[] = { -+ [VCAP_AF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 5, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 6, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 9, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 10, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 3, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 23, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 46, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 47, -+ .width = 10, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 89, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 92, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is2_base_type_actionfield[] = { -+ [VCAP_AF_PIPELINE_FORCE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_PIPELINE_PT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 5, -+ }, -+ [VCAP_AF_HIT_ME_ONCE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 7, -+ .width = 1, -+ }, -+ [VCAP_AF_INTR_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 8, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_COPY_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 9, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 10, -+ .width = 3, -+ }, -+ [VCAP_AF_LRN_DIS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_AF_RT_DIS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 16, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 17, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 5, -+ }, -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 23, -+ .width = 1, -+ }, -+ [VCAP_AF_MASK_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_PORT_MASK] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 30, -+ .width = 37, -+ }, -+ [VCAP_AF_MIRROR_PROBE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 78, -+ .width = 2, -+ }, -+ [VCAP_AF_MATCH_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 131, -+ .width = 16, -+ }, -+ [VCAP_AF_MATCH_ID_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 147, -+ .width = 16, -+ }, -+ [VCAP_AF_CNT_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 163, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field es0_es0_actionfield[] = { -+ [VCAP_AF_PUSH_OUTER_TAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_AF_PUSH_INNER_TAG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_AF_TAG_A_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_A_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 6, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_A_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 8, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_A_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 11, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_B_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 19, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 22, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 31, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_A_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 34, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_A_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 46, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_A_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 49, -+ .width = 1, -+ }, -+ [VCAP_AF_VID_B_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 50, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_B_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 62, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_B_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 65, -+ .width = 1, -+ }, -+ [VCAP_AF_VID_C_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 66, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_C_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 78, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_C_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 81, -+ .width = 1, -+ }, -+ [VCAP_AF_POP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 82, -+ .width = 2, -+ }, -+ [VCAP_AF_UNTAG_VID_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_AF_PUSH_CUSTOMER_TAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 85, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_C_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 87, -+ .width = 2, -+ }, -+ [VCAP_AF_DSCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 127, -+ .width = 3, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 130, -+ .width = 6, -+ }, -+ [VCAP_AF_ESDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 319, -+ .width = 10, -+ }, -+ [VCAP_AF_FWD_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 438, -+ .width = 2, -+ }, -+ [VCAP_AF_CPU_QU] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 440, -+ .width = 3, -+ }, -+ [VCAP_AF_PIPELINE_PT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 443, -+ .width = 2, -+ }, -+ [VCAP_AF_PIPELINE_ACT] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 445, -+ .width = 1, -+ }, -+ [VCAP_AF_SWAP_MACS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 454, -+ .width = 1, -+ }, -+ [VCAP_AF_LOOP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 455, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_base_type_actionfield[] = { -+ [VCAP_AF_HIT_ME_ONCE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_INTR_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_FWD_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 2, -+ }, -+ [VCAP_AF_COPY_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 4, -+ .width = 14, -+ }, -+ [VCAP_AF_COPY_PORT_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 6, -+ }, -+ [VCAP_AF_MIRROR_PROBE_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 24, -+ .width = 2, -+ }, -+ [VCAP_AF_CPU_COPY_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_POLICE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 30, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_REMARK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 31, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 32, -+ .width = 5, -+ }, -+ [VCAP_AF_ES2_REW_CMD] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 37, -+ .width = 3, -+ }, -+ [VCAP_AF_CNT_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 40, -+ .width = 9, -+ }, -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 49, -+ .width = 1, -+ }, -+}; -+ -+/* actionfield_set */ -+static const struct vcap_set is0_actionfield_set[] = { -+ [VCAP_AFS_CLASSIFICATION] = { -+ .type_id = 1, -+ .sw_per_item = 2, -+ .sw_cnt = 6, -+ }, -+ [VCAP_AFS_FULL] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+ [VCAP_AFS_CLASS_REDUCED] = { -+ .type_id = 1, -+ .sw_per_item = 1, -+ .sw_cnt = 12, -+ }, -+}; -+ -+static const struct vcap_set is2_actionfield_set[] = { -+ [VCAP_AFS_BASE_TYPE] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+}; -+ -+static const struct vcap_set es0_actionfield_set[] = { -+ [VCAP_AFS_ES0] = { -+ .type_id = -1, -+ .sw_per_item = 1, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es2_actionfield_set[] = { -+ [VCAP_AFS_BASE_TYPE] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+}; -+ -+/* actionfield_set map */ -+static const struct vcap_field *is0_actionfield_set_map[] = { -+ [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, -+ [VCAP_AFS_FULL] = is0_full_actionfield, -+ [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, -+}; -+ -+static const struct vcap_field *is2_actionfield_set_map[] = { -+ [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, -+}; -+ -+static const struct vcap_field *es0_actionfield_set_map[] = { -+ [VCAP_AFS_ES0] = es0_es0_actionfield, -+}; -+ -+static const struct vcap_field *es2_actionfield_set_map[] = { -+ [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, -+}; -+ -+/* actionfield_set map size */ -+static int is0_actionfield_set_map_size[] = { -+ [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), -+ [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), -+ [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), -+}; -+ -+static int is2_actionfield_set_map_size[] = { -+ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), -+}; -+ -+static int es0_actionfield_set_map_size[] = { -+ [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), -+}; -+ -+static int es2_actionfield_set_map_size[] = { -+ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), -+}; -+ -+/* Type Groups */ -+static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 5, -+ .value = 16, -+ }, -+ { -+ .offset = 52, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 104, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 156, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 208, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 260, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 4, -+ .value = 0, -+ }, -+ { -+ .offset = 364, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 416, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 520, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 572, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 4, -+ .value = 8, -+ }, -+ { -+ .offset = 52, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 104, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 156, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 208, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 260, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { -+ [12] = is0_x12_keyfield_set_typegroups, -+ [6] = is0_x6_keyfield_set_typegroups, -+ [3] = is0_x3_keyfield_set_typegroups, -+ [2] = is0_x2_keyfield_set_typegroups, -+ [1] = is0_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { -+ [12] = is2_x12_keyfield_set_typegroups, -+ [6] = is2_x6_keyfield_set_typegroups, -+ [3] = is2_x3_keyfield_set_typegroups, -+ [1] = is2_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { -+ [1] = es0_x1_keyfield_set_typegroups, -+ [2] = NULL, -+}; -+ -+static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { -+ [12] = es2_x12_keyfield_set_typegroups, -+ [6] = es2_x6_keyfield_set_typegroups, -+ [3] = es2_x3_keyfield_set_typegroups, -+ [1] = es2_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 103, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 206, -+ .width = 2, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 103, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 1, -+ .value = 1, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 95, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 190, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 19, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 38, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { -+ [3] = is0_x3_actionfield_set_typegroups, -+ [2] = is0_x2_actionfield_set_typegroups, -+ [1] = is0_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { -+ [3] = is2_x3_actionfield_set_typegroups, -+ [1] = is2_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { -+ [1] = es0_x1_actionfield_set_typegroups, -+ [2] = NULL, -+}; -+ -+static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { -+ [3] = es2_x3_actionfield_set_typegroups, -+ [1] = es2_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+/* Keyfieldset names */ -+static const char * const vcap_keyfield_set_names[] = { -+ [VCAP_KFS_NO_VALUE] = "(None)", -+ [VCAP_KFS_ARP] = "VCAP_KFS_ARP", -+ [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", -+ [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", -+ [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", -+ [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", -+ [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", -+ [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", -+ [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", -+ [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", -+ [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", -+ [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", -+ [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", -+ [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", -+ [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", -+ [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", -+ [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", -+ [VCAP_KFS_OAM] = "VCAP_KFS_OAM", -+ [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", -+ [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", -+ [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", -+}; -+ -+/* Actionfieldset names */ -+static const char * const vcap_actionfield_set_names[] = { -+ [VCAP_AFS_NO_VALUE] = "(None)", -+ [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", -+ [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", -+ [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", -+ [VCAP_AFS_ES0] = "VCAP_AFS_ES0", -+ [VCAP_AFS_FULL] = "VCAP_AFS_FULL", -+ [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", -+}; -+ -+/* Keyfield names */ -+static const char * const vcap_keyfield_names[] = { -+ [VCAP_KF_NO_VALUE] = "(None)", -+ [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", -+ [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", -+ [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", -+ [VCAP_KF_8021BR_GRP] = "8021BR_GRP", -+ [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", -+ [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", -+ [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", -+ [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", -+ [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", -+ [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", -+ [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", -+ [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", -+ [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", -+ [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", -+ [VCAP_KF_8021Q_TPID] = "8021Q_TPID", -+ [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", -+ [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", -+ [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", -+ [VCAP_KF_8021Q_VID0] = "8021Q_VID0", -+ [VCAP_KF_8021Q_VID1] = "8021Q_VID1", -+ [VCAP_KF_8021Q_VID2] = "8021Q_VID2", -+ [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", -+ [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", -+ [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", -+ [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", -+ [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", -+ [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", -+ [VCAP_KF_COSID_CLS] = "COSID_CLS", -+ [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", -+ [VCAP_KF_ETYPE] = "ETYPE", -+ [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", -+ [VCAP_KF_HOST_MATCH] = "HOST_MATCH", -+ [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", -+ [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", -+ [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", -+ [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", -+ [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", -+ [VCAP_KF_IP4_IS] = "IP4_IS", -+ [VCAP_KF_IP_MC_IS] = "IP_MC_IS", -+ [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", -+ [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", -+ [VCAP_KF_ISDX_CLS] = "ISDX_CLS", -+ [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", -+ [VCAP_KF_L2_BC_IS] = "L2_BC_IS", -+ [VCAP_KF_L2_DMAC] = "L2_DMAC", -+ [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", -+ [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", -+ [VCAP_KF_L2_LLC] = "L2_LLC", -+ [VCAP_KF_L2_MC_IS] = "L2_MC_IS", -+ [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", -+ [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", -+ [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", -+ [VCAP_KF_L2_SMAC] = "L2_SMAC", -+ [VCAP_KF_L2_SNAP] = "L2_SNAP", -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", -+ [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", -+ [VCAP_KF_L3_DSCP] = "L3_DSCP", -+ [VCAP_KF_L3_DST_IS] = "L3_DST_IS", -+ [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", -+ [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", -+ [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", -+ [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", -+ [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", -+ [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", -+ [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", -+ [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", -+ [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", -+ [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", -+ [VCAP_KF_L3_RT_IS] = "L3_RT_IS", -+ [VCAP_KF_L3_TOS] = "L3_TOS", -+ [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", -+ [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", -+ [VCAP_KF_L4_1588_VER] = "L4_1588_VER", -+ [VCAP_KF_L4_ACK] = "L4_ACK", -+ [VCAP_KF_L4_DPORT] = "L4_DPORT", -+ [VCAP_KF_L4_FIN] = "L4_FIN", -+ [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", -+ [VCAP_KF_L4_PSH] = "L4_PSH", -+ [VCAP_KF_L4_RNG] = "L4_RNG", -+ [VCAP_KF_L4_RST] = "L4_RST", -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", -+ [VCAP_KF_L4_SPORT] = "L4_SPORT", -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", -+ [VCAP_KF_L4_SYN] = "L4_SYN", -+ [VCAP_KF_L4_URG] = "L4_URG", -+ [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", -+ [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", -+ [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", -+ [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", -+ [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", -+ [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", -+ [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", -+ [VCAP_KF_OAM_MEPID] = "OAM_MEPID", -+ [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", -+ [VCAP_KF_OAM_VER] = "OAM_VER", -+ [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", -+ [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", -+ [VCAP_KF_TCP_IS] = "TCP_IS", -+ [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", -+ [VCAP_KF_TYPE] = "TYPE", -+}; -+ -+/* Actionfield names */ -+static const char * const vcap_actionfield_names[] = { -+ [VCAP_AF_NO_VALUE] = "(None)", -+ [VCAP_AF_ACL_ID] = "ACL_ID", -+ [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", -+ [VCAP_AF_CNT_ID] = "CNT_ID", -+ [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", -+ [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", -+ [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", -+ [VCAP_AF_CPU_QU] = "CPU_QU", -+ [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", -+ [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", -+ [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", -+ [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", -+ [VCAP_AF_DEI_ENA] = "DEI_ENA", -+ [VCAP_AF_DEI_VAL] = "DEI_VAL", -+ [VCAP_AF_DP_ENA] = "DP_ENA", -+ [VCAP_AF_DP_VAL] = "DP_VAL", -+ [VCAP_AF_DSCP_ENA] = "DSCP_ENA", -+ [VCAP_AF_DSCP_SEL] = "DSCP_SEL", -+ [VCAP_AF_DSCP_VAL] = "DSCP_VAL", -+ [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", -+ [VCAP_AF_ESDX] = "ESDX", -+ [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", -+ [VCAP_AF_FWD_MODE] = "FWD_MODE", -+ [VCAP_AF_FWD_SEL] = "FWD_SEL", -+ [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", -+ [VCAP_AF_HOST_MATCH] = "HOST_MATCH", -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", -+ [VCAP_AF_INTR_ENA] = "INTR_ENA", -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", -+ [VCAP_AF_ISDX_ENA] = "ISDX_ENA", -+ [VCAP_AF_ISDX_VAL] = "ISDX_VAL", -+ [VCAP_AF_LOOP_ENA] = "LOOP_ENA", -+ [VCAP_AF_LRN_DIS] = "LRN_DIS", -+ [VCAP_AF_MAP_IDX] = "MAP_IDX", -+ [VCAP_AF_MAP_KEY] = "MAP_KEY", -+ [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", -+ [VCAP_AF_MASK_MODE] = "MASK_MODE", -+ [VCAP_AF_MATCH_ID] = "MATCH_ID", -+ [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", -+ [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", -+ [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", -+ [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", -+ [VCAP_AF_NXT_IDX] = "NXT_IDX", -+ [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", -+ [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", -+ [VCAP_AF_PAG_VAL] = "PAG_VAL", -+ [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", -+ [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", -+ [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", -+ [VCAP_AF_PCP_ENA] = "PCP_ENA", -+ [VCAP_AF_PCP_VAL] = "PCP_VAL", -+ [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", -+ [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", -+ [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", -+ [VCAP_AF_POLICE_ENA] = "POLICE_ENA", -+ [VCAP_AF_POLICE_IDX] = "POLICE_IDX", -+ [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", -+ [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", -+ [VCAP_AF_POP_VAL] = "POP_VAL", -+ [VCAP_AF_PORT_MASK] = "PORT_MASK", -+ [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", -+ [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", -+ [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", -+ [VCAP_AF_QOS_ENA] = "QOS_ENA", -+ [VCAP_AF_QOS_VAL] = "QOS_VAL", -+ [VCAP_AF_REW_OP] = "REW_OP", -+ [VCAP_AF_RT_DIS] = "RT_DIS", -+ [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", -+ [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", -+ [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", -+ [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", -+ [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", -+ [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", -+ [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", -+ [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", -+ [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", -+ [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", -+ [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", -+ [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", -+ [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", -+ [VCAP_AF_TYPE] = "TYPE", -+ [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", -+ [VCAP_AF_VID_A_VAL] = "VID_A_VAL", -+ [VCAP_AF_VID_B_VAL] = "VID_B_VAL", -+ [VCAP_AF_VID_C_VAL] = "VID_C_VAL", -+ [VCAP_AF_VID_VAL] = "VID_VAL", -+}; -+ -+/* VCAPs */ -+const struct vcap_info lan969x_vcaps[] = { -+ [VCAP_TYPE_IS0] = { -+ .name = "is0", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 103, -+ .default_cnt = 70, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = is0_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), -+ .actionfield_set = is0_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), -+ .keyfield_set_map = is0_keyfield_set_map, -+ .keyfield_set_map_size = is0_keyfield_set_map_size, -+ .actionfield_set_map = is0_actionfield_set_map, -+ .actionfield_set_map_size = is0_actionfield_set_map_size, -+ .keyfield_set_typegroups = is0_keyfield_set_typegroups, -+ .actionfield_set_typegroups = is0_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_IS2] = { -+ .name = "is2", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 103, -+ .default_cnt = 38, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = is2_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), -+ .actionfield_set = is2_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), -+ .keyfield_set_map = is2_keyfield_set_map, -+ .keyfield_set_map_size = is2_keyfield_set_map_size, -+ .actionfield_set_map = is2_actionfield_set_map, -+ .actionfield_set_map_size = is2_actionfield_set_map_size, -+ .keyfield_set_typegroups = is2_keyfield_set_typegroups, -+ .actionfield_set_typegroups = is2_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_ES0] = { -+ .name = "es0", -+ .rows = 1536, -+ .sw_count = 1, -+ .sw_width = 51, -+ .sticky_width = 1, -+ .act_width = 469, -+ .default_cnt = 35, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = es0_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), -+ .actionfield_set = es0_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), -+ .keyfield_set_map = es0_keyfield_set_map, -+ .keyfield_set_map_size = es0_keyfield_set_map_size, -+ .actionfield_set_map = es0_actionfield_set_map, -+ .actionfield_set_map_size = es0_actionfield_set_map_size, -+ .keyfield_set_typegroups = es0_keyfield_set_typegroups, -+ .actionfield_set_typegroups = es0_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_ES2] = { -+ .name = "es2", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 19, -+ .default_cnt = 39, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = es2_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), -+ .actionfield_set = es2_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), -+ .keyfield_set_map = es2_keyfield_set_map, -+ .keyfield_set_map_size = es2_keyfield_set_map_size, -+ .actionfield_set_map = es2_actionfield_set_map, -+ .actionfield_set_map_size = es2_actionfield_set_map_size, -+ .keyfield_set_typegroups = es2_keyfield_set_typegroups, -+ .actionfield_set_typegroups = es2_actionfield_set_typegroups, -+ }, -+}; -+ -+const struct vcap_statistics lan969x_vcap_stats = { -+ .name = "lan969x", -+ .count = 4, -+ .keyfield_set_names = vcap_keyfield_set_names, -+ .actionfield_set_names = vcap_actionfield_set_names, -+ .keyfield_names = vcap_keyfield_names, -+ .actionfield_names = vcap_actionfield_names, -+}; diff --git a/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch b/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch deleted file mode 100644 index 803c991d54..0000000000 --- a/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 4a4336e333f869544dabc729812f57f99f5f2ff8 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 1 Nov 2024 08:09:12 +0100 -Subject: [PATCH 63/82] net: lan969x: add VCAP configuration data -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add configuration data (for consumption by the VCAP API) for the four -VCAP's that we are going to support. The following VCAP's will be -supported: - - - VCAP CLM: (also known as IS0) is part of the analyzer and enables - frame classification using VCAP functionality. - - - VCAP IS2: is part of ANA_ACL and enables access control lists, using - VCAP functionality. - - - VCAP ES0: is part of the rewriter and enables rewriting of frames - using VCAP functionality. - - - VCAP ES2: is part of EACL and enables egress access control lists - using VCAP functionality - -The two VCAP's: CLM and IS2 use shared resources from the SUPER VCAP. -The SUPER VCAP is a shared pool of 6 blocks that can be distributed -freely among CLM and IS2. Each block in the pool has 3,072 addresses -with entries, actions, and counters. ES0 and ES2 does not use shared -resources. - -In the configuration data for lan969x CLM uses blocks 2-4 with a total -of 6 lookups. IS2 uses blocks 0-1 with a total of 4 lookups. - -Reviewed-by: Steen Hegelund -Reviewed-by: Jens Emil Schulz Østergaard -Signed-off-by: Daniel Machon -Signed-off-by: Paolo Abeni ---- - .../net/ethernet/microchip/lan969x/Makefile | 2 +- - .../net/ethernet/microchip/lan969x/lan969x.c | 1 + - .../net/ethernet/microchip/lan969x/lan969x.h | 3 + - .../microchip/lan969x/lan969x_vcap_impl.c | 85 +++++++++++++++++++ - 4 files changed, 90 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c - ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -6,7 +6,7 @@ - obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o - - lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ -- lan969x_vcap_ag_api.o -+ lan969x_vcap_ag_api.o lan969x_vcap_impl.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c -@@ -321,6 +321,7 @@ static const struct sparx5_consts lan969 - .tod_pin = 4, - .vcaps = lan969x_vcaps, - .vcap_stats = &lan969x_vcap_stats, -+ .vcaps_cfg = lan969x_vcap_inst_cfg, - }; - - static const struct sparx5_ops lan969x_ops = { ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h -@@ -18,6 +18,9 @@ extern const struct sparx5_match_data la - extern const struct vcap_statistics lan969x_vcap_stats; - extern const struct vcap_info lan969x_vcaps[]; - -+/* lan969x_vcap_impl.c */ -+extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; -+ - /* lan969x_regs.c */ - extern const unsigned int lan969x_tsize[TSIZE_LAST]; - extern const unsigned int lan969x_raddr[RADDR_LAST]; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c -@@ -0,0 +1,85 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "vcap_api.h" -+#include "lan969x.h" -+ -+const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-0 */ -+ .vinst = 0, -+ .map_id = 1, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L0, -+ .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, -+ .blockno = 2, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-1 */ -+ .vinst = 1, -+ .map_id = 2, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L2, -+ .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, -+ .blockno = 3, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-2 */ -+ .vinst = 2, -+ .map_id = 3, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L4, -+ .last_cid = SPARX5_VCAP_CID_IS0_MAX, -+ .blockno = 4, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS2, /* IS2-0 */ -+ .vinst = 0, -+ .map_id = 4, -+ .lookups = SPARX5_IS2_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -+ .first_cid = SPARX5_VCAP_CID_IS2_L0, -+ .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, -+ .blockno = 0, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS2, /* IS2-1 */ -+ .vinst = 1, -+ .map_id = 5, -+ .lookups = SPARX5_IS2_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -+ .first_cid = SPARX5_VCAP_CID_IS2_L2, -+ .last_cid = SPARX5_VCAP_CID_IS2_MAX, -+ .blockno = 1, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_ES0, -+ .lookups = SPARX5_ES0_LOOKUPS, -+ .lookups_per_instance = SPARX5_ES0_LOOKUPS, -+ .first_cid = SPARX5_VCAP_CID_ES0_L0, -+ .last_cid = SPARX5_VCAP_CID_ES0_MAX, -+ .count = 1536, -+ .ingress = false, -+ }, -+ { -+ .vtype = VCAP_TYPE_ES2, -+ .lookups = SPARX5_ES2_LOOKUPS, -+ .lookups_per_instance = SPARX5_ES2_LOOKUPS, -+ .first_cid = SPARX5_VCAP_CID_ES2_L0, -+ .last_cid = SPARX5_VCAP_CID_ES2_MAX, -+ .count = 1024, -+ .ingress = false, -+ }, -+}; diff --git a/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch b/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch deleted file mode 100644 index fb93fd7f74..0000000000 --- a/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e63e43479af9d5817eecd34e26af67a5064937b4 Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Wed, 13 Nov 2024 12:55:08 +0100 -Subject: [PATCH 64/82] net: sparx5: add missing lan969x Kconfig dependency - -The sparx5 switchdev driver can be built either with or without support -for the Lan969x switch. However, it cannot be built-in when the lan969x -driver is a loadable module because of a link-time dependency: - -arm-linux-gnueabi-ld: drivers/net/ethernet/microchip/sparx5/sparx5_main.o:(.rodata+0xd44): undefined reference to `lan969x_desc' - -Add a Kconfig dependency to reflect this in Kconfig, allowing all -the valid configurations but forcing sparx5 to be a loadable module -as well if lan969x is. - -Fixes: 98a01119608d ("net: sparx5: add compatible string for lan969x") -Signed-off-by: Arnd Bergmann -Reviewed-by: Daniel Machon -Link: https://patch.msgid.link/20241113115513.4132548-1-arnd@kernel.org -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/lan969x/Kconfig | 2 +- - drivers/net/ethernet/microchip/lan969x/Makefile | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/lan969x/Kconfig -+++ b/drivers/net/ethernet/microchip/lan969x/Kconfig -@@ -1,5 +1,5 @@ - config LAN969X_SWITCH -- tristate "Lan969x switch driver" -+ bool "Lan969x switch driver" - depends on SPARX5_SWITCH - help - This driver supports the lan969x family of network switch devices. ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ b/drivers/net/ethernet/microchip/lan969x/Makefile -@@ -3,7 +3,7 @@ - # Makefile for the Microchip lan969x network device drivers. - # - --obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o -+obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o - - lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ - lan969x_vcap_ag_api.o lan969x_vcap_impl.o diff --git a/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch b/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch deleted file mode 100644 index 425c6c5009..0000000000 --- a/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch +++ /dev/null @@ -1,9733 +0,0 @@ -From 8b097eba8b5e48efe73d5298ff2dce11cd9d16cb Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 5 Dec 2024 14:54:24 +0100 -Subject: [PATCH 65/82] net: lan969x: fix cyclic dependency reported by depmod - -Depmod reports a cyclic dependency between modules sparx5-switch.ko and -lan969x-switch.ko: - -depmod: ERROR: Cycle detected: lan969x_switch -> sparx5_switch -> lan969x_switch -depmod: ERROR: Found 2 modules in dependency cycles! -make[2]: *** [scripts/Makefile.modinst:132: depmod] Error 1 -make: *** [Makefile:224: __sub-make] Error 2 - -This makes sense, as they both require symbols from each other. - -Fix this by compiling lan969x support into the sparx5-switch.ko module. -In order to do this, in a sensible way, we move the lan969x/ dir into -the sparx5/ dir and do some code cleanup of code that is no longer -required. - -After this patch, depmod will no longer complain, as lan969x support is -compiled into the sparx5-swicth.ko module, and can no longer be compiled -as a standalone module. - -Fixes: 98a01119608d ("net: sparx5: add compatible string for lan969x") -Signed-off-by: Daniel Machon -Signed-off-by: David S. Miller ---- - MAINTAINERS | 2 +- - drivers/net/ethernet/microchip/Kconfig | 1 - - drivers/net/ethernet/microchip/Makefile | 1 - - drivers/net/ethernet/microchip/lan969x/Kconfig | 5 ----- - drivers/net/ethernet/microchip/lan969x/Makefile | 13 ------------- - drivers/net/ethernet/microchip/sparx5/Kconfig | 6 ++++++ - drivers/net/ethernet/microchip/sparx5/Makefile | 6 ++++++ - .../microchip/{ => sparx5}/lan969x/lan969x.c | 5 ----- - .../microchip/{ => sparx5}/lan969x/lan969x.h | 0 - .../{ => sparx5}/lan969x/lan969x_calendar.c | 0 - .../microchip/{ => sparx5}/lan969x/lan969x_regs.c | 0 - .../{ => sparx5}/lan969x/lan969x_vcap_ag_api.c | 0 - .../{ => sparx5}/lan969x/lan969x_vcap_impl.c | 0 - .../net/ethernet/microchip/sparx5/sparx5_calendar.c | 2 -- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 4 ++-- - drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c | 1 - - 16 files changed, 15 insertions(+), 31 deletions(-) - delete mode 100644 drivers/net/ethernet/microchip/lan969x/Kconfig - delete mode 100644 drivers/net/ethernet/microchip/lan969x/Makefile - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.c (98%) - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.h (100%) - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_calendar.c (100%) - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_regs.c (100%) - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_ag_api.c (100%) - rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_impl.c (100%) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -15165,7 +15165,7 @@ M: Daniel Machon ---- a/drivers/net/ethernet/microchip/Kconfig -+++ b/drivers/net/ethernet/microchip/Kconfig -@@ -59,7 +59,6 @@ config LAN743X - - source "drivers/net/ethernet/microchip/lan865x/Kconfig" - source "drivers/net/ethernet/microchip/lan966x/Kconfig" --source "drivers/net/ethernet/microchip/lan969x/Kconfig" - source "drivers/net/ethernet/microchip/sparx5/Kconfig" - source "drivers/net/ethernet/microchip/vcap/Kconfig" - source "drivers/net/ethernet/microchip/fdma/Kconfig" ---- a/drivers/net/ethernet/microchip/Makefile -+++ b/drivers/net/ethernet/microchip/Makefile -@@ -11,7 +11,6 @@ lan743x-objs := lan743x_main.o lan743x_e - - obj-$(CONFIG_LAN865X) += lan865x/ - obj-$(CONFIG_LAN966X_SWITCH) += lan966x/ --obj-$(CONFIG_LAN969X_SWITCH) += lan969x/ - obj-$(CONFIG_SPARX5_SWITCH) += sparx5/ - obj-$(CONFIG_VCAP) += vcap/ - obj-$(CONFIG_FDMA) += fdma/ ---- a/drivers/net/ethernet/microchip/lan969x/Kconfig -+++ /dev/null -@@ -1,5 +0,0 @@ --config LAN969X_SWITCH -- bool "Lan969x switch driver" -- depends on SPARX5_SWITCH -- help -- This driver supports the lan969x family of network switch devices. ---- a/drivers/net/ethernet/microchip/lan969x/Makefile -+++ /dev/null -@@ -1,13 +0,0 @@ --# SPDX-License-Identifier: GPL-2.0-only --# --# Makefile for the Microchip lan969x network device drivers. --# -- --obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o -- --lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ -- lan969x_vcap_ag_api.o lan969x_vcap_impl.o -- --# Provide include files --ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma --ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap ---- a/drivers/net/ethernet/microchip/sparx5/Kconfig -+++ b/drivers/net/ethernet/microchip/sparx5/Kconfig -@@ -24,3 +24,9 @@ config SPARX5_DCB - DSCP and PCP. - - If unsure, set to Y. -+ -+config LAN969X_SWITCH -+ bool "Lan969x switch driver" -+ depends on SPARX5_SWITCH -+ help -+ This driver supports the lan969x family of network switch devices. ---- a/drivers/net/ethernet/microchip/sparx5/Makefile -+++ b/drivers/net/ethernet/microchip/sparx5/Makefile -@@ -16,6 +16,12 @@ sparx5-switch-y := sparx5_main.o sparx5 - sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o - sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o - -+sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \ -+ lan969x/lan969x.o \ -+ lan969x/lan969x_calendar.o \ -+ lan969x/lan969x_vcap_ag_api.o \ -+ lan969x/lan969x_vcap_impl.o -+ - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.c -+++ /dev/null -@@ -1,353 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* Microchip lan969x Switch driver -- * -- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -- */ -- --#include "lan969x.h" -- --#define LAN969X_SDLB_GRP_CNT 5 --#define LAN969X_HSCH_LEAK_GRP_CNT 4 -- --static const struct sparx5_main_io_resource lan969x_main_iomap[] = { -- { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ -- { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ -- { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ -- { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ -- { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ -- { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ -- { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ -- { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ -- { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ -- { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ -- { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ -- { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ -- { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ -- { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ -- { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ -- { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ -- { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ -- { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ -- { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ -- { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ -- { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ -- { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ -- { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ -- { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ -- { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ -- { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ -- { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ -- { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ -- { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ -- { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ -- { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ -- { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ -- { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ -- { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ -- { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ -- { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ -- { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ -- { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ -- { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ -- { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ -- { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ -- { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ -- { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ -- { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ -- { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ -- { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ -- { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ -- { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ -- { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ -- { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ -- { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ -- { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ -- { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ -- { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ -- { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ -- { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ -- { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ -- { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ -- { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ -- { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ -- { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ -- { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ -- { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ -- { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ -- { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ -- { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ -- { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ -- { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ -- { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ -- { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ -- { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ -- { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ -- { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ -- { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ -- { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ -- { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ -- { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ -- { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ -- { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ -- { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ -- { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ -- { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ -- { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ --}; -- --static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { -- { 1000000000, 8192 / 2, 64 }, /* 1 G */ -- { 500000000, 8192 / 2, 64 }, /* 500 M */ -- { 100000000, 8192 / 4, 64 }, /* 100 M */ -- { 50000000, 8192 / 4, 64 }, /* 50 M */ -- { 5000000, 8192 / 8, 64 }, /* 10 M */ --}; -- --static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { -- 655355, 1048568, 6553550, 10485680 --}; -- --static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) --{ -- return &lan969x_sdlb_groups[idx]; --} -- --static u32 lan969x_get_hsch_max_group_rate(int grp) --{ -- return lan969x_hsch_max_group_rate[grp]; --} -- --static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) --{ -- if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) -- return port; -- -- /* 10G */ -- switch (port) { -- case 0: -- return 12; -- case 4: -- return 13; -- case 8: -- return 14; -- case 12: -- return 0; -- default: -- return port; -- } --} -- --static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) --{ -- if (lan969x_port_is_5g(port)) { -- switch (port) { -- case 9: -- return 0; -- case 13: -- return 1; -- case 17: -- return 2; -- case 21: -- return 3; -- } -- } -- -- if (lan969x_port_is_10g(port)) { -- switch (port) { -- case 0: -- return 0; -- case 4: -- return 1; -- case 8: -- return 2; -- case 12: -- return 3; -- case 16: -- return 4; -- case 20: -- return 5; -- case 24: -- return 6; -- case 25: -- return 7; -- case 26: -- return 8; -- case 27: -- return 9; -- } -- } -- -- /* 2g5 port */ -- return port; --} -- --static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, -- struct sparx5_port_config *conf) --{ -- u32 portno = port->portno; -- u32 inst; -- -- if (port->conf.portmode == conf->portmode) -- return 0; /* Nothing to do */ -- -- switch (conf->portmode) { -- case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ -- inst = (portno - portno % 4) / 4; -- spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); -- break; -- default: -- break; -- } -- return 0; --} -- --static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) --{ -- int budget = SPARX5_MAX_PTP_ID; -- struct sparx5 *sparx5 = args; -- -- while (budget--) { -- struct sk_buff *skb, *skb_tmp, *skb_match = NULL; -- struct skb_shared_hwtstamps shhwtstamps; -- struct sparx5_port *port; -- struct timespec64 ts; -- unsigned long flags; -- u32 val, id, txport; -- u32 delay; -- -- val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -- -- /* Check if a timestamp can be retrieved */ -- if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -- break; -- -- WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); -- -- if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) -- continue; -- -- /* Retrieve the ts Tx port */ -- txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); -- -- /* Retrieve its associated skb */ -- port = sparx5->ports[txport]; -- -- /* Retrieve the delay */ -- delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -- delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); -- -- /* Get next timestamp from fifo, which needs to be the -- * rx timestamp which represents the id of the frame -- */ -- spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -- PTP_TWOSTEP_CTRL_PTP_NXT, -- sparx5, PTP_TWOSTEP_CTRL); -- -- val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -- -- /* Check if a timestamp can be retrieved */ -- if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -- break; -- -- /* Read RX timestamping to get the ID */ -- id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -- id <<= 8; -- id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); -- -- spin_lock_irqsave(&port->tx_skbs.lock, flags); -- skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { -- if (SPARX5_SKB_CB(skb)->ts_id != id) -- continue; -- -- __skb_unlink(skb, &port->tx_skbs); -- skb_match = skb; -- break; -- } -- spin_unlock_irqrestore(&port->tx_skbs.lock, flags); -- -- /* Next ts */ -- spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -- PTP_TWOSTEP_CTRL_PTP_NXT, -- sparx5, PTP_TWOSTEP_CTRL); -- -- if (WARN_ON(!skb_match)) -- continue; -- -- spin_lock(&sparx5->ptp_ts_id_lock); -- sparx5->ptp_skbs--; -- spin_unlock(&sparx5->ptp_ts_id_lock); -- -- /* Get the h/w timestamp */ -- sparx5_get_hwtimestamp(sparx5, &ts, delay); -- -- /* Set the timestamp in the skb */ -- shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); -- skb_tstamp_tx(skb_match, &shhwtstamps); -- -- dev_kfree_skb_any(skb_match); -- } -- -- return IRQ_HANDLED; --} -- --static const struct sparx5_regs lan969x_regs = { -- .tsize = lan969x_tsize, -- .gaddr = lan969x_gaddr, -- .gcnt = lan969x_gcnt, -- .gsize = lan969x_gsize, -- .raddr = lan969x_raddr, -- .rcnt = lan969x_rcnt, -- .fpos = lan969x_fpos, -- .fsize = lan969x_fsize, --}; -- --static const struct sparx5_consts lan969x_consts = { -- .n_ports = 30, -- .n_ports_all = 35, -- .n_hsch_l1_elems = 32, -- .n_hsch_queues = 4, -- .n_lb_groups = 5, -- .n_pgids = 1054, /* (1024 + n_ports) */ -- .n_sio_clks = 1, -- .n_own_upsids = 1, -- .n_auto_cals = 4, -- .n_filters = 256, -- .n_gates = 256, -- .n_sdlbs = 496, -- .n_dsm_cal_taxis = 5, -- .buf_size = 1572864, -- .qres_max_prio_idx = 315, -- .qres_max_colour_idx = 323, -- .tod_pin = 4, -- .vcaps = lan969x_vcaps, -- .vcap_stats = &lan969x_vcap_stats, -- .vcaps_cfg = lan969x_vcap_inst_cfg, --}; -- --static const struct sparx5_ops lan969x_ops = { -- .is_port_2g5 = &lan969x_port_is_2g5, -- .is_port_5g = &lan969x_port_is_5g, -- .is_port_10g = &lan969x_port_is_10g, -- .is_port_25g = &lan969x_port_is_25g, -- .get_port_dev_index = &lan969x_port_dev_mapping, -- .get_port_dev_bit = &lan969x_get_dev_mode_bit, -- .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, -- .get_sdlb_group = &lan969x_get_sdlb_group, -- .set_port_mux = &lan969x_port_mux_set, -- .ptp_irq_handler = &lan969x_ptp_irq_handler, -- .dsm_calendar_calc = &lan969x_dsm_calendar_calc, --}; -- --const struct sparx5_match_data lan969x_desc = { -- .iomap = lan969x_main_iomap, -- .iomap_size = ARRAY_SIZE(lan969x_main_iomap), -- .ioranges = 2, -- .regs = &lan969x_regs, -- .consts = &lan969x_consts, -- .ops = &lan969x_ops, --}; --EXPORT_SYMBOL_GPL(lan969x_desc); -- --MODULE_DESCRIPTION("Microchip lan969x switch driver"); --MODULE_AUTHOR("Daniel Machon "); --MODULE_LICENSE("Dual MIT/GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -0,0 +1,348 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "lan969x.h" -+ -+#define LAN969X_SDLB_GRP_CNT 5 -+#define LAN969X_HSCH_LEAK_GRP_CNT 4 -+ -+static const struct sparx5_main_io_resource lan969x_main_iomap[] = { -+ { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ -+ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ -+ { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ -+ { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ -+ { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ -+ { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ -+ { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ -+ { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ -+ { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ -+ { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ -+ { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ -+ { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ -+ { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ -+ { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ -+ { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ -+ { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ -+ { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ -+ { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ -+ { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ -+ { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ -+ { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ -+ { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ -+ { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ -+ { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ -+ { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ -+ { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ -+ { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ -+ { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ -+ { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ -+ { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ -+ { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ -+ { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ -+ { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ -+ { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ -+ { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ -+ { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ -+ { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ -+ { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ -+ { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ -+ { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ -+ { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ -+ { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ -+ { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ -+ { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ -+ { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ -+ { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ -+ { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ -+ { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ -+ { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ -+ { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ -+ { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ -+ { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ -+ { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ -+ { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ -+ { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ -+ { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ -+ { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ -+ { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ -+ { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ -+ { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ -+ { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ -+ { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ -+ { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ -+ { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ -+ { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ -+ { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ -+ { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ -+ { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ -+ { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ -+ { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ -+ { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ -+ { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ -+ { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ -+ { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ -+ { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ -+ { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ -+ { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ -+ { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ -+ { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ -+ { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ -+ { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ -+ { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ -+ { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ -+}; -+ -+static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { -+ { 1000000000, 8192 / 2, 64 }, /* 1 G */ -+ { 500000000, 8192 / 2, 64 }, /* 500 M */ -+ { 100000000, 8192 / 4, 64 }, /* 100 M */ -+ { 50000000, 8192 / 4, 64 }, /* 50 M */ -+ { 5000000, 8192 / 8, 64 }, /* 10 M */ -+}; -+ -+static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { -+ 655355, 1048568, 6553550, 10485680 -+}; -+ -+static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) -+{ -+ return &lan969x_sdlb_groups[idx]; -+} -+ -+static u32 lan969x_get_hsch_max_group_rate(int grp) -+{ -+ return lan969x_hsch_max_group_rate[grp]; -+} -+ -+static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) -+{ -+ if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) -+ return port; -+ -+ /* 10G */ -+ switch (port) { -+ case 0: -+ return 12; -+ case 4: -+ return 13; -+ case 8: -+ return 14; -+ case 12: -+ return 0; -+ default: -+ return port; -+ } -+} -+ -+static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) -+{ -+ if (lan969x_port_is_5g(port)) { -+ switch (port) { -+ case 9: -+ return 0; -+ case 13: -+ return 1; -+ case 17: -+ return 2; -+ case 21: -+ return 3; -+ } -+ } -+ -+ if (lan969x_port_is_10g(port)) { -+ switch (port) { -+ case 0: -+ return 0; -+ case 4: -+ return 1; -+ case 8: -+ return 2; -+ case 12: -+ return 3; -+ case 16: -+ return 4; -+ case 20: -+ return 5; -+ case 24: -+ return 6; -+ case 25: -+ return 7; -+ case 26: -+ return 8; -+ case 27: -+ return 9; -+ } -+ } -+ -+ /* 2g5 port */ -+ return port; -+} -+ -+static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ u32 portno = port->portno; -+ u32 inst; -+ -+ if (port->conf.portmode == conf->portmode) -+ return 0; /* Nothing to do */ -+ -+ switch (conf->portmode) { -+ case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ -+ inst = (portno - portno % 4) / 4; -+ spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); -+ break; -+ default: -+ break; -+ } -+ return 0; -+} -+ -+static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) -+{ -+ int budget = SPARX5_MAX_PTP_ID; -+ struct sparx5 *sparx5 = args; -+ -+ while (budget--) { -+ struct sk_buff *skb, *skb_tmp, *skb_match = NULL; -+ struct skb_shared_hwtstamps shhwtstamps; -+ struct sparx5_port *port; -+ struct timespec64 ts; -+ unsigned long flags; -+ u32 val, id, txport; -+ u32 delay; -+ -+ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -+ -+ /* Check if a timestamp can be retrieved */ -+ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -+ break; -+ -+ WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); -+ -+ if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) -+ continue; -+ -+ /* Retrieve the ts Tx port */ -+ txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); -+ -+ /* Retrieve its associated skb */ -+ port = sparx5->ports[txport]; -+ -+ /* Retrieve the delay */ -+ delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -+ delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); -+ -+ /* Get next timestamp from fifo, which needs to be the -+ * rx timestamp which represents the id of the frame -+ */ -+ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -+ PTP_TWOSTEP_CTRL_PTP_NXT, -+ sparx5, PTP_TWOSTEP_CTRL); -+ -+ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); -+ -+ /* Check if a timestamp can be retrieved */ -+ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) -+ break; -+ -+ /* Read RX timestamping to get the ID */ -+ id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); -+ id <<= 8; -+ id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); -+ -+ spin_lock_irqsave(&port->tx_skbs.lock, flags); -+ skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { -+ if (SPARX5_SKB_CB(skb)->ts_id != id) -+ continue; -+ -+ __skb_unlink(skb, &port->tx_skbs); -+ skb_match = skb; -+ break; -+ } -+ spin_unlock_irqrestore(&port->tx_skbs.lock, flags); -+ -+ /* Next ts */ -+ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), -+ PTP_TWOSTEP_CTRL_PTP_NXT, -+ sparx5, PTP_TWOSTEP_CTRL); -+ -+ if (WARN_ON(!skb_match)) -+ continue; -+ -+ spin_lock(&sparx5->ptp_ts_id_lock); -+ sparx5->ptp_skbs--; -+ spin_unlock(&sparx5->ptp_ts_id_lock); -+ -+ /* Get the h/w timestamp */ -+ sparx5_get_hwtimestamp(sparx5, &ts, delay); -+ -+ /* Set the timestamp in the skb */ -+ shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); -+ skb_tstamp_tx(skb_match, &shhwtstamps); -+ -+ dev_kfree_skb_any(skb_match); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct sparx5_regs lan969x_regs = { -+ .tsize = lan969x_tsize, -+ .gaddr = lan969x_gaddr, -+ .gcnt = lan969x_gcnt, -+ .gsize = lan969x_gsize, -+ .raddr = lan969x_raddr, -+ .rcnt = lan969x_rcnt, -+ .fpos = lan969x_fpos, -+ .fsize = lan969x_fsize, -+}; -+ -+static const struct sparx5_consts lan969x_consts = { -+ .n_ports = 30, -+ .n_ports_all = 35, -+ .n_hsch_l1_elems = 32, -+ .n_hsch_queues = 4, -+ .n_lb_groups = 5, -+ .n_pgids = 1054, /* (1024 + n_ports) */ -+ .n_sio_clks = 1, -+ .n_own_upsids = 1, -+ .n_auto_cals = 4, -+ .n_filters = 256, -+ .n_gates = 256, -+ .n_sdlbs = 496, -+ .n_dsm_cal_taxis = 5, -+ .buf_size = 1572864, -+ .qres_max_prio_idx = 315, -+ .qres_max_colour_idx = 323, -+ .tod_pin = 4, -+ .vcaps = lan969x_vcaps, -+ .vcap_stats = &lan969x_vcap_stats, -+ .vcaps_cfg = lan969x_vcap_inst_cfg, -+}; -+ -+static const struct sparx5_ops lan969x_ops = { -+ .is_port_2g5 = &lan969x_port_is_2g5, -+ .is_port_5g = &lan969x_port_is_5g, -+ .is_port_10g = &lan969x_port_is_10g, -+ .is_port_25g = &lan969x_port_is_25g, -+ .get_port_dev_index = &lan969x_port_dev_mapping, -+ .get_port_dev_bit = &lan969x_get_dev_mode_bit, -+ .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, -+ .get_sdlb_group = &lan969x_get_sdlb_group, -+ .set_port_mux = &lan969x_port_mux_set, -+ .ptp_irq_handler = &lan969x_ptp_irq_handler, -+ .dsm_calendar_calc = &lan969x_dsm_calendar_calc, -+}; -+ -+const struct sparx5_match_data lan969x_desc = { -+ .iomap = lan969x_main_iomap, -+ .iomap_size = ARRAY_SIZE(lan969x_main_iomap), -+ .ioranges = 2, -+ .regs = &lan969x_regs, -+ .consts = &lan969x_consts, -+ .ops = &lan969x_ops, -+}; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c -@@ -98,7 +98,6 @@ u32 sparx5_cal_speed_to_value(enum sparx - default: return 0; - } - } --EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); - - static u32 sparx5_bandwidth_to_calendar(u32 bw) - { -@@ -150,7 +149,6 @@ enum sparx5_cal_bw sparx5_get_port_cal_s - return SPX5_CAL_SPEED_NONE; - return sparx5_bandwidth_to_calendar(port->conf.bandwidth); - } --EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); - - /* Auto configure the QSYS calendar based on port configuration */ - int sparx5_config_auto_calendar(struct sparx5 *sparx5) ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -24,7 +24,7 @@ - #include - #include - --#include "../lan969x/lan969x.h" /* for lan969x match data */ -+#include "lan969x/lan969x.h" /* for lan969x match data */ - - #include "sparx5_main_regs.h" - #include "sparx5_main.h" -@@ -1092,7 +1092,7 @@ static const struct sparx5_match_data sp - - static const struct of_device_id mchp_sparx5_match[] = { - { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, --#if IS_ENABLED(CONFIG_LAN969X_SWITCH) -+#ifdef CONFIG_LAN969X_SWITCH - { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, - #endif - { } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c -@@ -303,7 +303,6 @@ void sparx5_get_hwtimestamp(struct sparx - - spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); - } --EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp); - - irqreturn_t sparx5_ptp_irq_handler(int irq, void *args) - { ---- a/drivers/net/ethernet/microchip/lan969x/lan969x.h -+++ /dev/null -@@ -1,65 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* Microchip lan969x Switch driver -- * -- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -- */ -- --#ifndef __LAN969X_H__ --#define __LAN969X_H__ -- --#include "../sparx5/sparx5_main.h" --#include "../sparx5/sparx5_regs.h" --#include "../sparx5/sparx5_vcap_impl.h" -- --/* lan969x.c */ --extern const struct sparx5_match_data lan969x_desc; -- --/* lan969x_vcap_ag_api.c */ --extern const struct vcap_statistics lan969x_vcap_stats; --extern const struct vcap_info lan969x_vcaps[]; -- --/* lan969x_vcap_impl.c */ --extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; -- --/* lan969x_regs.c */ --extern const unsigned int lan969x_tsize[TSIZE_LAST]; --extern const unsigned int lan969x_raddr[RADDR_LAST]; --extern const unsigned int lan969x_rcnt[RCNT_LAST]; --extern const unsigned int lan969x_gaddr[GADDR_LAST]; --extern const unsigned int lan969x_gcnt[GCNT_LAST]; --extern const unsigned int lan969x_gsize[GSIZE_LAST]; --extern const unsigned int lan969x_fpos[FPOS_LAST]; --extern const unsigned int lan969x_fsize[FSIZE_LAST]; -- --static inline bool lan969x_port_is_2g5(int portno) --{ -- return portno == 1 || portno == 2 || portno == 3 || -- portno == 5 || portno == 6 || portno == 7 || -- portno == 10 || portno == 11 || portno == 14 || -- portno == 15 || portno == 18 || portno == 19 || -- portno == 22 || portno == 23; --} -- --static inline bool lan969x_port_is_5g(int portno) --{ -- return portno == 9 || portno == 13 || portno == 17 || -- portno == 21; --} -- --static inline bool lan969x_port_is_10g(int portno) --{ -- return portno == 0 || portno == 4 || portno == 8 || -- portno == 12 || portno == 16 || portno == 20 || -- portno == 24 || portno == 25 || portno == 26 || -- portno == 27; --} -- --static inline bool lan969x_port_is_25g(int portno) --{ -- return false; --} -- --/* lan969x_calendar.c */ --int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -- struct sparx5_calendar_data *data); --#endif ---- a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c -+++ /dev/null -@@ -1,191 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* Microchip lan969x Switch driver -- * -- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -- */ -- --#include "lan969x.h" -- --#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 --#define LAN969X_DSM_CAL_TAXIS 5 -- --enum lan969x_dsm_cal_dev { -- DSM_CAL_DEV_2G5, -- DSM_CAL_DEV_5G, -- DSM_CAL_DEV_10G, -- DSM_CAL_DEV_OTHER, /* 1G or less */ -- DSM_CAL_DEV_MAX --}; -- --/* Each entry in the following struct defines properties for a given speed -- * (10G, 5G, 2.5G, or 1G or less). -- */ --struct lan969x_dsm_cal_dev_speed { -- /* Number of devices that requires this speed. */ -- u32 n_devs; -- -- /* Array of devices that requires this speed. */ -- u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; -- -- /* Number of slots required for one device running this speed. */ -- u32 n_slots; -- -- /* Gap between two slots for one device running this speed. */ -- u32 gap; --}; -- --static u32 --lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { -- { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, -- { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, -- { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, -- { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, -- { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } --}; -- --static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) --{ -- if (*cal_idx >= cal_len) -- return -EINVAL; -- -- do { -- if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) -- return 0; -- -- (*cal_idx)++; -- } while (*cal_idx < cal_len); -- -- return -ENOENT; --} -- --static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) --{ -- return (speed == 10000 ? DSM_CAL_DEV_10G : -- speed == 5000 ? DSM_CAL_DEV_5G : -- speed == 2500 ? DSM_CAL_DEV_2G5 : -- DSM_CAL_DEV_OTHER); --} -- --static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) --{ -- return (dev == DSM_CAL_DEV_10G ? 10000 : -- dev == DSM_CAL_DEV_5G ? 5000 : -- dev == DSM_CAL_DEV_2G5 ? 2500 : -- 1000); --} -- --int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -- struct sparx5_calendar_data *data) --{ -- struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; -- u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; -- struct lan969x_dsm_cal_dev_speed *speed; -- int err; -- -- /* Maximum bandwidth for this taxi */ -- taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); -- -- memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], -- LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); -- -- for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -- u32 portno = data->taxi_ports[i]; -- enum sparx5_cal_bw bw; -- -- bw = sparx5_get_port_cal_speed(sparx5, portno); -- -- if (portno < sparx5->data->consts->n_ports_all) -- data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); -- else -- data->taxi_speeds[i] = 0; -- } -- -- /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the -- * this taxi map. -- */ -- for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -- u32 taxi_speed = data->taxi_speeds[i]; -- enum lan969x_dsm_cal_dev dev; -- -- if (taxi_speed == 0) -- continue; -- -- required_bw += taxi_speed; -- -- dev = lan969x_dsm_cal_get_dev(taxi_speed); -- speed = &dev_speeds[dev]; -- speed->devs[speed->n_devs++] = i; -- n_devs++; -- } -- -- if (required_bw > taxi_bw) { -- pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", -- required_bw, taxi_bw); -- return -EINVAL; -- } -- -- if (n_devs == 0) { -- data->schedule[0] = SPX5_DSM_CAL_EMPTY; -- return 0; -- } -- -- cal_len = n_devs; -- -- /* Search for a calendar length that fits all active devices. */ -- while (cal_len < SPX5_DSM_CAL_LEN) { -- u32 bw_per_slot = taxi_bw / cal_len; -- -- n_slots = 0; -- -- for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { -- speed = &dev_speeds[i]; -- -- if (speed->n_devs == 0) -- continue; -- -- required_bw = lan969x_dsm_cal_get_speed(i); -- speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); -- -- if (speed->n_slots) -- speed->gap = DIV_ROUND_UP(cal_len, -- speed->n_slots); -- else -- speed->gap = 0; -- -- n_slots += speed->n_slots * speed->n_devs; -- } -- -- if (n_slots <= cal_len) -- break; /* Found a suitable calendar length. */ -- -- /* Not good enough yet. */ -- cal_len = n_slots; -- } -- -- if (cal_len > SPX5_DSM_CAL_LEN) { -- pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); -- return -EINVAL; -- } -- -- for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) -- data->schedule[i] = SPX5_DSM_CAL_EMPTY; -- -- /* Place the remaining devices */ -- for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { -- speed = &dev_speeds[i]; -- for (u32 dev = 0; dev < speed->n_devs; dev++) { -- u32 idx = 0; -- -- for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { -- err = lan969x_dsm_cal_idx_get(data->schedule, -- cal_len, &idx); -- if (err) -- return err; -- data->schedule[idx] = speed->devs[dev]; -- idx += speed->gap; -- } -- } -- } -- -- return 0; --} ---- a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c -+++ /dev/null -@@ -1,222 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* Microchip lan969x Switch driver -- * -- * Copyright (c) 2024 Microchip Technology Inc. -- */ -- --/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. -- * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b -- */ -- --#include "lan969x.h" -- --const unsigned int lan969x_tsize[TSIZE_LAST] = { -- [TC_DEV10G] = 10, -- [TC_DEV2G5] = 28, -- [TC_DEV5G] = 4, -- [TC_PCS10G_BR] = 10, -- [TC_PCS5G_BR] = 4, --}; -- --const unsigned int lan969x_raddr[RADDR_LAST] = { -- [RA_CPU_PROC_CTRL] = 160, -- [RA_GCB_SOFT_RST] = 12, -- [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, --}; -- --const unsigned int lan969x_rcnt[RCNT_LAST] = { -- [RC_ANA_AC_OWN_UPSID] = 1, -- [RC_ANA_ACL_VCAP_S2_CFG] = 35, -- [RC_ANA_ACL_OWN_UPSID] = 1, -- [RC_ANA_CL_OWN_UPSID] = 1, -- [RC_ANA_L2_OWN_UPSID] = 1, -- [RC_ASM_PORT_CFG] = 32, -- [RC_DSM_BUF_CFG] = 32, -- [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, -- [RC_DSM_RX_PAUSE_CFG] = 32, -- [RC_DSM_MAC_CFG] = 32, -- [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, -- [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, -- [RC_DSM_TAXI_CAL_CFG] = 6, -- [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, -- [RC_HSCH_PORT_MODE] = 35, -- [RC_QFWD_SWITCH_PORT_MODE] = 35, -- [RC_QSYS_PAUSE_CFG] = 35, -- [RC_QSYS_ATOP] = 35, -- [RC_QSYS_FWD_PRESSURE] = 35, -- [RC_QSYS_CAL_AUTO] = 4, -- [RC_REW_OWN_UPSID] = 1, -- [RC_REW_RTAG_ETAG_CTRL] = 35, --}; -- --const unsigned int lan969x_gaddr[GADDR_LAST] = { -- [GA_ANA_AC_RAM_CTRL] = 202000, -- [GA_ANA_AC_PS_COMMON] = 202880, -- [GA_ANA_AC_MIRROR_PROBE] = 203232, -- [GA_ANA_AC_SRC] = 201728, -- [GA_ANA_AC_PGID] = 131072, -- [GA_ANA_AC_TSN_SF] = 202028, -- [GA_ANA_AC_TSN_SF_CFG] = 148480, -- [GA_ANA_AC_TSN_SF_STATUS] = 147936, -- [GA_ANA_AC_SG_ACCESS] = 202032, -- [GA_ANA_AC_SG_CONFIG] = 202752, -- [GA_ANA_AC_SG_STATUS] = 147952, -- [GA_ANA_AC_SG_STATUS_STICKY] = 202044, -- [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, -- [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, -- [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, -- [GA_ANA_ACL_COMMON] = 8192, -- [GA_ANA_ACL_KEY_SEL] = 9204, -- [GA_ANA_ACL_CNT_B] = 4096, -- [GA_ANA_ACL_STICKY] = 10852, -- [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, -- [GA_ANA_AC_POL_COMMON_BDLB] = 19464, -- [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, -- [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, -- [GA_ANA_CL_PORT] = 65536, -- [GA_ANA_CL_COMMON] = 87040, -- [GA_ANA_L2_COMMON] = 561928, -- [GA_ANA_L3_COMMON] = 370752, -- [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, -- [GA_ASM_CFG] = 18304, -- [GA_ASM_PFC_TIMER_CFG] = 15568, -- [GA_ASM_LBK_WM_CFG] = 15596, -- [GA_ASM_LBK_MISC_CFG] = 15608, -- [GA_ASM_RAM_CTRL] = 15684, -- [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, -- [GA_EACL_CNT_TBL] = 30720, -- [GA_EACL_POL_CFG] = 38400, -- [GA_EACL_ES2_STICKY] = 29072, -- [GA_EACL_RAM_CTRL] = 29112, -- [GA_GCB_SIO_CTRL] = 560, -- [GA_HSCH_HSCH_DWRR] = 36480, -- [GA_HSCH_HSCH_MISC] = 36608, -- [GA_HSCH_HSCH_LEAK_LISTS] = 37256, -- [GA_HSCH_SYSTEM] = 37384, -- [GA_HSCH_MMGT] = 36260, -- [GA_HSCH_TAS_CONFIG] = 37696, -- [GA_PTP_PTP_CFG] = 512, -- [GA_PTP_PTP_TOD_DOMAINS] = 528, -- [GA_PTP_PHASE_DETECTOR_CTRL] = 628, -- [GA_QSYS_CALCFG] = 2164, -- [GA_QSYS_RAM_CTRL] = 2204, -- [GA_REW_COMMON] = 98304, -- [GA_REW_PORT] = 49152, -- [GA_REW_VOE_PORT_LM_CNT] = 90112, -- [GA_REW_RAM_CTRL] = 93992, -- [GA_VOP_RAM_CTRL] = 16368, -- [GA_XQS_SYSTEM] = 5744, -- [GA_XQS_QLIMIT_SHR] = 6912, --}; -- --const unsigned int lan969x_gcnt[GCNT_LAST] = { -- [GC_ANA_AC_SRC] = 67, -- [GC_ANA_AC_PGID] = 1054, -- [GC_ANA_AC_TSN_SF_CFG] = 256, -- [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, -- [GC_ANA_ACL_KEY_SEL] = 99, -- [GC_ANA_ACL_CNT_A] = 1024, -- [GC_ANA_ACL_CNT_B] = 1024, -- [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, -- [GC_ANA_AC_SDLB_LBSET_TBL] = 496, -- [GC_ANA_CL_PORT] = 35, -- [GC_ANA_L2_ISDX_LIMIT] = 256, -- [GC_ANA_L2_ISDX] = 1024, -- [GC_ANA_L3_VLAN] = 4608, -- [GC_ASM_DEV_STATISTICS] = 30, -- [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, -- [GC_EACL_CNT_TBL] = 512, -- [GC_GCB_SIO_CTRL] = 1, -- [GC_HSCH_HSCH_CFG] = 1120, -- [GC_HSCH_HSCH_DWRR] = 32, -- [GC_PTP_PTP_PINS] = 8, -- [GC_PTP_PHASE_DETECTOR_CTRL] = 8, -- [GC_REW_PORT] = 35, -- [GC_REW_VOE_PORT_LM_CNT] = 240, --}; -- --const unsigned int lan969x_gsize[GSIZE_LAST] = { -- [GW_ANA_AC_SRC] = 4, -- [GW_ANA_L2_COMMON] = 712, -- [GW_ASM_CFG] = 1092, -- [GW_CPU_CPU_REGS] = 180, -- [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, -- [GW_FDMA_FDMA] = 448, -- [GW_GCB_CHIP_REGS] = 180, -- [GW_HSCH_TAS_CONFIG] = 16, -- [GW_PTP_PHASE_DETECTOR_CTRL] = 12, -- [GW_QSYS_PAUSE_CFG] = 988, --}; -- --const unsigned int lan969x_fpos[FPOS_LAST] = { -- [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, -- [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, -- [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, -- [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, -- [FP_CPU_PROC_CTRL_VINITHI] = 3, -- [FP_CPU_PROC_CTRL_CFGTE] = 2, -- [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, -- [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, -- [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, -- [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, -- [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, -- [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, -- [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, -- [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, -- [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, -- [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, -- [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, -- [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, -- [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, --}; -- --const unsigned int lan969x_fsize[FSIZE_LAST] = { -- [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, -- [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, -- [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, -- [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, -- [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, -- [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, -- [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, -- [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, -- [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, -- [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, -- [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, -- [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, -- [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, -- [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, -- [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, -- [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, -- [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, -- [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, -- [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, -- [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, -- [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, -- [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, -- [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, -- [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, -- [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, -- [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, -- [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, -- [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, -- [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, -- [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, -- [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, -- [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, -- [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, -- [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, -- [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, -- [FW_QRES_RES_CFG_WM_HIGH] = 11, -- [FW_QRES_RES_STAT_MAXUSE] = 19, -- [FW_QRES_RES_STAT_CUR_INUSE] = 19, -- [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, -- [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, -- [FW_QSYS_ATOP_ATOP] = 11, -- [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, -- [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, -- [FW_XQS_STAT_CFG_STAT_VIEW] = 10, -- [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, -- [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, -- [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, -- [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, --}; ---- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c -+++ /dev/null -@@ -1,3843 +0,0 @@ --// SPDX-License-Identifier: BSD-3-Clause --/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. -- * Microchip VCAP API -- */ -- --/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. -- * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 -- */ -- --#include --#include -- --#include "lan969x.h" -- --/* keyfields */ --static const struct vcap_field is0_normal_7tuple_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 1, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 2, -- .width = 2, -- }, -- [VCAP_KF_LOOKUP_GEN_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 4, -- .width = 10, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U72, -- .offset = 16, -- .width = 65, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 81, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 82, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGS] = { -- .type = VCAP_FIELD_U32, -- .offset = 83, -- .width = 3, -- }, -- [VCAP_KF_8021Q_TPID0] = { -- .type = VCAP_FIELD_U32, -- .offset = 86, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP0] = { -- .type = VCAP_FIELD_U32, -- .offset = 89, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID0] = { -- .type = VCAP_FIELD_U32, -- .offset = 93, -- .width = 12, -- }, -- [VCAP_KF_8021Q_TPID1] = { -- .type = VCAP_FIELD_U32, -- .offset = 105, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP1] = { -- .type = VCAP_FIELD_U32, -- .offset = 108, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI1] = { -- .type = VCAP_FIELD_BIT, -- .offset = 111, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID1] = { -- .type = VCAP_FIELD_U32, -- .offset = 112, -- .width = 12, -- }, -- [VCAP_KF_8021Q_TPID2] = { -- .type = VCAP_FIELD_U32, -- .offset = 124, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP2] = { -- .type = VCAP_FIELD_U32, -- .offset = 127, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI2] = { -- .type = VCAP_FIELD_BIT, -- .offset = 130, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID2] = { -- .type = VCAP_FIELD_U32, -- .offset = 131, -- .width = 12, -- }, -- [VCAP_KF_L2_DMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 144, -- .width = 48, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 192, -- .width = 48, -- }, -- [VCAP_KF_IP_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 240, -- .width = 1, -- }, -- [VCAP_KF_ETYPE_LEN_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 241, -- .width = 1, -- }, -- [VCAP_KF_ETYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 242, -- .width = 16, -- }, -- [VCAP_KF_IP_SNAP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 258, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 259, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 260, -- .width = 2, -- }, -- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 262, -- .width = 1, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 263, -- .width = 1, -- }, -- [VCAP_KF_L3_DSCP] = { -- .type = VCAP_FIELD_U32, -- .offset = 264, -- .width = 6, -- }, -- [VCAP_KF_L3_IP6_DIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 270, -- .width = 128, -- }, -- [VCAP_KF_L3_IP6_SIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 398, -- .width = 128, -- }, -- [VCAP_KF_TCP_UDP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 526, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 527, -- .width = 1, -- }, -- [VCAP_KF_L4_SPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 528, -- .width = 16, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 544, -- .width = 8, -- }, --}; -- --static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 2, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 2, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 3, -- .width = 2, -- }, -- [VCAP_KF_LOOKUP_GEN_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 10, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 15, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U72, -- .offset = 17, -- .width = 65, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 82, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 83, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_TPID0] = { -- .type = VCAP_FIELD_U32, -- .offset = 87, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP0] = { -- .type = VCAP_FIELD_U32, -- .offset = 90, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 93, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID0] = { -- .type = VCAP_FIELD_U32, -- .offset = 94, -- .width = 12, -- }, -- [VCAP_KF_8021Q_TPID1] = { -- .type = VCAP_FIELD_U32, -- .offset = 106, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP1] = { -- .type = VCAP_FIELD_U32, -- .offset = 109, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI1] = { -- .type = VCAP_FIELD_BIT, -- .offset = 112, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID1] = { -- .type = VCAP_FIELD_U32, -- .offset = 113, -- .width = 12, -- }, -- [VCAP_KF_8021Q_TPID2] = { -- .type = VCAP_FIELD_U32, -- .offset = 125, -- .width = 3, -- }, -- [VCAP_KF_8021Q_PCP2] = { -- .type = VCAP_FIELD_U32, -- .offset = 128, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI2] = { -- .type = VCAP_FIELD_BIT, -- .offset = 131, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID2] = { -- .type = VCAP_FIELD_U32, -- .offset = 132, -- .width = 12, -- }, -- [VCAP_KF_IP_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 145, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 146, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 147, -- .width = 2, -- }, -- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 149, -- .width = 1, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 150, -- .width = 1, -- }, -- [VCAP_KF_L3_DSCP] = { -- .type = VCAP_FIELD_U32, -- .offset = 151, -- .width = 6, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 157, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 189, -- .width = 32, -- }, -- [VCAP_KF_L3_IP_PROTO] = { -- .type = VCAP_FIELD_U32, -- .offset = 221, -- .width = 8, -- }, -- [VCAP_KF_TCP_UDP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 229, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 230, -- .width = 1, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 231, -- .width = 8, -- }, -- [VCAP_KF_IP_PAYLOAD_5TUPLE] = { -- .type = VCAP_FIELD_U32, -- .offset = 239, -- .width = 32, -- }, --}; -- --static const struct vcap_field is2_mac_etype_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 4, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 4, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 32, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 52, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 53, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 54, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 56, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 57, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 80, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_L3_DST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 88, -- .width = 1, -- }, -- [VCAP_KF_L2_DMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 89, -- .width = 48, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 137, -- .width = 48, -- }, -- [VCAP_KF_ETYPE_LEN_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 185, -- .width = 1, -- }, -- [VCAP_KF_ETYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 186, -- .width = 16, -- }, -- [VCAP_KF_L2_PAYLOAD_ETYPE] = { -- .type = VCAP_FIELD_U64, -- .offset = 202, -- .width = 64, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 266, -- .width = 16, -- }, -- [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 282, -- .width = 1, -- }, -- [VCAP_KF_OAM_Y1731_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 283, -- .width = 1, -- }, --}; -- --static const struct vcap_field is2_arp_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 4, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 4, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 32, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 52, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 53, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 54, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 56, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 57, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 80, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 85, -- .width = 48, -- }, -- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 133, -- .width = 1, -- }, -- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 134, -- .width = 1, -- }, -- [VCAP_KF_ARP_LEN_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 135, -- .width = 1, -- }, -- [VCAP_KF_ARP_TGT_MATCH_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 136, -- .width = 1, -- }, -- [VCAP_KF_ARP_SENDER_MATCH_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 137, -- .width = 1, -- }, -- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 138, -- .width = 1, -- }, -- [VCAP_KF_ARP_OPCODE] = { -- .type = VCAP_FIELD_U32, -- .offset = 139, -- .width = 2, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 141, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 173, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 205, -- .width = 1, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 206, -- .width = 16, -- }, --}; -- --static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 4, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 4, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 32, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 52, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 53, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 54, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 56, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 57, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 80, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_L3_DST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 88, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 89, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 90, -- .width = 2, -- }, -- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 93, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 94, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 95, -- .width = 8, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 103, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 135, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 167, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 168, -- .width = 1, -- }, -- [VCAP_KF_L4_DPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 169, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 185, -- .width = 16, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 201, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 217, -- .width = 1, -- }, -- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 218, -- .width = 1, -- }, -- [VCAP_KF_L4_FIN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 219, -- .width = 1, -- }, -- [VCAP_KF_L4_SYN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 220, -- .width = 1, -- }, -- [VCAP_KF_L4_RST] = { -- .type = VCAP_FIELD_BIT, -- .offset = 221, -- .width = 1, -- }, -- [VCAP_KF_L4_PSH] = { -- .type = VCAP_FIELD_BIT, -- .offset = 222, -- .width = 1, -- }, -- [VCAP_KF_L4_ACK] = { -- .type = VCAP_FIELD_BIT, -- .offset = 223, -- .width = 1, -- }, -- [VCAP_KF_L4_URG] = { -- .type = VCAP_FIELD_BIT, -- .offset = 224, -- .width = 1, -- }, -- [VCAP_KF_L4_PAYLOAD] = { -- .type = VCAP_FIELD_U64, -- .offset = 225, -- .width = 64, -- }, --}; -- --static const struct vcap_field is2_ip4_other_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 4, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 4, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 32, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 52, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 53, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 54, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 56, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 57, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 80, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_L3_DST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 88, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 89, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 90, -- .width = 2, -- }, -- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 93, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 94, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 95, -- .width = 8, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 103, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 135, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 167, -- .width = 1, -- }, -- [VCAP_KF_L3_IP_PROTO] = { -- .type = VCAP_FIELD_U32, -- .offset = 168, -- .width = 8, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 176, -- .width = 16, -- }, -- [VCAP_KF_L3_PAYLOAD] = { -- .type = VCAP_FIELD_U112, -- .offset = 192, -- .width = 96, -- }, --}; -- --static const struct vcap_field is2_ip6_std_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 4, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 4, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 5, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 32, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 52, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 53, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 54, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 56, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 57, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 80, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 89, -- .width = 1, -- }, -- [VCAP_KF_L3_IP6_SIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 90, -- .width = 128, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 218, -- .width = 1, -- }, -- [VCAP_KF_L3_IP_PROTO] = { -- .type = VCAP_FIELD_U32, -- .offset = 219, -- .width = 8, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 227, -- .width = 16, -- }, -- [VCAP_KF_L3_PAYLOAD] = { -- .type = VCAP_FIELD_U48, -- .offset = 243, -- .width = 40, -- }, --}; -- --static const struct vcap_field is2_ip_7tuple_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 2, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 2, -- .width = 1, -- }, -- [VCAP_KF_LOOKUP_PAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 3, -- .width = 8, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -- .type = VCAP_FIELD_BIT, -- .offset = 11, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 12, -- .width = 4, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 2, -- }, -- [VCAP_KF_IF_IGR_PORT_MASK] = { -- .type = VCAP_FIELD_U72, -- .offset = 18, -- .width = 65, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 83, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 85, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 98, -- .width = 13, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 111, -- .width = 1, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 112, -- .width = 3, -- }, -- [VCAP_KF_L2_FWD_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 115, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 118, -- .width = 1, -- }, -- [VCAP_KF_L3_DST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 119, -- .width = 1, -- }, -- [VCAP_KF_L2_DMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 120, -- .width = 48, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 168, -- .width = 48, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 218, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 219, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 220, -- .width = 8, -- }, -- [VCAP_KF_L3_IP6_DIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 228, -- .width = 128, -- }, -- [VCAP_KF_L3_IP6_SIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 356, -- .width = 128, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 484, -- .width = 1, -- }, -- [VCAP_KF_TCP_UDP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 485, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 486, -- .width = 1, -- }, -- [VCAP_KF_L4_DPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 487, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 503, -- .width = 16, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 519, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 535, -- .width = 1, -- }, -- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 536, -- .width = 1, -- }, -- [VCAP_KF_L4_FIN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 537, -- .width = 1, -- }, -- [VCAP_KF_L4_SYN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 538, -- .width = 1, -- }, -- [VCAP_KF_L4_RST] = { -- .type = VCAP_FIELD_BIT, -- .offset = 539, -- .width = 1, -- }, -- [VCAP_KF_L4_PSH] = { -- .type = VCAP_FIELD_BIT, -- .offset = 540, -- .width = 1, -- }, -- [VCAP_KF_L4_ACK] = { -- .type = VCAP_FIELD_BIT, -- .offset = 541, -- .width = 1, -- }, -- [VCAP_KF_L4_URG] = { -- .type = VCAP_FIELD_BIT, -- .offset = 542, -- .width = 1, -- }, -- [VCAP_KF_L4_PAYLOAD] = { -- .type = VCAP_FIELD_U64, -- .offset = 543, -- .width = 64, -- }, --}; -- --static const struct vcap_field es0_isdx_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_KF_IF_EGR_PORT_NO] = { -- .type = VCAP_FIELD_U32, -- .offset = 1, -- .width = 6, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 7, -- .width = 13, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 20, -- .width = 3, -- }, -- [VCAP_KF_8021Q_TPID] = { -- .type = VCAP_FIELD_U32, -- .offset = 23, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 27, -- .width = 1, -- }, -- [VCAP_KF_PROT_ACTIVE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 28, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 38, -- .width = 10, -- }, --}; -- --static const struct vcap_field es2_mac_etype_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 3, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 3, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 14, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 44, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 76, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 77, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 91, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_L2_DMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 96, -- .width = 48, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 144, -- .width = 48, -- }, -- [VCAP_KF_ETYPE_LEN_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 192, -- .width = 1, -- }, -- [VCAP_KF_ETYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 193, -- .width = 16, -- }, -- [VCAP_KF_L2_PAYLOAD_ETYPE] = { -- .type = VCAP_FIELD_U64, -- .offset = 209, -- .width = 64, -- }, -- [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 273, -- .width = 1, -- }, -- [VCAP_KF_OAM_Y1731_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 274, -- .width = 1, -- }, --}; -- --static const struct vcap_field es2_arp_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 3, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 3, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 14, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 44, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 76, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 77, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 91, -- .width = 1, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 95, -- .width = 48, -- }, -- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 143, -- .width = 1, -- }, -- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 144, -- .width = 1, -- }, -- [VCAP_KF_ARP_LEN_OK_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 145, -- .width = 1, -- }, -- [VCAP_KF_ARP_TGT_MATCH_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 146, -- .width = 1, -- }, -- [VCAP_KF_ARP_SENDER_MATCH_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 147, -- .width = 1, -- }, -- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 148, -- .width = 1, -- }, -- [VCAP_KF_ARP_OPCODE] = { -- .type = VCAP_FIELD_U32, -- .offset = 149, -- .width = 2, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 151, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 183, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 215, -- .width = 1, -- }, --}; -- --static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 3, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 3, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 14, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 44, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 76, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 77, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 91, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 96, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 97, -- .width = 2, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 99, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 100, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 101, -- .width = 8, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 109, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 141, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 173, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 174, -- .width = 1, -- }, -- [VCAP_KF_L4_DPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 175, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 191, -- .width = 16, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 207, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 223, -- .width = 1, -- }, -- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 224, -- .width = 1, -- }, -- [VCAP_KF_L4_FIN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 225, -- .width = 1, -- }, -- [VCAP_KF_L4_SYN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 226, -- .width = 1, -- }, -- [VCAP_KF_L4_RST] = { -- .type = VCAP_FIELD_BIT, -- .offset = 227, -- .width = 1, -- }, -- [VCAP_KF_L4_PSH] = { -- .type = VCAP_FIELD_BIT, -- .offset = 228, -- .width = 1, -- }, -- [VCAP_KF_L4_ACK] = { -- .type = VCAP_FIELD_BIT, -- .offset = 229, -- .width = 1, -- }, -- [VCAP_KF_L4_URG] = { -- .type = VCAP_FIELD_BIT, -- .offset = 230, -- .width = 1, -- }, -- [VCAP_KF_L4_PAYLOAD] = { -- .type = VCAP_FIELD_U64, -- .offset = 231, -- .width = 64, -- }, --}; -- --static const struct vcap_field es2_ip4_other_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 3, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 3, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 14, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 44, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 76, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 77, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 91, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 96, -- .width = 1, -- }, -- [VCAP_KF_L3_FRAGMENT_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 97, -- .width = 2, -- }, -- [VCAP_KF_L3_OPTIONS_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 99, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 100, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 101, -- .width = 8, -- }, -- [VCAP_KF_L3_IP4_DIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 109, -- .width = 32, -- }, -- [VCAP_KF_L3_IP4_SIP] = { -- .type = VCAP_FIELD_U32, -- .offset = 141, -- .width = 32, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 173, -- .width = 1, -- }, -- [VCAP_KF_L3_IP_PROTO] = { -- .type = VCAP_FIELD_U32, -- .offset = 174, -- .width = 8, -- }, -- [VCAP_KF_L3_PAYLOAD] = { -- .type = VCAP_FIELD_U112, -- .offset = 182, -- .width = 96, -- }, --}; -- --static const struct vcap_field es2_ip_7tuple_keyfield[] = { -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 10, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 11, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 12, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 13, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 23, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 25, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 38, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 73, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 74, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 81, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 85, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 88, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 89, -- .width = 1, -- }, -- [VCAP_KF_L2_DMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 93, -- .width = 48, -- }, -- [VCAP_KF_L2_SMAC] = { -- .type = VCAP_FIELD_U48, -- .offset = 141, -- .width = 48, -- }, -- [VCAP_KF_IP4_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 191, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 192, -- .width = 1, -- }, -- [VCAP_KF_L3_TOS] = { -- .type = VCAP_FIELD_U32, -- .offset = 193, -- .width = 8, -- }, -- [VCAP_KF_L3_IP6_DIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 201, -- .width = 128, -- }, -- [VCAP_KF_L3_IP6_SIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 329, -- .width = 128, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 457, -- .width = 1, -- }, -- [VCAP_KF_TCP_UDP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 458, -- .width = 1, -- }, -- [VCAP_KF_TCP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 459, -- .width = 1, -- }, -- [VCAP_KF_L4_DPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 460, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 476, -- .width = 16, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 492, -- .width = 16, -- }, -- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 508, -- .width = 1, -- }, -- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 509, -- .width = 1, -- }, -- [VCAP_KF_L4_FIN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 510, -- .width = 1, -- }, -- [VCAP_KF_L4_SYN] = { -- .type = VCAP_FIELD_BIT, -- .offset = 511, -- .width = 1, -- }, -- [VCAP_KF_L4_RST] = { -- .type = VCAP_FIELD_BIT, -- .offset = 512, -- .width = 1, -- }, -- [VCAP_KF_L4_PSH] = { -- .type = VCAP_FIELD_BIT, -- .offset = 513, -- .width = 1, -- }, -- [VCAP_KF_L4_ACK] = { -- .type = VCAP_FIELD_BIT, -- .offset = 514, -- .width = 1, -- }, -- [VCAP_KF_L4_URG] = { -- .type = VCAP_FIELD_BIT, -- .offset = 515, -- .width = 1, -- }, -- [VCAP_KF_L4_PAYLOAD] = { -- .type = VCAP_FIELD_U64, -- .offset = 516, -- .width = 64, -- }, --}; -- --static const struct vcap_field es2_ip6_std_keyfield[] = { -- [VCAP_KF_TYPE] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 3, -- }, -- [VCAP_KF_LOOKUP_FIRST_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 3, -- .width = 1, -- }, -- [VCAP_KF_L2_MC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 13, -- .width = 1, -- }, -- [VCAP_KF_L2_BC_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 14, -- .width = 1, -- }, -- [VCAP_KF_ISDX_GT0_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_KF_ISDX_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 10, -- }, -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_KF_8021Q_VID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 13, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 41, -- .width = 3, -- }, -- [VCAP_KF_IF_EGR_PORT_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 44, -- .width = 32, -- }, -- [VCAP_KF_IF_IGR_PORT_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 76, -- .width = 1, -- }, -- [VCAP_KF_IF_IGR_PORT] = { -- .type = VCAP_FIELD_U32, -- .offset = 77, -- .width = 7, -- }, -- [VCAP_KF_8021Q_PCP_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 84, -- .width = 3, -- }, -- [VCAP_KF_8021Q_DEI_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 87, -- .width = 1, -- }, -- [VCAP_KF_COSID_CLS] = { -- .type = VCAP_FIELD_U32, -- .offset = 88, -- .width = 3, -- }, -- [VCAP_KF_L3_DPL_CLS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 91, -- .width = 1, -- }, -- [VCAP_KF_L3_RT_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 92, -- .width = 1, -- }, -- [VCAP_KF_L3_TTL_GT0] = { -- .type = VCAP_FIELD_BIT, -- .offset = 96, -- .width = 1, -- }, -- [VCAP_KF_L3_IP6_SIP] = { -- .type = VCAP_FIELD_U128, -- .offset = 97, -- .width = 128, -- }, -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 225, -- .width = 1, -- }, -- [VCAP_KF_L3_IP_PROTO] = { -- .type = VCAP_FIELD_U32, -- .offset = 226, -- .width = 8, -- }, -- [VCAP_KF_L4_RNG] = { -- .type = VCAP_FIELD_U32, -- .offset = 234, -- .width = 16, -- }, -- [VCAP_KF_L3_PAYLOAD] = { -- .type = VCAP_FIELD_U48, -- .offset = 250, -- .width = 40, -- }, --}; -- --/* keyfield_set */ --static const struct vcap_set is0_keyfield_set[] = { -- [VCAP_KFS_NORMAL_7TUPLE] = { -- .type_id = 0, -- .sw_per_item = 12, -- .sw_cnt = 1, -- }, -- [VCAP_KFS_NORMAL_5TUPLE_IP4] = { -- .type_id = 2, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, --}; -- --static const struct vcap_set is2_keyfield_set[] = { -- [VCAP_KFS_MAC_ETYPE] = { -- .type_id = 0, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_ARP] = { -- .type_id = 3, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP4_TCP_UDP] = { -- .type_id = 4, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP4_OTHER] = { -- .type_id = 5, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP6_STD] = { -- .type_id = 6, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP_7TUPLE] = { -- .type_id = 1, -- .sw_per_item = 12, -- .sw_cnt = 1, -- }, --}; -- --static const struct vcap_set es0_keyfield_set[] = { -- [VCAP_KFS_ISDX] = { -- .type_id = 0, -- .sw_per_item = 1, -- .sw_cnt = 1, -- }, --}; -- --static const struct vcap_set es2_keyfield_set[] = { -- [VCAP_KFS_MAC_ETYPE] = { -- .type_id = 0, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_ARP] = { -- .type_id = 1, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP4_TCP_UDP] = { -- .type_id = 2, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP4_OTHER] = { -- .type_id = 3, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, -- [VCAP_KFS_IP_7TUPLE] = { -- .type_id = -1, -- .sw_per_item = 12, -- .sw_cnt = 1, -- }, -- [VCAP_KFS_IP6_STD] = { -- .type_id = 4, -- .sw_per_item = 6, -- .sw_cnt = 2, -- }, --}; -- --/* keyfield_set map */ --static const struct vcap_field *is0_keyfield_set_map[] = { -- [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, -- [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, --}; -- --static const struct vcap_field *is2_keyfield_set_map[] = { -- [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, -- [VCAP_KFS_ARP] = is2_arp_keyfield, -- [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, -- [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, -- [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, -- [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, --}; -- --static const struct vcap_field *es0_keyfield_set_map[] = { -- [VCAP_KFS_ISDX] = es0_isdx_keyfield, --}; -- --static const struct vcap_field *es2_keyfield_set_map[] = { -- [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, -- [VCAP_KFS_ARP] = es2_arp_keyfield, -- [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, -- [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, -- [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, -- [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, --}; -- --/* keyfield_set map sizes */ --static int is0_keyfield_set_map_size[] = { -- [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), -- [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), --}; -- --static int is2_keyfield_set_map_size[] = { -- [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), -- [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), -- [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), -- [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), -- [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), -- [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), --}; -- --static int es0_keyfield_set_map_size[] = { -- [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), --}; -- --static int es2_keyfield_set_map_size[] = { -- [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), -- [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), -- [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), -- [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), -- [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), -- [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), --}; -- --/* actionfields */ --static const struct vcap_field is0_classification_actionfield[] = { -- [VCAP_AF_TYPE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_AF_DSCP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 1, -- .width = 1, -- }, -- [VCAP_AF_DSCP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 2, -- .width = 6, -- }, -- [VCAP_AF_QOS_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 12, -- .width = 1, -- }, -- [VCAP_AF_QOS_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 13, -- .width = 3, -- }, -- [VCAP_AF_DP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 16, -- .width = 1, -- }, -- [VCAP_AF_DP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 17, -- .width = 2, -- }, -- [VCAP_AF_DEI_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 19, -- .width = 1, -- }, -- [VCAP_AF_DEI_VAL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 20, -- .width = 1, -- }, -- [VCAP_AF_PCP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 21, -- .width = 1, -- }, -- [VCAP_AF_PCP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 22, -- .width = 3, -- }, -- [VCAP_AF_MAP_LOOKUP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 25, -- .width = 2, -- }, -- [VCAP_AF_MAP_KEY] = { -- .type = VCAP_FIELD_U32, -- .offset = 27, -- .width = 3, -- }, -- [VCAP_AF_MAP_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 30, -- .width = 7, -- }, -- [VCAP_AF_CLS_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 37, -- .width = 3, -- }, -- [VCAP_AF_VID_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 43, -- .width = 13, -- }, -- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 66, -- .width = 1, -- }, -- [VCAP_AF_ISDX_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 67, -- .width = 10, -- }, -- [VCAP_AF_PAG_OVERRIDE_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 107, -- .width = 8, -- }, -- [VCAP_AF_PAG_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 115, -- .width = 8, -- }, -- [VCAP_AF_NXT_IDX_CTRL] = { -- .type = VCAP_FIELD_U32, -- .offset = 167, -- .width = 3, -- }, -- [VCAP_AF_NXT_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 170, -- .width = 10, -- }, --}; -- --static const struct vcap_field is0_full_actionfield[] = { -- [VCAP_AF_DSCP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_AF_DSCP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 1, -- .width = 6, -- }, -- [VCAP_AF_QOS_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 11, -- .width = 1, -- }, -- [VCAP_AF_QOS_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 12, -- .width = 3, -- }, -- [VCAP_AF_DP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_AF_DP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 16, -- .width = 2, -- }, -- [VCAP_AF_DEI_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 18, -- .width = 1, -- }, -- [VCAP_AF_DEI_VAL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 19, -- .width = 1, -- }, -- [VCAP_AF_PCP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 20, -- .width = 1, -- }, -- [VCAP_AF_PCP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 21, -- .width = 3, -- }, -- [VCAP_AF_MAP_LOOKUP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 24, -- .width = 2, -- }, -- [VCAP_AF_MAP_KEY] = { -- .type = VCAP_FIELD_U32, -- .offset = 26, -- .width = 3, -- }, -- [VCAP_AF_MAP_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 29, -- .width = 7, -- }, -- [VCAP_AF_CLS_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 36, -- .width = 3, -- }, -- [VCAP_AF_VID_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 42, -- .width = 13, -- }, -- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 65, -- .width = 1, -- }, -- [VCAP_AF_ISDX_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 66, -- .width = 10, -- }, -- [VCAP_AF_MASK_MODE] = { -- .type = VCAP_FIELD_U32, -- .offset = 76, -- .width = 3, -- }, -- [VCAP_AF_PORT_MASK] = { -- .type = VCAP_FIELD_U48, -- .offset = 79, -- .width = 37, -- }, -- [VCAP_AF_PAG_OVERRIDE_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 174, -- .width = 8, -- }, -- [VCAP_AF_PAG_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 182, -- .width = 8, -- }, -- [VCAP_AF_NXT_IDX_CTRL] = { -- .type = VCAP_FIELD_U32, -- .offset = 266, -- .width = 3, -- }, -- [VCAP_AF_NXT_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 269, -- .width = 10, -- }, --}; -- --static const struct vcap_field is0_class_reduced_actionfield[] = { -- [VCAP_AF_TYPE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_AF_QOS_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 5, -- .width = 1, -- }, -- [VCAP_AF_QOS_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 6, -- .width = 3, -- }, -- [VCAP_AF_DP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 9, -- .width = 1, -- }, -- [VCAP_AF_DP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 10, -- .width = 2, -- }, -- [VCAP_AF_MAP_LOOKUP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 12, -- .width = 2, -- }, -- [VCAP_AF_MAP_KEY] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 3, -- }, -- [VCAP_AF_CLS_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 17, -- .width = 3, -- }, -- [VCAP_AF_VID_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 23, -- .width = 13, -- }, -- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 46, -- .width = 1, -- }, -- [VCAP_AF_ISDX_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 47, -- .width = 10, -- }, -- [VCAP_AF_NXT_IDX_CTRL] = { -- .type = VCAP_FIELD_U32, -- .offset = 89, -- .width = 3, -- }, -- [VCAP_AF_NXT_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 92, -- .width = 10, -- }, --}; -- --static const struct vcap_field is2_base_type_actionfield[] = { -- [VCAP_AF_PIPELINE_FORCE_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 1, -- .width = 1, -- }, -- [VCAP_AF_PIPELINE_PT] = { -- .type = VCAP_FIELD_U32, -- .offset = 2, -- .width = 5, -- }, -- [VCAP_AF_HIT_ME_ONCE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 7, -- .width = 1, -- }, -- [VCAP_AF_INTR_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 8, -- .width = 1, -- }, -- [VCAP_AF_CPU_COPY_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 9, -- .width = 1, -- }, -- [VCAP_AF_CPU_QUEUE_NUM] = { -- .type = VCAP_FIELD_U32, -- .offset = 10, -- .width = 3, -- }, -- [VCAP_AF_LRN_DIS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 15, -- .width = 1, -- }, -- [VCAP_AF_RT_DIS] = { -- .type = VCAP_FIELD_BIT, -- .offset = 16, -- .width = 1, -- }, -- [VCAP_AF_POLICE_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 17, -- .width = 1, -- }, -- [VCAP_AF_POLICE_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 5, -- }, -- [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 23, -- .width = 1, -- }, -- [VCAP_AF_MASK_MODE] = { -- .type = VCAP_FIELD_U32, -- .offset = 27, -- .width = 3, -- }, -- [VCAP_AF_PORT_MASK] = { -- .type = VCAP_FIELD_U48, -- .offset = 30, -- .width = 37, -- }, -- [VCAP_AF_MIRROR_PROBE] = { -- .type = VCAP_FIELD_U32, -- .offset = 78, -- .width = 2, -- }, -- [VCAP_AF_MATCH_ID] = { -- .type = VCAP_FIELD_U32, -- .offset = 131, -- .width = 16, -- }, -- [VCAP_AF_MATCH_ID_MASK] = { -- .type = VCAP_FIELD_U32, -- .offset = 147, -- .width = 16, -- }, -- [VCAP_AF_CNT_ID] = { -- .type = VCAP_FIELD_U32, -- .offset = 163, -- .width = 10, -- }, --}; -- --static const struct vcap_field es0_es0_actionfield[] = { -- [VCAP_AF_PUSH_OUTER_TAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 0, -- .width = 2, -- }, -- [VCAP_AF_PUSH_INNER_TAG] = { -- .type = VCAP_FIELD_BIT, -- .offset = 2, -- .width = 1, -- }, -- [VCAP_AF_TAG_A_TPID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 3, -- .width = 3, -- }, -- [VCAP_AF_TAG_A_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 6, -- .width = 2, -- }, -- [VCAP_AF_TAG_A_PCP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 8, -- .width = 3, -- }, -- [VCAP_AF_TAG_A_DEI_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 11, -- .width = 3, -- }, -- [VCAP_AF_TAG_B_TPID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 14, -- .width = 3, -- }, -- [VCAP_AF_TAG_B_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 17, -- .width = 2, -- }, -- [VCAP_AF_TAG_B_PCP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 19, -- .width = 3, -- }, -- [VCAP_AF_TAG_B_DEI_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 22, -- .width = 3, -- }, -- [VCAP_AF_TAG_C_TPID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 25, -- .width = 3, -- }, -- [VCAP_AF_TAG_C_PCP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 28, -- .width = 3, -- }, -- [VCAP_AF_TAG_C_DEI_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 31, -- .width = 3, -- }, -- [VCAP_AF_VID_A_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 34, -- .width = 12, -- }, -- [VCAP_AF_PCP_A_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 46, -- .width = 3, -- }, -- [VCAP_AF_DEI_A_VAL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 49, -- .width = 1, -- }, -- [VCAP_AF_VID_B_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 50, -- .width = 12, -- }, -- [VCAP_AF_PCP_B_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 62, -- .width = 3, -- }, -- [VCAP_AF_DEI_B_VAL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 65, -- .width = 1, -- }, -- [VCAP_AF_VID_C_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 66, -- .width = 12, -- }, -- [VCAP_AF_PCP_C_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 78, -- .width = 3, -- }, -- [VCAP_AF_DEI_C_VAL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 81, -- .width = 1, -- }, -- [VCAP_AF_POP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 82, -- .width = 2, -- }, -- [VCAP_AF_UNTAG_VID_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 84, -- .width = 1, -- }, -- [VCAP_AF_PUSH_CUSTOMER_TAG] = { -- .type = VCAP_FIELD_U32, -- .offset = 85, -- .width = 2, -- }, -- [VCAP_AF_TAG_C_VID_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 87, -- .width = 2, -- }, -- [VCAP_AF_DSCP_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 127, -- .width = 3, -- }, -- [VCAP_AF_DSCP_VAL] = { -- .type = VCAP_FIELD_U32, -- .offset = 130, -- .width = 6, -- }, -- [VCAP_AF_ESDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 319, -- .width = 10, -- }, -- [VCAP_AF_FWD_SEL] = { -- .type = VCAP_FIELD_U32, -- .offset = 438, -- .width = 2, -- }, -- [VCAP_AF_CPU_QU] = { -- .type = VCAP_FIELD_U32, -- .offset = 440, -- .width = 3, -- }, -- [VCAP_AF_PIPELINE_PT] = { -- .type = VCAP_FIELD_U32, -- .offset = 443, -- .width = 2, -- }, -- [VCAP_AF_PIPELINE_ACT] = { -- .type = VCAP_FIELD_BIT, -- .offset = 445, -- .width = 1, -- }, -- [VCAP_AF_SWAP_MACS_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 454, -- .width = 1, -- }, -- [VCAP_AF_LOOP_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 455, -- .width = 1, -- }, --}; -- --static const struct vcap_field es2_base_type_actionfield[] = { -- [VCAP_AF_HIT_ME_ONCE] = { -- .type = VCAP_FIELD_BIT, -- .offset = 0, -- .width = 1, -- }, -- [VCAP_AF_INTR_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 1, -- .width = 1, -- }, -- [VCAP_AF_FWD_MODE] = { -- .type = VCAP_FIELD_U32, -- .offset = 2, -- .width = 2, -- }, -- [VCAP_AF_COPY_QUEUE_NUM] = { -- .type = VCAP_FIELD_U32, -- .offset = 4, -- .width = 14, -- }, -- [VCAP_AF_COPY_PORT_NUM] = { -- .type = VCAP_FIELD_U32, -- .offset = 18, -- .width = 6, -- }, -- [VCAP_AF_MIRROR_PROBE_ID] = { -- .type = VCAP_FIELD_U32, -- .offset = 24, -- .width = 2, -- }, -- [VCAP_AF_CPU_COPY_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 26, -- .width = 1, -- }, -- [VCAP_AF_CPU_QUEUE_NUM] = { -- .type = VCAP_FIELD_U32, -- .offset = 27, -- .width = 3, -- }, -- [VCAP_AF_POLICE_ENA] = { -- .type = VCAP_FIELD_BIT, -- .offset = 30, -- .width = 1, -- }, -- [VCAP_AF_POLICE_REMARK] = { -- .type = VCAP_FIELD_BIT, -- .offset = 31, -- .width = 1, -- }, -- [VCAP_AF_POLICE_IDX] = { -- .type = VCAP_FIELD_U32, -- .offset = 32, -- .width = 5, -- }, -- [VCAP_AF_ES2_REW_CMD] = { -- .type = VCAP_FIELD_U32, -- .offset = 37, -- .width = 3, -- }, -- [VCAP_AF_CNT_ID] = { -- .type = VCAP_FIELD_U32, -- .offset = 40, -- .width = 9, -- }, -- [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -- .type = VCAP_FIELD_BIT, -- .offset = 49, -- .width = 1, -- }, --}; -- --/* actionfield_set */ --static const struct vcap_set is0_actionfield_set[] = { -- [VCAP_AFS_CLASSIFICATION] = { -- .type_id = 1, -- .sw_per_item = 2, -- .sw_cnt = 6, -- }, -- [VCAP_AFS_FULL] = { -- .type_id = -1, -- .sw_per_item = 3, -- .sw_cnt = 4, -- }, -- [VCAP_AFS_CLASS_REDUCED] = { -- .type_id = 1, -- .sw_per_item = 1, -- .sw_cnt = 12, -- }, --}; -- --static const struct vcap_set is2_actionfield_set[] = { -- [VCAP_AFS_BASE_TYPE] = { -- .type_id = -1, -- .sw_per_item = 3, -- .sw_cnt = 4, -- }, --}; -- --static const struct vcap_set es0_actionfield_set[] = { -- [VCAP_AFS_ES0] = { -- .type_id = -1, -- .sw_per_item = 1, -- .sw_cnt = 1, -- }, --}; -- --static const struct vcap_set es2_actionfield_set[] = { -- [VCAP_AFS_BASE_TYPE] = { -- .type_id = -1, -- .sw_per_item = 3, -- .sw_cnt = 4, -- }, --}; -- --/* actionfield_set map */ --static const struct vcap_field *is0_actionfield_set_map[] = { -- [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, -- [VCAP_AFS_FULL] = is0_full_actionfield, -- [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, --}; -- --static const struct vcap_field *is2_actionfield_set_map[] = { -- [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, --}; -- --static const struct vcap_field *es0_actionfield_set_map[] = { -- [VCAP_AFS_ES0] = es0_es0_actionfield, --}; -- --static const struct vcap_field *es2_actionfield_set_map[] = { -- [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, --}; -- --/* actionfield_set map size */ --static int is0_actionfield_set_map_size[] = { -- [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), -- [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), -- [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), --}; -- --static int is2_actionfield_set_map_size[] = { -- [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), --}; -- --static int es0_actionfield_set_map_size[] = { -- [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), --}; -- --static int es2_actionfield_set_map_size[] = { -- [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), --}; -- --/* Type Groups */ --static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 5, -- .value = 16, -- }, -- { -- .offset = 52, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 104, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 156, -- .width = 3, -- .value = 0, -- }, -- { -- .offset = 208, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 260, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 312, -- .width = 4, -- .value = 0, -- }, -- { -- .offset = 364, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 416, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 468, -- .width = 3, -- .value = 0, -- }, -- { -- .offset = 520, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 572, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 4, -- .value = 8, -- }, -- { -- .offset = 52, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 104, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 156, -- .width = 3, -- .value = 0, -- }, -- { -- .offset = 208, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 260, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 3, -- .value = 4, -- }, -- { -- .offset = 156, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 312, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 468, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 2, -- .value = 2, -- }, -- { -- .offset = 156, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 3, -- .value = 4, -- }, -- { -- .offset = 156, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 312, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 468, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 2, -- .value = 2, -- }, -- { -- .offset = 156, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { -- [12] = is0_x12_keyfield_set_typegroups, -- [6] = is0_x6_keyfield_set_typegroups, -- [3] = is0_x3_keyfield_set_typegroups, -- [2] = is0_x2_keyfield_set_typegroups, -- [1] = is0_x1_keyfield_set_typegroups, -- [13] = NULL, --}; -- --static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { -- [12] = is2_x12_keyfield_set_typegroups, -- [6] = is2_x6_keyfield_set_typegroups, -- [3] = is2_x3_keyfield_set_typegroups, -- [1] = is2_x1_keyfield_set_typegroups, -- [13] = NULL, --}; -- --static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { -- [1] = es0_x1_keyfield_set_typegroups, -- [2] = NULL, --}; -- --static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { -- [12] = es2_x12_keyfield_set_typegroups, -- [6] = es2_x6_keyfield_set_typegroups, -- [3] = es2_x3_keyfield_set_typegroups, -- [1] = es2_x1_keyfield_set_typegroups, -- [13] = NULL, --}; -- --static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 3, -- .value = 4, -- }, -- { -- .offset = 103, -- .width = 2, -- .value = 0, -- }, -- { -- .offset = 206, -- .width = 2, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 2, -- .value = 2, -- }, -- { -- .offset = 103, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 1, -- .value = 1, -- }, -- {} --}; -- --static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 2, -- .value = 2, -- }, -- { -- .offset = 95, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 190, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { -- { -- .offset = 0, -- .width = 2, -- .value = 2, -- }, -- { -- .offset = 19, -- .width = 1, -- .value = 0, -- }, -- { -- .offset = 38, -- .width = 1, -- .value = 0, -- }, -- {} --}; -- --static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { -- {} --}; -- --static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { -- [3] = is0_x3_actionfield_set_typegroups, -- [2] = is0_x2_actionfield_set_typegroups, -- [1] = is0_x1_actionfield_set_typegroups, -- [13] = NULL, --}; -- --static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { -- [3] = is2_x3_actionfield_set_typegroups, -- [1] = is2_x1_actionfield_set_typegroups, -- [13] = NULL, --}; -- --static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { -- [1] = es0_x1_actionfield_set_typegroups, -- [2] = NULL, --}; -- --static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { -- [3] = es2_x3_actionfield_set_typegroups, -- [1] = es2_x1_actionfield_set_typegroups, -- [13] = NULL, --}; -- --/* Keyfieldset names */ --static const char * const vcap_keyfield_set_names[] = { -- [VCAP_KFS_NO_VALUE] = "(None)", -- [VCAP_KFS_ARP] = "VCAP_KFS_ARP", -- [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", -- [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", -- [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", -- [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", -- [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", -- [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", -- [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", -- [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", -- [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", -- [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", -- [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", -- [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", -- [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", -- [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", -- [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", -- [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", -- [VCAP_KFS_OAM] = "VCAP_KFS_OAM", -- [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", -- [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", -- [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", --}; -- --/* Actionfieldset names */ --static const char * const vcap_actionfield_set_names[] = { -- [VCAP_AFS_NO_VALUE] = "(None)", -- [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", -- [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", -- [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", -- [VCAP_AFS_ES0] = "VCAP_AFS_ES0", -- [VCAP_AFS_FULL] = "VCAP_AFS_FULL", -- [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", --}; -- --/* Keyfield names */ --static const char * const vcap_keyfield_names[] = { -- [VCAP_KF_NO_VALUE] = "(None)", -- [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", -- [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", -- [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", -- [VCAP_KF_8021BR_GRP] = "8021BR_GRP", -- [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", -- [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", -- [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", -- [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", -- [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", -- [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", -- [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", -- [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", -- [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", -- [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", -- [VCAP_KF_8021Q_TPID] = "8021Q_TPID", -- [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", -- [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", -- [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", -- [VCAP_KF_8021Q_VID0] = "8021Q_VID0", -- [VCAP_KF_8021Q_VID1] = "8021Q_VID1", -- [VCAP_KF_8021Q_VID2] = "8021Q_VID2", -- [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", -- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", -- [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", -- [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", -- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", -- [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", -- [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", -- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", -- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", -- [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", -- [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", -- [VCAP_KF_COSID_CLS] = "COSID_CLS", -- [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", -- [VCAP_KF_ETYPE] = "ETYPE", -- [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", -- [VCAP_KF_HOST_MATCH] = "HOST_MATCH", -- [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", -- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", -- [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", -- [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", -- [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", -- [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", -- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", -- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", -- [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", -- [VCAP_KF_IP4_IS] = "IP4_IS", -- [VCAP_KF_IP_MC_IS] = "IP_MC_IS", -- [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", -- [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", -- [VCAP_KF_ISDX_CLS] = "ISDX_CLS", -- [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", -- [VCAP_KF_L2_BC_IS] = "L2_BC_IS", -- [VCAP_KF_L2_DMAC] = "L2_DMAC", -- [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", -- [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", -- [VCAP_KF_L2_LLC] = "L2_LLC", -- [VCAP_KF_L2_MC_IS] = "L2_MC_IS", -- [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", -- [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", -- [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", -- [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", -- [VCAP_KF_L2_SMAC] = "L2_SMAC", -- [VCAP_KF_L2_SNAP] = "L2_SNAP", -- [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", -- [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", -- [VCAP_KF_L3_DSCP] = "L3_DSCP", -- [VCAP_KF_L3_DST_IS] = "L3_DST_IS", -- [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", -- [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", -- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", -- [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", -- [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", -- [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", -- [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", -- [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", -- [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", -- [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", -- [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", -- [VCAP_KF_L3_RT_IS] = "L3_RT_IS", -- [VCAP_KF_L3_TOS] = "L3_TOS", -- [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", -- [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", -- [VCAP_KF_L4_1588_VER] = "L4_1588_VER", -- [VCAP_KF_L4_ACK] = "L4_ACK", -- [VCAP_KF_L4_DPORT] = "L4_DPORT", -- [VCAP_KF_L4_FIN] = "L4_FIN", -- [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", -- [VCAP_KF_L4_PSH] = "L4_PSH", -- [VCAP_KF_L4_RNG] = "L4_RNG", -- [VCAP_KF_L4_RST] = "L4_RST", -- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", -- [VCAP_KF_L4_SPORT] = "L4_SPORT", -- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", -- [VCAP_KF_L4_SYN] = "L4_SYN", -- [VCAP_KF_L4_URG] = "L4_URG", -- [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", -- [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", -- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", -- [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", -- [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", -- [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", -- [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", -- [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", -- [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", -- [VCAP_KF_OAM_MEPID] = "OAM_MEPID", -- [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", -- [VCAP_KF_OAM_VER] = "OAM_VER", -- [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", -- [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", -- [VCAP_KF_TCP_IS] = "TCP_IS", -- [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", -- [VCAP_KF_TYPE] = "TYPE", --}; -- --/* Actionfield names */ --static const char * const vcap_actionfield_names[] = { -- [VCAP_AF_NO_VALUE] = "(None)", -- [VCAP_AF_ACL_ID] = "ACL_ID", -- [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", -- [VCAP_AF_CNT_ID] = "CNT_ID", -- [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", -- [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", -- [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", -- [VCAP_AF_CPU_QU] = "CPU_QU", -- [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", -- [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", -- [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", -- [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", -- [VCAP_AF_DEI_ENA] = "DEI_ENA", -- [VCAP_AF_DEI_VAL] = "DEI_VAL", -- [VCAP_AF_DP_ENA] = "DP_ENA", -- [VCAP_AF_DP_VAL] = "DP_VAL", -- [VCAP_AF_DSCP_ENA] = "DSCP_ENA", -- [VCAP_AF_DSCP_SEL] = "DSCP_SEL", -- [VCAP_AF_DSCP_VAL] = "DSCP_VAL", -- [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", -- [VCAP_AF_ESDX] = "ESDX", -- [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", -- [VCAP_AF_FWD_MODE] = "FWD_MODE", -- [VCAP_AF_FWD_SEL] = "FWD_SEL", -- [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", -- [VCAP_AF_HOST_MATCH] = "HOST_MATCH", -- [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", -- [VCAP_AF_INTR_ENA] = "INTR_ENA", -- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", -- [VCAP_AF_ISDX_ENA] = "ISDX_ENA", -- [VCAP_AF_ISDX_VAL] = "ISDX_VAL", -- [VCAP_AF_LOOP_ENA] = "LOOP_ENA", -- [VCAP_AF_LRN_DIS] = "LRN_DIS", -- [VCAP_AF_MAP_IDX] = "MAP_IDX", -- [VCAP_AF_MAP_KEY] = "MAP_KEY", -- [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", -- [VCAP_AF_MASK_MODE] = "MASK_MODE", -- [VCAP_AF_MATCH_ID] = "MATCH_ID", -- [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", -- [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", -- [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", -- [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", -- [VCAP_AF_NXT_IDX] = "NXT_IDX", -- [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", -- [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", -- [VCAP_AF_PAG_VAL] = "PAG_VAL", -- [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", -- [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", -- [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", -- [VCAP_AF_PCP_ENA] = "PCP_ENA", -- [VCAP_AF_PCP_VAL] = "PCP_VAL", -- [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", -- [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", -- [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", -- [VCAP_AF_POLICE_ENA] = "POLICE_ENA", -- [VCAP_AF_POLICE_IDX] = "POLICE_IDX", -- [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", -- [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", -- [VCAP_AF_POP_VAL] = "POP_VAL", -- [VCAP_AF_PORT_MASK] = "PORT_MASK", -- [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", -- [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", -- [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", -- [VCAP_AF_QOS_ENA] = "QOS_ENA", -- [VCAP_AF_QOS_VAL] = "QOS_VAL", -- [VCAP_AF_REW_OP] = "REW_OP", -- [VCAP_AF_RT_DIS] = "RT_DIS", -- [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", -- [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", -- [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", -- [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", -- [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", -- [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", -- [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", -- [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", -- [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", -- [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", -- [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", -- [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", -- [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", -- [VCAP_AF_TYPE] = "TYPE", -- [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", -- [VCAP_AF_VID_A_VAL] = "VID_A_VAL", -- [VCAP_AF_VID_B_VAL] = "VID_B_VAL", -- [VCAP_AF_VID_C_VAL] = "VID_C_VAL", -- [VCAP_AF_VID_VAL] = "VID_VAL", --}; -- --/* VCAPs */ --const struct vcap_info lan969x_vcaps[] = { -- [VCAP_TYPE_IS0] = { -- .name = "is0", -- .rows = 256, -- .sw_count = 12, -- .sw_width = 52, -- .sticky_width = 1, -- .act_width = 103, -- .default_cnt = 70, -- .require_cnt_dis = 0, -- .version = 1, -- .keyfield_set = is0_keyfield_set, -- .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), -- .actionfield_set = is0_actionfield_set, -- .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), -- .keyfield_set_map = is0_keyfield_set_map, -- .keyfield_set_map_size = is0_keyfield_set_map_size, -- .actionfield_set_map = is0_actionfield_set_map, -- .actionfield_set_map_size = is0_actionfield_set_map_size, -- .keyfield_set_typegroups = is0_keyfield_set_typegroups, -- .actionfield_set_typegroups = is0_actionfield_set_typegroups, -- }, -- [VCAP_TYPE_IS2] = { -- .name = "is2", -- .rows = 256, -- .sw_count = 12, -- .sw_width = 52, -- .sticky_width = 1, -- .act_width = 103, -- .default_cnt = 38, -- .require_cnt_dis = 0, -- .version = 1, -- .keyfield_set = is2_keyfield_set, -- .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), -- .actionfield_set = is2_actionfield_set, -- .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), -- .keyfield_set_map = is2_keyfield_set_map, -- .keyfield_set_map_size = is2_keyfield_set_map_size, -- .actionfield_set_map = is2_actionfield_set_map, -- .actionfield_set_map_size = is2_actionfield_set_map_size, -- .keyfield_set_typegroups = is2_keyfield_set_typegroups, -- .actionfield_set_typegroups = is2_actionfield_set_typegroups, -- }, -- [VCAP_TYPE_ES0] = { -- .name = "es0", -- .rows = 1536, -- .sw_count = 1, -- .sw_width = 51, -- .sticky_width = 1, -- .act_width = 469, -- .default_cnt = 35, -- .require_cnt_dis = 0, -- .version = 1, -- .keyfield_set = es0_keyfield_set, -- .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), -- .actionfield_set = es0_actionfield_set, -- .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), -- .keyfield_set_map = es0_keyfield_set_map, -- .keyfield_set_map_size = es0_keyfield_set_map_size, -- .actionfield_set_map = es0_actionfield_set_map, -- .actionfield_set_map_size = es0_actionfield_set_map_size, -- .keyfield_set_typegroups = es0_keyfield_set_typegroups, -- .actionfield_set_typegroups = es0_actionfield_set_typegroups, -- }, -- [VCAP_TYPE_ES2] = { -- .name = "es2", -- .rows = 256, -- .sw_count = 12, -- .sw_width = 52, -- .sticky_width = 1, -- .act_width = 19, -- .default_cnt = 39, -- .require_cnt_dis = 0, -- .version = 1, -- .keyfield_set = es2_keyfield_set, -- .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), -- .actionfield_set = es2_actionfield_set, -- .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), -- .keyfield_set_map = es2_keyfield_set_map, -- .keyfield_set_map_size = es2_keyfield_set_map_size, -- .actionfield_set_map = es2_actionfield_set_map, -- .actionfield_set_map_size = es2_actionfield_set_map_size, -- .keyfield_set_typegroups = es2_keyfield_set_typegroups, -- .actionfield_set_typegroups = es2_actionfield_set_typegroups, -- }, --}; -- --const struct vcap_statistics lan969x_vcap_stats = { -- .name = "lan969x", -- .count = 4, -- .keyfield_set_names = vcap_keyfield_set_names, -- .actionfield_set_names = vcap_actionfield_set_names, -- .keyfield_names = vcap_keyfield_names, -- .actionfield_names = vcap_actionfield_names, --}; ---- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c -+++ /dev/null -@@ -1,85 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ -- --#include "vcap_api.h" --#include "lan969x.h" -- --const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { -- { -- .vtype = VCAP_TYPE_IS0, /* CLM-0 */ -- .vinst = 0, -- .map_id = 1, -- .lookups = SPARX5_IS0_LOOKUPS, -- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -- .first_cid = SPARX5_VCAP_CID_IS0_L0, -- .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, -- .blockno = 2, -- .blocks = 1, -- .ingress = true, -- }, -- { -- .vtype = VCAP_TYPE_IS0, /* CLM-1 */ -- .vinst = 1, -- .map_id = 2, -- .lookups = SPARX5_IS0_LOOKUPS, -- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -- .first_cid = SPARX5_VCAP_CID_IS0_L2, -- .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, -- .blockno = 3, -- .blocks = 1, -- .ingress = true, -- }, -- { -- .vtype = VCAP_TYPE_IS0, /* CLM-2 */ -- .vinst = 2, -- .map_id = 3, -- .lookups = SPARX5_IS0_LOOKUPS, -- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -- .first_cid = SPARX5_VCAP_CID_IS0_L4, -- .last_cid = SPARX5_VCAP_CID_IS0_MAX, -- .blockno = 4, -- .blocks = 1, -- .ingress = true, -- }, -- { -- .vtype = VCAP_TYPE_IS2, /* IS2-0 */ -- .vinst = 0, -- .map_id = 4, -- .lookups = SPARX5_IS2_LOOKUPS, -- .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -- .first_cid = SPARX5_VCAP_CID_IS2_L0, -- .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, -- .blockno = 0, -- .blocks = 1, -- .ingress = true, -- }, -- { -- .vtype = VCAP_TYPE_IS2, /* IS2-1 */ -- .vinst = 1, -- .map_id = 5, -- .lookups = SPARX5_IS2_LOOKUPS, -- .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -- .first_cid = SPARX5_VCAP_CID_IS2_L2, -- .last_cid = SPARX5_VCAP_CID_IS2_MAX, -- .blockno = 1, -- .blocks = 1, -- .ingress = true, -- }, -- { -- .vtype = VCAP_TYPE_ES0, -- .lookups = SPARX5_ES0_LOOKUPS, -- .lookups_per_instance = SPARX5_ES0_LOOKUPS, -- .first_cid = SPARX5_VCAP_CID_ES0_L0, -- .last_cid = SPARX5_VCAP_CID_ES0_MAX, -- .count = 1536, -- .ingress = false, -- }, -- { -- .vtype = VCAP_TYPE_ES2, -- .lookups = SPARX5_ES2_LOOKUPS, -- .lookups_per_instance = SPARX5_ES2_LOOKUPS, -- .first_cid = SPARX5_VCAP_CID_ES2_L0, -- .last_cid = SPARX5_VCAP_CID_ES2_MAX, -- .count = 1024, -- .ingress = false, -- }, --}; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -@@ -0,0 +1,65 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#ifndef __LAN969X_H__ -+#define __LAN969X_H__ -+ -+#include "../sparx5/sparx5_main.h" -+#include "../sparx5/sparx5_regs.h" -+#include "../sparx5/sparx5_vcap_impl.h" -+ -+/* lan969x.c */ -+extern const struct sparx5_match_data lan969x_desc; -+ -+/* lan969x_vcap_ag_api.c */ -+extern const struct vcap_statistics lan969x_vcap_stats; -+extern const struct vcap_info lan969x_vcaps[]; -+ -+/* lan969x_vcap_impl.c */ -+extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; -+ -+/* lan969x_regs.c */ -+extern const unsigned int lan969x_tsize[TSIZE_LAST]; -+extern const unsigned int lan969x_raddr[RADDR_LAST]; -+extern const unsigned int lan969x_rcnt[RCNT_LAST]; -+extern const unsigned int lan969x_gaddr[GADDR_LAST]; -+extern const unsigned int lan969x_gcnt[GCNT_LAST]; -+extern const unsigned int lan969x_gsize[GSIZE_LAST]; -+extern const unsigned int lan969x_fpos[FPOS_LAST]; -+extern const unsigned int lan969x_fsize[FSIZE_LAST]; -+ -+static inline bool lan969x_port_is_2g5(int portno) -+{ -+ return portno == 1 || portno == 2 || portno == 3 || -+ portno == 5 || portno == 6 || portno == 7 || -+ portno == 10 || portno == 11 || portno == 14 || -+ portno == 15 || portno == 18 || portno == 19 || -+ portno == 22 || portno == 23; -+} -+ -+static inline bool lan969x_port_is_5g(int portno) -+{ -+ return portno == 9 || portno == 13 || portno == 17 || -+ portno == 21; -+} -+ -+static inline bool lan969x_port_is_10g(int portno) -+{ -+ return portno == 0 || portno == 4 || portno == 8 || -+ portno == 12 || portno == 16 || portno == 20 || -+ portno == 24 || portno == 25 || portno == 26 || -+ portno == 27; -+} -+ -+static inline bool lan969x_port_is_25g(int portno) -+{ -+ return false; -+} -+ -+/* lan969x_calendar.c */ -+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data); -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_calendar.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "lan969x.h" -+ -+#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 -+#define LAN969X_DSM_CAL_TAXIS 5 -+ -+enum lan969x_dsm_cal_dev { -+ DSM_CAL_DEV_2G5, -+ DSM_CAL_DEV_5G, -+ DSM_CAL_DEV_10G, -+ DSM_CAL_DEV_OTHER, /* 1G or less */ -+ DSM_CAL_DEV_MAX -+}; -+ -+/* Each entry in the following struct defines properties for a given speed -+ * (10G, 5G, 2.5G, or 1G or less). -+ */ -+struct lan969x_dsm_cal_dev_speed { -+ /* Number of devices that requires this speed. */ -+ u32 n_devs; -+ -+ /* Array of devices that requires this speed. */ -+ u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; -+ -+ /* Number of slots required for one device running this speed. */ -+ u32 n_slots; -+ -+ /* Gap between two slots for one device running this speed. */ -+ u32 gap; -+}; -+ -+static u32 -+lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { -+ { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, -+ { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, -+ { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, -+ { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, -+ { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } -+}; -+ -+static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) -+{ -+ if (*cal_idx >= cal_len) -+ return -EINVAL; -+ -+ do { -+ if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) -+ return 0; -+ -+ (*cal_idx)++; -+ } while (*cal_idx < cal_len); -+ -+ return -ENOENT; -+} -+ -+static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) -+{ -+ return (speed == 10000 ? DSM_CAL_DEV_10G : -+ speed == 5000 ? DSM_CAL_DEV_5G : -+ speed == 2500 ? DSM_CAL_DEV_2G5 : -+ DSM_CAL_DEV_OTHER); -+} -+ -+static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) -+{ -+ return (dev == DSM_CAL_DEV_10G ? 10000 : -+ dev == DSM_CAL_DEV_5G ? 5000 : -+ dev == DSM_CAL_DEV_2G5 ? 2500 : -+ 1000); -+} -+ -+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, -+ struct sparx5_calendar_data *data) -+{ -+ struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; -+ u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; -+ struct lan969x_dsm_cal_dev_speed *speed; -+ int err; -+ -+ /* Maximum bandwidth for this taxi */ -+ taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); -+ -+ memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], -+ LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); -+ -+ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -+ u32 portno = data->taxi_ports[i]; -+ enum sparx5_cal_bw bw; -+ -+ bw = sparx5_get_port_cal_speed(sparx5, portno); -+ -+ if (portno < sparx5->data->consts->n_ports_all) -+ data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); -+ else -+ data->taxi_speeds[i] = 0; -+ } -+ -+ /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the -+ * this taxi map. -+ */ -+ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { -+ u32 taxi_speed = data->taxi_speeds[i]; -+ enum lan969x_dsm_cal_dev dev; -+ -+ if (taxi_speed == 0) -+ continue; -+ -+ required_bw += taxi_speed; -+ -+ dev = lan969x_dsm_cal_get_dev(taxi_speed); -+ speed = &dev_speeds[dev]; -+ speed->devs[speed->n_devs++] = i; -+ n_devs++; -+ } -+ -+ if (required_bw > taxi_bw) { -+ pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", -+ required_bw, taxi_bw); -+ return -EINVAL; -+ } -+ -+ if (n_devs == 0) { -+ data->schedule[0] = SPX5_DSM_CAL_EMPTY; -+ return 0; -+ } -+ -+ cal_len = n_devs; -+ -+ /* Search for a calendar length that fits all active devices. */ -+ while (cal_len < SPX5_DSM_CAL_LEN) { -+ u32 bw_per_slot = taxi_bw / cal_len; -+ -+ n_slots = 0; -+ -+ for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { -+ speed = &dev_speeds[i]; -+ -+ if (speed->n_devs == 0) -+ continue; -+ -+ required_bw = lan969x_dsm_cal_get_speed(i); -+ speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); -+ -+ if (speed->n_slots) -+ speed->gap = DIV_ROUND_UP(cal_len, -+ speed->n_slots); -+ else -+ speed->gap = 0; -+ -+ n_slots += speed->n_slots * speed->n_devs; -+ } -+ -+ if (n_slots <= cal_len) -+ break; /* Found a suitable calendar length. */ -+ -+ /* Not good enough yet. */ -+ cal_len = n_slots; -+ } -+ -+ if (cal_len > SPX5_DSM_CAL_LEN) { -+ pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); -+ return -EINVAL; -+ } -+ -+ for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) -+ data->schedule[i] = SPX5_DSM_CAL_EMPTY; -+ -+ /* Place the remaining devices */ -+ for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { -+ speed = &dev_speeds[i]; -+ for (u32 dev = 0; dev < speed->n_devs; dev++) { -+ u32 idx = 0; -+ -+ for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { -+ err = lan969x_dsm_cal_idx_get(data->schedule, -+ cal_len, &idx); -+ if (err) -+ return err; -+ data->schedule[idx] = speed->devs[dev]; -+ idx += speed->gap; -+ } -+ } -+ } -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c -@@ -0,0 +1,222 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. -+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b -+ */ -+ -+#include "lan969x.h" -+ -+const unsigned int lan969x_tsize[TSIZE_LAST] = { -+ [TC_DEV10G] = 10, -+ [TC_DEV2G5] = 28, -+ [TC_DEV5G] = 4, -+ [TC_PCS10G_BR] = 10, -+ [TC_PCS5G_BR] = 4, -+}; -+ -+const unsigned int lan969x_raddr[RADDR_LAST] = { -+ [RA_CPU_PROC_CTRL] = 160, -+ [RA_GCB_SOFT_RST] = 12, -+ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, -+}; -+ -+const unsigned int lan969x_rcnt[RCNT_LAST] = { -+ [RC_ANA_AC_OWN_UPSID] = 1, -+ [RC_ANA_ACL_VCAP_S2_CFG] = 35, -+ [RC_ANA_ACL_OWN_UPSID] = 1, -+ [RC_ANA_CL_OWN_UPSID] = 1, -+ [RC_ANA_L2_OWN_UPSID] = 1, -+ [RC_ASM_PORT_CFG] = 32, -+ [RC_DSM_BUF_CFG] = 32, -+ [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, -+ [RC_DSM_RX_PAUSE_CFG] = 32, -+ [RC_DSM_MAC_CFG] = 32, -+ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, -+ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, -+ [RC_DSM_TAXI_CAL_CFG] = 6, -+ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, -+ [RC_HSCH_PORT_MODE] = 35, -+ [RC_QFWD_SWITCH_PORT_MODE] = 35, -+ [RC_QSYS_PAUSE_CFG] = 35, -+ [RC_QSYS_ATOP] = 35, -+ [RC_QSYS_FWD_PRESSURE] = 35, -+ [RC_QSYS_CAL_AUTO] = 4, -+ [RC_REW_OWN_UPSID] = 1, -+ [RC_REW_RTAG_ETAG_CTRL] = 35, -+}; -+ -+const unsigned int lan969x_gaddr[GADDR_LAST] = { -+ [GA_ANA_AC_RAM_CTRL] = 202000, -+ [GA_ANA_AC_PS_COMMON] = 202880, -+ [GA_ANA_AC_MIRROR_PROBE] = 203232, -+ [GA_ANA_AC_SRC] = 201728, -+ [GA_ANA_AC_PGID] = 131072, -+ [GA_ANA_AC_TSN_SF] = 202028, -+ [GA_ANA_AC_TSN_SF_CFG] = 148480, -+ [GA_ANA_AC_TSN_SF_STATUS] = 147936, -+ [GA_ANA_AC_SG_ACCESS] = 202032, -+ [GA_ANA_AC_SG_CONFIG] = 202752, -+ [GA_ANA_AC_SG_STATUS] = 147952, -+ [GA_ANA_AC_SG_STATUS_STICKY] = 202044, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, -+ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, -+ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, -+ [GA_ANA_ACL_COMMON] = 8192, -+ [GA_ANA_ACL_KEY_SEL] = 9204, -+ [GA_ANA_ACL_CNT_B] = 4096, -+ [GA_ANA_ACL_STICKY] = 10852, -+ [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, -+ [GA_ANA_AC_POL_COMMON_BDLB] = 19464, -+ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, -+ [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, -+ [GA_ANA_CL_PORT] = 65536, -+ [GA_ANA_CL_COMMON] = 87040, -+ [GA_ANA_L2_COMMON] = 561928, -+ [GA_ANA_L3_COMMON] = 370752, -+ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, -+ [GA_ASM_CFG] = 18304, -+ [GA_ASM_PFC_TIMER_CFG] = 15568, -+ [GA_ASM_LBK_WM_CFG] = 15596, -+ [GA_ASM_LBK_MISC_CFG] = 15608, -+ [GA_ASM_RAM_CTRL] = 15684, -+ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, -+ [GA_EACL_CNT_TBL] = 30720, -+ [GA_EACL_POL_CFG] = 38400, -+ [GA_EACL_ES2_STICKY] = 29072, -+ [GA_EACL_RAM_CTRL] = 29112, -+ [GA_GCB_SIO_CTRL] = 560, -+ [GA_HSCH_HSCH_DWRR] = 36480, -+ [GA_HSCH_HSCH_MISC] = 36608, -+ [GA_HSCH_HSCH_LEAK_LISTS] = 37256, -+ [GA_HSCH_SYSTEM] = 37384, -+ [GA_HSCH_MMGT] = 36260, -+ [GA_HSCH_TAS_CONFIG] = 37696, -+ [GA_PTP_PTP_CFG] = 512, -+ [GA_PTP_PTP_TOD_DOMAINS] = 528, -+ [GA_PTP_PHASE_DETECTOR_CTRL] = 628, -+ [GA_QSYS_CALCFG] = 2164, -+ [GA_QSYS_RAM_CTRL] = 2204, -+ [GA_REW_COMMON] = 98304, -+ [GA_REW_PORT] = 49152, -+ [GA_REW_VOE_PORT_LM_CNT] = 90112, -+ [GA_REW_RAM_CTRL] = 93992, -+ [GA_VOP_RAM_CTRL] = 16368, -+ [GA_XQS_SYSTEM] = 5744, -+ [GA_XQS_QLIMIT_SHR] = 6912, -+}; -+ -+const unsigned int lan969x_gcnt[GCNT_LAST] = { -+ [GC_ANA_AC_SRC] = 67, -+ [GC_ANA_AC_PGID] = 1054, -+ [GC_ANA_AC_TSN_SF_CFG] = 256, -+ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, -+ [GC_ANA_ACL_KEY_SEL] = 99, -+ [GC_ANA_ACL_CNT_A] = 1024, -+ [GC_ANA_ACL_CNT_B] = 1024, -+ [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, -+ [GC_ANA_AC_SDLB_LBSET_TBL] = 496, -+ [GC_ANA_CL_PORT] = 35, -+ [GC_ANA_L2_ISDX_LIMIT] = 256, -+ [GC_ANA_L2_ISDX] = 1024, -+ [GC_ANA_L3_VLAN] = 4608, -+ [GC_ASM_DEV_STATISTICS] = 30, -+ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, -+ [GC_EACL_CNT_TBL] = 512, -+ [GC_GCB_SIO_CTRL] = 1, -+ [GC_HSCH_HSCH_CFG] = 1120, -+ [GC_HSCH_HSCH_DWRR] = 32, -+ [GC_PTP_PTP_PINS] = 8, -+ [GC_PTP_PHASE_DETECTOR_CTRL] = 8, -+ [GC_REW_PORT] = 35, -+ [GC_REW_VOE_PORT_LM_CNT] = 240, -+}; -+ -+const unsigned int lan969x_gsize[GSIZE_LAST] = { -+ [GW_ANA_AC_SRC] = 4, -+ [GW_ANA_L2_COMMON] = 712, -+ [GW_ASM_CFG] = 1092, -+ [GW_CPU_CPU_REGS] = 180, -+ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, -+ [GW_FDMA_FDMA] = 448, -+ [GW_GCB_CHIP_REGS] = 180, -+ [GW_HSCH_TAS_CONFIG] = 16, -+ [GW_PTP_PHASE_DETECTOR_CTRL] = 12, -+ [GW_QSYS_PAUSE_CFG] = 988, -+}; -+ -+const unsigned int lan969x_fpos[FPOS_LAST] = { -+ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, -+ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, -+ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, -+ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, -+ [FP_CPU_PROC_CTRL_VINITHI] = 3, -+ [FP_CPU_PROC_CTRL_CFGTE] = 2, -+ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, -+ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, -+ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, -+ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, -+ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, -+ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, -+ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, -+ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, -+ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, -+ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, -+}; -+ -+const unsigned int lan969x_fsize[FSIZE_LAST] = { -+ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, -+ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, -+ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, -+ [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, -+ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, -+ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, -+ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, -+ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, -+ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, -+ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, -+ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, -+ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, -+ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, -+ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, -+ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, -+ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, -+ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, -+ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, -+ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, -+ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, -+ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, -+ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, -+ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, -+ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, -+ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, -+ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, -+ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, -+ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, -+ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, -+ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, -+ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, -+ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, -+ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, -+ [FW_QRES_RES_CFG_WM_HIGH] = 11, -+ [FW_QRES_RES_STAT_MAXUSE] = 19, -+ [FW_QRES_RES_STAT_CUR_INUSE] = 19, -+ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, -+ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, -+ [FW_QSYS_ATOP_ATOP] = 11, -+ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, -+ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, -+ [FW_XQS_STAT_CFG_STAT_VIEW] = 10, -+ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, -+ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, -+ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, -+ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, -+}; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c -@@ -0,0 +1,3843 @@ -+// SPDX-License-Identifier: BSD-3-Clause -+/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. -+ * Microchip VCAP API -+ */ -+ -+/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. -+ * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 -+ */ -+ -+#include -+#include -+ -+#include "lan969x.h" -+ -+/* keyfields */ -+static const struct vcap_field is0_normal_7tuple_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 4, -+ .width = 10, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 16, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 81, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 82, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 83, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 86, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 89, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 93, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 105, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 108, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI1] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 111, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 112, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 124, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 127, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI2] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 130, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 131, -+ .width = 12, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 144, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 192, -+ .width = 48, -+ }, -+ [VCAP_KF_IP_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 240, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 241, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 242, -+ .width = 16, -+ }, -+ [VCAP_KF_IP_SNAP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 258, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 259, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 260, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 262, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 263, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DSCP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 264, -+ .width = 6, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 270, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 398, -+ .width = 128, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 526, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 527, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 528, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 544, -+ .width = 8, -+ }, -+}; -+ -+static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_GEN_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 10, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 15, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 17, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 82, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 83, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 87, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID0] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 94, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 106, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI1] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 112, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID1] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 113, -+ .width = 12, -+ }, -+ [VCAP_KF_8021Q_TPID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 125, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_PCP2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 128, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI2] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 131, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID2] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 132, -+ .width = 12, -+ }, -+ [VCAP_KF_IP_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 145, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 146, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 147, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 149, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 150, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DSCP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 151, -+ .width = 6, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 157, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 189, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 221, -+ .width = 8, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 229, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 230, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 231, -+ .width = 8, -+ }, -+ [VCAP_KF_IP_PAYLOAD_5TUPLE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 239, -+ .width = 32, -+ }, -+}; -+ -+static const struct vcap_field is2_mac_etype_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 89, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 137, -+ .width = 48, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 185, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 186, -+ .width = 16, -+ }, -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 202, -+ .width = 64, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 266, -+ .width = 16, -+ }, -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 282, -+ .width = 1, -+ }, -+ [VCAP_KF_OAM_Y1731_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 283, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field is2_arp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 85, -+ .width = 48, -+ }, -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 133, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 134, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_LEN_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 135, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_TGT_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 136, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 137, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 138, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 139, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 173, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 205, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 206, -+ .width = 16, -+ }, -+}; -+ -+static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 94, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 95, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 103, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 135, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 167, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 168, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 169, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 185, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 201, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 217, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 219, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 220, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 221, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 222, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 223, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 224, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 225, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field is2_ip4_other_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 90, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 93, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 94, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 95, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 103, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 135, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 167, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 168, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 176, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U112, -+ .offset = 192, -+ .width = 96, -+ }, -+}; -+ -+static const struct vcap_field is2_ip6_std_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 4, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 4, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 5, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 32, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 52, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 53, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 54, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 56, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 57, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 80, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 90, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 219, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 227, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 243, -+ .width = 40, -+ }, -+}; -+ -+static const struct vcap_field is2_ip_7tuple_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_KF_LOOKUP_PAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 8, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 4, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 2, -+ }, -+ [VCAP_KF_IF_IGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U72, -+ .offset = 18, -+ .width = 65, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 83, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 85, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 98, -+ .width = 13, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 111, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 112, -+ .width = 3, -+ }, -+ [VCAP_KF_L2_FWD_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 115, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 118, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_DST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 119, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 120, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 168, -+ .width = 48, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 218, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 219, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 220, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 228, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 356, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 484, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 485, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 486, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 487, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 503, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 519, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 535, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 536, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 537, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 538, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 539, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 540, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 541, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 542, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 543, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es0_isdx_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_EGR_PORT_NO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 1, -+ .width = 6, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 7, -+ .width = 13, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 20, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_TPID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 23, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 27, -+ .width = 1, -+ }, -+ [VCAP_KF_PROT_ACTIVE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 28, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 38, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field es2_mac_etype_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 96, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 144, -+ .width = 48, -+ }, -+ [VCAP_KF_ETYPE_LEN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 192, -+ .width = 1, -+ }, -+ [VCAP_KF_ETYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 193, -+ .width = 16, -+ }, -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 209, -+ .width = 64, -+ }, -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 273, -+ .width = 1, -+ }, -+ [VCAP_KF_OAM_Y1731_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 274, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_arp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 95, -+ .width = 48, -+ }, -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 143, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 144, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_LEN_OK_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 145, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_TGT_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 146, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 147, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 148, -+ .width = 1, -+ }, -+ [VCAP_KF_ARP_OPCODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 149, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 151, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 183, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 215, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 97, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 99, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 100, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 101, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 173, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 174, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 175, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 191, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 207, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 223, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 224, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 225, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 226, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 227, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 228, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 229, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 230, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 231, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es2_ip4_other_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_FRAGMENT_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 97, -+ .width = 2, -+ }, -+ [VCAP_KF_L3_OPTIONS_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 99, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 100, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 101, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP4_DIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 109, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_IP4_SIP] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 141, -+ .width = 32, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 173, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 174, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U112, -+ .offset = 182, -+ .width = 96, -+ }, -+}; -+ -+static const struct vcap_field es2_ip_7tuple_keyfield[] = { -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 10, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 12, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 13, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 23, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 38, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 73, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 74, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 81, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 85, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 88, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 89, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_DMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 93, -+ .width = 48, -+ }, -+ [VCAP_KF_L2_SMAC] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 141, -+ .width = 48, -+ }, -+ [VCAP_KF_IP4_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 191, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 192, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TOS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 193, -+ .width = 8, -+ }, -+ [VCAP_KF_L3_IP6_DIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 201, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 329, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 457, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_UDP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 458, -+ .width = 1, -+ }, -+ [VCAP_KF_TCP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 459, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_DPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 460, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 476, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 492, -+ .width = 16, -+ }, -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 508, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 509, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_FIN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 510, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_SYN] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 511, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_RST] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 512, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PSH] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 513, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_ACK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 514, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_URG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 515, -+ .width = 1, -+ }, -+ [VCAP_KF_L4_PAYLOAD] = { -+ .type = VCAP_FIELD_U64, -+ .offset = 516, -+ .width = 64, -+ }, -+}; -+ -+static const struct vcap_field es2_ip6_std_keyfield[] = { -+ [VCAP_KF_TYPE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 3, -+ }, -+ [VCAP_KF_LOOKUP_FIRST_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 3, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_MC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 13, -+ .width = 1, -+ }, -+ [VCAP_KF_L2_BC_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 14, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_GT0_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_KF_ISDX_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 10, -+ }, -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_KF_8021Q_VID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 13, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 41, -+ .width = 3, -+ }, -+ [VCAP_KF_IF_EGR_PORT_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 44, -+ .width = 32, -+ }, -+ [VCAP_KF_IF_IGR_PORT_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 76, -+ .width = 1, -+ }, -+ [VCAP_KF_IF_IGR_PORT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 77, -+ .width = 7, -+ }, -+ [VCAP_KF_8021Q_PCP_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 84, -+ .width = 3, -+ }, -+ [VCAP_KF_8021Q_DEI_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 87, -+ .width = 1, -+ }, -+ [VCAP_KF_COSID_CLS] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 88, -+ .width = 3, -+ }, -+ [VCAP_KF_L3_DPL_CLS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 91, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_RT_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 92, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_TTL_GT0] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 96, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP6_SIP] = { -+ .type = VCAP_FIELD_U128, -+ .offset = 97, -+ .width = 128, -+ }, -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 225, -+ .width = 1, -+ }, -+ [VCAP_KF_L3_IP_PROTO] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 226, -+ .width = 8, -+ }, -+ [VCAP_KF_L4_RNG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 234, -+ .width = 16, -+ }, -+ [VCAP_KF_L3_PAYLOAD] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 250, -+ .width = 40, -+ }, -+}; -+ -+/* keyfield_set */ -+static const struct vcap_set is0_keyfield_set[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = { -+ .type_id = 0, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = { -+ .type_id = 2, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+}; -+ -+static const struct vcap_set is2_keyfield_set[] = { -+ [VCAP_KFS_MAC_ETYPE] = { -+ .type_id = 0, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_ARP] = { -+ .type_id = 3, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_TCP_UDP] = { -+ .type_id = 4, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_OTHER] = { -+ .type_id = 5, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP6_STD] = { -+ .type_id = 6, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP_7TUPLE] = { -+ .type_id = 1, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es0_keyfield_set[] = { -+ [VCAP_KFS_ISDX] = { -+ .type_id = 0, -+ .sw_per_item = 1, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es2_keyfield_set[] = { -+ [VCAP_KFS_MAC_ETYPE] = { -+ .type_id = 0, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_ARP] = { -+ .type_id = 1, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_TCP_UDP] = { -+ .type_id = 2, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP4_OTHER] = { -+ .type_id = 3, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+ [VCAP_KFS_IP_7TUPLE] = { -+ .type_id = -1, -+ .sw_per_item = 12, -+ .sw_cnt = 1, -+ }, -+ [VCAP_KFS_IP6_STD] = { -+ .type_id = 4, -+ .sw_per_item = 6, -+ .sw_cnt = 2, -+ }, -+}; -+ -+/* keyfield_set map */ -+static const struct vcap_field *is0_keyfield_set_map[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, -+}; -+ -+static const struct vcap_field *is2_keyfield_set_map[] = { -+ [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, -+ [VCAP_KFS_ARP] = is2_arp_keyfield, -+ [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, -+ [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, -+ [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, -+ [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, -+}; -+ -+static const struct vcap_field *es0_keyfield_set_map[] = { -+ [VCAP_KFS_ISDX] = es0_isdx_keyfield, -+}; -+ -+static const struct vcap_field *es2_keyfield_set_map[] = { -+ [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, -+ [VCAP_KFS_ARP] = es2_arp_keyfield, -+ [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, -+ [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, -+ [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, -+ [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, -+}; -+ -+/* keyfield_set map sizes */ -+static int is0_keyfield_set_map_size[] = { -+ [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), -+}; -+ -+static int is2_keyfield_set_map_size[] = { -+ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), -+ [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), -+ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), -+ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), -+ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), -+ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), -+}; -+ -+static int es0_keyfield_set_map_size[] = { -+ [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), -+}; -+ -+static int es2_keyfield_set_map_size[] = { -+ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), -+ [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), -+ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), -+ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), -+ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), -+ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), -+}; -+ -+/* actionfields */ -+static const struct vcap_field is0_classification_actionfield[] = { -+ [VCAP_AF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 6, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 12, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 13, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 16, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 2, -+ }, -+ [VCAP_AF_DEI_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 19, -+ .width = 1, -+ }, -+ [VCAP_AF_DEI_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 20, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 21, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 22, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 30, -+ .width = 7, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 37, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 43, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 66, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 67, -+ .width = 10, -+ }, -+ [VCAP_AF_PAG_OVERRIDE_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 107, -+ .width = 8, -+ }, -+ [VCAP_AF_PAG_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 115, -+ .width = 8, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 167, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 170, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is0_full_actionfield[] = { -+ [VCAP_AF_DSCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 1, -+ .width = 6, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 11, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 16, -+ .width = 2, -+ }, -+ [VCAP_AF_DEI_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 18, -+ .width = 1, -+ }, -+ [VCAP_AF_DEI_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 19, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 20, -+ .width = 1, -+ }, -+ [VCAP_AF_PCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 21, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 24, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 26, -+ .width = 3, -+ }, -+ [VCAP_AF_MAP_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 29, -+ .width = 7, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 36, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 42, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 65, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 66, -+ .width = 10, -+ }, -+ [VCAP_AF_MASK_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 76, -+ .width = 3, -+ }, -+ [VCAP_AF_PORT_MASK] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 79, -+ .width = 37, -+ }, -+ [VCAP_AF_PAG_OVERRIDE_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 174, -+ .width = 8, -+ }, -+ [VCAP_AF_PAG_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 182, -+ .width = 8, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 266, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 269, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is0_class_reduced_actionfield[] = { -+ [VCAP_AF_TYPE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 5, -+ .width = 1, -+ }, -+ [VCAP_AF_QOS_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 6, -+ .width = 3, -+ }, -+ [VCAP_AF_DP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 9, -+ .width = 1, -+ }, -+ [VCAP_AF_DP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 10, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_LOOKUP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 12, -+ .width = 2, -+ }, -+ [VCAP_AF_MAP_KEY] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 3, -+ }, -+ [VCAP_AF_CLS_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 23, -+ .width = 13, -+ }, -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 46, -+ .width = 1, -+ }, -+ [VCAP_AF_ISDX_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 47, -+ .width = 10, -+ }, -+ [VCAP_AF_NXT_IDX_CTRL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 89, -+ .width = 3, -+ }, -+ [VCAP_AF_NXT_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 92, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field is2_base_type_actionfield[] = { -+ [VCAP_AF_PIPELINE_FORCE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_PIPELINE_PT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 5, -+ }, -+ [VCAP_AF_HIT_ME_ONCE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 7, -+ .width = 1, -+ }, -+ [VCAP_AF_INTR_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 8, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_COPY_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 9, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 10, -+ .width = 3, -+ }, -+ [VCAP_AF_LRN_DIS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 15, -+ .width = 1, -+ }, -+ [VCAP_AF_RT_DIS] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 16, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 17, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 5, -+ }, -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 23, -+ .width = 1, -+ }, -+ [VCAP_AF_MASK_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_PORT_MASK] = { -+ .type = VCAP_FIELD_U48, -+ .offset = 30, -+ .width = 37, -+ }, -+ [VCAP_AF_MIRROR_PROBE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 78, -+ .width = 2, -+ }, -+ [VCAP_AF_MATCH_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 131, -+ .width = 16, -+ }, -+ [VCAP_AF_MATCH_ID_MASK] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 147, -+ .width = 16, -+ }, -+ [VCAP_AF_CNT_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 163, -+ .width = 10, -+ }, -+}; -+ -+static const struct vcap_field es0_es0_actionfield[] = { -+ [VCAP_AF_PUSH_OUTER_TAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 0, -+ .width = 2, -+ }, -+ [VCAP_AF_PUSH_INNER_TAG] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 2, -+ .width = 1, -+ }, -+ [VCAP_AF_TAG_A_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 3, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_A_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 6, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_A_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 8, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_A_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 11, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 14, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 17, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_B_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 19, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_B_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 22, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_TPID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 25, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_PCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 28, -+ .width = 3, -+ }, -+ [VCAP_AF_TAG_C_DEI_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 31, -+ .width = 3, -+ }, -+ [VCAP_AF_VID_A_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 34, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_A_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 46, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_A_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 49, -+ .width = 1, -+ }, -+ [VCAP_AF_VID_B_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 50, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_B_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 62, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_B_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 65, -+ .width = 1, -+ }, -+ [VCAP_AF_VID_C_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 66, -+ .width = 12, -+ }, -+ [VCAP_AF_PCP_C_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 78, -+ .width = 3, -+ }, -+ [VCAP_AF_DEI_C_VAL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 81, -+ .width = 1, -+ }, -+ [VCAP_AF_POP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 82, -+ .width = 2, -+ }, -+ [VCAP_AF_UNTAG_VID_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 84, -+ .width = 1, -+ }, -+ [VCAP_AF_PUSH_CUSTOMER_TAG] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 85, -+ .width = 2, -+ }, -+ [VCAP_AF_TAG_C_VID_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 87, -+ .width = 2, -+ }, -+ [VCAP_AF_DSCP_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 127, -+ .width = 3, -+ }, -+ [VCAP_AF_DSCP_VAL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 130, -+ .width = 6, -+ }, -+ [VCAP_AF_ESDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 319, -+ .width = 10, -+ }, -+ [VCAP_AF_FWD_SEL] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 438, -+ .width = 2, -+ }, -+ [VCAP_AF_CPU_QU] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 440, -+ .width = 3, -+ }, -+ [VCAP_AF_PIPELINE_PT] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 443, -+ .width = 2, -+ }, -+ [VCAP_AF_PIPELINE_ACT] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 445, -+ .width = 1, -+ }, -+ [VCAP_AF_SWAP_MACS_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 454, -+ .width = 1, -+ }, -+ [VCAP_AF_LOOP_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 455, -+ .width = 1, -+ }, -+}; -+ -+static const struct vcap_field es2_base_type_actionfield[] = { -+ [VCAP_AF_HIT_ME_ONCE] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 0, -+ .width = 1, -+ }, -+ [VCAP_AF_INTR_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 1, -+ .width = 1, -+ }, -+ [VCAP_AF_FWD_MODE] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 2, -+ .width = 2, -+ }, -+ [VCAP_AF_COPY_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 4, -+ .width = 14, -+ }, -+ [VCAP_AF_COPY_PORT_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 18, -+ .width = 6, -+ }, -+ [VCAP_AF_MIRROR_PROBE_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 24, -+ .width = 2, -+ }, -+ [VCAP_AF_CPU_COPY_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 26, -+ .width = 1, -+ }, -+ [VCAP_AF_CPU_QUEUE_NUM] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 27, -+ .width = 3, -+ }, -+ [VCAP_AF_POLICE_ENA] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 30, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_REMARK] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 31, -+ .width = 1, -+ }, -+ [VCAP_AF_POLICE_IDX] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 32, -+ .width = 5, -+ }, -+ [VCAP_AF_ES2_REW_CMD] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 37, -+ .width = 3, -+ }, -+ [VCAP_AF_CNT_ID] = { -+ .type = VCAP_FIELD_U32, -+ .offset = 40, -+ .width = 9, -+ }, -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { -+ .type = VCAP_FIELD_BIT, -+ .offset = 49, -+ .width = 1, -+ }, -+}; -+ -+/* actionfield_set */ -+static const struct vcap_set is0_actionfield_set[] = { -+ [VCAP_AFS_CLASSIFICATION] = { -+ .type_id = 1, -+ .sw_per_item = 2, -+ .sw_cnt = 6, -+ }, -+ [VCAP_AFS_FULL] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+ [VCAP_AFS_CLASS_REDUCED] = { -+ .type_id = 1, -+ .sw_per_item = 1, -+ .sw_cnt = 12, -+ }, -+}; -+ -+static const struct vcap_set is2_actionfield_set[] = { -+ [VCAP_AFS_BASE_TYPE] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+}; -+ -+static const struct vcap_set es0_actionfield_set[] = { -+ [VCAP_AFS_ES0] = { -+ .type_id = -1, -+ .sw_per_item = 1, -+ .sw_cnt = 1, -+ }, -+}; -+ -+static const struct vcap_set es2_actionfield_set[] = { -+ [VCAP_AFS_BASE_TYPE] = { -+ .type_id = -1, -+ .sw_per_item = 3, -+ .sw_cnt = 4, -+ }, -+}; -+ -+/* actionfield_set map */ -+static const struct vcap_field *is0_actionfield_set_map[] = { -+ [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, -+ [VCAP_AFS_FULL] = is0_full_actionfield, -+ [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, -+}; -+ -+static const struct vcap_field *is2_actionfield_set_map[] = { -+ [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, -+}; -+ -+static const struct vcap_field *es0_actionfield_set_map[] = { -+ [VCAP_AFS_ES0] = es0_es0_actionfield, -+}; -+ -+static const struct vcap_field *es2_actionfield_set_map[] = { -+ [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, -+}; -+ -+/* actionfield_set map size */ -+static int is0_actionfield_set_map_size[] = { -+ [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), -+ [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), -+ [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), -+}; -+ -+static int is2_actionfield_set_map_size[] = { -+ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), -+}; -+ -+static int es0_actionfield_set_map_size[] = { -+ [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), -+}; -+ -+static int es2_actionfield_set_map_size[] = { -+ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), -+}; -+ -+/* Type Groups */ -+static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 5, -+ .value = 16, -+ }, -+ { -+ .offset = 52, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 104, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 156, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 208, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 260, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 4, -+ .value = 0, -+ }, -+ { -+ .offset = 364, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 416, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 520, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 572, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 4, -+ .value = 8, -+ }, -+ { -+ .offset = 52, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 104, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 156, -+ .width = 3, -+ .value = 0, -+ }, -+ { -+ .offset = 208, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 260, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 312, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 468, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 156, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { -+ [12] = is0_x12_keyfield_set_typegroups, -+ [6] = is0_x6_keyfield_set_typegroups, -+ [3] = is0_x3_keyfield_set_typegroups, -+ [2] = is0_x2_keyfield_set_typegroups, -+ [1] = is0_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { -+ [12] = is2_x12_keyfield_set_typegroups, -+ [6] = is2_x6_keyfield_set_typegroups, -+ [3] = is2_x3_keyfield_set_typegroups, -+ [1] = is2_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { -+ [1] = es0_x1_keyfield_set_typegroups, -+ [2] = NULL, -+}; -+ -+static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { -+ [12] = es2_x12_keyfield_set_typegroups, -+ [6] = es2_x6_keyfield_set_typegroups, -+ [3] = es2_x3_keyfield_set_typegroups, -+ [1] = es2_x1_keyfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 3, -+ .value = 4, -+ }, -+ { -+ .offset = 103, -+ .width = 2, -+ .value = 0, -+ }, -+ { -+ .offset = 206, -+ .width = 2, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 103, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 1, -+ .value = 1, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 95, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 190, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { -+ { -+ .offset = 0, -+ .width = 2, -+ .value = 2, -+ }, -+ { -+ .offset = 19, -+ .width = 1, -+ .value = 0, -+ }, -+ { -+ .offset = 38, -+ .width = 1, -+ .value = 0, -+ }, -+ {} -+}; -+ -+static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { -+ {} -+}; -+ -+static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { -+ [3] = is0_x3_actionfield_set_typegroups, -+ [2] = is0_x2_actionfield_set_typegroups, -+ [1] = is0_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { -+ [3] = is2_x3_actionfield_set_typegroups, -+ [1] = is2_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { -+ [1] = es0_x1_actionfield_set_typegroups, -+ [2] = NULL, -+}; -+ -+static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { -+ [3] = es2_x3_actionfield_set_typegroups, -+ [1] = es2_x1_actionfield_set_typegroups, -+ [13] = NULL, -+}; -+ -+/* Keyfieldset names */ -+static const char * const vcap_keyfield_set_names[] = { -+ [VCAP_KFS_NO_VALUE] = "(None)", -+ [VCAP_KFS_ARP] = "VCAP_KFS_ARP", -+ [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", -+ [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", -+ [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", -+ [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", -+ [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", -+ [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", -+ [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", -+ [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", -+ [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", -+ [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", -+ [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", -+ [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", -+ [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", -+ [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", -+ [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", -+ [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", -+ [VCAP_KFS_OAM] = "VCAP_KFS_OAM", -+ [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", -+ [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", -+ [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", -+}; -+ -+/* Actionfieldset names */ -+static const char * const vcap_actionfield_set_names[] = { -+ [VCAP_AFS_NO_VALUE] = "(None)", -+ [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", -+ [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", -+ [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", -+ [VCAP_AFS_ES0] = "VCAP_AFS_ES0", -+ [VCAP_AFS_FULL] = "VCAP_AFS_FULL", -+ [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", -+}; -+ -+/* Keyfield names */ -+static const char * const vcap_keyfield_names[] = { -+ [VCAP_KF_NO_VALUE] = "(None)", -+ [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", -+ [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", -+ [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", -+ [VCAP_KF_8021BR_GRP] = "8021BR_GRP", -+ [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", -+ [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", -+ [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", -+ [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", -+ [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", -+ [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", -+ [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", -+ [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", -+ [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", -+ [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", -+ [VCAP_KF_8021Q_TPID] = "8021Q_TPID", -+ [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", -+ [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", -+ [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", -+ [VCAP_KF_8021Q_VID0] = "8021Q_VID0", -+ [VCAP_KF_8021Q_VID1] = "8021Q_VID1", -+ [VCAP_KF_8021Q_VID2] = "8021Q_VID2", -+ [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", -+ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", -+ [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", -+ [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", -+ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", -+ [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", -+ [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", -+ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", -+ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", -+ [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", -+ [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", -+ [VCAP_KF_COSID_CLS] = "COSID_CLS", -+ [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", -+ [VCAP_KF_ETYPE] = "ETYPE", -+ [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", -+ [VCAP_KF_HOST_MATCH] = "HOST_MATCH", -+ [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", -+ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", -+ [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", -+ [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", -+ [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", -+ [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", -+ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", -+ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", -+ [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", -+ [VCAP_KF_IP4_IS] = "IP4_IS", -+ [VCAP_KF_IP_MC_IS] = "IP_MC_IS", -+ [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", -+ [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", -+ [VCAP_KF_ISDX_CLS] = "ISDX_CLS", -+ [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", -+ [VCAP_KF_L2_BC_IS] = "L2_BC_IS", -+ [VCAP_KF_L2_DMAC] = "L2_DMAC", -+ [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", -+ [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", -+ [VCAP_KF_L2_LLC] = "L2_LLC", -+ [VCAP_KF_L2_MC_IS] = "L2_MC_IS", -+ [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", -+ [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", -+ [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", -+ [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", -+ [VCAP_KF_L2_SMAC] = "L2_SMAC", -+ [VCAP_KF_L2_SNAP] = "L2_SNAP", -+ [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", -+ [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", -+ [VCAP_KF_L3_DSCP] = "L3_DSCP", -+ [VCAP_KF_L3_DST_IS] = "L3_DST_IS", -+ [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", -+ [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", -+ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", -+ [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", -+ [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", -+ [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", -+ [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", -+ [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", -+ [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", -+ [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", -+ [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", -+ [VCAP_KF_L3_RT_IS] = "L3_RT_IS", -+ [VCAP_KF_L3_TOS] = "L3_TOS", -+ [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", -+ [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", -+ [VCAP_KF_L4_1588_VER] = "L4_1588_VER", -+ [VCAP_KF_L4_ACK] = "L4_ACK", -+ [VCAP_KF_L4_DPORT] = "L4_DPORT", -+ [VCAP_KF_L4_FIN] = "L4_FIN", -+ [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", -+ [VCAP_KF_L4_PSH] = "L4_PSH", -+ [VCAP_KF_L4_RNG] = "L4_RNG", -+ [VCAP_KF_L4_RST] = "L4_RST", -+ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", -+ [VCAP_KF_L4_SPORT] = "L4_SPORT", -+ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", -+ [VCAP_KF_L4_SYN] = "L4_SYN", -+ [VCAP_KF_L4_URG] = "L4_URG", -+ [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", -+ [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", -+ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", -+ [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", -+ [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", -+ [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", -+ [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", -+ [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", -+ [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", -+ [VCAP_KF_OAM_MEPID] = "OAM_MEPID", -+ [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", -+ [VCAP_KF_OAM_VER] = "OAM_VER", -+ [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", -+ [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", -+ [VCAP_KF_TCP_IS] = "TCP_IS", -+ [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", -+ [VCAP_KF_TYPE] = "TYPE", -+}; -+ -+/* Actionfield names */ -+static const char * const vcap_actionfield_names[] = { -+ [VCAP_AF_NO_VALUE] = "(None)", -+ [VCAP_AF_ACL_ID] = "ACL_ID", -+ [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", -+ [VCAP_AF_CNT_ID] = "CNT_ID", -+ [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", -+ [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", -+ [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", -+ [VCAP_AF_CPU_QU] = "CPU_QU", -+ [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", -+ [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", -+ [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", -+ [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", -+ [VCAP_AF_DEI_ENA] = "DEI_ENA", -+ [VCAP_AF_DEI_VAL] = "DEI_VAL", -+ [VCAP_AF_DP_ENA] = "DP_ENA", -+ [VCAP_AF_DP_VAL] = "DP_VAL", -+ [VCAP_AF_DSCP_ENA] = "DSCP_ENA", -+ [VCAP_AF_DSCP_SEL] = "DSCP_SEL", -+ [VCAP_AF_DSCP_VAL] = "DSCP_VAL", -+ [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", -+ [VCAP_AF_ESDX] = "ESDX", -+ [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", -+ [VCAP_AF_FWD_MODE] = "FWD_MODE", -+ [VCAP_AF_FWD_SEL] = "FWD_SEL", -+ [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", -+ [VCAP_AF_HOST_MATCH] = "HOST_MATCH", -+ [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", -+ [VCAP_AF_INTR_ENA] = "INTR_ENA", -+ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", -+ [VCAP_AF_ISDX_ENA] = "ISDX_ENA", -+ [VCAP_AF_ISDX_VAL] = "ISDX_VAL", -+ [VCAP_AF_LOOP_ENA] = "LOOP_ENA", -+ [VCAP_AF_LRN_DIS] = "LRN_DIS", -+ [VCAP_AF_MAP_IDX] = "MAP_IDX", -+ [VCAP_AF_MAP_KEY] = "MAP_KEY", -+ [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", -+ [VCAP_AF_MASK_MODE] = "MASK_MODE", -+ [VCAP_AF_MATCH_ID] = "MATCH_ID", -+ [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", -+ [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", -+ [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", -+ [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", -+ [VCAP_AF_NXT_IDX] = "NXT_IDX", -+ [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", -+ [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", -+ [VCAP_AF_PAG_VAL] = "PAG_VAL", -+ [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", -+ [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", -+ [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", -+ [VCAP_AF_PCP_ENA] = "PCP_ENA", -+ [VCAP_AF_PCP_VAL] = "PCP_VAL", -+ [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", -+ [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", -+ [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", -+ [VCAP_AF_POLICE_ENA] = "POLICE_ENA", -+ [VCAP_AF_POLICE_IDX] = "POLICE_IDX", -+ [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", -+ [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", -+ [VCAP_AF_POP_VAL] = "POP_VAL", -+ [VCAP_AF_PORT_MASK] = "PORT_MASK", -+ [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", -+ [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", -+ [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", -+ [VCAP_AF_QOS_ENA] = "QOS_ENA", -+ [VCAP_AF_QOS_VAL] = "QOS_VAL", -+ [VCAP_AF_REW_OP] = "REW_OP", -+ [VCAP_AF_RT_DIS] = "RT_DIS", -+ [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", -+ [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", -+ [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", -+ [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", -+ [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", -+ [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", -+ [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", -+ [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", -+ [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", -+ [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", -+ [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", -+ [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", -+ [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", -+ [VCAP_AF_TYPE] = "TYPE", -+ [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", -+ [VCAP_AF_VID_A_VAL] = "VID_A_VAL", -+ [VCAP_AF_VID_B_VAL] = "VID_B_VAL", -+ [VCAP_AF_VID_C_VAL] = "VID_C_VAL", -+ [VCAP_AF_VID_VAL] = "VID_VAL", -+}; -+ -+/* VCAPs */ -+const struct vcap_info lan969x_vcaps[] = { -+ [VCAP_TYPE_IS0] = { -+ .name = "is0", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 103, -+ .default_cnt = 70, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = is0_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), -+ .actionfield_set = is0_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), -+ .keyfield_set_map = is0_keyfield_set_map, -+ .keyfield_set_map_size = is0_keyfield_set_map_size, -+ .actionfield_set_map = is0_actionfield_set_map, -+ .actionfield_set_map_size = is0_actionfield_set_map_size, -+ .keyfield_set_typegroups = is0_keyfield_set_typegroups, -+ .actionfield_set_typegroups = is0_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_IS2] = { -+ .name = "is2", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 103, -+ .default_cnt = 38, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = is2_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), -+ .actionfield_set = is2_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), -+ .keyfield_set_map = is2_keyfield_set_map, -+ .keyfield_set_map_size = is2_keyfield_set_map_size, -+ .actionfield_set_map = is2_actionfield_set_map, -+ .actionfield_set_map_size = is2_actionfield_set_map_size, -+ .keyfield_set_typegroups = is2_keyfield_set_typegroups, -+ .actionfield_set_typegroups = is2_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_ES0] = { -+ .name = "es0", -+ .rows = 1536, -+ .sw_count = 1, -+ .sw_width = 51, -+ .sticky_width = 1, -+ .act_width = 469, -+ .default_cnt = 35, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = es0_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), -+ .actionfield_set = es0_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), -+ .keyfield_set_map = es0_keyfield_set_map, -+ .keyfield_set_map_size = es0_keyfield_set_map_size, -+ .actionfield_set_map = es0_actionfield_set_map, -+ .actionfield_set_map_size = es0_actionfield_set_map_size, -+ .keyfield_set_typegroups = es0_keyfield_set_typegroups, -+ .actionfield_set_typegroups = es0_actionfield_set_typegroups, -+ }, -+ [VCAP_TYPE_ES2] = { -+ .name = "es2", -+ .rows = 256, -+ .sw_count = 12, -+ .sw_width = 52, -+ .sticky_width = 1, -+ .act_width = 19, -+ .default_cnt = 39, -+ .require_cnt_dis = 0, -+ .version = 1, -+ .keyfield_set = es2_keyfield_set, -+ .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), -+ .actionfield_set = es2_actionfield_set, -+ .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), -+ .keyfield_set_map = es2_keyfield_set_map, -+ .keyfield_set_map_size = es2_keyfield_set_map_size, -+ .actionfield_set_map = es2_actionfield_set_map, -+ .actionfield_set_map_size = es2_actionfield_set_map_size, -+ .keyfield_set_typegroups = es2_keyfield_set_typegroups, -+ .actionfield_set_typegroups = es2_actionfield_set_typegroups, -+ }, -+}; -+ -+const struct vcap_statistics lan969x_vcap_stats = { -+ .name = "lan969x", -+ .count = 4, -+ .keyfield_set_names = vcap_keyfield_set_names, -+ .actionfield_set_names = vcap_actionfield_set_names, -+ .keyfield_names = vcap_keyfield_names, -+ .actionfield_names = vcap_actionfield_names, -+}; ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_impl.c -@@ -0,0 +1,85 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "vcap_api.h" -+#include "lan969x.h" -+ -+const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-0 */ -+ .vinst = 0, -+ .map_id = 1, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L0, -+ .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, -+ .blockno = 2, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-1 */ -+ .vinst = 1, -+ .map_id = 2, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L2, -+ .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, -+ .blockno = 3, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS0, /* CLM-2 */ -+ .vinst = 2, -+ .map_id = 3, -+ .lookups = SPARX5_IS0_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, -+ .first_cid = SPARX5_VCAP_CID_IS0_L4, -+ .last_cid = SPARX5_VCAP_CID_IS0_MAX, -+ .blockno = 4, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS2, /* IS2-0 */ -+ .vinst = 0, -+ .map_id = 4, -+ .lookups = SPARX5_IS2_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -+ .first_cid = SPARX5_VCAP_CID_IS2_L0, -+ .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, -+ .blockno = 0, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_IS2, /* IS2-1 */ -+ .vinst = 1, -+ .map_id = 5, -+ .lookups = SPARX5_IS2_LOOKUPS, -+ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, -+ .first_cid = SPARX5_VCAP_CID_IS2_L2, -+ .last_cid = SPARX5_VCAP_CID_IS2_MAX, -+ .blockno = 1, -+ .blocks = 1, -+ .ingress = true, -+ }, -+ { -+ .vtype = VCAP_TYPE_ES0, -+ .lookups = SPARX5_ES0_LOOKUPS, -+ .lookups_per_instance = SPARX5_ES0_LOOKUPS, -+ .first_cid = SPARX5_VCAP_CID_ES0_L0, -+ .last_cid = SPARX5_VCAP_CID_ES0_MAX, -+ .count = 1536, -+ .ingress = false, -+ }, -+ { -+ .vtype = VCAP_TYPE_ES2, -+ .lookups = SPARX5_ES2_LOOKUPS, -+ .lookups_per_instance = SPARX5_ES2_LOOKUPS, -+ .first_cid = SPARX5_VCAP_CID_ES2_L0, -+ .last_cid = SPARX5_VCAP_CID_ES2_MAX, -+ .count = 1024, -+ .ingress = false, -+ }, -+}; diff --git a/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch b/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch deleted file mode 100644 index 691092ba16..0000000000 --- a/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch +++ /dev/null @@ -1,33 +0,0 @@ -From f7a21fee946712acc54102479f0ebaaff48164e4 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 5 Dec 2024 14:54:25 +0100 -Subject: [PATCH 66/82] net: lan969x: fix the use of spin_lock in PTP handler - -We are mixing the use of spin_lock() and spin_lock_irqsave() functions -in the PTP handler of lan969x. Fix this by correctly using the _irqsave -variants. - -Fixes: 24fe83541755 ("net: lan969x: add PTP handler function") -Signed-off-by: Daniel Machon - -[1]: https://lore.kernel.org/netdev/20241024-sparx5-lan969x-switch-driver-2-v2-10-a0b5fae88a0f@microchip.com/ - -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -273,9 +273,9 @@ static irqreturn_t lan969x_ptp_irq_handl - if (WARN_ON(!skb_match)) - continue; - -- spin_lock(&sparx5->ptp_ts_id_lock); -+ spin_lock_irqsave(&sparx5->ptp_ts_id_lock, flags); - sparx5->ptp_skbs--; -- spin_unlock(&sparx5->ptp_ts_id_lock); -+ spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); - - /* Get the h/w timestamp */ - sparx5_get_hwtimestamp(sparx5, &ts, delay); diff --git a/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch b/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch deleted file mode 100644 index 9ad9fe82ae..0000000000 --- a/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e647f95a65d299fbb58ef8d44795abab3bc63d41 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Thu, 5 Dec 2024 14:54:27 +0100 -Subject: [PATCH 67/82] net: sparx5: fix default value of monitor ports - -When doing port mirroring, the physical port to send the frame to, is -written to the FRMC_PORT_VAL field of the QFWD_FRAME_COPY_CFG register. -This field is 7 bits wide on sparx5 and 6 bits wide on lan969x, and has -a default value of 65 and 30, respectively (the number of front ports). - -On mirror deletion, we set the default value of the monitor port to -65 for this field, in case no more ports exists for the mirror. Needless -to say, this will not fit the 6 bits on lan969x. - -Fix this by correctly using the n_ports constant instead. - -Fixes: 3f9e46347a46 ("net: sparx5: use SPX5_CONST for constants which already have a symbol") -Signed-off-by: Daniel Machon -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c -@@ -12,7 +12,6 @@ - #define SPX5_MIRROR_DISABLED 0 - #define SPX5_MIRROR_EGRESS 1 - #define SPX5_MIRROR_INGRESS 2 --#define SPX5_MIRROR_MONITOR_PORT_DEFAULT 65 - #define SPX5_QFWD_MP_OFFSET 9 /* Mirror port offset in the QFWD register */ - - /* Convert from bool ingress/egress to mirror direction */ -@@ -200,7 +199,7 @@ void sparx5_mirror_del(struct sparx5_mal - - sparx5_mirror_monitor_set(sparx5, - mirror_idx, -- SPX5_MIRROR_MONITOR_PORT_DEFAULT); -+ sparx5->data->consts->n_ports); - } - - void sparx5_mirror_stats(struct sparx5_mall_entry *entry, diff --git a/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch b/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch deleted file mode 100644 index 75cf4d1f41..0000000000 --- a/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 4bb216d318259f940eb2248dc91ade01edea1cc4 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:40 +0100 -Subject: [PATCH 68/82] net: sparx5: do some preparation work - -The sparx5_port_init() does initial configuration of a variety of -different features and options for each port. Some are shared for all -types of devices, some are not. As it is now, common configuration is -done after configuration of low-speed devices. This will not work when -adding RGMII support in a subsequent patch. - -In preparation for lan969x RGMII support, move a block of code, that -configures 2g5 devices, down. This ensures that the configuration common -to all devices is done before configuration of 2g5, 5g, 10g and 25g -devices. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-1-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_port.c | 36 +++++++++---------- - 1 file changed, 18 insertions(+), 18 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -1067,24 +1067,6 @@ int sparx5_port_init(struct sparx5 *spar - if (err) - return err; - -- /* Configure MAC vlan awareness */ -- err = sparx5_port_max_tags_set(sparx5, port); -- if (err) -- return err; -- -- /* Set Max Length */ -- spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), -- DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, -- sparx5, -- DEV2G5_MAC_MAXLEN_CFG(port->portno)); -- -- /* 1G/2G5: Signal Detect configuration */ -- spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | -- DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | -- DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), -- sparx5, -- DEV2G5_PCS1G_SD_CFG(port->portno)); -- - /* Set Pause WM hysteresis */ - spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | - QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | -@@ -1108,6 +1090,24 @@ int sparx5_port_init(struct sparx5 *spar - ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, - sparx5, ANA_CL_FILTER_CTRL(port->portno)); - -+ /* Configure MAC vlan awareness */ -+ err = sparx5_port_max_tags_set(sparx5, port); -+ if (err) -+ return err; -+ -+ /* Set Max Length */ -+ spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), -+ DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, -+ sparx5, -+ DEV2G5_MAC_MAXLEN_CFG(port->portno)); -+ -+ /* 1G/2G5: Signal Detect configuration */ -+ spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | -+ DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | -+ DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), -+ sparx5, -+ DEV2G5_PCS1G_SD_CFG(port->portno)); -+ - if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || - conf->portmode == PHY_INTERFACE_MODE_SGMII) { - err = sparx5_serdes_set(sparx5, port, conf); diff --git a/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch b/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch deleted file mode 100644 index e332d6e045..0000000000 --- a/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch +++ /dev/null @@ -1,82 +0,0 @@ -From b479572cf00c11a1b57c2fc61e2d2e0f4fb84c4e Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:41 +0100 -Subject: [PATCH 69/82] net: sparx5: add function for RGMII port check - -The lan969x device contains two RGMII port interfaces, sitting at port -28 and 29. Add function: is_port_rgmii() to the match data ops, that -checks if a given port is an RGMII port or not. For Sparx5, this -function always returns false. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-2-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c | 1 + - drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h | 5 +++++ - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 1 + - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 1 + - drivers/net/ethernet/microchip/sparx5/sparx5_port.h | 5 +++++ - 5 files changed, 13 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -329,6 +329,7 @@ static const struct sparx5_ops lan969x_o - .is_port_5g = &lan969x_port_is_5g, - .is_port_10g = &lan969x_port_is_10g, - .is_port_25g = &lan969x_port_is_25g, -+ .is_port_rgmii = &lan969x_port_is_rgmii, - .get_port_dev_index = &lan969x_port_dev_mapping, - .get_port_dev_bit = &lan969x_get_dev_mode_bit, - .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -@@ -59,6 +59,11 @@ static inline bool lan969x_port_is_25g(i - return false; - } - -+static inline bool lan969x_port_is_rgmii(int portno) -+{ -+ return portno == 28 || portno == 29; -+} -+ - /* lan969x_calendar.c */ - int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -1072,6 +1072,7 @@ static const struct sparx5_ops sparx5_op - .is_port_5g = &sparx5_port_is_5g, - .is_port_10g = &sparx5_port_is_10g, - .is_port_25g = &sparx5_port_is_25g, -+ .is_port_rgmii = &sparx5_port_is_rgmii, - .get_port_dev_index = &sparx5_port_dev_mapping, - .get_port_dev_bit = &sparx5_port_dev_mapping, - .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -313,6 +313,7 @@ struct sparx5_ops { - bool (*is_port_5g)(int portno); - bool (*is_port_10g)(int portno); - bool (*is_port_25g)(int portno); -+ bool (*is_port_rgmii)(int portno); - u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); - u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); - u32 (*get_hsch_max_group_rate)(int grp); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h -@@ -40,6 +40,11 @@ static inline bool sparx5_port_is_25g(in - return portno >= 56 && portno <= 63; - } - -+static inline bool sparx5_port_is_rgmii(int portno) -+{ -+ return false; -+} -+ - static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) - { - const struct sparx5_ops *ops = sparx5->data->ops; diff --git a/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch b/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch deleted file mode 100644 index 9928c62303..0000000000 --- a/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 1593303768bbf218cb4a7a8f9a9b1968e5e63aa7 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:42 +0100 -Subject: [PATCH 70/82] net: sparx5: use is_port_rgmii() throughout - -Now that we can check if a given port is an RGMII port, use it in the -following cases: - - - To set RGMII PHY modes for RGMII port devices. - - - To avoid checking for a SerDes node in the devicetree, when the port - is an RGMII port. - - - To bail out of sparx5_port_init() when the common configuration is - done. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-3-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_main.c | 28 +++++++++++++------ - .../ethernet/microchip/sparx5/sparx5_port.c | 3 ++ - 2 files changed, 23 insertions(+), 8 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -313,10 +313,13 @@ static int sparx5_create_port(struct spa - struct initial_port_config *config) - { - struct sparx5_port *spx5_port; -+ const struct sparx5_ops *ops; - struct net_device *ndev; - struct phylink *phylink; - int err; - -+ ops = sparx5->data->ops; -+ - ndev = sparx5_create_netdev(sparx5, config->portno); - if (IS_ERR(ndev)) { - dev_err(sparx5->dev, "Could not create net device: %02u\n", -@@ -357,6 +360,9 @@ static int sparx5_create_port(struct spa - MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | - MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; - -+ if (ops->is_port_rgmii(spx5_port->portno)) -+ phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces); -+ - __set_bit(PHY_INTERFACE_MODE_SGMII, - spx5_port->phylink_config.supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_QSGMII, -@@ -830,6 +836,7 @@ static int mchp_sparx5_probe(struct plat - struct initial_port_config *configs, *config; - struct device_node *np = pdev->dev.of_node; - struct device_node *ports, *portnp; -+ const struct sparx5_ops *ops; - struct reset_control *reset; - struct sparx5 *sparx5; - int idx = 0, err = 0; -@@ -851,6 +858,7 @@ static int mchp_sparx5_probe(struct plat - return -EINVAL; - - regs = sparx5->data->regs; -+ ops = sparx5->data->ops; - - /* Do switch core reset if available */ - reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); -@@ -880,7 +888,7 @@ static int mchp_sparx5_probe(struct plat - - for_each_available_child_of_node(ports, portnp) { - struct sparx5_port_config *conf; -- struct phy *serdes; -+ struct phy *serdes = NULL; - u32 portno; - - err = of_property_read_u32(portnp, "reg", &portno); -@@ -910,13 +918,17 @@ static int mchp_sparx5_probe(struct plat - conf->sd_sgpio = ~0; - else - sparx5->sd_sgpio_remapping = true; -- serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); -- if (IS_ERR(serdes)) { -- err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), -- "port %u: missing serdes\n", -- portno); -- of_node_put(portnp); -- goto cleanup_config; -+ /* There is no SerDes node for RGMII ports. */ -+ if (!ops->is_port_rgmii(portno)) { -+ serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); -+ if (IS_ERR(serdes)) { -+ err = dev_err_probe(sparx5->dev, -+ PTR_ERR(serdes), -+ "port %u: missing serdes\n", -+ portno); -+ of_node_put(portnp); -+ goto cleanup_config; -+ } - } - config->portno = portno; - config->node = portnp; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -1090,6 +1090,9 @@ int sparx5_port_init(struct sparx5 *spar - ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, - sparx5, ANA_CL_FILTER_CTRL(port->portno)); - -+ if (ops->is_port_rgmii(port->portno)) -+ return 0; /* RGMII device - nothing more to configure */ -+ - /* Configure MAC vlan awareness */ - err = sparx5_port_max_tags_set(sparx5, port); - if (err) diff --git a/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch b/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch deleted file mode 100644 index 44a6f08a07..0000000000 --- a/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 013f57f35a14c04449ff58684d9986bb663375d7 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:43 +0100 -Subject: [PATCH 71/82] net: sparx5: skip low-speed configuration when port is - RGMII - -When doing a port config, we configure low-speed port devices, among -other things. We have a check to ensure, that the device is indeed a -low-speed device, an not a high-speed device. Add an additional check, -to ensure that the device is not an RGMII device. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-4-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -994,6 +994,7 @@ int sparx5_port_config(struct sparx5 *sp - struct sparx5_port *port, - struct sparx5_port_config *conf) - { -+ bool rgmii = phy_interface_mode_is_rgmii(conf->phy_mode); - bool high_speed_dev = sparx5_is_baser(conf->portmode); - const struct sparx5_ops *ops = sparx5->data->ops; - int err, urgency, stop_wm; -@@ -1003,7 +1004,7 @@ int sparx5_port_config(struct sparx5 *sp - return err; - - /* high speed device is already configured */ -- if (!high_speed_dev) -+ if (!rgmii && !high_speed_dev) - sparx5_port_config_low_set(sparx5, port, conf); - - /* Configure flow control */ diff --git a/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch b/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch deleted file mode 100644 index 381a31c186..0000000000 --- a/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch +++ /dev/null @@ -1,40 +0,0 @@ -From be45d246122e57af37216fa846439205ed2cf671 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:44 +0100 -Subject: [PATCH 72/82] net: sparx5: only return PCS for modes that require it - -The RGMII ports have no PCS to configure. Make sure we only return the -PCS for port modes that require it. - -Reviewed-by: Russell King (Oracle) -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-5-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/sparx5/sparx5_phylink.c | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c -@@ -32,7 +32,19 @@ sparx5_phylink_mac_select_pcs(struct phy - { - struct sparx5_port *port = netdev_priv(to_net_dev(config->dev)); - -- return &port->phylink_pcs; -+ /* Return the PCS for all the modes that require it. */ -+ switch (interface) { -+ case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_QSGMII: -+ case PHY_INTERFACE_MODE_1000BASEX: -+ case PHY_INTERFACE_MODE_2500BASEX: -+ case PHY_INTERFACE_MODE_5GBASER: -+ case PHY_INTERFACE_MODE_10GBASER: -+ case PHY_INTERFACE_MODE_25GBASER: -+ return &port->phylink_pcs; -+ default: -+ return NULL; -+ } - } - - static void sparx5_phylink_mac_config(struct phylink_config *config, diff --git a/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch b/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch deleted file mode 100644 index bb814fc6ae..0000000000 --- a/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 3695a85ef07bf3ac9a2ecc458a4c199b5ab755b1 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:45 +0100 -Subject: [PATCH 73/82] net: sparx5: verify RGMII speeds - -When doing a port config, we verify the port speed against the PHY mode -and supported speeds of that PHY mode. Add checks for the four RGMII phy -modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-6-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -257,6 +257,15 @@ static int sparx5_port_verify_speed(stru - conf->speed != SPEED_25000)) - return sparx5_port_error(port, conf, SPX5_PERR_SPEED); - break; -+ case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ if (conf->speed != SPEED_1000 && -+ conf->speed != SPEED_100 && -+ conf->speed != SPEED_10) -+ return sparx5_port_error(port, conf, SPX5_PERR_SPEED); -+ break; - default: - return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); - } diff --git a/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch b/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch deleted file mode 100644 index 0283b04b30..0000000000 --- a/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 49fbe4bb20903f595b1c22b51aa6a9d3bf0ed5de Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:46 +0100 -Subject: [PATCH 74/82] net: lan969x: add RGMII registers - -Configuration of RGMII is done by configuring the GPIO and clock -settings in the HSIOWRAP target, and configuring the RGMII port devices -in the DEVRGMII target. Both targets contain registers replicated for -the number of RGMII port devices, which is two. - -Add said targets and register macros required to configure RGMII. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-7-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../microchip/sparx5/lan969x/lan969x.c | 3 + - .../microchip/sparx5/sparx5_main_regs.h | 145 ++++++++++++++++++ - 2 files changed, 148 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -90,9 +90,12 @@ static const struct sparx5_main_io_resou - { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ - { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ - { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ -+ { TARGET_DEVRGMII, 0x30e4000, 1 }, /* 0xe30e4000 */ -+ { TARGET_DEVRGMII + 1, 0x30e8000, 1 }, /* 0xe30e8000 */ - { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ - { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ - { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ -+ { TARGET_HSIO_WRAP, 0x3408000, 1 }, /* 0xe3408000 */ - }; - - static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -@@ -37,6 +37,7 @@ enum sparx5_target { - TARGET_FDMA = 117, - TARGET_GCB = 118, - TARGET_HSCH = 119, -+ TARGET_HSIO_WRAP = 120, - TARGET_LRN = 122, - TARGET_PCEP = 129, - TARGET_PCS10G_BR = 132, -@@ -54,6 +55,7 @@ enum sparx5_target { - TARGET_VCAP_SUPER = 326, - TARGET_VOP = 327, - TARGET_XQS = 331, -+ TARGET_DEVRGMII = 392, - NUM_TARGETS = 517 - }; - -@@ -5367,6 +5369,69 @@ extern const struct sparx5_regs *regs; - #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ - FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) - -+/* LAN969X ONLY */ -+/* HSIOWRAP:XMII_CFG:XMII_CFG */ -+#define HSIO_WRAP_XMII_CFG(g) \ -+ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4) -+ -+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1) -+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) -+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\ -+ FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) -+ -+/* LAN969X ONLY */ -+/* HSIOWRAP:XMII_CFG:RGMII_CFG */ -+#define HSIO_WRAP_RGMII_CFG(g) \ -+ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4) -+ -+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2) -+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) -+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\ -+ FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) -+ -+#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1) -+#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) -+#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\ -+ FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) -+ -+#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST BIT(0) -+#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) -+#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\ -+ FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) -+ -+/* LAN969X ONLY */ -+/* HSIOWRAP:XMII_CFG:DLL_CFG */ -+#define HSIO_WRAP_DLL_CFG(g, r) \ -+ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4) -+ -+#define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19) -+#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x) -+#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\ -+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x) -+ -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18) -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\ -+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) -+ -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15) -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) -+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\ -+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) -+ -+#define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0) -+#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\ -+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x) -+#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\ -+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x) -+ - /* LRN:COMMON:COMMON_ACCESS_CTRL */ - #define LRN_COMMON_ACCESS_CTRL \ - __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) -@@ -8110,4 +8175,84 @@ extern const struct sparx5_regs *regs; - #define XQS_CNT(g) \ - __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) - -+/* LAN969X ONLY */ -+/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ -+#define DEVRGMII_DEV_RST_CTRL(t) \ -+ __REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4) -+ -+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) -+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\ -+ FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) -+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\ -+ FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) -+ -+/* LAN969X ONLY */ -+/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ -+#define DEVRGMII_MAC_ENA_CFG(t) \ -+ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4) -+ -+#define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4) -+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) -+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) -+ -+#define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0) -+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) -+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) -+ -+/* LAN969X ONLY */ -+/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ -+#define DEVRGMII_MAC_TAGS_CFG(t) \ -+ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4) -+ -+#define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) -+#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) -+#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) -+ -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) -+ -+#define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) -+#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) -+#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) -+ -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) -+#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) -+ -+/* LAN969X ONLY */ -+/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ -+#define DEVRGMII_MAC_IFG_CFG(t) \ -+ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4) -+ -+#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) -+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) -+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) -+ -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) -+ -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) -+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) -+ - #endif /* _SPARX5_MAIN_REGS_H_ */ diff --git a/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch b/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch deleted file mode 100644 index af196f44cc..0000000000 --- a/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch +++ /dev/null @@ -1,320 +0,0 @@ -From d5444792be67ed47aed76685e62b0f0c29c5e22c Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 20 Dec 2024 14:48:47 +0100 -Subject: [PATCH 75/82] net: lan969x: add RGMII implementation - -The lan969x switch device includes two RGMII port interfaces (port 28 -and 29) supporting data speeds of 1 Gbps, 100 Mbps and 10 Mbps. MAC -level delays are configurable through the HSIO_WRAP target, by choosing -a phase shift selector, corresponding to a certain time delay in nano -seconds. - -Add new file: lan969x_rgmii.c that contains the implementation for -configuring the RGMII port devices. MAC level delays are configured -using the "{rx,tx}-internal-delay-ps" properties. These properties must -be specified independently of the phy-mode. If missing, or set to zero, -the MAC will not apply any delay. - -Reviewed-by: Steen Hegelund -Reviewed-by: Horatiu Vultur -Tested-by: Robert Marko -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-8-fa8ba5dff732@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/microchip/sparx5/Makefile | 3 +- - .../microchip/sparx5/lan969x/lan969x.c | 1 + - .../microchip/sparx5/lan969x/lan969x.h | 5 + - .../microchip/sparx5/lan969x/lan969x_rgmii.c | 224 ++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_main.h | 2 + - .../ethernet/microchip/sparx5/sparx5_port.c | 6 + - 6 files changed, 240 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c - ---- a/drivers/net/ethernet/microchip/sparx5/Makefile -+++ b/drivers/net/ethernet/microchip/sparx5/Makefile -@@ -20,7 +20,8 @@ sparx5-switch-$(CONFIG_LAN969X_SWITCH) + - lan969x/lan969x.o \ - lan969x/lan969x_calendar.o \ - lan969x/lan969x_vcap_ag_api.o \ -- lan969x/lan969x_vcap_impl.o -+ lan969x/lan969x_vcap_impl.o \ -+ lan969x/lan969x_rgmii.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -340,6 +340,7 @@ static const struct sparx5_ops lan969x_o - .set_port_mux = &lan969x_port_mux_set, - .ptp_irq_handler = &lan969x_ptp_irq_handler, - .dsm_calendar_calc = &lan969x_dsm_calendar_calc, -+ .port_config_rgmii = &lan969x_port_config_rgmii, - }; - - const struct sparx5_match_data lan969x_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -@@ -67,4 +67,9 @@ static inline bool lan969x_port_is_rgmii - /* lan969x_calendar.c */ - int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data); -+ -+/* lan969x_rgmii.c */ -+int lan969x_port_config_rgmii(struct sparx5_port *port, -+ struct sparx5_port_config *conf); -+ - #endif ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c -@@ -0,0 +1,224 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "lan969x.h" -+ -+/* Tx clock selectors */ -+#define LAN969X_RGMII_TX_CLK_SEL_125MHZ 1 /* 1000Mbps */ -+#define LAN969X_RGMII_TX_CLK_SEL_25MHZ 2 /* 100Mbps */ -+#define LAN969X_RGMII_TX_CLK_SEL_2M5MHZ 3 /* 10Mbps */ -+ -+/* Port speed selectors */ -+#define LAN969X_RGMII_SPEED_SEL_10 0 /* Select 10Mbps speed */ -+#define LAN969X_RGMII_SPEED_SEL_100 1 /* Select 100Mbps speed */ -+#define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */ -+ -+/* Clock delay selectors */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3 /* Phase shift 77deg */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4 /* Phase shift 90deg */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5 /* Phase shift 112deg */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6 /* Phase shift 135deg */ -+#define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7 /* Phase shift 147deg */ -+ -+#define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */ -+#define LAN969X_RGMII_IFG_TX 4 /* TX Inter Frame Gap value */ -+#define LAN969X_RGMII_IFG_RX1 5 /* RX1 Inter Frame Gap value */ -+#define LAN969X_RGMII_IFG_RX2 1 /* RX2 Inter Frame Gap value */ -+ -+#define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX) -+ -+/* Get the tx clock selector based on the port speed. */ -+static int lan969x_rgmii_get_clk_sel(int speed) -+{ -+ return (speed == SPEED_10 ? LAN969X_RGMII_TX_CLK_SEL_2M5MHZ : -+ speed == SPEED_100 ? LAN969X_RGMII_TX_CLK_SEL_25MHZ : -+ LAN969X_RGMII_TX_CLK_SEL_125MHZ); -+} -+ -+/* Get the port speed selector based on the port speed. */ -+static int lan969x_rgmii_get_speed_sel(int speed) -+{ -+ return (speed == SPEED_10 ? LAN969X_RGMII_SPEED_SEL_10 : -+ speed == SPEED_100 ? LAN969X_RGMII_SPEED_SEL_100 : -+ LAN969X_RGMII_SPEED_SEL_1000); -+} -+ -+/* Get the clock delay selector based on the clock delay in picoseconds. */ -+static int lan969x_rgmii_get_clk_delay_sel(struct sparx5_port *port, -+ u32 delay_ps, u32 *clk_delay_sel) -+{ -+ switch (delay_ps) { -+ case 0: -+ /* Hardware default selector. */ -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS; -+ break; -+ case 1000: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS; -+ break; -+ case 1700: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS; -+ break; -+ case 2000: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS; -+ break; -+ case 2500: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS; -+ break; -+ case 3000: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS; -+ break; -+ case 3300: -+ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS; -+ break; -+ default: -+ dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* Configure the RGMII tx clock frequency. */ -+static void lan969x_rgmii_tx_clk_config(struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed); -+ u32 idx = RGMII_PORT_IDX(port); -+ -+ /* Take the RGMII clock domain out of reset and set tx clock -+ * frequency. -+ */ -+ spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) | -+ HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(0) | -+ HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(0), -+ HSIO_WRAP_RGMII_CFG_TX_CLK_CFG | -+ HSIO_WRAP_RGMII_CFG_RGMII_TX_RST | -+ HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, -+ port->sparx5, HSIO_WRAP_RGMII_CFG(idx)); -+} -+ -+/* Configure the RGMII port device. */ -+static void lan969x_rgmii_port_device_config(struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ u32 dtag, dotag, etype, speed_sel, idx = RGMII_PORT_IDX(port); -+ -+ speed_sel = lan969x_rgmii_get_speed_sel(conf->speed); -+ -+ etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? -+ port->custom_etype : -+ port->vlan_type == SPX5_VLAN_PORT_TYPE_C ? -+ ETH_P_8021Q : ETH_P_8021AD); -+ -+ dtag = port->max_vlan_tags == SPX5_PORT_MAX_TAGS_TWO; -+ dotag = port->max_vlan_tags != SPX5_PORT_MAX_TAGS_NONE; -+ -+ /* Enable the MAC. */ -+ spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) | -+ DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1), -+ port->sparx5, DEVRGMII_MAC_ENA_CFG(idx)); -+ -+ /* Configure the Inter Frame Gap. */ -+ spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) | -+ DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(LAN969X_RGMII_IFG_RX1) | -+ DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(LAN969X_RGMII_IFG_RX2), -+ port->sparx5, DEVRGMII_MAC_IFG_CFG(idx)); -+ -+ /* Configure port data rate. */ -+ spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(speed_sel), -+ port->sparx5, DEVRGMII_DEV_RST_CTRL(idx)); -+ -+ /* Configure VLAN awareness. */ -+ spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) | -+ DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(dtag) | -+ DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(dotag) | -+ DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(dotag), -+ port->sparx5, -+ DEVRGMII_MAC_TAGS_CFG(idx)); -+} -+ -+/* Configure the RGMII delay lines in the MAC. -+ * -+ * We use the rx-internal-delay-ps" and "tx-internal-delay-ps" properties to -+ * configure the rx and tx delays for the MAC. If these properties are missing -+ * or set to zero, the MAC will not apply any delay. -+ * -+ * The PHY side delays are determined by the PHY mode -+ * (e.g. PHY_INTERFACE_MODE_RGMII_{ID, RXID, TXID}), and ignored by the MAC side -+ * entirely. -+ */ -+static int lan969x_rgmii_delay_config(struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ u32 tx_clk_sel, rx_clk_sel, tx_delay_ps = 0, rx_delay_ps = 0; -+ u32 idx = RGMII_PORT_IDX(port); -+ int err; -+ -+ of_property_read_u32(port->of_node, "rx-internal-delay-ps", -+ &rx_delay_ps); -+ -+ of_property_read_u32(port->of_node, "tx-internal-delay-ps", -+ &tx_delay_ps); -+ -+ err = lan969x_rgmii_get_clk_delay_sel(port, rx_delay_ps, &rx_clk_sel); -+ if (err) -+ return err; -+ -+ err = lan969x_rgmii_get_clk_delay_sel(port, tx_delay_ps, &tx_clk_sel); -+ if (err) -+ return err; -+ -+ /* Configure rx delay. */ -+ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | -+ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!rx_delay_ps) | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(rx_clk_sel), -+ HSIO_WRAP_DLL_CFG_DLL_RST | -+ HSIO_WRAP_DLL_CFG_DLL_ENA | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, -+ port->sparx5, HSIO_WRAP_DLL_CFG(idx, 0)); -+ -+ /* Configure tx delay. */ -+ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | -+ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!tx_delay_ps) | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(tx_clk_sel), -+ HSIO_WRAP_DLL_CFG_DLL_RST | -+ HSIO_WRAP_DLL_CFG_DLL_ENA | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | -+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, -+ port->sparx5, HSIO_WRAP_DLL_CFG(idx, 1)); -+ -+ return 0; -+} -+ -+/* Configure GPIO's to be used as RGMII interface. */ -+static void lan969x_rgmii_gpio_config(struct sparx5_port *port) -+{ -+ u32 idx = RGMII_PORT_IDX(port); -+ -+ /* Enable the RGMII on the GPIOs. */ -+ spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), port->sparx5, -+ HSIO_WRAP_XMII_CFG(!idx)); -+} -+ -+int lan969x_port_config_rgmii(struct sparx5_port *port, -+ struct sparx5_port_config *conf) -+{ -+ int err; -+ -+ err = lan969x_rgmii_delay_config(port, conf); -+ if (err) -+ return err; -+ -+ lan969x_rgmii_tx_clk_config(port, conf); -+ lan969x_rgmii_gpio_config(port); -+ lan969x_rgmii_port_device_config(port, conf); -+ -+ return 0; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -324,6 +324,8 @@ struct sparx5_ops { - irqreturn_t (*ptp_irq_handler)(int irq, void *args); - int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data); -+ int (*port_config_rgmii)(struct sparx5_port *port, -+ struct sparx5_port_config *conf); - }; - - struct sparx5_main_io_resource { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c -@@ -1012,6 +1012,12 @@ int sparx5_port_config(struct sparx5 *sp - if (err) - return err; - -+ if (rgmii) { -+ err = ops->port_config_rgmii(port, conf); -+ if (err) -+ return err; -+ } -+ - /* high speed device is already configured */ - if (!rgmii && !high_speed_dev) - sparx5_port_config_low_set(sparx5, port, conf); diff --git a/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch b/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch deleted file mode 100644 index bb016ffb6b..0000000000 --- a/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f7c39a31269c23cba94476b0fa99f547cde1a4ed Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 13 Jan 2025 20:36:05 +0100 -Subject: [PATCH 76/82] net: sparx5: enable FDMA on lan969x - -In a previous series, we made sure that FDMA was not initialized and -started on lan969x. Now that we are going to support it, undo that -change. In addition, make sure the chip ID check is only applicable on -Sparx5, as this is a check that is only relevant on this platform. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-1-c468f02fd623@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -784,8 +784,9 @@ static int sparx5_start(struct sparx5 *s - - /* Start Frame DMA with fallback to register based INJ/XTR */ - err = -ENXIO; -- if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { -- if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) -+ if (sparx5->fdma_irq >= 0) { -+ if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0 || -+ !is_sparx5(sparx5)) - err = devm_request_irq(sparx5->dev, - sparx5->fdma_irq, - sparx5_fdma_handler, diff --git a/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch b/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch deleted file mode 100644 index a9195e3e68..0000000000 --- a/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch +++ /dev/null @@ -1,135 +0,0 @@ -From c4448d20c23c45be9d59b40f3892e134d2e3f155 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 13 Jan 2025 20:36:06 +0100 -Subject: [PATCH 77/82] net: sparx5: split sparx5_fdma_{start(),stop()} - -The two functions: sparx5_fdma_{start(),stop()} are responsible for a -number of things, namely: allocation and initialization of FDMA buffers, -activation FDMA channels in hardware and activation of the NAPI -instance. - -This patch splits the buffer allocation and initialization into init and -deinit functions, and the channel and NAPI activation into start and -stop functions. This serves two purposes: 1) the start() and stop() -functions can be reused for lan969x and 2) prepares for future MTU -change support, where we must be able to stop and start the FDMA -channels and NAPI instance, without free'ing and reallocating the FDMA -buffers. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-2-c468f02fd623@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_fdma.c | 44 ++++++++++++++----- - .../ethernet/microchip/sparx5/sparx5_main.c | 7 ++- - .../ethernet/microchip/sparx5/sparx5_main.h | 2 + - 3 files changed, 41 insertions(+), 12 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -260,10 +260,6 @@ static int sparx5_fdma_rx_alloc(struct s - fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), - FDMA_DCB_STATUS_INTR); - -- netif_napi_add_weight(rx->ndev, &rx->napi, sparx5_fdma_napi_callback, -- FDMA_WEIGHT); -- napi_enable(&rx->napi); -- sparx5_fdma_rx_activate(sparx5, rx); - return 0; - } - -@@ -410,7 +406,7 @@ static void sparx5_fdma_injection_mode(s - } - } - --int sparx5_fdma_start(struct sparx5 *sparx5) -+int sparx5_fdma_init(struct sparx5 *sparx5) - { - int err; - -@@ -443,24 +439,52 @@ int sparx5_fdma_start(struct sparx5 *spa - return err; - } - -+int sparx5_fdma_deinit(struct sparx5 *sparx5) -+{ -+ sparx5_fdma_stop(sparx5); -+ fdma_free_phys(&sparx5->rx.fdma); -+ fdma_free_phys(&sparx5->tx.fdma); -+ -+ return 0; -+} -+ - static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5) - { - return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); - } - -+int sparx5_fdma_start(struct sparx5 *sparx5) -+{ -+ struct sparx5_rx *rx = &sparx5->rx; -+ -+ netif_napi_add_weight(rx->ndev, -+ &rx->napi, -+ sparx5_fdma_napi_callback, -+ FDMA_WEIGHT); -+ -+ napi_enable(&rx->napi); -+ -+ sparx5_fdma_rx_activate(sparx5, rx); -+ -+ return 0; -+} -+ - int sparx5_fdma_stop(struct sparx5 *sparx5) - { -+ struct sparx5_rx *rx = &sparx5->rx; -+ struct sparx5_tx *tx = &sparx5->tx; - u32 val; - -- napi_disable(&sparx5->rx.napi); -+ napi_disable(&rx->napi); -+ - /* Stop the fdma and channel interrupts */ -- sparx5_fdma_rx_deactivate(sparx5, &sparx5->rx); -- sparx5_fdma_tx_deactivate(sparx5, &sparx5->tx); -+ sparx5_fdma_rx_deactivate(sparx5, rx); -+ sparx5_fdma_tx_deactivate(sparx5, tx); -+ - /* Wait for the RX channel to stop */ - read_poll_timeout(sparx5_fdma_port_ctrl, val, - FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(val) == 0, - 500, 10000, 0, sparx5); -- fdma_free_phys(&sparx5->rx.fdma); -- fdma_free_phys(&sparx5->tx.fdma); -+ - return 0; - } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -792,8 +792,11 @@ static int sparx5_start(struct sparx5 *s - sparx5_fdma_handler, - 0, - "sparx5-fdma", sparx5); -- if (!err) -- err = sparx5_fdma_start(sparx5); -+ if (!err) { -+ err = sparx5_fdma_init(sparx5); -+ if (!err) -+ sparx5_fdma_start(sparx5); -+ } - if (err) - sparx5->fdma_irq = -ENXIO; - } else { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -436,6 +436,8 @@ int sparx5_manual_injection_mode(struct - void sparx5_port_inj_timer_setup(struct sparx5_port *port); - - /* sparx5_fdma.c */ -+int sparx5_fdma_init(struct sparx5 *sparx5); -+int sparx5_fdma_deinit(struct sparx5 *sparx5); - int sparx5_fdma_start(struct sparx5 *sparx5); - int sparx5_fdma_stop(struct sparx5 *sparx5); - int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); diff --git a/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch b/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch deleted file mode 100644 index 86ff7b7d88..0000000000 --- a/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 9415d95bb109ed59b4487ff2a90ef8309a8e7e06 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 13 Jan 2025 20:36:07 +0100 -Subject: [PATCH 78/82] net: sparx5: activate FDMA tx in start() - -The function sparx5_fdma_tx_activate() is responsible for configuring -the TX FDMA instance and activating the channel. TX activation has -previously been done in the xmit() function, when the first frame is -transmitted. Now that we have separate functions for starting and -stopping the FDMA, it seems reasonable to move the TX activation to the -start function. This change has no implications on the functionality. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-3-c468f02fd623@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 11 ++++------- - 1 file changed, 4 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -217,7 +217,6 @@ int sparx5_fdma_xmit(struct sparx5 *spar - { - struct sparx5_tx *tx = &sparx5->tx; - struct fdma *fdma = &tx->fdma; -- static bool first_time = true; - void *virt_addr; - - fdma_dcb_advance(fdma); -@@ -238,12 +237,8 @@ int sparx5_fdma_xmit(struct sparx5 *spar - FDMA_DCB_STATUS_BLOCKO(0) | - FDMA_DCB_STATUS_BLOCKL(skb->len + IFH_LEN * 4 + 4)); - -- if (first_time) { -- sparx5_fdma_tx_activate(sparx5, tx); -- first_time = false; -- } else { -- sparx5_fdma_reload(sparx5, fdma); -- } -+ sparx5_fdma_reload(sparx5, fdma); -+ - return NETDEV_TX_OK; - } - -@@ -456,6 +451,7 @@ static u32 sparx5_fdma_port_ctrl(struct - int sparx5_fdma_start(struct sparx5 *sparx5) - { - struct sparx5_rx *rx = &sparx5->rx; -+ struct sparx5_tx *tx = &sparx5->tx; - - netif_napi_add_weight(rx->ndev, - &rx->napi, -@@ -465,6 +461,7 @@ int sparx5_fdma_start(struct sparx5 *spa - napi_enable(&rx->napi); - - sparx5_fdma_rx_activate(sparx5, rx); -+ sparx5_fdma_tx_activate(sparx5, tx); - - return 0; - } diff --git a/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch b/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch deleted file mode 100644 index ea55d8564b..0000000000 --- a/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch +++ /dev/null @@ -1,146 +0,0 @@ -From 72d96799c80510f1bec9d72e6b4f9b5273069201 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 13 Jan 2025 20:36:08 +0100 -Subject: [PATCH 79/82] net: sparx5: ops out certain FDMA functions - -We are going to implement the RX and TX paths a bit differently on -lan969x and therefore need to introduce new ops for FDMA functions: -init, deinit, xmit and poll. Assign the Sparx5 equivalents for these and -update the code throughout. Also add a 'struct net_device' argument to -the xmit() function, as we will be needing that for lan969x. - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-4-c468f02fd623@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 8 +++++--- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 9 +++++++-- - drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 9 ++++++++- - drivers/net/ethernet/microchip/sparx5/sparx5_packet.c | 5 ++++- - 4 files changed, 24 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -183,7 +183,7 @@ static bool sparx5_fdma_rx_get_frame(str - return true; - } - --static int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight) -+int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight) - { - struct sparx5_rx *rx = container_of(napi, struct sparx5_rx, napi); - struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); -@@ -213,7 +213,8 @@ static int sparx5_fdma_napi_callback(str - return counter; - } - --int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb) -+int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, -+ struct net_device *dev) - { - struct sparx5_tx *tx = &sparx5->tx; - struct fdma *fdma = &tx->fdma; -@@ -450,12 +451,13 @@ static u32 sparx5_fdma_port_ctrl(struct - - int sparx5_fdma_start(struct sparx5 *sparx5) - { -+ const struct sparx5_ops *ops = sparx5->data->ops; - struct sparx5_rx *rx = &sparx5->rx; - struct sparx5_tx *tx = &sparx5->tx; - - netif_napi_add_weight(rx->ndev, - &rx->napi, -- sparx5_fdma_napi_callback, -+ ops->fdma_poll, - FDMA_WEIGHT); - - napi_enable(&rx->napi); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -793,7 +793,7 @@ static int sparx5_start(struct sparx5 *s - 0, - "sparx5-fdma", sparx5); - if (!err) { -- err = sparx5_fdma_init(sparx5); -+ err = ops->fdma_init(sparx5); - if (!err) - sparx5_fdma_start(sparx5); - } -@@ -1030,6 +1030,7 @@ cleanup_pnode: - static void mchp_sparx5_remove(struct platform_device *pdev) - { - struct sparx5 *sparx5 = platform_get_drvdata(pdev); -+ const struct sparx5_ops *ops = sparx5->data->ops; - - debugfs_remove_recursive(sparx5->debugfs_root); - if (sparx5->xtr_irq) { -@@ -1041,7 +1042,7 @@ static void mchp_sparx5_remove(struct pl - sparx5->fdma_irq = -ENXIO; - } - sparx5_ptp_deinit(sparx5); -- sparx5_fdma_stop(sparx5); -+ ops->fdma_deinit(sparx5); - sparx5_cleanup_ports(sparx5); - sparx5_vcap_destroy(sparx5); - /* Unregister netdevs */ -@@ -1096,6 +1097,10 @@ static const struct sparx5_ops sparx5_op - .set_port_mux = &sparx5_port_mux_set, - .ptp_irq_handler = &sparx5_ptp_irq_handler, - .dsm_calendar_calc = &sparx5_dsm_calendar_calc, -+ .fdma_init = &sparx5_fdma_init, -+ .fdma_deinit = &sparx5_fdma_deinit, -+ .fdma_poll = &sparx5_fdma_napi_callback, -+ .fdma_xmit = &sparx5_fdma_xmit, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -326,6 +326,11 @@ struct sparx5_ops { - struct sparx5_calendar_data *data); - int (*port_config_rgmii)(struct sparx5_port *port, - struct sparx5_port_config *conf); -+ int (*fdma_init)(struct sparx5 *sparx5); -+ int (*fdma_deinit)(struct sparx5 *sparx5); -+ int (*fdma_poll)(struct napi_struct *napi, int weight); -+ int (*fdma_xmit)(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, -+ struct net_device *dev); - }; - - struct sparx5_main_io_resource { -@@ -440,7 +445,9 @@ int sparx5_fdma_init(struct sparx5 *spar - int sparx5_fdma_deinit(struct sparx5 *sparx5); - int sparx5_fdma_start(struct sparx5 *sparx5); - int sparx5_fdma_stop(struct sparx5 *sparx5); --int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); -+int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight); -+int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, -+ struct net_device *dev); - irqreturn_t sparx5_fdma_handler(int irq, void *args); - - /* sparx5_mactable.c */ ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -232,9 +232,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct - struct net_device_stats *stats = &dev->stats; - struct sparx5_port *port = netdev_priv(dev); - struct sparx5 *sparx5 = port->sparx5; -+ const struct sparx5_ops *ops; - u32 ifh[IFH_LEN]; - netdev_tx_t ret; - -+ ops = sparx5->data->ops; -+ - memset(ifh, 0, IFH_LEN * 4); - sparx5_set_port_ifh(sparx5, ifh, port->portno); - -@@ -254,7 +257,7 @@ netdev_tx_t sparx5_port_xmit_impl(struct - skb_tx_timestamp(skb); - spin_lock(&sparx5->tx_lock); - if (sparx5->fdma_irq > 0) -- ret = sparx5_fdma_xmit(sparx5, ifh, skb); -+ ret = ops->fdma_xmit(sparx5, ifh, skb, dev); - else - ret = sparx5_inject(sparx5, ifh, skb, dev); - spin_unlock(&sparx5->tx_lock); diff --git a/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch b/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch deleted file mode 100644 index b3ebf47a2d..0000000000 --- a/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch +++ /dev/null @@ -1,609 +0,0 @@ -From 181ee0484e3a966b02ddb238c2abfdbecebafe97 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Mon, 13 Jan 2025 20:36:09 +0100 -Subject: [PATCH 80/82] net: lan969x: add FDMA implementation - -The lan969x switch device supports manual frame injection and extraction -to and from the switch core, using a number of injection and extraction -queues. This technique is currently supported, but delivers poor -performance compared to Frame DMA (FDMA). - -This lan969x implementation of FDMA, hooks into the existing FDMA for -Sparx5, but requires its own RX and TX handling, as lan969x does not -support the same native cache coherency that Sparx5 does. Effectively, -this means that we are going to use the DMA mapping API for mapping and -unmapping TX buffers. The RX loop will utilize the page pool API for -efficient RX handling. Other than that, the implementation is largely -the same, and utilizes the FDMA library for DCB and DB handling. - -Some numbers: - -Manual injection/extraction (before this series): - -// iperf3 -c 1.0.1.1 - -[ ID] Interval Transfer Bitrate -[ 5] 0.00-10.02 sec 345 MBytes 289 Mbits/sec sender -[ 5] 0.00-10.06 sec 345 MBytes 288 Mbits/sec receiver - -FDMA (after this series): - -// iperf3 -c 1.0.1.1 - -[ ID] Interval Transfer Bitrate -[ 5] 0.00-10.03 sec 1.10 GBytes 940 Mbits/sec sender -[ 5] 0.00-10.07 sec 1.10 GBytes 936 Mbits/sec receiver - -Reviewed-by: Steen Hegelund -Signed-off-by: Daniel Machon -Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-5-c468f02fd623@microchip.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/Kconfig | 1 + - .../net/ethernet/microchip/sparx5/Makefile | 3 +- - .../microchip/sparx5/lan969x/lan969x.c | 4 + - .../microchip/sparx5/lan969x/lan969x.h | 7 + - .../microchip/sparx5/lan969x/lan969x_fdma.c | 406 ++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_fdma.c | 7 +- - .../ethernet/microchip/sparx5/sparx5_main.h | 21 +- - .../ethernet/microchip/sparx5/sparx5_packet.c | 6 + - 8 files changed, 448 insertions(+), 7 deletions(-) - create mode 100644 drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c - ---- a/drivers/net/ethernet/microchip/sparx5/Kconfig -+++ b/drivers/net/ethernet/microchip/sparx5/Kconfig -@@ -28,5 +28,6 @@ config SPARX5_DCB - config LAN969X_SWITCH - bool "Lan969x switch driver" - depends on SPARX5_SWITCH -+ select PAGE_POOL - help - This driver supports the lan969x family of network switch devices. ---- a/drivers/net/ethernet/microchip/sparx5/Makefile -+++ b/drivers/net/ethernet/microchip/sparx5/Makefile -@@ -21,7 +21,8 @@ sparx5-switch-$(CONFIG_LAN969X_SWITCH) + - lan969x/lan969x_calendar.o \ - lan969x/lan969x_vcap_ag_api.o \ - lan969x/lan969x_vcap_impl.o \ -- lan969x/lan969x_rgmii.o -+ lan969x/lan969x_rgmii.o \ -+ lan969x/lan969x_fdma.o - - # Provide include files - ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -341,6 +341,10 @@ static const struct sparx5_ops lan969x_o - .ptp_irq_handler = &lan969x_ptp_irq_handler, - .dsm_calendar_calc = &lan969x_dsm_calendar_calc, - .port_config_rgmii = &lan969x_port_config_rgmii, -+ .fdma_init = &lan969x_fdma_init, -+ .fdma_deinit = &lan969x_fdma_deinit, -+ .fdma_poll = &lan969x_fdma_napi_poll, -+ .fdma_xmit = &lan969x_fdma_xmit, - }; - - const struct sparx5_match_data lan969x_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -@@ -72,4 +72,11 @@ int lan969x_dsm_calendar_calc(struct spa - int lan969x_port_config_rgmii(struct sparx5_port *port, - struct sparx5_port_config *conf); - -+/* lan969x_fdma.c */ -+int lan969x_fdma_init(struct sparx5 *sparx5); -+int lan969x_fdma_deinit(struct sparx5 *sparx5); -+int lan969x_fdma_napi_poll(struct napi_struct *napi, int weight); -+int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, -+ struct net_device *dev); -+ - #endif ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c -@@ -0,0 +1,406 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip lan969x Switch driver -+ * -+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. -+ */ -+#include -+ -+#include "../sparx5_main.h" -+#include "../sparx5_main_regs.h" -+#include "../sparx5_port.h" -+ -+#include "fdma_api.h" -+#include "lan969x.h" -+ -+#define FDMA_PRIV(fdma) ((struct sparx5 *)((fdma)->priv)) -+ -+static int lan969x_fdma_tx_dataptr_cb(struct fdma *fdma, int dcb, int db, -+ u64 *dataptr) -+{ -+ *dataptr = FDMA_PRIV(fdma)->tx.dbs[dcb].dma_addr; -+ -+ return 0; -+} -+ -+static int lan969x_fdma_rx_dataptr_cb(struct fdma *fdma, int dcb, int db, -+ u64 *dataptr) -+{ -+ struct sparx5_rx *rx = &FDMA_PRIV(fdma)->rx; -+ struct page *page; -+ -+ page = page_pool_dev_alloc_pages(rx->page_pool); -+ if (unlikely(!page)) -+ return -ENOMEM; -+ -+ rx->page[dcb][db] = page; -+ -+ *dataptr = page_pool_get_dma_addr(page); -+ -+ return 0; -+} -+ -+static int lan969x_fdma_get_next_dcb(struct sparx5_tx *tx) -+{ -+ struct fdma *fdma = &tx->fdma; -+ -+ for (int i = 0; i < fdma->n_dcbs; ++i) -+ if (!tx->dbs[i].used && !fdma_is_last(fdma, &fdma->dcbs[i])) -+ return i; -+ -+ return -ENOSPC; -+} -+ -+static void lan969x_fdma_tx_clear_buf(struct sparx5 *sparx5, int weight) -+{ -+ struct fdma *fdma = &sparx5->tx.fdma; -+ struct sparx5_tx_buf *db; -+ unsigned long flags; -+ int i; -+ -+ spin_lock_irqsave(&sparx5->tx_lock, flags); -+ -+ for (i = 0; i < fdma->n_dcbs; ++i) { -+ db = &sparx5->tx.dbs[i]; -+ -+ if (!db->used) -+ continue; -+ -+ if (!fdma_db_is_done(fdma_db_get(fdma, i, 0))) -+ continue; -+ -+ db->dev->stats.tx_bytes += db->skb->len; -+ db->dev->stats.tx_packets++; -+ sparx5->tx.packets++; -+ -+ dma_unmap_single(sparx5->dev, -+ db->dma_addr, -+ db->skb->len, -+ DMA_TO_DEVICE); -+ -+ if (!db->ptp) -+ napi_consume_skb(db->skb, weight); -+ -+ db->used = false; -+ } -+ -+ spin_unlock_irqrestore(&sparx5->tx_lock, flags); -+} -+ -+static void lan969x_fdma_free_pages(struct sparx5_rx *rx) -+{ -+ struct fdma *fdma = &rx->fdma; -+ -+ for (int i = 0; i < fdma->n_dcbs; ++i) { -+ for (int j = 0; j < fdma->n_dbs; ++j) -+ page_pool_put_full_page(rx->page_pool, -+ rx->page[i][j], false); -+ } -+} -+ -+static struct sk_buff *lan969x_fdma_rx_get_frame(struct sparx5 *sparx5, -+ struct sparx5_rx *rx) -+{ -+ const struct sparx5_consts *consts = sparx5->data->consts; -+ struct fdma *fdma = &rx->fdma; -+ struct sparx5_port *port; -+ struct frame_info fi; -+ struct sk_buff *skb; -+ struct fdma_db *db; -+ struct page *page; -+ -+ db = &fdma->dcbs[fdma->dcb_index].db[fdma->db_index]; -+ page = rx->page[fdma->dcb_index][fdma->db_index]; -+ -+ sparx5_ifh_parse(sparx5, page_address(page), &fi); -+ port = fi.src_port < consts->n_ports ? sparx5->ports[fi.src_port] : -+ NULL; -+ if (WARN_ON(!port)) -+ goto free_page; -+ -+ skb = build_skb(page_address(page), fdma->db_size); -+ if (unlikely(!skb)) -+ goto free_page; -+ -+ skb_mark_for_recycle(skb); -+ skb_put(skb, fdma_db_len_get(db)); -+ skb_pull(skb, IFH_LEN * sizeof(u32)); -+ -+ skb->dev = port->ndev; -+ -+ if (likely(!(skb->dev->features & NETIF_F_RXFCS))) -+ skb_trim(skb, skb->len - ETH_FCS_LEN); -+ -+ sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp); -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ -+ if (test_bit(port->portno, sparx5->bridge_mask)) -+ skb->offload_fwd_mark = 1; -+ -+ skb->dev->stats.rx_bytes += skb->len; -+ skb->dev->stats.rx_packets++; -+ -+ return skb; -+ -+free_page: -+ page_pool_recycle_direct(rx->page_pool, page); -+ -+ return NULL; -+} -+ -+static int lan969x_fdma_rx_alloc(struct sparx5 *sparx5) -+{ -+ struct sparx5_rx *rx = &sparx5->rx; -+ struct fdma *fdma = &rx->fdma; -+ int err; -+ -+ struct page_pool_params pp_params = { -+ .order = 0, -+ .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, -+ .pool_size = fdma->n_dcbs * fdma->n_dbs, -+ .nid = NUMA_NO_NODE, -+ .dev = sparx5->dev, -+ .dma_dir = DMA_FROM_DEVICE, -+ .offset = 0, -+ .max_len = fdma->db_size - -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), -+ }; -+ -+ rx->page_pool = page_pool_create(&pp_params); -+ if (IS_ERR(rx->page_pool)) -+ return PTR_ERR(rx->page_pool); -+ -+ err = fdma_alloc_coherent(sparx5->dev, fdma); -+ if (err) -+ return err; -+ -+ fdma_dcbs_init(fdma, -+ FDMA_DCB_INFO_DATAL(fdma->db_size), -+ FDMA_DCB_STATUS_INTR); -+ -+ return 0; -+} -+ -+static int lan969x_fdma_tx_alloc(struct sparx5 *sparx5) -+{ -+ struct sparx5_tx *tx = &sparx5->tx; -+ struct fdma *fdma = &tx->fdma; -+ int err; -+ -+ tx->dbs = kcalloc(fdma->n_dcbs, -+ sizeof(struct sparx5_tx_buf), -+ GFP_KERNEL); -+ if (!tx->dbs) -+ return -ENOMEM; -+ -+ err = fdma_alloc_coherent(sparx5->dev, fdma); -+ if (err) { -+ kfree(tx->dbs); -+ return err; -+ } -+ -+ fdma_dcbs_init(fdma, -+ FDMA_DCB_INFO_DATAL(fdma->db_size), -+ FDMA_DCB_STATUS_DONE); -+ -+ return 0; -+} -+ -+static void lan969x_fdma_rx_init(struct sparx5 *sparx5) -+{ -+ struct fdma *fdma = &sparx5->rx.fdma; -+ -+ fdma->channel_id = FDMA_XTR_CHANNEL; -+ fdma->n_dcbs = FDMA_DCB_MAX; -+ fdma->n_dbs = 1; -+ fdma->priv = sparx5; -+ fdma->size = fdma_get_size(fdma); -+ fdma->db_size = PAGE_SIZE; -+ fdma->ops.dataptr_cb = &lan969x_fdma_rx_dataptr_cb; -+ fdma->ops.nextptr_cb = &fdma_nextptr_cb; -+ -+ /* Fetch a netdev for SKB and NAPI use, any will do */ -+ for (int idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { -+ struct sparx5_port *port = sparx5->ports[idx]; -+ -+ if (port && port->ndev) { -+ sparx5->rx.ndev = port->ndev; -+ break; -+ } -+ } -+} -+ -+static void lan969x_fdma_tx_init(struct sparx5 *sparx5) -+{ -+ struct fdma *fdma = &sparx5->tx.fdma; -+ -+ fdma->channel_id = FDMA_INJ_CHANNEL; -+ fdma->n_dcbs = FDMA_DCB_MAX; -+ fdma->n_dbs = 1; -+ fdma->priv = sparx5; -+ fdma->size = fdma_get_size(fdma); -+ fdma->db_size = PAGE_SIZE; -+ fdma->ops.dataptr_cb = &lan969x_fdma_tx_dataptr_cb; -+ fdma->ops.nextptr_cb = &fdma_nextptr_cb; -+} -+ -+int lan969x_fdma_napi_poll(struct napi_struct *napi, int weight) -+{ -+ struct sparx5_rx *rx = container_of(napi, struct sparx5_rx, napi); -+ struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); -+ int old_dcb, dcb_reload, counter = 0; -+ struct fdma *fdma = &rx->fdma; -+ struct sk_buff *skb; -+ -+ dcb_reload = fdma->dcb_index; -+ -+ lan969x_fdma_tx_clear_buf(sparx5, weight); -+ -+ /* Process RX data */ -+ while (counter < weight) { -+ if (!fdma_has_frames(fdma)) -+ break; -+ -+ skb = lan969x_fdma_rx_get_frame(sparx5, rx); -+ if (!skb) -+ break; -+ -+ napi_gro_receive(&rx->napi, skb); -+ -+ fdma_db_advance(fdma); -+ counter++; -+ /* Check if the DCB can be reused */ -+ if (fdma_dcb_is_reusable(fdma)) -+ continue; -+ -+ fdma_db_reset(fdma); -+ fdma_dcb_advance(fdma); -+ } -+ -+ /* Allocate new pages and map them */ -+ while (dcb_reload != fdma->dcb_index) { -+ old_dcb = dcb_reload; -+ dcb_reload++; -+ /* n_dcbs must be a power of 2 */ -+ dcb_reload &= fdma->n_dcbs - 1; -+ -+ fdma_dcb_add(fdma, -+ old_dcb, -+ FDMA_DCB_INFO_DATAL(fdma->db_size), -+ FDMA_DCB_STATUS_INTR); -+ -+ sparx5_fdma_reload(sparx5, fdma); -+ } -+ -+ if (counter < weight && napi_complete_done(napi, counter)) -+ spx5_wr(0xff, sparx5, FDMA_INTR_DB_ENA); -+ -+ return counter; -+} -+ -+int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ int next_dcb, needed_headroom, needed_tailroom, err; -+ struct sparx5_tx *tx = &sparx5->tx; -+ struct fdma *fdma = &tx->fdma; -+ struct sparx5_tx_buf *db_buf; -+ u64 status; -+ -+ next_dcb = lan969x_fdma_get_next_dcb(tx); -+ if (next_dcb < 0) -+ return -EBUSY; -+ -+ needed_headroom = max_t(int, IFH_LEN * 4 - skb_headroom(skb), 0); -+ needed_tailroom = max_t(int, ETH_FCS_LEN - skb_tailroom(skb), 0); -+ if (needed_headroom || needed_tailroom || skb_header_cloned(skb)) { -+ err = pskb_expand_head(skb, needed_headroom, needed_tailroom, -+ GFP_ATOMIC); -+ if (unlikely(err)) -+ return err; -+ } -+ -+ skb_push(skb, IFH_LEN * 4); -+ memcpy(skb->data, ifh, IFH_LEN * 4); -+ skb_put(skb, ETH_FCS_LEN); -+ -+ db_buf = &tx->dbs[next_dcb]; -+ db_buf->dma_addr = dma_map_single(sparx5->dev, -+ skb->data, -+ skb->len, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(sparx5->dev, db_buf->dma_addr)) -+ return -ENOMEM; -+ -+ db_buf->dev = dev; -+ db_buf->skb = skb; -+ db_buf->ptp = false; -+ db_buf->used = true; -+ -+ if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && -+ SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP) -+ db_buf->ptp = true; -+ -+ status = FDMA_DCB_STATUS_SOF | -+ FDMA_DCB_STATUS_EOF | -+ FDMA_DCB_STATUS_BLOCKO(0) | -+ FDMA_DCB_STATUS_BLOCKL(skb->len) | -+ FDMA_DCB_STATUS_INTR; -+ -+ fdma_dcb_advance(fdma); -+ fdma_dcb_add(fdma, next_dcb, 0, status); -+ -+ sparx5_fdma_reload(sparx5, fdma); -+ -+ return NETDEV_TX_OK; -+} -+ -+int lan969x_fdma_init(struct sparx5 *sparx5) -+{ -+ struct sparx5_rx *rx = &sparx5->rx; -+ int err; -+ -+ lan969x_fdma_rx_init(sparx5); -+ lan969x_fdma_tx_init(sparx5); -+ sparx5_fdma_injection_mode(sparx5); -+ -+ err = dma_set_mask_and_coherent(sparx5->dev, DMA_BIT_MASK(64)); -+ if (err) { -+ dev_err(sparx5->dev, "Failed to set 64-bit FDMA mask"); -+ return err; -+ } -+ -+ err = lan969x_fdma_rx_alloc(sparx5); -+ if (err) { -+ dev_err(sparx5->dev, "Failed to allocate RX buffers: %d\n", -+ err); -+ return err; -+ } -+ -+ err = lan969x_fdma_tx_alloc(sparx5); -+ if (err) { -+ fdma_free_coherent(sparx5->dev, &rx->fdma); -+ dev_err(sparx5->dev, "Failed to allocate TX buffers: %d\n", -+ err); -+ return err; -+ } -+ -+ /* Reset FDMA state */ -+ spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); -+ spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); -+ -+ return err; -+} -+ -+int lan969x_fdma_deinit(struct sparx5 *sparx5) -+{ -+ struct sparx5_rx *rx = &sparx5->rx; -+ struct sparx5_tx *tx = &sparx5->tx; -+ -+ sparx5_fdma_stop(sparx5); -+ fdma_free_coherent(sparx5->dev, &tx->fdma); -+ fdma_free_coherent(sparx5->dev, &rx->fdma); -+ lan969x_fdma_free_pages(rx); -+ page_pool_destroy(rx->page_pool); -+ -+ return 0; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -18,9 +18,6 @@ - #include "sparx5_main.h" - #include "sparx5_port.h" - --#define FDMA_XTR_CHANNEL 6 --#define FDMA_INJ_CHANNEL 0 -- - #define FDMA_XTR_BUFFER_SIZE 2048 - #define FDMA_WEIGHT 4 - -@@ -133,7 +130,7 @@ static void sparx5_fdma_tx_deactivate(st - sparx5, FDMA_CH_ACTIVATE); - } - --static void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) -+void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) - { - /* Reload the RX channel */ - spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD); -@@ -340,7 +337,7 @@ irqreturn_t sparx5_fdma_handler(int irq, - return IRQ_HANDLED; - } - --static void sparx5_fdma_injection_mode(struct sparx5 *sparx5) -+void sparx5_fdma_injection_mode(struct sparx5 *sparx5) - { - const int byte_swap = 1; - int portno; ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -112,6 +112,8 @@ enum sparx5_feature { - #define XTR_QUEUE 0 - #define INJ_QUEUE 0 - -+#define FDMA_XTR_CHANNEL 6 -+#define FDMA_INJ_CHANNEL 0 - #define FDMA_DCB_MAX 64 - #define FDMA_RX_DCB_MAX_DBS 15 - #define FDMA_TX_DCB_MAX_DBS 1 -@@ -157,11 +159,25 @@ struct sparx5_calendar_data { - */ - struct sparx5_rx { - struct fdma fdma; -- struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; -+ struct page_pool *page_pool; -+ union { -+ struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; -+ struct page *page[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; -+ }; - dma_addr_t dma; - struct napi_struct napi; - struct net_device *ndev; - u64 packets; -+ u8 page_order; -+}; -+ -+/* Used to store information about TX buffers. */ -+struct sparx5_tx_buf { -+ struct net_device *dev; -+ struct sk_buff *skb; -+ dma_addr_t dma_addr; -+ bool used; -+ bool ptp; - }; - - /* Frame DMA transmit state: -@@ -169,6 +185,7 @@ struct sparx5_rx { - */ - struct sparx5_tx { - struct fdma fdma; -+ struct sparx5_tx_buf *dbs; - u64 packets; - u64 dropped; - }; -@@ -449,6 +466,8 @@ int sparx5_fdma_napi_callback(struct nap - int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, - struct net_device *dev); - irqreturn_t sparx5_fdma_handler(int irq, void *args); -+void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma); -+void sparx5_fdma_injection_mode(struct sparx5 *sparx5); - - /* sparx5_mactable.c */ - void sparx5_mact_pull_work(struct work_struct *work); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c -@@ -267,6 +267,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct - if (ret < 0) - goto drop; - -+ if (!is_sparx5(sparx5)) -+ /* When lan969x and TX_OK, stats and SKB consumption is handled -+ * in the TX completion loop, so dont go any further. -+ */ -+ return NETDEV_TX_OK; -+ - stats->tx_bytes += skb->len; - stats->tx_packets++; - sparx5->tx.packets++; diff --git a/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch b/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch deleted file mode 100644 index 6e5ddff63a..0000000000 --- a/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch +++ /dev/null @@ -1,62 +0,0 @@ -From b3461fb971b0db9158653bdbcb99d1327f7eeff0 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Wed, 17 Sep 2025 13:49:43 +0200 -Subject: [PATCH 82/82] net: sparx5/lan969x: Add support for ethtool pause - parameters - -Implement get_pauseparam() and set_pauseparam() ethtool operations for -Sparx5 ports. This allows users to query and configure IEEE 802.3x -pause frame settings via: - -ethtool -a ethX -ethtool -A ethX rx on|off tx on|off autoneg on|off - -The driver delegates pause parameter handling to phylink through -phylink_ethtool_get_pauseparam() and phylink_ethtool_set_pauseparam(). - -The underlying configuration of pause frame generation and reception is -already implemented in the driver; this patch only wires it up to the -standard ethtool interface, making the feature accessible to userspace. - -Signed-off-by: Daniel Machon -Reviewed-by: Russell King (Oracle) -Link: https://patch.msgid.link/20250917-802-3x-pause-v1-1-3d1565a68a96@microchip.com -Signed-off-by: Jakub Kicinski ---- - .../ethernet/microchip/sparx5/sparx5_ethtool.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c -@@ -1212,6 +1212,22 @@ static int sparx5_get_ts_info(struct net - return 0; - } - -+static void sparx5_get_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *pause) -+{ -+ struct sparx5_port *port = netdev_priv(dev); -+ -+ phylink_ethtool_get_pauseparam(port->phylink, pause); -+} -+ -+static int sparx5_set_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *pause) -+{ -+ struct sparx5_port *port = netdev_priv(dev); -+ -+ return phylink_ethtool_set_pauseparam(port->phylink, pause); -+} -+ - const struct ethtool_ops sparx5_ethtool_ops = { - .get_sset_count = sparx5_get_sset_count, - .get_strings = sparx5_get_sset_strings, -@@ -1224,6 +1240,8 @@ const struct ethtool_ops sparx5_ethtool_ - .get_eth_ctrl_stats = sparx5_get_eth_mac_ctrl_stats, - .get_rmon_stats = sparx5_get_eth_rmon_stats, - .get_ts_info = sparx5_get_ts_info, -+ .get_pauseparam = sparx5_get_pauseparam, -+ .set_pauseparam = sparx5_set_pauseparam, - }; - - int sparx_stats_init(struct sparx5 *sparx5) diff --git a/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch b/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch deleted file mode 100644 index e005bb8f98..0000000000 --- a/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch +++ /dev/null @@ -1,1175 +0,0 @@ -From 388e3b42aa5a15009457e250d623b2ee74bf4f92 Mon Sep 17 00:00:00 2001 -From: Tudor Ambarus -Date: Thu, 28 Nov 2024 18:43:15 +0100 -Subject: [PATCH 098/112] spi: atmel-quadspi: Add support for sama7g5 QSPI -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The sama7g5 QSPI controller uses dedicated clocks for the -QSPI Controller Interface and the QSPI Controller Core, and -requires synchronization before accessing registers or bit -fields. - -QSPI_SR.SYNCBSY must be zero before accessing any of the bits: -QSPI_CR.QSPIEN, QSPI_CR.QSPIDIS, QSPI_CR.SRFRSH, QSPI_CR.SWRST, -QSPI_CR.UPDCFG, QSPI_CR.STTFR, QSPI_CR.RTOUT, QSPI_CR.LASTXFER. - -Also, the QSPI controller core configuration can be updated by -writing the QSPI_CR.UPDCFG bit to ‘1’. This is needed by the -following registers: QSPI_MR, QSPI_SCR, QSPI_IAR, QSPI_WICR, -QSPI_IFR, QSPI_RICR, QSPI_SMR, QSPI_SKR,QSPI_REFRESH, QSPI_WRACNT -QSPI_PCALCFG. - -The Octal SPI supports frequencies up to 200 MHZ DDR. The need -for output impedance calibration arises. To avoid the degradation -of the signal quality, a PAD calibration cell is used to adjust -the output impedance to the driven I/Os. - -The transmission flow requires different sequences for setting -the configuration and for the actual transfer, than what is in -the sama5d2 and sam9x60 versions of the IP. Different interrupts -are handled. aq->ops->set_cfg() and aq->ops->transfer() are -introduced to help differentiating the flows. - -Tested single and octal SPI mode with mx66lm1g45g. - -Signed-off-by: Tudor Ambarus -Link: https://lore.kernel.org/r/20211214133404.121739-1-tudor.ambarus@microchip.com -[varshini.rajendran@microchip.com: Fixed conflicts and ported to 6.1.4] -Signed-off-by: Varshini Rajendran -[ csokas.bence: Forward-port to master and address feedback ] -Signed-off-by: Csókás, Bence -Link: https://patch.msgid.link/20241128174316.3209354-3-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 816 +++++++++++++++++++++++++++++++++++- - 1 file changed, 798 insertions(+), 18 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -11,11 +11,15 @@ - * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. - */ - -+#include - #include - #include -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -34,6 +38,7 @@ - #define QSPI_IDR 0x0018 /* Interrupt Disable Register */ - #define QSPI_IMR 0x001c /* Interrupt Mask Register */ - #define QSPI_SCR 0x0020 /* Serial Clock Register */ -+#define QSPI_SR2 0x0024 /* SAMA7G5 Status Register */ - - #define QSPI_IAR 0x0030 /* Instruction Address Register */ - #define QSPI_ICR 0x0034 /* Instruction Code Register */ -@@ -44,16 +49,32 @@ - #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ - #define QSPI_SKR 0x0044 /* Scrambling Key Register */ - -+#define QSPI_REFRESH 0x0050 /* Refresh Register */ -+#define QSPI_WRACNT 0x0054 /* Write Access Counter Register */ -+#define QSPI_DLLCFG 0x0058 /* DLL Configuration Register */ -+#define QSPI_PCALCFG 0x005C /* Pad Calibration Configuration Register */ -+#define QSPI_PCALBP 0x0060 /* Pad Calibration Bypass Register */ -+#define QSPI_TOUT 0x0064 /* Timeout Register */ -+ - #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */ - #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */ - - #define QSPI_VERSION 0x00FC /* Version Register */ - -+#define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 -+#define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 - - /* Bitfields in QSPI_CR (Control Register) */ - #define QSPI_CR_QSPIEN BIT(0) - #define QSPI_CR_QSPIDIS BIT(1) -+#define QSPI_CR_DLLON BIT(2) -+#define QSPI_CR_DLLOFF BIT(3) -+#define QSPI_CR_STPCAL BIT(4) -+#define QSPI_CR_SRFRSH BIT(5) - #define QSPI_CR_SWRST BIT(7) -+#define QSPI_CR_UPDCFG BIT(8) -+#define QSPI_CR_STTFR BIT(9) -+#define QSPI_CR_RTOUT BIT(10) - #define QSPI_CR_LASTXFER BIT(24) - - /* Bitfields in QSPI_MR (Mode Register) */ -@@ -61,12 +82,14 @@ - #define QSPI_MR_LLB BIT(1) - #define QSPI_MR_WDRBT BIT(2) - #define QSPI_MR_SMRM BIT(3) -+#define QSPI_MR_DQSDLYEN BIT(3) - #define QSPI_MR_CSMODE_MASK GENMASK(5, 4) - #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) - #define QSPI_MR_CSMODE_LASTXFER (1 << 4) - #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) - #define QSPI_MR_NBBITS_MASK GENMASK(11, 8) - #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) -+#define QSPI_MR_OENSD BIT(15) - #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) - #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) - #define QSPI_MR_DLYCS_MASK GENMASK(31, 24) -@@ -80,6 +103,13 @@ - #define QSPI_SR_CSR BIT(8) - #define QSPI_SR_CSS BIT(9) - #define QSPI_SR_INSTRE BIT(10) -+#define QSPI_SR_LWRA BIT(11) -+#define QSPI_SR_QITF BIT(12) -+#define QSPI_SR_QITR BIT(13) -+#define QSPI_SR_CSFA BIT(14) -+#define QSPI_SR_CSRA BIT(15) -+#define QSPI_SR_RFRSHD BIT(16) -+#define QSPI_SR_TOUT BIT(17) - #define QSPI_SR_QSPIENS BIT(24) - - #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) -@@ -92,9 +122,22 @@ - #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) - #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) - -+/* Bitfields in QSPI_SR2 (SAMA7G5 Status Register) */ -+#define QSPI_SR2_SYNCBSY BIT(0) -+#define QSPI_SR2_QSPIENS BIT(1) -+#define QSPI_SR2_CSS BIT(2) -+#define QSPI_SR2_RBUSY BIT(3) -+#define QSPI_SR2_HIDLE BIT(4) -+#define QSPI_SR2_DLOCK BIT(5) -+#define QSPI_SR2_CALBSY BIT(6) -+ -+/* Bitfields in QSPI_IAR (Instruction Address Register) */ -+#define QSPI_IAR_ADDR GENMASK(31, 0) -+ - /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ - #define QSPI_ICR_INST_MASK GENMASK(7, 0) - #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) -+#define QSPI_ICR_INST_MASK_SAMA7G5 GENMASK(15, 0) - #define QSPI_ICR_OPT_MASK GENMASK(23, 16) - #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK) - -@@ -107,6 +150,9 @@ - #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0) - #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0) - #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0) -+#define QSPI_IFR_WIDTH_OCT_OUTPUT (7 << 0) -+#define QSPI_IFR_WIDTH_OCT_IO (8 << 0) -+#define QSPI_IFR_WIDTH_OCT_CMD (9 << 0) - #define QSPI_IFR_INSTEN BIT(4) - #define QSPI_IFR_ADDREN BIT(5) - #define QSPI_IFR_OPTEN BIT(6) -@@ -117,19 +163,60 @@ - #define QSPI_IFR_OPTL_4BIT (2 << 8) - #define QSPI_IFR_OPTL_8BIT (3 << 8) - #define QSPI_IFR_ADDRL BIT(10) -+#define QSPI_IFR_ADDRL_SAMA7G5 GENMASK(11, 10) - #define QSPI_IFR_TFRTYP_MEM BIT(12) - #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) - #define QSPI_IFR_CRM BIT(14) -+#define QSPI_IFR_DDREN BIT(15) - #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) - #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) -+#define QSPI_IFR_END BIT(22) -+#define QSPI_IFR_SMRM BIT(23) - #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */ -+#define QSPI_IFR_DQSEN BIT(25) -+#define QSPI_IFR_DDRCMDEN BIT(26) -+#define QSPI_IFR_HFWBEN BIT(27) -+#define QSPI_IFR_PROTTYP GENMASK(29, 28) -+#define QSPI_IFR_PROTTYP_STD_SPI 0 -+#define QSPI_IFR_PROTTYP_TWIN_QUAD 1 -+#define QSPI_IFR_PROTTYP_OCTAFLASH 2 -+#define QSPI_IFR_PROTTYP_HYPERFLASH 3 - - /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ - #define QSPI_SMR_SCREN BIT(0) - #define QSPI_SMR_RVDIS BIT(1) -+#define QSPI_SMR_SCRKL BIT(2) -+ -+/* Bitfields in QSPI_REFRESH (Refresh Register) */ -+#define QSPI_REFRESH_DELAY_COUNTER GENMASK(31, 0) -+ -+/* Bitfields in QSPI_WRACNT (Write Access Counter Register) */ -+#define QSPI_WRACNT_NBWRA GENMASK(31, 0) -+ -+/* Bitfields in QSPI_DLLCFG (DLL Configuration Register) */ -+#define QSPI_DLLCFG_RANGE BIT(0) -+ -+/* Bitfields in QSPI_PCALCFG (DLL Pad Calibration Configuration Register) */ -+#define QSPI_PCALCFG_AAON BIT(0) -+#define QSPI_PCALCFG_DAPCAL BIT(1) -+#define QSPI_PCALCFG_DIFFPM BIT(2) -+#define QSPI_PCALCFG_CLKDIV GENMASK(6, 4) -+#define QSPI_PCALCFG_CALCNT GENMASK(16, 8) -+#define QSPI_PCALCFG_CALP GENMASK(27, 24) -+#define QSPI_PCALCFG_CALN GENMASK(31, 28) -+ -+/* Bitfields in QSPI_PCALBP (DLL Pad Calibration Bypass Register) */ -+#define QSPI_PCALBP_BPEN BIT(0) -+#define QSPI_PCALBP_CALPBP GENMASK(11, 8) -+#define QSPI_PCALBP_CALNBP GENMASK(19, 16) -+ -+/* Bitfields in QSPI_TOUT (Timeout Register) */ -+#define QSPI_TOUT_TCNTM GENMASK(15, 0) - - /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ - #define QSPI_WPMR_WPEN BIT(0) -+#define QSPI_WPMR_WPITEN BIT(1) -+#define QSPI_WPMR_WPCREN BIT(2) - #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8) - #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK) - -@@ -139,10 +226,42 @@ - #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) - - #define ATMEL_QSPI_TIMEOUT 1000 /* ms */ -+#define ATMEL_QSPI_SYNC_TIMEOUT 300 /* ms */ -+#define QSPI_DLLCFG_THRESHOLD_FREQ 90000000U -+#define QSPI_CALIB_TIME 2000 /* 2 us */ -+ -+/* Use PIO for small transfers. */ -+#define ATMEL_QSPI_DMA_MIN_BYTES 16 -+/** -+ * struct atmel_qspi_pcal - Pad Calibration Clock Division -+ * @pclk_rate: peripheral clock rate. -+ * @pclkdiv: calibration clock division. The clock applied to the calibration -+ * cell is divided by pclkdiv + 1. -+ */ -+struct atmel_qspi_pcal { -+ u32 pclk_rate; -+ u8 pclk_div; -+}; -+ -+#define ATMEL_QSPI_PCAL_ARRAY_SIZE 8 -+static const struct atmel_qspi_pcal pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE] = { -+ {25000000, 0}, -+ {50000000, 1}, -+ {75000000, 2}, -+ {100000000, 3}, -+ {125000000, 4}, -+ {150000000, 5}, -+ {175000000, 6}, -+ {200000000, 7}, -+}; - - struct atmel_qspi_caps { -+ u32 max_speed_hz; - bool has_qspick; -+ bool has_gclk; - bool has_ricr; -+ bool octal; -+ bool has_dma; - }; - - struct atmel_qspi_ops; -@@ -152,6 +271,7 @@ struct atmel_qspi { - void __iomem *mem; - struct clk *pclk; - struct clk *qspick; -+ struct clk *gclk; - struct platform_device *pdev; - const struct atmel_qspi_caps *caps; - const struct atmel_qspi_ops *ops; -@@ -160,7 +280,12 @@ struct atmel_qspi { - u32 irq_mask; - u32 mr; - u32 scr; -+ u32 slave_max_speed_hz; - struct completion cmd_completion; -+ struct completion dma_completion; -+ dma_addr_t mmap_phys_base; -+ struct dma_chan *rx_chan; -+ struct dma_chan *tx_chan; - }; - - struct atmel_qspi_ops { -@@ -187,6 +312,19 @@ static const struct atmel_qspi_mode atme - { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, - }; - -+static const struct atmel_qspi_mode atmel_qspi_sama7g5_modes[] = { -+ { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, -+ { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, -+ { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, -+ { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, -+ { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, -+ { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, -+ { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, -+ { 1, 1, 8, QSPI_IFR_WIDTH_OCT_OUTPUT }, -+ { 1, 8, 8, QSPI_IFR_WIDTH_OCT_IO }, -+ { 8, 8, 8, QSPI_IFR_WIDTH_OCT_CMD }, -+}; -+ - #ifdef VERBOSE_DEBUG - static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) - { -@@ -209,6 +347,8 @@ static const char *atmel_qspi_reg_name(u - return "IMR"; - case QSPI_SCR: - return "SCR"; -+ case QSPI_SR2: -+ return "SR2"; - case QSPI_IAR: - return "IAR"; - case QSPI_ICR: -@@ -221,6 +361,18 @@ static const char *atmel_qspi_reg_name(u - return "SMR"; - case QSPI_SKR: - return "SKR"; -+ case QSPI_REFRESH: -+ return "REFRESH"; -+ case QSPI_WRACNT: -+ return "WRACNT"; -+ case QSPI_DLLCFG: -+ return "DLLCFG"; -+ case QSPI_PCALCFG: -+ return "PCALCFG"; -+ case QSPI_PCALBP: -+ return "PCALBP"; -+ case QSPI_TOUT: -+ return "TOUT"; - case QSPI_WPMR: - return "WPMR"; - case QSPI_WPSR: -@@ -288,12 +440,31 @@ static int atmel_qspi_find_mode(const st - return -EOPNOTSUPP; - } - -+static int atmel_qspi_sama7g5_find_mode(const struct spi_mem_op *op) -+{ -+ u32 i; -+ -+ for (i = 0; i < ARRAY_SIZE(atmel_qspi_sama7g5_modes); i++) -+ if (atmel_qspi_is_compatible(op, &atmel_qspi_sama7g5_modes[i])) -+ return i; -+ -+ return -EOPNOTSUPP; -+} -+ - static bool atmel_qspi_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { -+ struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); - if (!spi_mem_default_supports_op(mem, op)) - return false; - -+ if (aq->caps->octal) { -+ if (atmel_qspi_sama7g5_find_mode(op) < 0) -+ return false; -+ else -+ return true; -+ } -+ - if (atmel_qspi_find_mode(op) < 0) - return false; - -@@ -474,6 +645,296 @@ static int atmel_qspi_transfer(struct sp - return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED); - } - -+static int atmel_qspi_reg_sync(struct atmel_qspi *aq) -+{ -+ u32 val; -+ int ret; -+ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_SYNCBSY), 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ return ret; -+} -+ -+static int atmel_qspi_update_config(struct atmel_qspi *aq) -+{ -+ int ret; -+ -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) -+ return ret; -+ atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); -+ return atmel_qspi_reg_sync(aq); -+} -+ -+static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, -+ const struct spi_mem_op *op, u32 *offset) -+{ -+ u32 iar, icr, ifr; -+ int mode, ret; -+ -+ iar = 0; -+ icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode); -+ ifr = QSPI_IFR_INSTEN; -+ -+ mode = atmel_qspi_sama7g5_find_mode(op); -+ if (mode < 0) -+ return mode; -+ ifr |= atmel_qspi_sama7g5_modes[mode].config; -+ -+ if (op->dummy.buswidth && op->dummy.nbytes) { -+ if (op->addr.dtr && op->dummy.dtr && op->data.dtr) -+ ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / -+ (2 * op->dummy.buswidth)); -+ else -+ ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / -+ op->dummy.buswidth); -+ } -+ -+ if (op->addr.buswidth && op->addr.nbytes) { -+ ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) | -+ QSPI_IFR_ADDREN; -+ iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val); -+ } -+ -+ if (op->addr.dtr && op->dummy.dtr && op->data.dtr) { -+ ifr |= QSPI_IFR_DDREN; -+ if (op->cmd.dtr) -+ ifr |= QSPI_IFR_DDRCMDEN; -+ -+ ifr |= QSPI_IFR_DQSEN; -+ } -+ -+ if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 || -+ op->data.buswidth == 8) -+ ifr |= FIELD_PREP(QSPI_IFR_PROTTYP, QSPI_IFR_PROTTYP_OCTAFLASH); -+ -+ /* offset of the data access in the QSPI memory space */ -+ *offset = iar; -+ -+ /* Set data enable */ -+ if (op->data.nbytes) { -+ ifr |= QSPI_IFR_DATAEN; -+ -+ if (op->addr.nbytes) -+ ifr |= QSPI_IFR_TFRTYP_MEM; -+ } -+ -+ /* -+ * If the QSPI controller is set in regular SPI mode, set it in -+ * Serial Memory Mode (SMM). -+ */ -+ if (aq->mr != QSPI_MR_SMM) { -+ atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); -+ aq->mr = QSPI_MR_SMM; -+ -+ ret = atmel_qspi_update_config(aq); -+ if (ret) -+ return ret; -+ } -+ -+ /* Clear pending interrupts */ -+ (void)atmel_qspi_read(aq, QSPI_SR); -+ -+ /* Set QSPI Instruction Frame registers */ -+ if (op->addr.nbytes && !op->data.nbytes) -+ atmel_qspi_write(iar, aq, QSPI_IAR); -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ atmel_qspi_write(icr, aq, QSPI_RICR); -+ } else { -+ atmel_qspi_write(icr, aq, QSPI_WICR); -+ if (op->data.nbytes) -+ atmel_qspi_write(FIELD_PREP(QSPI_WRACNT_NBWRA, -+ op->data.nbytes), -+ aq, QSPI_WRACNT); -+ } -+ -+ atmel_qspi_write(ifr, aq, QSPI_IFR); -+ -+ return atmel_qspi_update_config(aq); -+} -+ -+static void atmel_qspi_dma_callback(void *param) -+{ -+ struct atmel_qspi *aq = param; -+ -+ complete(&aq->dma_completion); -+} -+ -+static int atmel_qspi_dma_xfer(struct atmel_qspi *aq, struct dma_chan *chan, -+ dma_addr_t dma_dst, dma_addr_t dma_src, -+ unsigned int len) -+{ -+ struct dma_async_tx_descriptor *tx; -+ dma_cookie_t cookie; -+ int ret; -+ -+ tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ if (!tx) { -+ dev_err(&aq->pdev->dev, "device_prep_dma_memcpy error\n"); -+ return -EIO; -+ } -+ -+ reinit_completion(&aq->dma_completion); -+ tx->callback = atmel_qspi_dma_callback; -+ tx->callback_param = aq; -+ cookie = tx->tx_submit(tx); -+ ret = dma_submit_error(cookie); -+ if (ret) { -+ dev_err(&aq->pdev->dev, "dma_submit_error %d\n", cookie); -+ return ret; -+ } -+ -+ dma_async_issue_pending(chan); -+ ret = wait_for_completion_timeout(&aq->dma_completion, -+ msecs_to_jiffies(20 * ATMEL_QSPI_TIMEOUT)); -+ if (ret == 0) { -+ dmaengine_terminate_sync(chan); -+ dev_err(&aq->pdev->dev, "DMA wait_for_completion_timeout\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int atmel_qspi_dma_rx_xfer(struct spi_mem *mem, -+ const struct spi_mem_op *op, -+ struct sg_table *sgt, loff_t loff) -+{ -+ struct atmel_qspi *aq = -+ spi_controller_get_devdata(mem->spi->controller); -+ struct scatterlist *sg; -+ dma_addr_t dma_src; -+ unsigned int i, len; -+ int ret; -+ -+ dma_src = aq->mmap_phys_base + loff; -+ -+ for_each_sg(sgt->sgl, sg, sgt->nents, i) { -+ len = sg_dma_len(sg); -+ ret = atmel_qspi_dma_xfer(aq, aq->rx_chan, sg_dma_address(sg), -+ dma_src, len); -+ if (ret) -+ return ret; -+ dma_src += len; -+ } -+ -+ return 0; -+} -+ -+static int atmel_qspi_dma_tx_xfer(struct spi_mem *mem, -+ const struct spi_mem_op *op, -+ struct sg_table *sgt, loff_t loff) -+{ -+ struct atmel_qspi *aq = -+ spi_controller_get_devdata(mem->spi->controller); -+ struct scatterlist *sg; -+ dma_addr_t dma_dst; -+ unsigned int i, len; -+ int ret; -+ -+ dma_dst = aq->mmap_phys_base + loff; -+ -+ for_each_sg(sgt->sgl, sg, sgt->nents, i) { -+ len = sg_dma_len(sg); -+ ret = atmel_qspi_dma_xfer(aq, aq->tx_chan, dma_dst, -+ sg_dma_address(sg), len); -+ if (ret) -+ return ret; -+ dma_dst += len; -+ } -+ -+ return 0; -+} -+ -+static int atmel_qspi_dma_transfer(struct spi_mem *mem, -+ const struct spi_mem_op *op, loff_t loff) -+{ -+ struct sg_table sgt; -+ int ret; -+ -+ ret = spi_controller_dma_map_mem_op_data(mem->spi->controller, op, -+ &sgt); -+ if (ret) -+ return ret; -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ ret = atmel_qspi_dma_rx_xfer(mem, op, &sgt, loff); -+ else -+ ret = atmel_qspi_dma_tx_xfer(mem, op, &sgt, loff); -+ -+ spi_controller_dma_unmap_mem_op_data(mem->spi->controller, op, &sgt); -+ -+ return ret; -+} -+ -+static int atmel_qspi_sama7g5_transfer(struct spi_mem *mem, -+ const struct spi_mem_op *op, u32 offset) -+{ -+ struct atmel_qspi *aq = -+ spi_controller_get_devdata(mem->spi->controller); -+ u32 val; -+ int ret; -+ -+ if (!op->data.nbytes) { -+ /* Start the transfer. */ -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) -+ return ret; -+ atmel_qspi_write(QSPI_CR_STTFR, aq, QSPI_CR); -+ -+ return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); -+ } -+ -+ /* Send/Receive data. */ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ if (aq->rx_chan && op->addr.nbytes && -+ op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { -+ ret = atmel_qspi_dma_transfer(mem, op, offset); -+ if (ret) -+ return ret; -+ } else { -+ memcpy_fromio(op->data.buf.in, aq->mem + offset, -+ op->data.nbytes); -+ } -+ -+ if (op->addr.nbytes) { -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_RBUSY), 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ if (ret) -+ return ret; -+ } -+ } else { -+ if (aq->tx_chan && op->addr.nbytes && -+ op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { -+ ret = atmel_qspi_dma_transfer(mem, op, offset); -+ if (ret) -+ return ret; -+ } else { -+ memcpy_toio(aq->mem + offset, op->data.buf.out, -+ op->data.nbytes); -+ } -+ -+ ret = atmel_qspi_wait_for_completion(aq, QSPI_SR_LWRA); -+ if (ret) -+ return ret; -+ } -+ -+ /* Release the chip-select. */ -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) { -+ pm_runtime_mark_last_busy(&aq->pdev->dev); -+ pm_runtime_put_autosuspend(&aq->pdev->dev); -+ return ret; -+ } -+ atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); -+ -+ return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); -+} -+ - static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) - { - struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); -@@ -518,6 +979,160 @@ static const struct spi_controller_mem_o - .get_name = atmel_qspi_get_name - }; - -+static int atmel_qspi_set_pad_calibration(struct atmel_qspi *aq) -+{ -+ unsigned long pclk_rate; -+ u32 status, val; -+ int i, ret; -+ u8 pclk_div = 0; -+ -+ pclk_rate = clk_get_rate(aq->pclk); -+ if (!pclk_rate) -+ return -EINVAL; -+ -+ for (i = 0; i < ATMEL_QSPI_PCAL_ARRAY_SIZE; i++) { -+ if (pclk_rate <= pcal[i].pclk_rate) { -+ pclk_div = pcal[i].pclk_div; -+ break; -+ } -+ } -+ -+ /* -+ * Use the biggest divider in case the peripheral clock exceeds -+ * 200MHZ. -+ */ -+ if (pclk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate) -+ pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div; -+ -+ /* Disable QSPI while configuring the pad calibration. */ -+ status = atmel_qspi_read(aq, QSPI_SR2); -+ if (status & QSPI_SR2_QSPIENS) { -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) -+ return ret; -+ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); -+ } -+ -+ /* -+ * The analog circuitry is not shut down at the end of the calibration -+ * and the start-up time is only required for the first calibration -+ * sequence, thus increasing performance. Set the delay between the Pad -+ * calibration analog circuitry and the calibration request to 2us. -+ */ -+ atmel_qspi_write(QSPI_PCALCFG_AAON | -+ FIELD_PREP(QSPI_PCALCFG_CLKDIV, pclk_div) | -+ FIELD_PREP(QSPI_PCALCFG_CALCNT, -+ 2 * (pclk_rate / 1000000)), -+ aq, QSPI_PCALCFG); -+ -+ /* DLL On + start calibration. */ -+ atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); -+ -+ /* Check synchronization status before updating configuration. */ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ (val & QSPI_SR2_DLOCK) && -+ !(val & QSPI_SR2_CALBSY), 40, -+ ATMEL_QSPI_TIMEOUT); -+ -+ /* Refresh analogic blocks every 1 ms.*/ -+ atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, -+ aq->slave_max_speed_hz / 1000), -+ aq, QSPI_REFRESH); -+ -+ return ret; -+} -+ -+static int atmel_qspi_set_gclk(struct atmel_qspi *aq) -+{ -+ u32 status, val; -+ int ret; -+ -+ /* Disable DLL before setting GCLK */ -+ status = atmel_qspi_read(aq, QSPI_SR2); -+ if (status & QSPI_SR2_DLOCK) { -+ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -+ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_DLOCK), 40, -+ ATMEL_QSPI_TIMEOUT); -+ if (ret) -+ return ret; -+ } -+ -+ if (aq->slave_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) -+ atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); -+ else -+ atmel_qspi_write(0, aq, QSPI_DLLCFG); -+ -+ ret = clk_set_rate(aq->gclk, aq->slave_max_speed_hz); -+ if (ret) { -+ dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); -+ return ret; -+ } -+ -+ /* Enable the QSPI generic clock */ -+ ret = clk_prepare_enable(aq->gclk); -+ if (ret) -+ dev_err(&aq->pdev->dev, "Failed to enable generic clock.\n"); -+ -+ return ret; -+} -+ -+static int atmel_qspi_sama7g5_init(struct atmel_qspi *aq) -+{ -+ u32 val; -+ int ret; -+ -+ ret = atmel_qspi_set_gclk(aq); -+ if (ret) -+ return ret; -+ -+ if (aq->caps->octal) { -+ ret = atmel_qspi_set_pad_calibration(aq); -+ if (ret) -+ return ret; -+ } else { -+ atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ (val & QSPI_SR2_DLOCK), 40, -+ ATMEL_QSPI_TIMEOUT); -+ } -+ -+ /* Set the QSPI controller by default in Serial Memory Mode */ -+ atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); -+ aq->mr = QSPI_MR_SMM; -+ ret = atmel_qspi_update_config(aq); -+ if (ret) -+ return ret; -+ -+ /* Enable the QSPI controller. */ -+ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ val & QSPI_SR2_QSPIENS, 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ if (ret) -+ return ret; -+ -+ if (aq->caps->octal) { -+ ret = readl_poll_timeout(aq->regs + QSPI_SR, val, -+ val & QSPI_SR_RFRSHD, 40, -+ ATMEL_QSPI_TIMEOUT); -+ } -+ -+ atmel_qspi_write(QSPI_TOUT_TCNTM, aq, QSPI_TOUT); -+ return ret; -+} -+ -+static int atmel_qspi_sama7g5_setup(struct spi_device *spi) -+{ -+ struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller); -+ -+ /* The controller can communicate with a single slave. */ -+ aq->slave_max_speed_hz = spi->max_speed_hz; -+ -+ return atmel_qspi_sama7g5_init(aq); -+} -+ - static int atmel_qspi_setup(struct spi_device *spi) - { - struct spi_controller *ctrl = spi->controller; -@@ -532,6 +1147,9 @@ static int atmel_qspi_setup(struct spi_d - if (!spi->max_speed_hz) - return -EINVAL; - -+ if (aq->caps->has_gclk) -+ return atmel_qspi_sama7g5_setup(spi); -+ - src_rate = clk_get_rate(aq->pclk); - if (!src_rate) - return -EINVAL; -@@ -589,8 +1207,18 @@ static int atmel_qspi_set_cs_timing(stru - return 0; - } - --static void atmel_qspi_init(struct atmel_qspi *aq) -+static int atmel_qspi_init(struct atmel_qspi *aq) - { -+ int ret; -+ -+ if (aq->caps->has_gclk) { -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) -+ return ret; -+ atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); -+ return 0; -+ } -+ - /* Reset the QSPI controller */ - atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); - -@@ -600,6 +1228,7 @@ static void atmel_qspi_init(struct atmel - - /* Enable the QSPI controller */ - atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); -+ return 0; - } - - static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) -@@ -621,11 +1250,59 @@ static irqreturn_t atmel_qspi_interrupt( - return IRQ_HANDLED; - } - -+static int atmel_qspi_dma_init(struct spi_controller *ctrl) -+{ -+ struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); -+ int ret; -+ -+ aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); -+ if (IS_ERR(aq->rx_chan)) { -+ aq->rx_chan = NULL; -+ return dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), -+ "RX DMA channel is not available\n"); -+ } -+ -+ aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); -+ if (IS_ERR(aq->tx_chan)) { -+ ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan), -+ "TX DMA channel is not available\n"); -+ goto release_rx_chan; -+ } -+ -+ ctrl->dma_rx = aq->rx_chan; -+ ctrl->dma_tx = aq->tx_chan; -+ init_completion(&aq->dma_completion); -+ -+ dev_info(&aq->pdev->dev, "Using %s (tx) and %s (rx) for DMA transfers\n", -+ dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan)); -+ -+ return 0; -+ -+release_rx_chan: -+ dma_release_channel(aq->rx_chan); -+ aq->rx_chan = NULL; -+ aq->tx_chan = NULL; -+ return ret; -+} -+ -+static void atmel_qspi_dma_release(struct atmel_qspi *aq) -+{ -+ if (aq->rx_chan) -+ dma_release_channel(aq->rx_chan); -+ if (aq->tx_chan) -+ dma_release_channel(aq->tx_chan); -+} -+ - static const struct atmel_qspi_ops atmel_qspi_ops = { - .set_cfg = atmel_qspi_set_cfg, - .transfer = atmel_qspi_transfer, - }; - -+static const struct atmel_qspi_ops atmel_qspi_sama7g5_ops = { -+ .set_cfg = atmel_qspi_sama7g5_set_cfg, -+ .transfer = atmel_qspi_sama7g5_transfer, -+}; -+ - static int atmel_qspi_probe(struct platform_device *pdev) - { - struct spi_controller *ctrl; -@@ -637,7 +1314,27 @@ static int atmel_qspi_probe(struct platf - if (!ctrl) - return -ENOMEM; - -+ aq = spi_controller_get_devdata(ctrl); -+ -+ aq->caps = of_device_get_match_data(&pdev->dev); -+ if (!aq->caps) { -+ dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); -+ return -EINVAL; -+ } -+ -+ init_completion(&aq->cmd_completion); -+ aq->pdev = pdev; -+ - ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; -+ if (aq->caps->octal) -+ ctrl->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; -+ -+ if (aq->caps->has_gclk) -+ aq->ops = &atmel_qspi_sama7g5_ops; -+ else -+ aq->ops = &atmel_qspi_ops; -+ -+ ctrl->max_speed_hz = aq->caps->max_speed_hz; - ctrl->setup = atmel_qspi_setup; - ctrl->set_cs_timing = atmel_qspi_set_cs_timing; - ctrl->bus_num = -1; -@@ -646,12 +1343,6 @@ static int atmel_qspi_probe(struct platf - ctrl->dev.of_node = pdev->dev.of_node; - platform_set_drvdata(pdev, ctrl); - -- aq = spi_controller_get_devdata(ctrl); -- -- init_completion(&aq->cmd_completion); -- aq->pdev = pdev; -- aq->ops = &atmel_qspi_ops; -- - /* Map the registers */ - aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base"); - if (IS_ERR(aq->regs)) -@@ -666,6 +1357,7 @@ static int atmel_qspi_probe(struct platf - "missing AHB memory\n"); - - aq->mmap_size = resource_size(res); -+ aq->mmap_phys_base = (dma_addr_t)res->start; - - /* Get the peripheral clock */ - aq->pclk = devm_clk_get(&pdev->dev, "pclk"); -@@ -682,13 +1374,6 @@ static int atmel_qspi_probe(struct platf - return dev_err_probe(&pdev->dev, err, - "failed to enable the peripheral clock\n"); - -- aq->caps = of_device_get_match_data(&pdev->dev); -- if (!aq->caps) { -- dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); -- err = -EINVAL; -- goto disable_pclk; -- } -- - if (aq->caps->has_qspick) { - /* Get the QSPI system clock */ - aq->qspick = devm_clk_get(&pdev->dev, "qspick"); -@@ -705,18 +1390,32 @@ static int atmel_qspi_probe(struct platf - "failed to enable the QSPI system clock\n"); - goto disable_pclk; - } -+ } else if (aq->caps->has_gclk) { -+ /* Get the QSPI generic clock */ -+ aq->gclk = devm_clk_get(&pdev->dev, "gclk"); -+ if (IS_ERR(aq->gclk)) { -+ dev_err(&pdev->dev, "missing Generic clock\n"); -+ err = PTR_ERR(aq->gclk); -+ goto disable_pclk; -+ } -+ } -+ -+ if (aq->caps->has_dma) { -+ err = atmel_qspi_dma_init(ctrl); -+ if (err == -EPROBE_DEFER) -+ goto disable_qspick; - } - - /* Request the IRQ */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - err = irq; -- goto disable_qspick; -+ goto dma_release; - } - err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, - 0, dev_name(&pdev->dev), aq); - if (err) -- goto disable_qspick; -+ goto dma_release; - - pm_runtime_set_autosuspend_delay(&pdev->dev, 500); - pm_runtime_use_autosuspend(&pdev->dev); -@@ -724,7 +1423,9 @@ static int atmel_qspi_probe(struct platf - pm_runtime_enable(&pdev->dev); - pm_runtime_get_noresume(&pdev->dev); - -- atmel_qspi_init(aq); -+ err = atmel_qspi_init(aq); -+ if (err) -+ goto dma_release; - - err = spi_register_controller(ctrl); - if (err) { -@@ -732,13 +1433,16 @@ static int atmel_qspi_probe(struct platf - pm_runtime_disable(&pdev->dev); - pm_runtime_set_suspended(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -- goto disable_qspick; -+ goto dma_release; - } - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); - - return 0; - -+dma_release: -+ if (aq->caps->has_dma) -+ atmel_qspi_dma_release(aq); - disable_qspick: - clk_disable_unprepare(aq->qspick); - disable_pclk: -@@ -747,6 +1451,44 @@ disable_pclk: - return err; - } - -+static int atmel_qspi_sama7g5_suspend(struct atmel_qspi *aq) -+{ -+ int ret; -+ u32 val; -+ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_RBUSY) && -+ (val & QSPI_SR2_HIDLE), 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ if (ret) -+ return ret; -+ -+ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_QSPIENS), 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ if (ret) -+ return ret; -+ -+ clk_disable_unprepare(aq->gclk); -+ -+ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_DLOCK), 40, -+ ATMEL_QSPI_TIMEOUT); -+ if (ret) -+ return ret; -+ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_CALBSY), 40, -+ ATMEL_QSPI_TIMEOUT); -+ if (ret) -+ return ret; -+ -+ clk_disable_unprepare(aq->pclk); -+ return 0; -+} -+ - static void atmel_qspi_remove(struct platform_device *pdev) - { - struct spi_controller *ctrl = platform_get_drvdata(pdev); -@@ -757,6 +1499,16 @@ static void atmel_qspi_remove(struct pla - - ret = pm_runtime_get_sync(&pdev->dev); - if (ret >= 0) { -+ if (aq->caps->has_dma) -+ atmel_qspi_dma_release(aq); -+ -+ if (aq->caps->has_gclk) { -+ ret = atmel_qspi_sama7g5_suspend(aq); -+ if (ret) -+ dev_warn(&pdev->dev, "Failed to de-init device on remove: %d\n", ret); -+ return; -+ } -+ - atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); - clk_disable(aq->qspick); - clk_disable(aq->pclk); -@@ -787,6 +1539,9 @@ static int __maybe_unused atmel_qspi_sus - if (ret < 0) - return ret; - -+ if (aq->caps->has_gclk) -+ return atmel_qspi_sama7g5_suspend(aq); -+ - atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); - - pm_runtime_mark_last_busy(dev); -@@ -814,6 +1569,9 @@ static int __maybe_unused atmel_qspi_res - return ret; - } - -+ if (aq->caps->has_gclk) -+ return atmel_qspi_sama7g5_init(aq); -+ - ret = pm_runtime_force_resume(dev); - if (ret < 0) - return ret; -@@ -869,6 +1627,19 @@ static const struct atmel_qspi_caps atme - .has_ricr = true, - }; - -+static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { -+ .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .octal = true, -+ .has_dma = true, -+}; -+ -+static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = { -+ .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .has_dma = true, -+}; -+ - static const struct of_device_id atmel_qspi_dt_ids[] = { - { - .compatible = "atmel,sama5d2-qspi", -@@ -878,6 +1649,15 @@ static const struct of_device_id atmel_q - .compatible = "microchip,sam9x60-qspi", - .data = &atmel_sam9x60_qspi_caps, - }, -+ { -+ .compatible = "microchip,sama7g5-ospi", -+ .data = &atmel_sama7g5_ospi_caps, -+ }, -+ { -+ .compatible = "microchip,sama7g5-qspi", -+ .data = &atmel_sama7g5_qspi_caps, -+ }, -+ - { /* sentinel */ } - }; - diff --git a/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch b/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch deleted file mode 100644 index f13641e1ce..0000000000 --- a/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 36087601ba5fed2fe42134bf59f6ba75029fd7f7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Wed, 18 Dec 2024 16:17:54 +0100 -Subject: [PATCH 099/112] spi: atmel-quadspi: Factor out switching to Serial - Memory Mode to function -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -SAMA7G5 support (that was forward-ported from v6.1) re-introduced -a bug that was fixed in v6.12, thankfully only in the codepath of -the new SoC. But to prevent similar mistakes in the future, we -split out the offending code to a function, and use this, fixed -version everywhere. - -To facilitate this, support function `atmel_qspi_update_config()` -also had to be moved upwards. For best viewing experience, use -`--color-moved-ws="allow-indentation-change" --color-moved`. - -Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") -Reported-by: Alexander Dahl -Closes: https://lore.kernel.org/linux-spi/20241218-appliance-jaws-90773405977a@thorsis.com/ -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20241218151754.365519-1-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 101 +++++++++++++++++++----------------- - 1 file changed, 53 insertions(+), 48 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -414,6 +414,28 @@ static void atmel_qspi_write(u32 value, - writel_relaxed(value, aq->regs + offset); - } - -+static int atmel_qspi_reg_sync(struct atmel_qspi *aq) -+{ -+ u32 val; -+ int ret; -+ -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_SYNCBSY), 40, -+ ATMEL_QSPI_SYNC_TIMEOUT); -+ return ret; -+} -+ -+static int atmel_qspi_update_config(struct atmel_qspi *aq) -+{ -+ int ret; -+ -+ ret = atmel_qspi_reg_sync(aq); -+ if (ret) -+ return ret; -+ atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); -+ return atmel_qspi_reg_sync(aq); -+} -+ - static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, - const struct atmel_qspi_mode *mode) - { -@@ -476,6 +498,25 @@ static bool atmel_qspi_supports_op(struc - return true; - } - -+/* -+ * If the QSPI controller is set in regular SPI mode, set it in -+ * Serial Memory Mode (SMM). -+ */ -+static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq) -+{ -+ int ret = 0; -+ -+ if (!(aq->mr & QSPI_MR_SMM)) { -+ aq->mr |= QSPI_MR_SMM; -+ atmel_qspi_write(aq->mr, aq, QSPI_MR); -+ -+ if (aq->caps->has_gclk) -+ ret = atmel_qspi_update_config(aq); -+ } -+ -+ return ret; -+} -+ - static int atmel_qspi_set_cfg(struct atmel_qspi *aq, - const struct spi_mem_op *op, u32 *offset) - { -@@ -555,14 +596,9 @@ static int atmel_qspi_set_cfg(struct atm - ifr |= QSPI_IFR_TFRTYP_MEM; - } - -- /* -- * If the QSPI controller is set in regular SPI mode, set it in -- * Serial Memory Mode (SMM). -- */ -- if (!(aq->mr & QSPI_MR_SMM)) { -- aq->mr |= QSPI_MR_SMM; -- atmel_qspi_write(aq->mr, aq, QSPI_MR); -- } -+ mode = atmel_qspi_set_serial_memory_mode(aq); -+ if (mode < 0) -+ return mode; - - /* Clear pending interrupts */ - (void)atmel_qspi_read(aq, QSPI_SR); -@@ -645,28 +681,6 @@ static int atmel_qspi_transfer(struct sp - return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED); - } - --static int atmel_qspi_reg_sync(struct atmel_qspi *aq) --{ -- u32 val; -- int ret; -- -- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -- !(val & QSPI_SR2_SYNCBSY), 40, -- ATMEL_QSPI_SYNC_TIMEOUT); -- return ret; --} -- --static int atmel_qspi_update_config(struct atmel_qspi *aq) --{ -- int ret; -- -- ret = atmel_qspi_reg_sync(aq); -- if (ret) -- return ret; -- atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); -- return atmel_qspi_reg_sync(aq); --} -- - static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, - const struct spi_mem_op *op, u32 *offset) - { -@@ -720,18 +734,9 @@ static int atmel_qspi_sama7g5_set_cfg(st - ifr |= QSPI_IFR_TFRTYP_MEM; - } - -- /* -- * If the QSPI controller is set in regular SPI mode, set it in -- * Serial Memory Mode (SMM). -- */ -- if (aq->mr != QSPI_MR_SMM) { -- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); -- aq->mr = QSPI_MR_SMM; -- -- ret = atmel_qspi_update_config(aq); -- if (ret) -- return ret; -- } -+ ret = atmel_qspi_set_serial_memory_mode(aq); -+ if (ret < 0) -+ return ret; - - /* Clear pending interrupts */ - (void)atmel_qspi_read(aq, QSPI_SR); -@@ -1099,10 +1104,9 @@ static int atmel_qspi_sama7g5_init(struc - } - - /* Set the QSPI controller by default in Serial Memory Mode */ -- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); -- aq->mr = QSPI_MR_SMM; -- ret = atmel_qspi_update_config(aq); -- if (ret) -+ aq->mr |= QSPI_MR_DQSDLYEN; -+ ret = atmel_qspi_set_serial_memory_mode(aq); -+ if (ret < 0) - return ret; - - /* Enable the QSPI controller. */ -@@ -1223,8 +1227,9 @@ static int atmel_qspi_init(struct atmel_ - atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); - - /* Set the QSPI controller by default in Serial Memory Mode */ -- aq->mr |= QSPI_MR_SMM; -- atmel_qspi_write(aq->mr, aq, QSPI_MR); -+ ret = atmel_qspi_set_serial_memory_mode(aq); -+ if (ret < 0) -+ return ret; - - /* Enable the QSPI controller */ - atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); diff --git a/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch b/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch deleted file mode 100644 index d84361567f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 7c8bec1bb999e6f44e326fdf7157d5e37b748aca Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Thu, 19 Dec 2024 15:28:51 +0100 -Subject: [PATCH 100/112] spi: atmel-quadspi: Use devm_ clock management -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Clean up error handling by using the new devm_ -clock handling functions. This should make it -easier to add new code, as we can eliminate the -"goto ladder" in probe(). - -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20241219142851.430959-1-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 42 ++++++++++--------------------------- - 1 file changed, 11 insertions(+), 31 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1365,50 +1365,37 @@ static int atmel_qspi_probe(struct platf - aq->mmap_phys_base = (dma_addr_t)res->start; - - /* Get the peripheral clock */ -- aq->pclk = devm_clk_get(&pdev->dev, "pclk"); -+ aq->pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); - if (IS_ERR(aq->pclk)) -- aq->pclk = devm_clk_get(&pdev->dev, NULL); -+ aq->pclk = devm_clk_get_enabled(&pdev->dev, NULL); - - if (IS_ERR(aq->pclk)) - return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk), - "missing peripheral clock\n"); - -- /* Enable the peripheral clock */ -- err = clk_prepare_enable(aq->pclk); -- if (err) -- return dev_err_probe(&pdev->dev, err, -- "failed to enable the peripheral clock\n"); -- - if (aq->caps->has_qspick) { - /* Get the QSPI system clock */ -- aq->qspick = devm_clk_get(&pdev->dev, "qspick"); -+ aq->qspick = devm_clk_get_enabled(&pdev->dev, "qspick"); - if (IS_ERR(aq->qspick)) { - dev_err(&pdev->dev, "missing system clock\n"); - err = PTR_ERR(aq->qspick); -- goto disable_pclk; -+ return err; - } - -- /* Enable the QSPI system clock */ -- err = clk_prepare_enable(aq->qspick); -- if (err) { -- dev_err(&pdev->dev, -- "failed to enable the QSPI system clock\n"); -- goto disable_pclk; -- } - } else if (aq->caps->has_gclk) { - /* Get the QSPI generic clock */ - aq->gclk = devm_clk_get(&pdev->dev, "gclk"); - if (IS_ERR(aq->gclk)) { - dev_err(&pdev->dev, "missing Generic clock\n"); - err = PTR_ERR(aq->gclk); -- goto disable_pclk; -+ return err; - } - } - - if (aq->caps->has_dma) { - err = atmel_qspi_dma_init(ctrl); - if (err == -EPROBE_DEFER) -- goto disable_qspick; -+ return err; - } - - /* Request the IRQ */ -@@ -1448,10 +1435,6 @@ static int atmel_qspi_probe(struct platf - dma_release: - if (aq->caps->has_dma) - atmel_qspi_dma_release(aq); --disable_qspick: -- clk_disable_unprepare(aq->qspick); --disable_pclk: -- clk_disable_unprepare(aq->pclk); - - return err; - } -@@ -1490,7 +1473,6 @@ static int atmel_qspi_sama7g5_suspend(st - if (ret) - return ret; - -- clk_disable_unprepare(aq->pclk); - return 0; - } - -@@ -1515,8 +1497,6 @@ static void atmel_qspi_remove(struct pla - } - - atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); -- clk_disable(aq->qspick); -- clk_disable(aq->pclk); - } else { - /* - * atmel_qspi_runtime_{suspend,resume} just disable and enable -@@ -1526,9 +1506,6 @@ static void atmel_qspi_remove(struct pla - dev_warn(&pdev->dev, "Failed to resume device on remove\n"); - } - -- clk_unprepare(aq->qspick); -- clk_unprepare(aq->pclk); -- - pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_put_noidle(&pdev->dev); -@@ -1544,8 +1521,11 @@ static int __maybe_unused atmel_qspi_sus - if (ret < 0) - return ret; - -- if (aq->caps->has_gclk) -- return atmel_qspi_sama7g5_suspend(aq); -+ if (aq->caps->has_gclk) { -+ ret = atmel_qspi_sama7g5_suspend(aq); -+ clk_disable_unprepare(aq->pclk); -+ return ret; -+ } - - atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); - diff --git a/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch b/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch deleted file mode 100644 index f5787551c5..0000000000 --- a/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 2eaa23a57b91442f98ae2c77ab1258a2bf0065b9 Mon Sep 17 00:00:00 2001 -From: Alexander Dahl -Date: Thu, 9 Jan 2025 10:48:43 +0100 -Subject: [PATCH 101/112] spi: atmel-quadspi: Update to current device naming - terminology - -For v6.9 the spi subsystem changed the terminology to host and target -devices, see commit 99769a52464d ("spi: Update the "master/slave" -terminology in documentation") for reference. Support for SAMA7G5 was -forward ported recently from an old vendor branch before that -terminology change, so naming for the new struct member is adapted to -follow the current scheme. - -Signed-off-by: Alexander Dahl -Link: https://patch.msgid.link/20250109094843.36014-1-ada@thorsis.com -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -280,7 +280,7 @@ struct atmel_qspi { - u32 irq_mask; - u32 mr; - u32 scr; -- u32 slave_max_speed_hz; -+ u32 target_max_speed_hz; - struct completion cmd_completion; - struct completion dma_completion; - dma_addr_t mmap_phys_base; -@@ -1041,7 +1041,7 @@ static int atmel_qspi_set_pad_calibratio - - /* Refresh analogic blocks every 1 ms.*/ - atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, -- aq->slave_max_speed_hz / 1000), -+ aq->target_max_speed_hz / 1000), - aq, QSPI_REFRESH); - - return ret; -@@ -1064,12 +1064,12 @@ static int atmel_qspi_set_gclk(struct at - return ret; - } - -- if (aq->slave_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) -+ if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) - atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); - else - atmel_qspi_write(0, aq, QSPI_DLLCFG); - -- ret = clk_set_rate(aq->gclk, aq->slave_max_speed_hz); -+ ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); - if (ret) { - dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); - return ret; -@@ -1131,8 +1131,8 @@ static int atmel_qspi_sama7g5_setup(stru - { - struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller); - -- /* The controller can communicate with a single slave. */ -- aq->slave_max_speed_hz = spi->max_speed_hz; -+ /* The controller can communicate with a single peripheral device (target). */ -+ aq->target_max_speed_hz = spi->max_speed_hz; - - return atmel_qspi_sama7g5_init(aq); - } diff --git a/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch b/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch deleted file mode 100644 index 6a919c1707..0000000000 --- a/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9a39bca30a65f571fae33ac9c76e67ebca44b2a4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Mon, 3 Feb 2025 16:12:49 +0100 -Subject: [PATCH 102/112] spi: atmel-quadspi: Fix warning in doc-comment -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The doc-comment for `struct atmel_qspi_pcal` had a typo in one of the -struct members' name, causing a warning with the `W=1` option. - -Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202501311707.Ltj0qXse-lkp@intel.com/ -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20250203151249.79876-2-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -235,8 +235,8 @@ - /** - * struct atmel_qspi_pcal - Pad Calibration Clock Division - * @pclk_rate: peripheral clock rate. -- * @pclkdiv: calibration clock division. The clock applied to the calibration -- * cell is divided by pclkdiv + 1. -+ * @pclk_div: calibration clock division. The clock applied to the calibration -+ * cell is divided by pclk_div + 1. - */ - struct atmel_qspi_pcal { - u32 pclk_rate; diff --git a/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch b/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch deleted file mode 100644 index 6ed49863a0..0000000000 --- a/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 74a3cec06e0d0604d9e075e4976a9f434f112488 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 7 Feb 2025 13:21:45 +0100 -Subject: [PATCH 103/112] spi: atmel-quadspi: remove references to runtime PM - on error path -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is no need to call runtime PM put APIs on error path of -`atmel_qspi_sama7g5_transfer()` as the caller (`atmel_qspi_exec_op()`) -of it will take care of this if needed. - -Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") -Signed-off-by: Claudiu Beznea -Signed-off-by: Durai Manickam KR -Reported-by: Alexander Dahl -Closes: https://lore.kernel.org/linux-spi/20250109-carat-festivity-5f088e1add3c@thorsis.com/ -[ csokas.bence: Rebase and clarify msg, fix/add tags ] -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20250207122145.162183-2-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -930,11 +930,8 @@ static int atmel_qspi_sama7g5_transfer(s - - /* Release the chip-select. */ - ret = atmel_qspi_reg_sync(aq); -- if (ret) { -- pm_runtime_mark_last_busy(&aq->pdev->dev); -- pm_runtime_put_autosuspend(&aq->pdev->dev); -+ if (ret) - return ret; -- } - atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); - - return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); diff --git a/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch b/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch deleted file mode 100644 index 1e56e50034..0000000000 --- a/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch +++ /dev/null @@ -1,49 +0,0 @@ -From c015516392a271e179e4f898908c402ec93ce13a Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Thu, 1 May 2025 17:01:59 +0200 -Subject: [PATCH 104/112] spi: atmel-quadspi: Fix printed error code during DMA - setup - -On dma_request_chan() failure driver NULL-ifies the 'rx_chan' and -immediately uses it as PTR_ERR() so dev_err_probe() prints incorrect -error code. Rework the code so proper error code will be printed and -NULL-ifying of 'rx_chan' will happen in common error handling block -(failure of DMA setup is not fatal for the driver and further code -depends on 'rx_chan' being non-NULL for DMA operations). - -Reported by Smatch: - drivers/spi/atmel-quadspi.c:1287 atmel_qspi_dma_init() warn: passing zero to 'PTR_ERR' - -Signed-off-by: Krzysztof Kozlowski -Link: https://patch.msgid.link/20250501-n-smatch-fixes-v2-1-d2ad9c1f2e67@linaro.org -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1259,9 +1259,9 @@ static int atmel_qspi_dma_init(struct sp - - aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); - if (IS_ERR(aq->rx_chan)) { -- aq->rx_chan = NULL; -- return dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), -- "RX DMA channel is not available\n"); -+ ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), -+ "RX DMA channel is not available\n"); -+ goto null_rx_chan; - } - - aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); -@@ -1282,8 +1282,9 @@ static int atmel_qspi_dma_init(struct sp - - release_rx_chan: - dma_release_channel(aq->rx_chan); -- aq->rx_chan = NULL; - aq->tx_chan = NULL; -+null_rx_chan: -+ aq->rx_chan = NULL; - return ret; - } - diff --git a/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch b/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch deleted file mode 100644 index 3853d7d23e..0000000000 --- a/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch +++ /dev/null @@ -1,62 +0,0 @@ -From e56d9480ea806b1d92d16b882c40e7216f2cf2f2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Thu, 27 Mar 2025 20:59:27 +0100 -Subject: [PATCH 106/112] spi: atmel-quadspi: Fix unbalanced pm_runtime by - using devm_ API -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Fix unbalanced PM in error path of `atmel_qspi_probe()` -by using `devm_pm_runtime_*()` functions. - -Reported-by: Alexander Dahl -Closes: https://lore.kernel.org/linux-spi/20250110-paycheck-irregular-bcddab1276c7@thorsis.com/ -Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20250327195928.680771-4-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 17 ++++------------- - 1 file changed, 4 insertions(+), 13 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1409,22 +1409,17 @@ static int atmel_qspi_probe(struct platf - - pm_runtime_set_autosuspend_delay(&pdev->dev, 500); - pm_runtime_use_autosuspend(&pdev->dev); -- pm_runtime_set_active(&pdev->dev); -- pm_runtime_enable(&pdev->dev); -- pm_runtime_get_noresume(&pdev->dev); -+ devm_pm_runtime_set_active_enabled(&pdev->dev); -+ devm_pm_runtime_get_noresume(&pdev->dev); - - err = atmel_qspi_init(aq); - if (err) - goto dma_release; - - err = spi_register_controller(ctrl); -- if (err) { -- pm_runtime_put_noidle(&pdev->dev); -- pm_runtime_disable(&pdev->dev); -- pm_runtime_set_suspended(&pdev->dev); -- pm_runtime_dont_use_autosuspend(&pdev->dev); -+ if (err) - goto dma_release; -- } -+ - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); - -@@ -1503,10 +1498,6 @@ static void atmel_qspi_remove(struct pla - */ - dev_warn(&pdev->dev, "Failed to resume device on remove\n"); - } -- -- pm_runtime_disable(&pdev->dev); -- pm_runtime_dont_use_autosuspend(&pdev->dev); -- pm_runtime_put_noidle(&pdev->dev); - } - - static int __maybe_unused atmel_qspi_suspend(struct device *dev) diff --git a/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch b/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch deleted file mode 100644 index 1349734383..0000000000 --- a/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 92da9095958114aca94d7ab0c8fa76ee556d412d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Tue, 10 Jun 2025 10:22:53 +0200 -Subject: [PATCH 107/112] dmaengine: Add devm_dma_request_chan() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Expand the arsenal of devm functions for DMA devices, this time for -requesting channels. - -Signed-off-by: Bence Csókás -Link: https://lore.kernel.org/r/20250610082256.400492-2-csokas.bence@prolan.hu -Signed-off-by: Vinod Koul ---- - drivers/dma/dmaengine.c | 30 ++++++++++++++++++++++++++++++ - include/linux/dmaengine.h | 7 +++++++ - 2 files changed, 37 insertions(+) - ---- a/drivers/dma/dmaengine.c -+++ b/drivers/dma/dmaengine.c -@@ -926,6 +926,36 @@ void dma_release_channel(struct dma_chan - } - EXPORT_SYMBOL_GPL(dma_release_channel); - -+static void dmaenginem_release_channel(void *chan) -+{ -+ dma_release_channel(chan); -+} -+ -+/** -+ * devm_dma_request_chan - try to allocate an exclusive slave channel -+ * @dev: pointer to client device structure -+ * @name: slave channel name -+ * -+ * Returns pointer to appropriate DMA channel on success or an error pointer. -+ * -+ * The operation is managed and will be undone on driver detach. -+ */ -+ -+struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name) -+{ -+ struct dma_chan *chan = dma_request_chan(dev, name); -+ int ret = 0; -+ -+ if (!IS_ERR(chan)) -+ ret = devm_add_action_or_reset(dev, dmaenginem_release_channel, chan); -+ -+ if (ret) -+ return ERR_PTR(ret); -+ -+ return chan; -+} -+EXPORT_SYMBOL_GPL(devm_dma_request_chan); -+ - /** - * dmaengine_get - register interest in dma_channels - */ ---- a/include/linux/dmaengine.h -+++ b/include/linux/dmaengine.h -@@ -1521,6 +1521,7 @@ struct dma_chan *__dma_request_channel(c - - struct dma_chan *dma_request_chan(struct device *dev, const char *name); - struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); -+struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name); - - void dma_release_channel(struct dma_chan *chan); - int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); -@@ -1557,6 +1558,12 @@ static inline struct dma_chan *dma_reque - { - return ERR_PTR(-ENODEV); - } -+ -+static inline struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name) -+{ -+ return ERR_PTR(-ENODEV); -+} -+ - static inline void dma_release_channel(struct dma_chan *chan) - { - } diff --git a/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch b/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch deleted file mode 100644 index 388ba0128a..0000000000 --- a/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 4b031c48133b762ef9bb6cb40b9ec040acaef970 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= -Date: Tue, 10 Jun 2025 10:22:54 +0200 -Subject: [PATCH 108/112] spi: atmel-quadspi: Use `devm_dma_request_chan()` -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Leave releasing of DMA channels up to the devm facilities. This way we can -eliminate the rest of the "goto ladder". - -Signed-off-by: Bence Csókás -Link: https://patch.msgid.link/20250610082256.400492-3-csokas.bence@prolan.hu -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 48 ++++++++++--------------------------- - 1 file changed, 13 insertions(+), 35 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1257,18 +1257,21 @@ static int atmel_qspi_dma_init(struct sp - struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); - int ret; - -- aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); -+ aq->rx_chan = devm_dma_request_chan(&aq->pdev->dev, "rx"); - if (IS_ERR(aq->rx_chan)) { - ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), - "RX DMA channel is not available\n"); -- goto null_rx_chan; -+ aq->rx_chan = NULL; -+ return ret; - } - -- aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); -+ aq->tx_chan = devm_dma_request_chan(&aq->pdev->dev, "tx"); - if (IS_ERR(aq->tx_chan)) { - ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan), - "TX DMA channel is not available\n"); -- goto release_rx_chan; -+ aq->rx_chan = NULL; -+ aq->tx_chan = NULL; -+ return ret; - } - - ctrl->dma_rx = aq->rx_chan; -@@ -1279,21 +1282,6 @@ static int atmel_qspi_dma_init(struct sp - dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan)); - - return 0; -- --release_rx_chan: -- dma_release_channel(aq->rx_chan); -- aq->tx_chan = NULL; --null_rx_chan: -- aq->rx_chan = NULL; -- return ret; --} -- --static void atmel_qspi_dma_release(struct atmel_qspi *aq) --{ -- if (aq->rx_chan) -- dma_release_channel(aq->rx_chan); -- if (aq->tx_chan) -- dma_release_channel(aq->tx_chan); - } - - static const struct atmel_qspi_ops atmel_qspi_ops = { -@@ -1398,14 +1386,13 @@ static int atmel_qspi_probe(struct platf - - /* Request the IRQ */ - irq = platform_get_irq(pdev, 0); -- if (irq < 0) { -- err = irq; -- goto dma_release; -- } -+ if (irq < 0) -+ return irq; -+ - err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, - 0, dev_name(&pdev->dev), aq); - if (err) -- goto dma_release; -+ return err; - - pm_runtime_set_autosuspend_delay(&pdev->dev, 500); - pm_runtime_use_autosuspend(&pdev->dev); -@@ -1414,22 +1401,16 @@ static int atmel_qspi_probe(struct platf - - err = atmel_qspi_init(aq); - if (err) -- goto dma_release; -+ return err; - - err = spi_register_controller(ctrl); - if (err) -- goto dma_release; -+ return err; - - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); - - return 0; -- --dma_release: -- if (aq->caps->has_dma) -- atmel_qspi_dma_release(aq); -- -- return err; - } - - static int atmel_qspi_sama7g5_suspend(struct atmel_qspi *aq) -@@ -1479,9 +1460,6 @@ static void atmel_qspi_remove(struct pla - - ret = pm_runtime_get_sync(&pdev->dev); - if (ret >= 0) { -- if (aq->caps->has_dma) -- atmel_qspi_dma_release(aq); -- - if (aq->caps->has_gclk) { - ret = atmel_qspi_sama7g5_suspend(aq); - if (ret) diff --git a/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch b/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch deleted file mode 100644 index 07450619e2..0000000000 --- a/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 0f52d98240cdce03944c967d4fe4faab032f8f57 Mon Sep 17 00:00:00 2001 -From: Varshini Rajendran -Date: Mon, 8 Sep 2025 09:44:18 +0530 -Subject: [PATCH 109/112] spi: atmel-quadspi: add padcalib, 2xgclk, and dllon - capabilities - -Introduce capability flags for SoC-specific variations of the QuadSPI -controller: - - - has_padcalib: controller supports pad calibration - - has_2xgclk: requires GCLK at half the data rate (2x clocking) - - has_dllon: controller supports DLL clock - -Set `has_padcalib` for Octal controllers that provide pad calibration -support. Use `has_2xgclk` for controllers that require the GCLK to run -at twice the data rate. Differentiate SoC integration variants with the -`has_dllon` flag and set it as needed. - -Signed-off-by: Varshini Rajendran -Signed-off-by: Dharma Balasubiramani -Link: https://patch.msgid.link/20250908-microchip-qspi-v2-3-8f3d69fdd5c9@microchip.com -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 92 ++++++++++++++++++++++++------------- - 1 file changed, 60 insertions(+), 32 deletions(-) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -262,6 +262,9 @@ struct atmel_qspi_caps { - bool has_ricr; - bool octal; - bool has_dma; -+ bool has_2xgclk; -+ bool has_padcalib; -+ bool has_dllon; - }; - - struct atmel_qspi_ops; -@@ -1028,13 +1031,25 @@ static int atmel_qspi_set_pad_calibratio - aq, QSPI_PCALCFG); - - /* DLL On + start calibration. */ -- atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); -+ if (aq->caps->has_dllon) -+ atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); -+ /* If there is no DLL support only start calibration. */ -+ else -+ atmel_qspi_write(QSPI_CR_STPCAL, aq, QSPI_CR); - -- /* Check synchronization status before updating configuration. */ -- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -- (val & QSPI_SR2_DLOCK) && -- !(val & QSPI_SR2_CALBSY), 40, -- ATMEL_QSPI_TIMEOUT); -+ /* -+ * Check DLL clock lock and synchronization status before updating -+ * configuration. -+ */ -+ if (aq->caps->has_dllon) -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ (val & QSPI_SR2_DLOCK) && -+ !(val & QSPI_SR2_CALBSY), 40, -+ ATMEL_QSPI_TIMEOUT); -+ else -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_CALBSY), 40, -+ ATMEL_QSPI_TIMEOUT); - - /* Refresh analogic blocks every 1 ms.*/ - atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, -@@ -1050,23 +1065,28 @@ static int atmel_qspi_set_gclk(struct at - int ret; - - /* Disable DLL before setting GCLK */ -- status = atmel_qspi_read(aq, QSPI_SR2); -- if (status & QSPI_SR2_DLOCK) { -- atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -+ if (aq->caps->has_dllon) { -+ status = atmel_qspi_read(aq, QSPI_SR2); -+ if (status & QSPI_SR2_DLOCK) { -+ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_DLOCK), 40, -+ ATMEL_QSPI_TIMEOUT); -+ if (ret) -+ return ret; -+ } - -- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -- !(val & QSPI_SR2_DLOCK), 40, -- ATMEL_QSPI_TIMEOUT); -- if (ret) -- return ret; -+ if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) -+ atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); -+ else -+ atmel_qspi_write(0, aq, QSPI_DLLCFG); - } - -- if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) -- atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); -+ if (aq->caps->has_2xgclk) -+ ret = clk_set_rate(aq->gclk, 2 * aq->target_max_speed_hz); - else -- atmel_qspi_write(0, aq, QSPI_DLLCFG); -+ ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); - -- ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); - if (ret) { - dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); - return ret; -@@ -1089,11 +1109,16 @@ static int atmel_qspi_sama7g5_init(struc - if (ret) - return ret; - -- if (aq->caps->octal) { -+ /* -+ * Check if the SoC supports pad calibration in Octal SPI mode. -+ * Proceed only if both the capabilities are true. -+ */ -+ if (aq->caps->octal && aq->caps->has_padcalib) { - ret = atmel_qspi_set_pad_calibration(aq); - if (ret) - return ret; -- } else { -+ /* Start DLL on only if the SoC supports the same */ -+ } else if (aq->caps->has_dllon) { - atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); - ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, - (val & QSPI_SR2_DLOCK), 40, -@@ -1434,19 +1459,19 @@ static int atmel_qspi_sama7g5_suspend(st - - clk_disable_unprepare(aq->gclk); - -- atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -- !(val & QSPI_SR2_DLOCK), 40, -- ATMEL_QSPI_TIMEOUT); -- if (ret) -- return ret; -- -- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -- !(val & QSPI_SR2_CALBSY), 40, -- ATMEL_QSPI_TIMEOUT); -- if (ret) -- return ret; -+ if (aq->caps->has_dllon) { -+ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); -+ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_DLOCK), 40, -+ ATMEL_QSPI_TIMEOUT); -+ if (ret) -+ return ret; -+ } - -+ if (aq->caps->has_padcalib) -+ return readl_poll_timeout(aq->regs + QSPI_SR2, val, -+ !(val & QSPI_SR2_CALBSY), 40, -+ ATMEL_QSPI_TIMEOUT); - return 0; - } - -@@ -1584,12 +1609,15 @@ static const struct atmel_qspi_caps atme - .has_gclk = true, - .octal = true, - .has_dma = true, -+ .has_padcalib = true, -+ .has_dllon = true, - }; - - static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = { - .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, - .has_gclk = true, - .has_dma = true, -+ .has_dllon = true, - }; - - static const struct of_device_id atmel_qspi_dt_ids[] = { diff --git a/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch b/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch deleted file mode 100644 index a4d9587de9..0000000000 --- a/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch +++ /dev/null @@ -1,58 +0,0 @@ -From ea6e579557cf85f3b0ed3c94c3e4d69afbcba46c Mon Sep 17 00:00:00 2001 -From: Varshini Rajendran -Date: Mon, 8 Sep 2025 09:44:19 +0530 -Subject: [PATCH 110/112] spi: atmel-quadspi: add support for SAM9X7 QSPI - controller - -Add support for the QuadSPI controller found on the SAM9X7 SoC. - -This controller does not implement pad calibration. It supports -operation up to 100 MHz, and requires the GCK to run at twice -the data rate. - -Signed-off-by: Varshini Rajendran -Signed-off-by: Dharma Balasubiramani -Link: https://patch.msgid.link/20250908-microchip-qspi-v2-4-8f3d69fdd5c9@microchip.com -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -63,6 +63,7 @@ - - #define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 - #define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 -+#define SAM9X7_QSPI_MAX_SPEED_HZ 100000000 - - /* Bitfields in QSPI_CR (Control Register) */ - #define QSPI_CR_QSPIEN BIT(0) -@@ -1604,6 +1605,16 @@ static const struct atmel_qspi_caps atme - .has_ricr = true, - }; - -+static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps = { -+ .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .octal = true, -+ .has_dma = true, -+ .has_2xgclk = true, -+ .has_padcalib = false, -+ .has_dllon = false, -+}; -+ - static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { - .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, - .has_gclk = true, -@@ -1637,6 +1648,10 @@ static const struct of_device_id atmel_q - .compatible = "microchip,sama7g5-qspi", - .data = &atmel_sama7g5_qspi_caps, - }, -+ { -+ .compatible = "microchip,sam9x7-ospi", -+ .data = &atmel_sam9x7_ospi_caps, -+ }, - - { /* sentinel */ } - }; diff --git a/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch b/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch deleted file mode 100644 index 305b75bb8e..0000000000 --- a/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f157bc4635178eccb282031d7c2ba2867bd3274c Mon Sep 17 00:00:00 2001 -From: Varshini Rajendran -Date: Mon, 8 Sep 2025 09:44:20 +0530 -Subject: [PATCH 111/112] spi: atmel-quadspi: Add support for sama7d65 QSPI - -Add support for sama7d65 QSPI controller and define its caps. - -Signed-off-by: Varshini Rajendran -Link: https://patch.msgid.link/20250908-microchip-qspi-v2-5-8f3d69fdd5c9@microchip.com -Signed-off-by: Mark Brown ---- - drivers/spi/atmel-quadspi.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1615,6 +1615,24 @@ static const struct atmel_qspi_caps atme - .has_dllon = false, - }; - -+static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps = { -+ .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .octal = true, -+ .has_dma = true, -+ .has_2xgclk = true, -+ .has_padcalib = true, -+ .has_dllon = false, -+}; -+ -+static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps = { -+ .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .has_dma = true, -+ .has_2xgclk = true, -+ .has_dllon = false, -+}; -+ - static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { - .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, - .has_gclk = true, -@@ -1652,6 +1670,15 @@ static const struct of_device_id atmel_q - .compatible = "microchip,sam9x7-ospi", - .data = &atmel_sam9x7_ospi_caps, - }, -+ { -+ .compatible = "microchip,sama7d65-ospi", -+ .data = &atmel_sama7d65_ospi_caps, -+ }, -+ { -+ .compatible = "microchip,sama7d65-qspi", -+ .data = &atmel_sama7d65_qspi_caps, -+ }, -+ - - { /* sentinel */ } - }; diff --git a/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch b/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch deleted file mode 100644 index 16093394d7..0000000000 --- a/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch +++ /dev/null @@ -1,137 +0,0 @@ -From c9d1b0b54258ba13b567dd116ead3c7c30cba7d8 Mon Sep 17 00:00:00 2001 -From: Daniel Machon -Date: Fri, 3 Oct 2025 14:35:59 +0200 -Subject: [PATCH] net: sparx5/lan969x: fix flooding configuration on bridge - join/leave -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The sparx5 driver programs UC/MC/BC flooding in sparx5_update_fwd() by -unconditionally applying bridge_fwd_mask to all flood PGIDs. Any bridge -topology change that triggers sparx5_update_fwd() (for example enslaving -another port) therefore reinstalls flooding in hardware for already -bridged ports, regardless of their per-port flood flags. - -This results in clobbering of the flood masks, and desynchronization -between software and hardware: the bridge still reports “flood off” for -the port, but hardware has flooding enabled due to unconditional PGID -reprogramming. - -Steps to reproduce: - - $ ip link add br0 type bridge - $ ip link set br0 up - $ ip link set eth0 master br0 - $ ip link set eth0 up - $ bridge link set dev eth0 flood off - $ ip link set eth1 master br0 - $ ip link set eth1 up - -At this point, flooding is silently re-enabled for eth0. Software still -shows “flood off” for eth0, but hardware has flooding enabled. - -To fix this, flooding is now set explicitly during bridge join/leave, -through sparx5_port_attr_bridge_flags(): - - On bridge join, UC/MC/BC flooding is enabled by default. - - On bridge leave, UC/MC/BC flooding is disabled. - - sparx5_update_fwd() no longer touches the flood PGIDs, clobbering - the flood masks, and desynchronizing software and hardware. - - Initialization of the flooding PGIDs have been moved to - sparx5_start(). This is required as flooding PGIDs defaults to - 0x3fffffff in hardware and the initialization was previously handled - in sparx5_update_fwd(), which was removed. - -With this change, user-configured flooding flags persist across bridge -updates and are no longer overridden by sparx5_update_fwd(). - -Fixes: d6fce5141929 ("net: sparx5: add switching support") -Signed-off-by: Daniel Machon -Reviewed-by: Simon Horman -Link: https://patch.msgid.link/20251003-fix-flood-fwd-v1-1-48eb478b2904@microchip.com -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ - .../net/ethernet/microchip/sparx5/sparx5_switchdev.c | 12 ++++++++++++ - drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c | 10 ---------- - 3 files changed, 17 insertions(+), 10 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -709,6 +709,11 @@ static int sparx5_start(struct sparx5 *s - /* Init masks */ - sparx5_update_fwd(sparx5); - -+ /* Init flood masks */ -+ for (int pgid = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); -+ pgid <= sparx5_get_pgid(sparx5, PGID_BCAST); pgid++) -+ sparx5_pgid_clear(sparx5, pgid); -+ - /* CPU copy CPU pgids */ - spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, - ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c -@@ -176,6 +176,7 @@ static int sparx5_port_bridge_join(struc - struct net_device *bridge, - struct netlink_ext_ack *extack) - { -+ struct switchdev_brport_flags flags = {0}; - struct sparx5 *sparx5 = port->sparx5; - struct net_device *ndev = port->ndev; - int err; -@@ -205,6 +206,11 @@ static int sparx5_port_bridge_join(struc - */ - __dev_mc_unsync(ndev, sparx5_mc_unsync); - -+ /* Enable uc/mc/bc flooding */ -+ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; -+ flags.val = flags.mask; -+ sparx5_port_attr_bridge_flags(port, flags); -+ - return 0; - - err_switchdev_offload: -@@ -215,6 +221,7 @@ err_switchdev_offload: - static void sparx5_port_bridge_leave(struct sparx5_port *port, - struct net_device *bridge) - { -+ struct switchdev_brport_flags flags = {0}; - struct sparx5 *sparx5 = port->sparx5; - - switchdev_bridge_port_unoffload(port->ndev, NULL, NULL, NULL); -@@ -234,6 +241,11 @@ static void sparx5_port_bridge_leave(str - - /* Port enters in host more therefore restore mc list */ - __dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync); -+ -+ /* Disable uc/mc/bc flooding */ -+ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; -+ flags.val = 0; -+ sparx5_port_attr_bridge_flags(port, flags); - } - - static int sparx5_port_changeupper(struct net_device *dev, ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -@@ -167,16 +167,6 @@ void sparx5_update_fwd(struct sparx5 *sp - /* Divide up fwd mask in 32 bit words */ - bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS); - -- /* Update flood masks */ -- for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); -- port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) { -- spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); -- if (is_sparx5(sparx5)) { -- spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); -- spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); -- } -- } -- - /* Update SRC masks */ - for (port = 0; port < sparx5->data->consts->n_ports; port++) { - if (test_bit(port, sparx5->bridge_fwd_mask)) { diff --git a/target/linux/microchipsw/patches-6.12/0093-v6.13-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/0093-v6.13-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch deleted file mode 100644 index b95304dc42..0000000000 --- a/target/linux/microchipsw/patches-6.12/0093-v6.13-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e7b012cb4db7253d186fd485ab07c7346c645dab Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 8 Nov 2024 12:22:34 +0100 -Subject: [PATCH] clk: lan966x: make it selectable for ARCH_LAN969X - -LAN969x uses the same LAN966x clock driver so make it selectable for -ARCH_LAN969X. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20241108112355.20251-1-robert.marko@sartura.hr -Signed-off-by: Stephen Boyd ---- - drivers/clk/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -259,7 +259,7 @@ config COMMON_CLK_LAN966X - tristate "Generic Clock Controller driver for LAN966X SoC" - depends on HAS_IOMEM - depends on OF -- depends on SOC_LAN966 || COMPILE_TEST -+ depends on SOC_LAN966 || ARCH_LAN969X || COMPILE_TEST - help - This driver provides support for Generic Clock Controller(GCK) on - LAN966X SoC. GCK generates and supplies clock to various peripherals diff --git a/target/linux/microchipsw/patches-6.12/0094-v6.20-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch b/target/linux/microchipsw/patches-6.12/0094-v6.20-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch deleted file mode 100644 index 85bdd6e97f..0000000000 --- a/target/linux/microchipsw/patches-6.12/0094-v6.20-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d543d3eb06873f0ab8edb0d1f8364e9af93544a0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 31 Oct 2025 13:18:12 +0100 -Subject: [PATCH] phy: sparx5-serdes: make it selectable for ARCH_LAN969X - -LAN969x uses the SparX-5 SERDES driver, so make it selectable for -ARCH_LAN969X. - -Reviewed-by: Daniel Machon -Signed-off-by: Robert Marko -Tested-by: Gabor Juhos -Tested-by: Vladimir Oltean -Link: https://patch.msgid.link/20251031121834.665987-1-robert.marko@sartura.hr -Signed-off-by: Vinod Koul ---- - drivers/phy/microchip/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/microchip/Kconfig -+++ b/drivers/phy/microchip/Kconfig -@@ -6,7 +6,7 @@ - config PHY_SPARX5_SERDES - tristate "Microchip Sparx5 SerDes PHY driver" - select GENERIC_PHY -- depends on ARCH_SPARX5 || COMPILE_TEST -+ depends on ARCH_SPARX5 || ARCH_LAN969X || COMPILE_TEST - depends on OF - depends on HAS_IOMEM - help diff --git a/target/linux/microchipsw/patches-6.12/0095-v6.19-reset-sparx5-add-LAN969x-support.patch b/target/linux/microchipsw/patches-6.12/0095-v6.19-reset-sparx5-add-LAN969x-support.patch deleted file mode 100644 index 154af04e3a..0000000000 --- a/target/linux/microchipsw/patches-6.12/0095-v6.19-reset-sparx5-add-LAN969x-support.patch +++ /dev/null @@ -1,27 +0,0 @@ -From bf919ccfced7d47d14ec2d20ae465e8ae410aee6 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 22 Sep 2025 16:27:29 +0200 -Subject: [PATCH] reset: sparx5: add LAN969x support - -LAN969x uses the same reset configuration as LAN966x, but we need to -allow compiling it when ARCH_LAN969X is selected. - -A fallback compatible to LAN966x will be used. - -Signed-off-by: Robert Marko -Signed-off-by: Philipp Zabel ---- - drivers/reset/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -147,7 +147,7 @@ config RESET_LPC18XX - - config RESET_MCHP_SPARX5 - bool "Microchip Sparx5 reset driver" -- depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST -+ depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || COMPILE_TEST - default y if SPARX5_SWITCH - select MFD_SYSCON - help diff --git a/target/linux/microchipsw/patches-6.12/0096-v6.20-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch b/target/linux/microchipsw/patches-6.12/0096-v6.20-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch deleted file mode 100644 index f9d56a42d6..0000000000 --- a/target/linux/microchipsw/patches-6.12/0096-v6.20-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch +++ /dev/null @@ -1,69 +0,0 @@ -From d3824968dbd9056844bbd5041020a3e28c748558 Mon Sep 17 00:00:00 2001 -From: Tony Han -Date: Wed, 3 Dec 2025 13:11:43 +0100 -Subject: [PATCH] dmaengine: at_xdmac: get the number of DMA channels from - device tree - -In case of kernel runs in non-secure mode, the number of DMA channels can -be got from device tree since the value read from GTYPE register is "0" as -it's always secured. - -As the number of channels can never be negative, update them to the type -"unsigned". - -This is required for LAN969x. - -Signed-off-by: Tony Han -Signed-off-by: Robert Marko -Link: https://patch.msgid.link/20251203121208.1269487-1-robert.marko@sartura.hr -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 26 +++++++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -2259,12 +2259,29 @@ static int __maybe_unused atmel_xdmac_ru - return clk_enable(atxdmac->clk); - } - -+static inline int at_xdmac_get_channel_number(struct platform_device *pdev, -+ u32 reg, u32 *pchannels) -+{ -+ int ret; -+ -+ if (reg) { -+ *pchannels = AT_XDMAC_NB_CH(reg); -+ return 0; -+ } -+ -+ ret = of_property_read_u32(pdev->dev.of_node, "dma-channels", pchannels); -+ if (ret) -+ dev_err(&pdev->dev, "can't get number of channels\n"); -+ -+ return ret; -+} -+ - static int at_xdmac_probe(struct platform_device *pdev) - { - struct at_xdmac *atxdmac; -- int irq, nr_channels, i, ret; -+ int irq, ret; - void __iomem *base; -- u32 reg; -+ u32 nr_channels, i, reg; - - irq = platform_get_irq(pdev, 0); - if (irq < 0) -@@ -2280,7 +2297,10 @@ static int at_xdmac_probe(struct platfor - * of channels to do the allocation. - */ - reg = readl_relaxed(base + AT_XDMAC_GTYPE); -- nr_channels = AT_XDMAC_NB_CH(reg); -+ ret = at_xdmac_get_channel_number(pdev, reg, &nr_channels); -+ if (ret) -+ return ret; -+ - if (nr_channels > AT_XDMAC_MAX_CHAN) { - dev_err(&pdev->dev, "invalid number of channels (%u)\n", - nr_channels); diff --git a/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch b/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch deleted file mode 100644 index d1eccda589..0000000000 --- a/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From fc6aa0e470e092873eddb213d996a8beee86bf4d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 10 Nov 2025 13:42:53 +0100 -Subject: [PATCH] net: sparx5/lan969x: populate netdev of_node - -Populate of_node for the port netdevs, to make the individual ports -of_nodes available in sysfs. - -Signed-off-by: Robert Marko -Link: https://patch.msgid.link/20251110124342.199216-1-robert.marko@sartura.hr -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -396,6 +396,8 @@ static int sparx5_create_port(struct spa - - spx5_port->phylink = phylink; - -+ spx5_port->ndev->dev.of_node = spx5_port->of_node; -+ - return 0; - } - diff --git a/target/linux/microchipsw/patches-6.12/0098-01-v7.1-arm64-dts-microchip-add-LAN969x-clock-header-file.patch b/target/linux/microchipsw/patches-6.12/0098-01-v7.1-arm64-dts-microchip-add-LAN969x-clock-header-file.patch deleted file mode 100644 index 134bbf1c41..0000000000 --- a/target/linux/microchipsw/patches-6.12/0098-01-v7.1-arm64-dts-microchip-add-LAN969x-clock-header-file.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 229eeb0ad913c1bb2dd6027e5983d1e4c409abd0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 2 Mar 2026 12:20:11 +0100 -Subject: [PATCH] arm64: dts: microchip: add LAN969x clock header file - -LAN969x uses hardware clock indexes, so document theses in a header to make -them humanly readable. - -Signed-off-by: Robert Marko -Reviewed-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20260302112153.464422-4-robert.marko@sartura.hr -Signed-off-by: Claudiu Beznea ---- - arch/arm64/boot/dts/microchip/clk-lan9691.h | 24 +++++++++++++++++++++ - 1 file changed, 24 insertions(+) - create mode 100644 arch/arm64/boot/dts/microchip/clk-lan9691.h - ---- /dev/null -+++ b/arch/arm64/boot/dts/microchip/clk-lan9691.h -@@ -0,0 +1,24 @@ -+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ -+ -+#ifndef _DTS_CLK_LAN9691_H -+#define _DTS_CLK_LAN9691_H -+ -+#define GCK_ID_QSPI0 0 -+#define GCK_ID_QSPI2 1 -+#define GCK_ID_SDMMC0 2 -+#define GCK_ID_SDMMC1 3 -+#define GCK_ID_MCAN0 4 -+#define GCK_ID_MCAN1 5 -+#define GCK_ID_FLEXCOM0 6 -+#define GCK_ID_FLEXCOM1 7 -+#define GCK_ID_FLEXCOM2 8 -+#define GCK_ID_FLEXCOM3 9 -+#define GCK_ID_TIMER 10 -+#define GCK_ID_USB_REFCLK 11 -+ -+/* Gate clocks */ -+#define GCK_GATE_USB_DRD 12 -+#define GCK_GATE_MCRAMC 13 -+#define GCK_GATE_HMATRIX 14 -+ -+#endif diff --git a/target/linux/microchipsw/patches-6.12/0098-02-v7.1-arm64-dts-microchip-add-LAN969x-support.patch b/target/linux/microchipsw/patches-6.12/0098-02-v7.1-arm64-dts-microchip-add-LAN969x-support.patch deleted file mode 100644 index 0ec8136a3e..0000000000 --- a/target/linux/microchipsw/patches-6.12/0098-02-v7.1-arm64-dts-microchip-add-LAN969x-support.patch +++ /dev/null @@ -1,508 +0,0 @@ -From 1effec9834710ec417861634c32208edcd2fcb2a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 2 Mar 2026 12:20:12 +0100 -Subject: [PATCH] arm64: dts: microchip: add LAN969x support - -Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI. - -Signed-off-by: Robert Marko -Reviewed-by: Claudiu Beznea -Acked-by: Daniel Machon -Link: https://lore.kernel.org/r/20260302112153.464422-5-robert.marko@sartura.hr -Signed-off-by: Claudiu Beznea ---- - arch/arm64/boot/dts/microchip/lan9691.dtsi | 488 +++++++++++++++++++++ - 1 file changed, 488 insertions(+) - create mode 100644 arch/arm64/boot/dts/microchip/lan9691.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi -@@ -0,0 +1,488 @@ -+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -+/* -+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "clk-lan9691.h" -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ model = "Microchip LAN969x"; -+ compatible = "microchip,lan9691"; -+ interrupt-parent = <&gic>; -+ -+ clocks { -+ fx100_clk: fx100-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <320000000>; -+ }; -+ -+ cpu_clk: cpu-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <1000000000>; -+ }; -+ -+ ddr_clk: ddr-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <600000000>; -+ }; -+ -+ fabric_clk: fabric-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <250000000>; -+ }; -+ }; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ compatible = "arm,cortex-a53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&l2_0>; -+ }; -+ -+ l2_0: l2-cache { -+ compatible = "cache"; -+ cache-level = <2>; -+ cache-unified; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = ; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Secure Phys IRQ */ -+ , /* Non-secure Phys IRQ */ -+ , /* Virt IRQ */ -+ ; /* Hyp IRQ */ -+ }; -+ -+ axi: axi { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ usb: usb@300000 { -+ compatible = "microchip,lan9691-dwc3", "snps,dwc3"; -+ reg = <0x300000 0x80000>; -+ interrupts = ; -+ clocks = <&clks GCK_GATE_USB_DRD>, -+ <&clks GCK_ID_USB_REFCLK>; -+ clock-names = "bus_early", "ref"; -+ assigned-clocks = <&clks GCK_ID_USB_REFCLK>; -+ assigned-clock-rates = <60000000>; -+ maximum-speed = "high-speed"; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ flx0: flexcom@e0040000 { -+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; -+ reg = <0xe0040000 0x100>; -+ ranges = <0x0 0xe0040000 0x800>; -+ clocks = <&clks GCK_ID_FLEXCOM0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "disabled"; -+ -+ usart0: serial@200 { -+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "usart"; -+ atmel,fifo-size = <32>; -+ atmel,usart-mode = ; -+ status = "disabled"; -+ }; -+ -+ spi0: spi@400 { -+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@600 { -+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx1: flexcom@e0044000 { -+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; -+ reg = <0xe0044000 0x100>; -+ ranges = <0x0 0xe0044000 0x800>; -+ clocks = <&clks GCK_ID_FLEXCOM1>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "disabled"; -+ -+ usart1: serial@200 { -+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "usart"; -+ atmel,fifo-size = <32>; -+ atmel,usart-mode = ; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@400 { -+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@600 { -+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>, -+ <&dma AT91_XDMAC_DT_PERID(2)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ trng: rng@e0048000 { -+ compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; -+ reg = <0xe0048000 0x100>; -+ clocks = <&fabric_clk>; -+ status = "disabled"; -+ }; -+ -+ aes: crypto@e004c000 { -+ compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; -+ reg = <0xe004c000 0x100>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(12)>, -+ <&dma AT91_XDMAC_DT_PERID(13)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "aes_clk"; -+ status = "disabled"; -+ }; -+ -+ flx2: flexcom@e0060000 { -+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; -+ reg = <0xe0060000 0x100>; -+ ranges = <0x0 0xe0060000 0x800>; -+ clocks = <&clks GCK_ID_FLEXCOM2>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "disabled"; -+ -+ usart2: serial@200 { -+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>, -+ <&dma AT91_XDMAC_DT_PERID(6)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "usart"; -+ atmel,fifo-size = <32>; -+ atmel,usart-mode = ; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@400 { -+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>, -+ <&dma AT91_XDMAC_DT_PERID(6)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@600 { -+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>, -+ <&dma AT91_XDMAC_DT_PERID(6)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx3: flexcom@e0064000 { -+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; -+ reg = <0xe0064000 0x100>; -+ ranges = <0x0 0xe0064000 0x800>; -+ clocks = <&clks GCK_ID_FLEXCOM3>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "disabled"; -+ -+ usart3: serial@200 { -+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>, -+ <&dma AT91_XDMAC_DT_PERID(8)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "usart"; -+ atmel,fifo-size = <32>; -+ atmel,usart-mode = ; -+ status = "disabled"; -+ }; -+ -+ spi3: spi@400 { -+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>, -+ <&dma AT91_XDMAC_DT_PERID(8)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@600 { -+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>, -+ <&dma AT91_XDMAC_DT_PERID(8)>; -+ dma-names = "tx", "rx"; -+ clocks = <&fabric_clk>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ dma: dma-controller@e0068000 { -+ compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma"; -+ reg = <0xe0068000 0x1000>; -+ interrupts = ; -+ dma-channels = <16>; -+ #dma-cells = <1>; -+ clocks = <&fabric_clk>; -+ clock-names = "dma_clk"; -+ }; -+ -+ sha: crypto@e006c000 { -+ compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; -+ reg = <0xe006c000 0xec>; -+ interrupts = ; -+ dmas = <&dma AT91_XDMAC_DT_PERID(14)>; -+ dma-names = "tx"; -+ clocks = <&fabric_clk>; -+ clock-names = "sha_clk"; -+ status = "disabled"; -+ }; -+ -+ timer: timer@e008c000 { -+ compatible = "snps,dw-apb-timer"; -+ reg = <0xe008c000 0x400>; -+ clocks = <&fabric_clk>; -+ clock-names = "timer"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ watchdog: watchdog@e0090000 { -+ compatible = "snps,dw-wdt"; -+ reg = <0xe0090000 0x1000>; -+ interrupts = ; -+ clocks = <&fabric_clk>; -+ }; -+ -+ cpu_ctrl: syscon@e00c0000 { -+ compatible = "microchip,lan966x-cpu-syscon", "syscon"; -+ reg = <0xe00c0000 0x350>; -+ }; -+ -+ switch: switch@e00c0000 { -+ compatible = "microchip,lan9691-switch"; -+ reg = <0xe00c0000 0x0010000>, -+ <0xe2010000 0x1410000>; -+ reg-names = "cpu", "devices"; -+ interrupt-names = "xtr", "fdma", "ptp"; -+ interrupts = , -+ , -+ ; -+ resets = <&reset 0>; -+ reset-names = "switch"; -+ status = "disabled"; -+ }; -+ -+ clks: clock-controller@e00c00b4 { -+ compatible = "microchip,lan9691-gck"; -+ reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>; -+ #clock-cells = <1>; -+ clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; -+ clock-names = "cpu", "ddr", "sys"; -+ }; -+ -+ reset: reset-controller@e201000c { -+ compatible = "microchip,lan9691-switch-reset", -+ "microchip,lan966x-switch-reset"; -+ reg = <0xe201000c 0x4>; -+ reg-names = "gcb"; -+ #reset-cells = <1>; -+ cpu-syscon = <&cpu_ctrl>; -+ }; -+ -+ gpio: pinctrl@e20100d4 { -+ compatible = "microchip,lan9691-pinctrl"; -+ reg = <0xe20100d4 0xd4>, -+ <0xe2010370 0xa8>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-ranges = <&gpio 0 0 66>; -+ interrupt-controller; -+ interrupts = ; -+ #interrupt-cells = <2>; -+ }; -+ -+ mdio0: mdio@e20101a8 { -+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; -+ reg = <0xe20101a8 0x24>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&fx100_clk>; -+ status = "disabled"; -+ }; -+ -+ mdio1: mdio@e20101cc { -+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; -+ reg = <0xe20101cc 0x24>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&fx100_clk>; -+ status = "disabled"; -+ }; -+ -+ sgpio: gpio@e2010230 { -+ compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; -+ reg = <0xe2010230 0x118>; -+ clocks = <&fx100_clk>; -+ resets = <&reset 0>; -+ reset-names = "switch"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgpio_in: gpio@0 { -+ compatible = "microchip,lan9691-sgpio-bank", -+ "microchip,sparx5-sgpio-bank"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <3>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ }; -+ -+ sgpio_out: gpio@1 { -+ compatible = "microchip,lan9691-sgpio-bank", -+ "microchip,sparx5-sgpio-bank"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <3>; -+ }; -+ }; -+ -+ tmon: hwmon@e2020100 { -+ compatible = "microchip,lan9691-temp", "microchip,sparx5-temp"; -+ reg = <0xe2020100 0xc>; -+ clocks = <&fx100_clk>; -+ #thermal-sensor-cells = <0>; -+ }; -+ -+ serdes: serdes@e3410000 { -+ compatible = "microchip,lan9691-serdes"; -+ reg = <0xe3410000 0x150000>; -+ #phy-cells = <1>; -+ clocks = <&fabric_clk>; -+ }; -+ -+ gic: interrupt-controller@e8c11000 { -+ compatible = "arm,gic-400"; -+ reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */ -+ <0xe8c12000 0x2000>, /* CPU interface GICC_ */ -+ <0xe8c14000 0x2000>, /* Virt interface control */ -+ <0xe8c16000 0x2000>; /* Virt CPU interface */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ }; -+}; diff --git a/target/linux/microchipsw/patches-6.12/0098-03-v7.1-arm64-dts-microchip-add-EV23X71A-board.patch b/target/linux/microchipsw/patches-6.12/0098-03-v7.1-arm64-dts-microchip-add-EV23X71A-board.patch deleted file mode 100644 index 5d766278b0..0000000000 --- a/target/linux/microchipsw/patches-6.12/0098-03-v7.1-arm64-dts-microchip-add-EV23X71A-board.patch +++ /dev/null @@ -1,786 +0,0 @@ -From 711cca0f1cfef57018654b969da4041c2bab68d3 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 2 Mar 2026 12:20:14 +0100 -Subject: [PATCH] arm64: dts: microchip: add EV23X71A board - -Microchip EV23X71A is an LAN9696 based evaluation board. - -Signed-off-by: Robert Marko -Reviewed-by: Claudiu Beznea -Acked-by: Daniel Machon -Tested-by: Daniel Machon -Link: https://lore.kernel.org/r/20260302112153.464422-7-robert.marko@sartura.hr -Signed-off-by: Claudiu Beznea ---- - arch/arm64/boot/dts/microchip/Makefile | 1 + - .../boot/dts/microchip/lan9696-ev23x71a.dts | 756 ++++++++++++++++++ - 2 files changed, 757 insertions(+) - create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts - ---- a/arch/arm64/boot/dts/microchip/Makefile -+++ b/arch/arm64/boot/dts/microchip/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_LAN969X) += lan9696-ev23x71a.dtb - dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb - dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb - dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts -@@ -0,0 +1,756 @@ -+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -+/* -+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include "lan9691.dtsi" -+ -+/ { -+ model = "Microchip EV23X71A"; -+ compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691"; -+ -+ aliases { -+ serial0 = &usart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&gpio 60 GPIO_ACTIVE_LOW>; -+ open-source; -+ priority = <200>; -+ }; -+ -+ i2c-mux { -+ compatible = "i2c-mux-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c-parent = <&i2c3>; -+ idle-state = <0x8>; -+ mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, -+ <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, -+ <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; -+ settle-time-us = <100>; -+ -+ i2c_sfp0: i2c@0 { -+ reg = <0x0>; -+ }; -+ -+ i2c_sfp1: i2c@1 { -+ reg = <0x1>; -+ }; -+ -+ i2c_sfp2: i2c@2 { -+ reg = <0x2>; -+ }; -+ -+ i2c_sfp3: i2c@3 { -+ reg = <0x3>; -+ }; -+ -+ i2c_poe: i2c@7 { -+ reg = <0x7>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-status { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio 61 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-sfp1-green { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <0>; -+ gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp1-yellow { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <0>; -+ gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp2-green { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <1>; -+ gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp2-yellow { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <1>; -+ gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp3-green { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <2>; -+ gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp3-yellow { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <2>; -+ gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp4-green { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <3>; -+ gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led-sfp4-yellow { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <3>; -+ gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ }; -+ -+ mux-controller { -+ compatible = "gpio-mux"; -+ #mux-control-cells = <0>; -+ mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, -+ <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sfp0: sfp0 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp0>; -+ tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; -+ los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; -+ tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ sfp1: sfp1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; -+ los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; -+ tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ sfp2: sfp2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; -+ los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; -+ tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ sfp3: sfp3 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp3>; -+ tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; -+ los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; -+ tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&gpio { -+ emmc_sd_pins: emmc-sd-pins { -+ /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ -+ pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", -+ "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", -+ "GPIO_22", "GPIO_23", "GPIO_24"; -+ function = "emmc_sd"; -+ }; -+ -+ fan_pins: fan-pins { -+ pins = "GPIO_25", "GPIO_26"; -+ function = "fan"; -+ }; -+ -+ fc0_pins: fc0-pins { -+ pins = "GPIO_3", "GPIO_4"; -+ function = "fc"; -+ }; -+ -+ fc2_pins: fc2-pins { -+ pins = "GPIO_64", "GPIO_65", "GPIO_66"; -+ function = "fc"; -+ }; -+ -+ fc3_pins: fc3-pins { -+ pins = "GPIO_55", "GPIO_56"; -+ function = "fc"; -+ }; -+ -+ mdio_irq_pins: mdio-irq-pins { -+ pins = "GPIO_11"; -+ function = "miim_irq"; -+ }; -+ -+ mdio_pins: mdio-pins { -+ pins = "GPIO_9", "GPIO_10"; -+ function = "miim"; -+ }; -+ -+ ptp_ext_pins: ptp-ext-pins { -+ pins = "GPIO_59"; -+ function = "ptpsync_5"; -+ }; -+ -+ ptp_out_pins: ptp-out-pins { -+ pins = "GPIO_58"; -+ function = "ptpsync_4"; -+ }; -+ -+ sgpio_pins: sgpio-pins { -+ /* SCK, D0, D1, LD */ -+ pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; -+ function = "sgpio_a"; -+ }; -+ -+ usb_over_pins: usb-over-pins { -+ pins = "GPIO_13"; -+ function = "usb_over_detect"; -+ }; -+ -+ usb_power_pins: usb-power-pins { -+ pins = "GPIO_1"; -+ function = "usb_power"; -+ }; -+ -+ usb_rst_pins: usb-rst-pins { -+ pins = "GPIO_12"; -+ function = "usb2phy_rst"; -+ }; -+ -+ usb_ulpi_pins: usb-ulpi-pins { -+ pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", -+ "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", -+ "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; -+ function = "usb_ulpi"; -+ }; -+}; -+ -+&flx0 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+}; -+ -+&flx2 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+}; -+ -+&flx3 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+}; -+ -+&i2c3 { -+ pinctrl-0 = <&fc3_pins>; -+ pinctrl-names = "default"; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ i2c-sda-hold-time-ns = <1500>; -+ status = "okay"; -+}; -+ -+&mdio0 { -+ pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; -+ pinctrl-names = "default"; -+ reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ phy3: phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy4: phy@4 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy5: phy@5 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <5>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy6: phy@6 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <6>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy7: phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy8: phy@8 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <8>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy9: phy@9 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <9>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy10: phy@10 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <10>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy11: phy@11 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <11>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy12: phy@12 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <12>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy13: phy@13 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <13>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy14: phy@14 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <14>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy15: phy@15 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <15>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy16: phy@16 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <16>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy17: phy@17 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <17>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy18: phy@18 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <18>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy19: phy@19 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <19>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy20: phy@20 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <20>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy21: phy@21 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <21>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy22: phy@22 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <22>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy23: phy@23 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <23>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy24: phy@24 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <24>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy25: phy@25 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <25>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy26: phy@26 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <26>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+ -+ phy27: phy@27 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <27>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio>; -+ }; -+}; -+ -+&serdes { -+ status = "okay"; -+}; -+ -+&sgpio { -+ pinctrl-0 = <&sgpio_pins>; -+ pinctrl-names = "default"; -+ microchip,sgpio-port-ranges = <0 1>, <6 9>; -+ status = "okay"; -+ -+ gpio@0 { -+ ngpios = <128>; -+ }; -+ gpio@1 { -+ ngpios = <128>; -+ }; -+}; -+ -+&spi2 { -+ pinctrl-0 = <&fc2_pins>; -+ pinctrl-names = "default"; -+ cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&switch { -+ pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ ethernet-ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port0: port@0 { -+ reg = <0>; -+ phy-handle = <&phy4>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 0>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port1: port@1 { -+ reg = <1>; -+ phy-handle = <&phy5>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 0>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port2: port@2 { -+ reg = <2>; -+ phy-handle = <&phy6>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 0>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port3: port@3 { -+ reg = <3>; -+ phy-handle = <&phy7>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 0>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port4: port@4 { -+ reg = <4>; -+ phy-handle = <&phy8>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 1>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port5: port@5 { -+ reg = <5>; -+ phy-handle = <&phy9>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 1>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port6: port@6 { -+ reg = <6>; -+ phy-handle = <&phy10>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 1>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port7: port@7 { -+ reg = <7>; -+ phy-handle = <&phy11>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 1>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port8: port@8 { -+ reg = <8>; -+ phy-handle = <&phy12>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 2>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port9: port@9 { -+ reg = <9>; -+ phy-handle = <&phy13>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 2>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port10: port@10 { -+ reg = <10>; -+ phy-handle = <&phy14>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 2>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port11: port@11 { -+ reg = <11>; -+ phy-handle = <&phy15>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 2>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port12: port@12 { -+ reg = <12>; -+ phy-handle = <&phy16>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 3>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port13: port@13 { -+ reg = <13>; -+ phy-handle = <&phy17>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 3>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port14: port@14 { -+ reg = <14>; -+ phy-handle = <&phy18>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 3>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port15: port@15 { -+ reg = <15>; -+ phy-handle = <&phy19>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 3>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port16: port@16 { -+ reg = <16>; -+ phy-handle = <&phy20>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 4>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port17: port@17 { -+ reg = <17>; -+ phy-handle = <&phy21>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 4>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port18: port@18 { -+ reg = <18>; -+ phy-handle = <&phy22>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 4>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port19: port@19 { -+ reg = <19>; -+ phy-handle = <&phy23>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 4>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port20: port@20 { -+ reg = <20>; -+ phy-handle = <&phy24>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 5>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port21: port@21 { -+ reg = <21>; -+ phy-handle = <&phy25>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 5>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port22: port@22 { -+ reg = <22>; -+ phy-handle = <&phy26>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 5>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port23: port@23 { -+ reg = <23>; -+ phy-handle = <&phy27>; -+ phy-mode = "qsgmii"; -+ phys = <&serdes 5>; -+ microchip,bandwidth = <1000>; -+ }; -+ -+ port24: port@24 { -+ reg = <24>; -+ phys = <&serdes 6>; -+ phy-mode = "10gbase-r"; -+ sfp = <&sfp0>; -+ managed = "in-band-status"; -+ microchip,bandwidth = <10000>; -+ microchip,sd-sgpio = <24>; -+ }; -+ -+ port25: port@25 { -+ reg = <25>; -+ phys = <&serdes 7>; -+ phy-mode = "10gbase-r"; -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ microchip,bandwidth = <10000>; -+ microchip,sd-sgpio = <28>; -+ }; -+ -+ port26: port@26 { -+ reg = <26>; -+ phys = <&serdes 8>; -+ phy-mode = "10gbase-r"; -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ microchip,bandwidth = <10000>; -+ microchip,sd-sgpio = <32>; -+ }; -+ -+ port27: port@27 { -+ reg = <27>; -+ phys = <&serdes 9>; -+ phy-mode = "10gbase-r"; -+ sfp = <&sfp3>; -+ managed = "in-band-status"; -+ microchip,bandwidth = <10000>; -+ microchip,sd-sgpio = <36>; -+ }; -+ -+ port29: port@29 { -+ reg = <29>; -+ phy-handle = <&phy3>; -+ phy-mode = "rgmii-id"; -+ microchip,bandwidth = <1000>; -+ }; -+ }; -+}; -+ -+&tmon { -+ pinctrl-0 = <&fan_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&usart0 { -+ pinctrl-0 = <&fc0_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&usb { -+ pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; diff --git a/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch deleted file mode 100644 index 6648f5fa3b..0000000000 --- a/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2d275ce15f57f3b61fdb06d65b7d159e9581203b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 5 Nov 2024 17:57:37 +0100 -Subject: [PATCH] hwmon: sparx5: make it selectable for ARCH_MICROCHIP - -LAN969x uses the same sensor and driver, so make it selectable for -ARCH_MICROCHIP. - -Signed-off-by: Robert Marko ---- - drivers/hwmon/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -602,7 +602,7 @@ config SENSORS_I5K_AMB - - config SENSORS_SPARX5 - tristate "Sparx5 SoC temperature sensor" -- depends on ARCH_SPARX5 || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - help - If you say yes here you get support for temperature monitoring - with the Microchip Sparx5 SoC. diff --git a/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch b/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch deleted file mode 100644 index adf01f2876..0000000000 --- a/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch +++ /dev/null @@ -1,66 +0,0 @@ -From de3bcf0068734c5076695dd8a6f7dd400c2abc2d Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 30 Mar 2020 13:32:37 +0300 -Subject: [PATCH 084/110] mmc: sdhci-of-at91: implement quirk: SDCLK stop while - reset and switch - -SAMA7G5 SDMMC HW block needs to have SDCLK stopped while resetting the -IP and changing UHS mode. -Implement this quirk. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -101,6 +101,11 @@ static void sdhci_at91_set_uhs_signaling - unsigned int timing) - { - u8 mc1r; -+ u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ /* SDCLK must be disabled while changing the mode */ -+ if (clk & SDHCI_CLOCK_CARD_EN) -+ sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, -+ SDHCI_CLOCK_CONTROL); - - if (timing == MMC_TIMING_MMC_DDR52) { - mc1r = sdhci_readb(host, SDMMC_MC1R); -@@ -108,6 +113,12 @@ static void sdhci_at91_set_uhs_signaling - sdhci_writeb(host, mc1r, SDMMC_MC1R); - } - sdhci_set_uhs_signaling(host, timing); -+ -+ /* reenable SDCLK */ -+ if (clk & SDHCI_CLOCK_CARD_EN) { -+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ sdhci_writew(host, clk | SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); -+ } - } - - static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) -@@ -115,9 +126,21 @@ static void sdhci_at91_reset(struct sdhc - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); - unsigned int tmp; -+ u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ -+ /* SDCLK must be disabled while resetting the HW block */ -+ if (clk & SDHCI_CLOCK_CARD_EN) -+ sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, -+ SDHCI_CLOCK_CONTROL); - - sdhci_reset(host, mask); - -+ /* reenable SDCLK */ -+ if (clk & SDHCI_CLOCK_CARD_EN) { -+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ sdhci_writew(host, clk | SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); -+ } -+ - if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) - || mmc_gpio_get_cd(host->mmc) >= 0) - sdhci_at91_set_force_card_detect(host); diff --git a/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch b/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch deleted file mode 100644 index 5f0f0f888c..0000000000 --- a/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch +++ /dev/null @@ -1,58 +0,0 @@ -From d471f0bf01a95c04d0bc1d907aba73db54877cbb Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Wed, 1 Jul 2020 16:17:36 +0300 -Subject: [PATCH 085/110] mmc: sdhci-of-at91: add hw_reset callback - -Add hardware reset callback that can reset an eMMC. -This is only used in combination with specific DT property cap-mmc-hw-reset. -It uses the MC1R register to enable and disable the reset pin. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -25,6 +25,7 @@ - - #define SDMMC_MC1R 0x204 - #define SDMMC_MC1R_DDR BIT(3) -+#define SDMMC_MC1R_RSTN BIT(6) - #define SDMMC_MC1R_FCD BIT(7) - #define SDMMC_CACR 0x230 - #define SDMMC_CACR_CAPWREN BIT(0) -@@ -157,12 +158,31 @@ static void sdhci_at91_reset(struct sdhc - } - } - -+static void sdhci_at91_hw_reset(struct sdhci_host *host) -+{ -+ u8 mc1r; -+ -+ mc1r = readb(host->ioaddr + SDMMC_MC1R); -+ -+ mc1r |= SDMMC_MC1R_RSTN; -+ writeb(mc1r, host->ioaddr + SDMMC_MC1R); -+ -+ udelay(10); -+ -+ mc1r &= ~SDMMC_MC1R_RSTN; -+ writeb(mc1r, host->ioaddr + SDMMC_MC1R); -+ -+ /* JEDEC specifies a minimum of 200us for tRSCA (reset to command) */ -+ usleep_range(200, 500); -+} -+ - static const struct sdhci_ops sdhci_at91_sama5d2_ops = { - .set_clock = sdhci_at91_set_clock, - .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_at91_reset, - .set_uhs_signaling = sdhci_at91_set_uhs_signaling, - .set_power = sdhci_set_power_and_bus_voltage, -+ .hw_reset = sdhci_at91_hw_reset, - }; - - static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { diff --git a/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch b/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch deleted file mode 100644 index 2e72783fb7..0000000000 --- a/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 31cf8b12619925d2229f1f7dfbed7025372acf24 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Wed, 1 Jul 2020 16:30:33 +0300 -Subject: [PATCH 086/110] mmc: sdhci-of-at91: add compatible to sama7g5 SoC - -Add compatible and support for sama7g5 SDMMC block. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -40,6 +40,8 @@ struct sdhci_at91_soc_data { - const struct sdhci_pltfm_data *pdata; - bool baseclk_is_generated_internally; - unsigned int divider_for_baseclk; -+ unsigned int max_sdr104_clk; -+ bool hs200_broken; - }; - - struct sdhci_at91_priv { -@@ -192,6 +194,8 @@ static const struct sdhci_pltfm_data sdh - static const struct sdhci_at91_soc_data soc_data_sama5d2 = { - .pdata = &sdhci_sama5d2_pdata, - .baseclk_is_generated_internally = false, -+ .max_sdr104_clk = 120000000, -+ .hs200_broken = true, - }; - - static const struct sdhci_at91_soc_data soc_data_sam9x60 = { -@@ -200,9 +204,17 @@ static const struct sdhci_at91_soc_data - .divider_for_baseclk = 2, - }; - -+static const struct sdhci_at91_soc_data soc_data_sama7g5 = { -+ .pdata = &sdhci_sama5d2_pdata, -+ .baseclk_is_generated_internally = true, -+ .divider_for_baseclk = 2, -+ .max_sdr104_clk = 200000000, -+}; -+ - static const struct of_device_id sdhci_at91_dt_match[] = { - { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, - { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, -+ { .compatible = "microchip,sama7g5-sdhci", .data = &soc_data_sama7g5 }, - {} - }; - MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); -@@ -259,7 +271,7 @@ static int sdhci_at91_set_clks_presets(s - preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; - writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, - host->ioaddr + SDHCI_PRESET_FOR_SDR50); -- preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; -+ preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; - writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, - host->ioaddr + SDHCI_PRESET_FOR_SDR104); - preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; -@@ -425,8 +437,9 @@ static int sdhci_at91_probe(struct platf - pm_runtime_set_autosuspend_delay(&pdev->dev, 50); - pm_runtime_use_autosuspend(&pdev->dev); - -- /* HS200 is broken at this moment */ -- host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -+ /* check if HS200 is broken on this platform */ -+ if (priv->soc_data->hs200_broken) -+ host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; - - ret = sdhci_add_host(host); - if (ret) diff --git a/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch b/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch deleted file mode 100644 index 57837a87f5..0000000000 --- a/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 760de36744213a6bdfb84c7b7a51e3eea2e83d6c Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Wed, 1 Jul 2020 16:43:01 +0300 -Subject: [PATCH 087/110] mmc: sdhci-of-at91: add support for HS400 and HS400ES - -Add support for HS400 and HS400ES timings. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 45 +++++++++++++++++++++++++++----- - 1 file changed, 39 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -27,6 +27,9 @@ - #define SDMMC_MC1R_DDR BIT(3) - #define SDMMC_MC1R_RSTN BIT(6) - #define SDMMC_MC1R_FCD BIT(7) -+#define SDMMC_MC3R 0x206 -+#define SDMMC_MC3R_HS400EN BIT(0) -+#define SDMMC_MC3R_ESMEN BIT(1) - #define SDMMC_CACR 0x230 - #define SDMMC_CACR_CAPWREN BIT(0) - #define SDMMC_CACR_KEY (0x46 << 8) -@@ -103,18 +106,32 @@ static void sdhci_at91_set_clock(struct - static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, - unsigned int timing) - { -- u8 mc1r; -- u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ u16 clk; -+ u8 mc3r, mc1r; -+ -+ mc1r = readb(host->ioaddr + SDMMC_MC1R); -+ mc3r = readb(host->ioaddr + SDMMC_MC3R); -+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+ - /* SDCLK must be disabled while changing the mode */ - if (clk & SDHCI_CLOCK_CARD_EN) - sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, - SDHCI_CLOCK_CONTROL); - -- if (timing == MMC_TIMING_MMC_DDR52) { -- mc1r = sdhci_readb(host, SDMMC_MC1R); -+ if (timing == MMC_TIMING_MMC_DDR52 || timing == MMC_TIMING_MMC_HS400) - mc1r |= SDMMC_MC1R_DDR; -- sdhci_writeb(host, mc1r, SDMMC_MC1R); -- } -+ else -+ mc1r &= ~SDMMC_MC1R_DDR; -+ -+ sdhci_writeb(host, mc1r, SDMMC_MC1R); -+ -+ if (timing == MMC_TIMING_MMC_HS400) -+ mc3r |= SDMMC_MC3R_HS400EN; -+ else -+ mc3r &= ~SDMMC_MC3R_HS400EN; -+ -+ writeb(mc3r, host->ioaddr + SDMMC_MC3R); -+ - sdhci_set_uhs_signaling(host, timing); - - /* reenable SDCLK */ -@@ -366,6 +383,20 @@ static const struct dev_pm_ops sdhci_at9 - NULL) - }; - -+static void at91_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) -+{ -+ struct sdhci_host *host = mmc_priv(mmc); -+ u8 mc3r; -+ -+ mc3r = readb(host->ioaddr + SDMMC_MC3R); -+ if (ios->enhanced_strobe) -+ mc3r |= SDMMC_MC3R_ESMEN; -+ else -+ mc3r &= ~SDMMC_MC3R_ESMEN; -+ -+ writeb(mc3r, host->ioaddr + SDMMC_MC3R); -+} -+ - static int sdhci_at91_probe(struct platform_device *pdev) - { - const struct sdhci_at91_soc_data *soc_data; -@@ -445,6 +476,8 @@ static int sdhci_at91_probe(struct platf - if (ret) - goto pm_runtime_disable; - -+ host->mmc_host_ops.hs400_enhanced_strobe = at91_sdhci_hs400_enhanced_strobe; -+ - /* - * When calling sdhci_runtime_suspend_host(), the sdhci layer makes - * the assumption that all the clocks of the controller are disabled. diff --git a/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch b/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch deleted file mode 100644 index 8dab7e7935..0000000000 --- a/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch +++ /dev/null @@ -1,28 +0,0 @@ -From bf303f307373baf222cb130253651b64c5533cf3 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 2 Jun 2020 12:36:13 +0300 -Subject: [PATCH 088/110] sdhci: sdhci-of-at91: issue IP reset at probe - -Issue IP reset at probe time. -This will avoid clock glitches if input clocks are being requested -again. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -417,6 +417,9 @@ static int sdhci_at91_probe(struct platf - priv = sdhci_pltfm_priv(pltfm_host); - priv->soc_data = soc_data; - -+ /* Perform a software reset before using the IP */ -+ sdhci_at91_reset(host, SDHCI_RESET_ALL); -+ - priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); - if (IS_ERR(priv->mainck)) { - if (soc_data->baseclk_is_generated_internally) { diff --git a/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch b/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch deleted file mode 100644 index 85e3398ad9..0000000000 --- a/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 32fa920f5dd8ba4b4ea79f2e9729bd57bed3db1b Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 3 Jul 2020 10:42:37 +0300 -Subject: [PATCH 089/110] mmc: sdhci-of-at91: perform a hardware reset at probe - time - -For eMMC, it may happen that the memory is left by the bootloader in a bad state. -We need to perform a hardware reset by asserting/deasserting the RSTN line. -This will ensure the memory comes out in a clean state. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -419,6 +419,8 @@ static int sdhci_at91_probe(struct platf - - /* Perform a software reset before using the IP */ - sdhci_at91_reset(host, SDHCI_RESET_ALL); -+ /* Perform a hardware reset before using the IP */ -+ sdhci_at91_hw_reset(host); - - priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); - if (IS_ERR(priv->mainck)) { diff --git a/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch b/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch deleted file mode 100644 index a36bf7b6b6..0000000000 --- a/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 01a24658497ed31d5b2de4c686772d27dcd19bbe Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 3 Aug 2020 15:29:37 +0300 -Subject: [PATCH 090/110] mmc: sdhci-of-at91: add preset for HS400 mode - -Add clock and driver strength preset for HS400 mode. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -39,6 +39,9 @@ - - #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ - -+/* drv type A, programmable clock mode */ -+#define SDHCI_AT91_PRESET_DRVA_CONF (SDHCI_AT91_PRESET_COMMON_CONF \ -+ | 0x4000) - struct sdhci_at91_soc_data { - const struct sdhci_pltfm_data *pdata; - bool baseclk_is_generated_internally; -@@ -294,6 +297,9 @@ static int sdhci_at91_set_clks_presets(s - preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; - writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, - host->ioaddr + SDHCI_PRESET_FOR_DDR50); -+ preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; -+ writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, -+ host->ioaddr + SDHCI_PRESET_FOR_HS400); - - clk_prepare_enable(priv->mainck); - clk_prepare_enable(priv->gck); diff --git a/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch b/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch deleted file mode 100644 index 5dffdb5a00..0000000000 --- a/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 23699095b2547a6714efb627783dc18478115328 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 26 Nov 2020 20:15:09 +0200 -Subject: [PATCH 091/110] mmc: sdhci-of-at91: disable selectively clocks on pm - runtime - -SAMA7G5's SDMMC run-time clock disabling is not supported. -Add support to avoid this scenario for SAMA7G5. - -Signed-off-by: Claudiu Beznea -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -48,6 +48,7 @@ struct sdhci_at91_soc_data { - unsigned int divider_for_baseclk; - unsigned int max_sdr104_clk; - bool hs200_broken; -+ bool pm_runtime_disable_clks; - }; - - struct sdhci_at91_priv { -@@ -216,12 +217,14 @@ static const struct sdhci_at91_soc_data - .baseclk_is_generated_internally = false, - .max_sdr104_clk = 120000000, - .hs200_broken = true, -+ .pm_runtime_disable_clks = true, - }; - - static const struct sdhci_at91_soc_data soc_data_sam9x60 = { - .pdata = &sdhci_sama5d2_pdata, - .baseclk_is_generated_internally = true, - .divider_for_baseclk = 2, -+ .pm_runtime_disable_clks = true, - }; - - static const struct sdhci_at91_soc_data soc_data_sama7g5 = { -@@ -336,9 +339,11 @@ static int sdhci_at91_runtime_suspend(st - if (host->tuning_mode != SDHCI_TUNING_MODE_3) - mmc_retune_needed(host->mmc); - -- clk_disable_unprepare(priv->gck); -- clk_disable_unprepare(priv->hclock); -- clk_disable_unprepare(priv->mainck); -+ if (priv->soc_data->pm_runtime_disable_clks) { -+ clk_disable_unprepare(priv->gck); -+ clk_disable_unprepare(priv->hclock); -+ clk_disable_unprepare(priv->mainck); -+ } - - return ret; - } -@@ -359,6 +364,9 @@ static int sdhci_at91_runtime_resume(str - goto out; - } - -+ if (!priv->soc_data->pm_runtime_disable_clks) -+ goto out; -+ - ret = clk_prepare_enable(priv->mainck); - if (ret) { - dev_err(dev, "can't enable mainck\n"); diff --git a/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch b/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch deleted file mode 100644 index d28f55a7d1..0000000000 --- a/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0538f47fa414e52843c75c3cc72790ad0ec196b8 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 20 Sep 2019 12:09:29 +0300 -Subject: [PATCH 092/110] mmc: sdhci-of-at91: do not advertise SDR104 mode - support - -There are several issues with SDR104 mode and tuning so remove it from -the capabilities of the host controller. - -Signed-off-by: Ludovic Desroches -[eugen.hristev@microchip.com: re-pick this commit was removed with upstream patch] -Signed-off-by: Eugen Hristev -Signed-off-by: Tudor Ambarus -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -256,6 +256,18 @@ static int sdhci_at91_set_clks_presets(s - caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); - caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); - -+ /* -+ * We experience some issues with SDR104. If the SD clock is higher -+ * than 100 MHz, we can get data corruption. With a 100 MHz clock, -+ * the tuning procedure may fail. For those reasons, it is useless to -+ * advertise that we can use SDR104 mode, so remove it from -+ * the capabilities. -+ */ -+ writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); -+ caps1 &= (~SDHCI_SUPPORT_SDR104); -+ writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); -+ writel(0, host->ioaddr + SDMMC_CACR); -+ - gck_rate = clk_get_rate(priv->gck); - if (priv->soc_data->baseclk_is_generated_internally) - clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; diff --git a/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch b/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch deleted file mode 100644 index 14742f38e2..0000000000 --- a/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch +++ /dev/null @@ -1,48 +0,0 @@ -From fa79ded408b14cbf687c7139eadce368c0f7003b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 13 Jan 2022 13:18:24 +0200 -Subject: [PATCH 093/110] mmc: sdhci-of-at91: avoid division by zero - -Avoid division by zero and setting invalid values to address pointed -by SDHCI_PRESET_FOR_SDR104. - -Fixes: bac9f2f1caa5 ("mmc: sdhci-of-at91: add preset for HS400 mode") -Fixes: d85a06913358 ("mmc: sdhci-of-at91: add compatible to sama7g5 SoC") -Signed-off-by: Claudiu Beznea -Reviewed-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -306,15 +306,21 @@ static int sdhci_at91_set_clks_presets(s - preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; - writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, - host->ioaddr + SDHCI_PRESET_FOR_SDR50); -- preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; -- writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, -- host->ioaddr + SDHCI_PRESET_FOR_SDR104); -+ if (priv->soc_data->max_sdr104_clk) { -+ preset_div = DIV_ROUND_UP(gck_rate, -+ priv->soc_data->max_sdr104_clk) - 1; -+ writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, -+ host->ioaddr + SDHCI_PRESET_FOR_SDR104); -+ } - preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; - writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, - host->ioaddr + SDHCI_PRESET_FOR_DDR50); -- preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; -- writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, -- host->ioaddr + SDHCI_PRESET_FOR_HS400); -+ if (priv->soc_data->max_sdr104_clk) { -+ preset_div = DIV_ROUND_UP(gck_rate, -+ priv->soc_data->max_sdr104_clk) - 1; -+ writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, -+ host->ioaddr + SDHCI_PRESET_FOR_HS400); -+ } - - clk_prepare_enable(priv->mainck); - clk_prepare_enable(priv->gck); diff --git a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch deleted file mode 100644 index 5f74ac87e4..0000000000 --- a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch +++ /dev/null @@ -1,24 +0,0 @@ -From f1f3703830bfc8d35e1535f78f38a4b5799f0e99 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 19 Dec 2022 12:52:00 +0200 -Subject: [PATCH 095/110] mmc: sdhci-of-at91: add sama7g5 required quirks - -Add quirks for sama7g5 product - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -232,6 +232,7 @@ static const struct sdhci_at91_soc_data - .baseclk_is_generated_internally = true, - .divider_for_baseclk = 2, - .max_sdr104_clk = 200000000, -+ .quirks2 = SDHCI_QUIRK2_AT91_HS400_PRESET, - }; - - static const struct of_device_id sdhci_at91_dt_match[] = { diff --git a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch deleted file mode 100644 index 69d2562413..0000000000 --- a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 63c7037be0a9c8e1155b78ce6448cc012401e441 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 19 Dec 2022 12:17:42 +0200 -Subject: [PATCH 094/110] mmc: sdhci-of-at91: add soc data field quirks2 - -Add a quirks2 field in the soc_data struct, this replaces -the hs200_broken bool. The purpose is to be able to add multiple -quirks in the soc_data without having bools for each of them. -Storing them in a single variable makes the code cleaner. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/at91/mmc) -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci-of-at91.c | 8 +++----- - 1 file changed, 3 insertions(+), 5 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -47,8 +47,8 @@ struct sdhci_at91_soc_data { - bool baseclk_is_generated_internally; - unsigned int divider_for_baseclk; - unsigned int max_sdr104_clk; -- bool hs200_broken; - bool pm_runtime_disable_clks; -+ u32 quirks2; - }; - - struct sdhci_at91_priv { -@@ -216,8 +216,8 @@ static const struct sdhci_at91_soc_data - .pdata = &sdhci_sama5d2_pdata, - .baseclk_is_generated_internally = false, - .max_sdr104_clk = 120000000, -- .hs200_broken = true, - .pm_runtime_disable_clks = true, -+ .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, - }; - - static const struct sdhci_at91_soc_data soc_data_sam9x60 = { -@@ -506,9 +506,7 @@ static int sdhci_at91_probe(struct platf - pm_runtime_set_autosuspend_delay(&pdev->dev, 50); - pm_runtime_use_autosuspend(&pdev->dev); - -- /* check if HS200 is broken on this platform */ -- if (priv->soc_data->hs200_broken) -- host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -+ host->quirks2 |= priv->soc_data->quirks2; - - ret = sdhci_add_host(host); - if (ret) diff --git a/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch b/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch deleted file mode 100644 index 8c72d543e6..0000000000 --- a/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 87ec8e4cb7d7e13d51c351c7e2fcb069081d54c4 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 3 Aug 2020 15:30:49 +0300 -Subject: [PATCH 096/110] mmc: introduce SDHCI_QUIRK2_AT91_HS400_PRESET - -AT91 architecture uses a different HS400 preset register offset. - -Signed-off-by: Eugen Hristev -(cherry picked from linux-6.1-trunk/mmc) -[andrei.simion: increment the value for left shift for - AT91 specific HS400 preset register] -Signed-off-by: Andrei Simion ---- - drivers/mmc/host/sdhci.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/mmc/host/sdhci.h -+++ b/drivers/mmc/host/sdhci.h -@@ -270,6 +270,7 @@ - #define SDHCI_PRESET_FOR_SDR104 0x6C - #define SDHCI_PRESET_FOR_DDR50 0x6E - #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ -+#define SDHCI_PRESET_FOR_HS400_AT91 0x244 /* AT91 specific */ - #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) - #define SDHCI_PRESET_CLKGEN_SEL BIT(10) - #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) -@@ -484,6 +485,10 @@ struct sdhci_host { - #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) - /* Issue CMD and DATA reset together */ - #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) -+/* -+ * AT91 specific HS400 preset register -+ */ -+#define SDHCI_QUIRK2_AT91_HS400_PRESET (1<<20) - - int irq; /* Device IRQ */ - void __iomem *ioaddr; /* Mapped address */ diff --git a/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch b/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch deleted file mode 100644 index 0f5c21ed1d..0000000000 --- a/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d3f47257f94abccd0e0dc61221cd3f36d3c8adfd Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 5 Nov 2024 15:48:27 +0100 -Subject: [PATCH 097/110] mmc: mmc: sdhci-of-at91: add LAN969x - -Add support for LAN969x SoC. - -Signed-off-by: Robert Marko ---- - drivers/mmc/host/sdhci-of-at91.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-at91.c -+++ b/drivers/mmc/host/sdhci-of-at91.c -@@ -235,10 +235,18 @@ static const struct sdhci_at91_soc_data - .quirks2 = SDHCI_QUIRK2_AT91_HS400_PRESET, - }; - -+static const struct sdhci_at91_soc_data soc_data_lan969x = { -+ .pdata = &sdhci_sama5d2_pdata, -+ .max_sdr104_clk = 100000000, -+ .baseclk_is_generated_internally = true, -+ .divider_for_baseclk = 2, -+}; -+ - static const struct of_device_id sdhci_at91_dt_match[] = { - { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, - { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, - { .compatible = "microchip,sama7g5-sdhci", .data = &soc_data_sama7g5 }, -+ { .compatible = "microchip,lan9691-sdhci", .data = &soc_data_lan969x }, - {} - }; - MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); diff --git a/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch b/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch deleted file mode 100644 index cd32fcd8b2..0000000000 --- a/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 9df17cd4cbde177d11fe5b42209cb07a8cc5fd2a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 22 Sep 2025 16:30:16 +0200 -Subject: [PATCH 112/112] spi: atmel-quadspi: Add support for LAN969x QSPI0 - -LAN969x has a similar QSPI0 controller to sama7g5 but with no octal mode -support. - -Sadly, DMA does not currently work and auto refresh must be disabled as -otherwise board will simply freeze. - -Signed-off-by: Robert Marko ---- - drivers/spi/Kconfig | 2 +- - drivers/spi/atmel-quadspi.c | 21 ++++++++++++++++++--- - 2 files changed, 19 insertions(+), 4 deletions(-) - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -147,7 +147,7 @@ config SPI_AT91_USART - - config SPI_ATMEL_QUADSPI - tristate "Atmel Quad SPI Controller" -- depends on ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_MICROCHIP || COMPILE_TEST - depends on OF && HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. ---- a/drivers/spi/atmel-quadspi.c -+++ b/drivers/spi/atmel-quadspi.c -@@ -1053,9 +1053,9 @@ static int atmel_qspi_set_pad_calibratio - ATMEL_QSPI_TIMEOUT); - - /* Refresh analogic blocks every 1 ms.*/ -- atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, -+ /*atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, - aq->target_max_speed_hz / 1000), -- aq, QSPI_REFRESH); -+ aq, QSPI_REFRESH);*/ - - return ret; - } -@@ -1114,7 +1114,7 @@ static int atmel_qspi_sama7g5_init(struc - * Check if the SoC supports pad calibration in Octal SPI mode. - * Proceed only if both the capabilities are true. - */ -- if (aq->caps->octal && aq->caps->has_padcalib) { -+ if (aq->caps->has_padcalib) { - ret = atmel_qspi_set_pad_calibration(aq); - if (ret) - return ret; -@@ -1649,6 +1649,17 @@ static const struct atmel_qspi_caps atme - .has_dllon = true, - }; - -+static const struct atmel_qspi_caps microchip_lan969x_qspi_caps = { -+ .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ, -+ .has_gclk = true, -+ .octal = false, -+ /* It supports using DMA but its currently broken */ -+ .has_dma = false, -+ .has_2xgclk = false, -+ .has_padcalib = true, -+ .has_dllon = true, -+}; -+ - static const struct of_device_id atmel_qspi_dt_ids[] = { - { - .compatible = "atmel,sama5d2-qspi", -@@ -1678,6 +1689,10 @@ static const struct of_device_id atmel_q - .compatible = "microchip,sama7d65-qspi", - .data = &atmel_sama7d65_qspi_caps, - }, -+ { -+ .compatible = "microchip,lan9691-qspi", -+ .data = µchip_lan969x_qspi_caps, -+ }, - - - { /* sentinel */ } diff --git a/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch b/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch deleted file mode 100644 index c317ebdab8..0000000000 --- a/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 7ec8c81eae48ceb1e07a00be65716769827b747e Mon Sep 17 00:00:00 2001 -From: Horatiu Vultur -Date: Wed, 3 Jan 2024 11:10:44 +0100 -Subject: [PATCH] nvmem: lan9662-otp: add support for LAN969x - -Microchip LAN969x provides OTP with the same control logic, only the size -differs as LAN969x has 16KB of OTP instead of 8KB like on LAN966x. - -Signed-off-by: Horatiu Vultur -Signed-off-by: Robert Marko ---- - drivers/nvmem/Kconfig | 2 +- - drivers/nvmem/lan9662-otpc.c | 12 +++++++++--- - 2 files changed, 10 insertions(+), 4 deletions(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -127,7 +127,7 @@ config NVMEM_JZ4780_EFUSE - - config NVMEM_LAN9662_OTPC - tristate "Microchip LAN9662 OTP controller support" -- depends on SOC_LAN966 || COMPILE_TEST -+ depends on SOC_LAN966 || ARCH_LAN969X || COMPILE_TEST - depends on HAS_IOMEM - help - This driver enables the OTP controller available on Microchip LAN9662 ---- a/drivers/nvmem/lan9662-otpc.c -+++ b/drivers/nvmem/lan9662-otpc.c -@@ -27,7 +27,6 @@ - #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1) - #define OTP_OTP_STATUS_OTP_BUSY BIT(0) - --#define OTP_MEM_SIZE 8192 - #define OTP_SLEEP_US 10 - #define OTP_TIMEOUT_US 500000 - -@@ -176,7 +175,6 @@ static struct nvmem_config otp_config = - .word_size = 1, - .reg_read = lan9662_otp_read, - .reg_write = lan9662_otp_write, -- .size = OTP_MEM_SIZE, - }; - - static int lan9662_otp_probe(struct platform_device *pdev) -@@ -196,6 +194,7 @@ static int lan9662_otp_probe(struct plat - - otp_config.priv = otp; - otp_config.dev = dev; -+ otp_config.size = (uintptr_t) device_get_match_data(dev); - - nvmem = devm_nvmem_register(dev, &otp_config); - -@@ -203,7 +202,14 @@ static int lan9662_otp_probe(struct plat - } - - static const struct of_device_id lan9662_otp_match[] = { -- { .compatible = "microchip,lan9662-otpc", }, -+ { -+ .compatible = "microchip,lan9662-otpc", -+ .data = (const void *) SZ_8K, -+ }, -+ { -+ .compatible = "microchip,lan9691-otpc", -+ .data = (const void *) SZ_16K, -+ }, - { }, - }; - MODULE_DEVICE_TABLE(of, lan9662_otp_match); diff --git a/target/linux/microchipsw/patches-6.12/122-arm64-dts-microchip-lan969x-add-QSPI-nodes.patch b/target/linux/microchipsw/patches-6.12/122-arm64-dts-microchip-lan969x-add-QSPI-nodes.patch deleted file mode 100644 index f05ea44dea..0000000000 --- a/target/linux/microchipsw/patches-6.12/122-arm64-dts-microchip-lan969x-add-QSPI-nodes.patch +++ /dev/null @@ -1,51 +0,0 @@ -From a03ebe904b22e0c3f80498fe0dbfc66090552f67 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 25 Sep 2025 22:26:13 +0200 -Subject: [PATCH 122/124] arm64: dts: microchip: lan969x: add QSPI nodes - -Add the required DT nodes for both QSPI controllers. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/microchip/lan9691.dtsi | 30 ++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/arm64/boot/dts/microchip/lan9691.dtsi -+++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi -@@ -391,6 +391,36 @@ - clock-names = "cpu", "ddr", "sys"; - }; - -+ qspi0: spi@e0804000 { -+ compatible = "microchip,lan9691-qspi"; -+ reg = <0xe0804000 0x00000100>, -+ <0x20000000 0x08000000>; -+ reg-names = "qspi_base", "qspi_mmap"; -+ interrupts = ; -+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>; -+ clock-names = "pclk", "gclk"; -+ assigned-clocks = <&clks GCK_ID_QSPI0>; -+ assigned-clock-rates = <100000000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ qspi2: spi@e0834000 { -+ compatible = "microchip,lan9691-qspi"; -+ reg = <0xe0834000 0x00000100>, -+ <0x30000000 0x04000000>; -+ reg-names = "qspi_base", "qspi_mmap"; -+ interrupts = ; -+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>; -+ clock-names = "pclk", "gclk"; -+ assigned-clocks = <&clks GCK_ID_QSPI2>; -+ assigned-clock-rates = <100000000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - reset: reset-controller@e201000c { - compatible = "microchip,lan9691-switch-reset", - "microchip,lan966x-switch-reset"; diff --git a/target/linux/microchipsw/patches-6.12/123-arm64-dts-microchip-lan969x-add-SDMMC-nodes.patch b/target/linux/microchipsw/patches-6.12/123-arm64-dts-microchip-lan969x-add-SDMMC-nodes.patch deleted file mode 100644 index f44ee1d4d1..0000000000 --- a/target/linux/microchipsw/patches-6.12/123-arm64-dts-microchip-lan969x-add-SDMMC-nodes.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 6751906070b6708ede20d896be7d62e19be6ef63 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 25 Sep 2025 22:26:58 +0200 -Subject: [PATCH 123/124] arm64: dts: microchip: lan969x: add SDMMC nodes - -Add nodes for both SDMMC controllers. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/microchip/lan9691.dtsi | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/microchip/lan9691.dtsi -+++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi -@@ -406,6 +406,28 @@ - status = "disabled"; - }; - -+ sdmmc0: mmc@e0830000 { -+ compatible = "microchip,lan9691-sdhci"; -+ reg = <0xe0830000 0x00000300>; -+ interrupts = ; -+ clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>; -+ clock-names = "hclock", "multclk"; -+ assigned-clocks = <&clks GCK_ID_SDMMC0>; -+ assigned-clock-rates = <100000000>; -+ status = "disabled"; -+ }; -+ -+ sdmmc1: mmc@e0838000 { -+ compatible = "microchip,lan9691-sdhci"; -+ reg = <0xe0838000 0x00000300>; -+ interrupts = ; -+ clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>; -+ clock-names = "hclock", "multclk"; -+ assigned-clocks = <&clks GCK_ID_SDMMC1>; -+ assigned-clock-rates = <45000000>; -+ status = "disabled"; -+ }; -+ - qspi2: spi@e0834000 { - compatible = "microchip,lan9691-qspi"; - reg = <0xe0834000 0x00000100>, diff --git a/target/linux/microchipsw/patches-6.12/124-arm64-dts-microchip-lan969x-add-OTP-node.patch b/target/linux/microchipsw/patches-6.12/124-arm64-dts-microchip-lan969x-add-OTP-node.patch deleted file mode 100644 index 48571cd283..0000000000 --- a/target/linux/microchipsw/patches-6.12/124-arm64-dts-microchip-lan969x-add-OTP-node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 477b5c9af4bb7c68bd4ec4807c94dac5a90dcd2f Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 24 Oct 2025 18:46:46 +0200 -Subject: [PATCH 124/124] arm64: dts: microchip: lan969x: add OTP node - -Add the required OTP on LAN969x. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/microchip/lan9691.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/microchip/lan9691.dtsi -+++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi -@@ -100,6 +100,11 @@ - status = "disabled"; - }; - -+ otp: otp@e0021000 { -+ compatible = "microchip,lan9691-otpc"; -+ reg = <0xe0021000 0x1000>; -+ }; -+ - flx0: flexcom@e0040000 { - compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; - reg = <0xe0040000 0x100>; diff --git a/target/linux/microchipsw/patches-6.12/125-arm64-dts-microchip-ev23x71a-enable-QSPI-and-eMMC.patch b/target/linux/microchipsw/patches-6.12/125-arm64-dts-microchip-ev23x71a-enable-QSPI-and-eMMC.patch deleted file mode 100644 index c18ac2ff77..0000000000 --- a/target/linux/microchipsw/patches-6.12/125-arm64-dts-microchip-ev23x71a-enable-QSPI-and-eMMC.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 78c8a6b2d6e98dbd384e93c68779582df04fc32a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 25 Sep 2025 22:27:58 +0200 -Subject: [PATCH] arm64: dts: microchip: ev23x71a: enable QSPI and eMMC - -Add the required nodes for QSPI and eMMC support. - -Signed-off-by: Robert Marko ---- - .../boot/dts/microchip/lan9696-ev23x71a.dts | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts -+++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts -@@ -463,6 +463,33 @@ - }; - }; - -+&qspi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <100000000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ m25p,fast-read; -+ }; -+}; -+ -+&sdmmc0 { -+ pinctrl-0 = <&emmc_sd_pins>; -+ pinctrl-names = "default"; -+ max-frequency = <100000000>; -+ bus-width = <8>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ disable-wp; -+ status = "okay"; -+}; -+ - &serdes { - status = "okay"; - }; diff --git a/target/linux/microchipsw/patches-6.12/126-net-lan969x-correct-RGMII-port-mapping-index.patch b/target/linux/microchipsw/patches-6.12/126-net-lan969x-correct-RGMII-port-mapping-index.patch deleted file mode 100644 index b8aef7e51a..0000000000 --- a/target/linux/microchipsw/patches-6.12/126-net-lan969x-correct-RGMII-port-mapping-index.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 44ed546c4231fbf9d0c92738c2c48c49f8249f48 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 24 Mar 2026 12:02:05 +0100 -Subject: [PATCH 126/130] net: lan969x: correct RGMII port mapping index - -Currently, the lan969x_port_dev_mapping does not check for RGMII ports -and just returns the physical port index. - -However, this does not work for RGMII ports as they have dedicated DEVRGMII -register space with an dedicated instance per RGMII port. - -So, check if requested port index is an RGMII port and return the correct -DEVRGMII index. - -Signed-off-by: Robert Marko ---- - drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -142,6 +142,15 @@ static u32 lan969x_get_dev_mode_bit(stru - - static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) - { -+ if (lan969x_port_is_rgmii(port)) { -+ switch (port) { -+ case 28: -+ return 0; -+ case 29: -+ return 1; -+ } -+ } -+ - if (lan969x_port_is_5g(port)) { - switch (port) { - case 9: diff --git a/target/linux/microchipsw/patches-6.12/127-net-sparx5-add-MTU-change-framework.patch b/target/linux/microchipsw/patches-6.12/127-net-sparx5-add-MTU-change-framework.patch deleted file mode 100644 index 874ac560b3..0000000000 --- a/target/linux/microchipsw/patches-6.12/127-net-sparx5-add-MTU-change-framework.patch +++ /dev/null @@ -1,264 +0,0 @@ -From 372e0295a1dbf0ea4333183ac82b8620bef9c0dc Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 24 Mar 2026 12:19:03 +0100 -Subject: [PATCH 127/130] net: sparx5: add MTU change framework - -Port the MTU change framework from Microchip BSP kernel. -This only wires the generic SparX-5 and LAN969x code. - -SparX-5 and LAN969x specific code to actually change the MTU will follow. - -Signed-off-by: Robert Marko ---- - .../net/ethernet/microchip/sparx5/Makefile | 2 +- - .../ethernet/microchip/sparx5/sparx5_fdma.c | 20 +++ - .../ethernet/microchip/sparx5/sparx5_main.h | 8 ++ - .../microchip/sparx5/sparx5_main_regs.h | 11 ++ - .../ethernet/microchip/sparx5/sparx5_mtu.c | 130 ++++++++++++++++++ - 5 files changed, 170 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_mtu.c - ---- a/drivers/net/ethernet/microchip/sparx5/Makefile -+++ b/drivers/net/ethernet/microchip/sparx5/Makefile -@@ -11,7 +11,7 @@ sparx5-switch-y := sparx5_main.o sparx5 - sparx5_ptp.o sparx5_pgid.o sparx5_tc.o sparx5_qos.o \ - sparx5_vcap_impl.o sparx5_vcap_ag_api.o sparx5_tc_flower.o \ - sparx5_tc_matchall.o sparx5_pool.o sparx5_sdlb.o sparx5_police.o \ -- sparx5_psfp.o sparx5_mirror.o sparx5_regs.o -+ sparx5_psfp.o sparx5_mirror.o sparx5_regs.o sparx5_mtu.o - - sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o - sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -462,6 +462,15 @@ int sparx5_fdma_start(struct sparx5 *spa - sparx5_fdma_rx_activate(sparx5, rx); - sparx5_fdma_tx_activate(sparx5, tx); - -+ for (int i = 0; i < sparx5->data->consts->n_ports; i++) { -+ struct sparx5_port *port = sparx5->ports[i]; -+ -+ if (!port) -+ continue; -+ if (netif_queue_stopped(port->ndev)) -+ netif_wake_queue(port->ndev); -+ } -+ - return 0; - } - -@@ -471,6 +480,7 @@ int sparx5_fdma_stop(struct sparx5 *spar - struct sparx5_tx *tx = &sparx5->tx; - u32 val; - -+ napi_synchronize(&sparx5->rx.napi); - napi_disable(&rx->napi); - - /* Stop the fdma and channel interrupts */ -@@ -482,5 +492,15 @@ int sparx5_fdma_stop(struct sparx5 *spar - FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(val) == 0, - 500, 10000, 0, sparx5); - -+ for (int i = 0; i < sparx5->data->consts->n_ports; i++) { -+ struct sparx5_port *port = sparx5->ports[i]; -+ -+ if (!port) -+ continue; -+ netif_stop_queue(port->ndev); -+ } -+ -+ netif_napi_del(&sparx5->rx.napi); -+ - return 0; - } ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -102,6 +102,7 @@ enum sparx5_feature { - #define PGID_TABLE_SIZE 3290 - - #define IFH_LEN 9 /* 36 bytes */ -+#define IFH_LEN_BYTES (IFH_LEN * sizeof(u32)) - #define NULL_VID 0 - #define SPX5_MACT_PULL_DELAY (2 * HZ) - #define SPX5_STATS_CHECK_DELAY (1 * HZ) -@@ -188,6 +189,7 @@ struct sparx5_tx { - struct sparx5_tx_buf *dbs; - u64 packets; - u64 dropped; -+ u16 max_mtu; - }; - - struct sparx5_port_config { -@@ -348,6 +350,8 @@ struct sparx5_ops { - int (*fdma_poll)(struct napi_struct *napi, int weight); - int (*fdma_xmit)(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, - struct net_device *dev); -+ int (*fdma_resize)(struct sparx5 *sparx5); -+ u32 (*get_mtu)(struct sparx5 *sparx5); - }; - - struct sparx5_main_io_resource { -@@ -712,6 +716,10 @@ void sparx5_mirror_del(struct sparx5_mal - void sparx5_mirror_stats(struct sparx5_mall_entry *entry, - struct flow_stats *fstats); - -+/* sparx5_mtu.c */ -+int sparx5_mtu_change(struct net_device *dev, int new_mtu); -+u32 sparx5_mtu_max(struct sparx5 *sparx5); -+ - /* Clock period in picoseconds */ - static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) - { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h -@@ -8204,6 +8204,17 @@ extern const struct sparx5_regs *regs; - FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) - - /* LAN969X ONLY */ -+/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ -+#define DEVRGMII_MAC_MAXLEN_CFG(t) \ -+ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 8, 0, 1, 4) -+ -+#define DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) -+#define DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ -+ FIELD_PREP(DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN, x) -+#define DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ -+ FIELD_GET(DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN, x) -+ -+/* LAN969X ONLY */ - /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ - #define DEVRGMII_MAC_TAGS_CFG(t) \ - __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4) ---- /dev/null -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mtu.c -@@ -0,0 +1,130 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* Microchip Sparx5 Switch driver -+ * -+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. -+ */ -+ -+#include "sparx5_main.h" -+ -+#define SPX5_HW_MTU(mtu) ((mtu) + ETH_ALEN + IFH_LEN * 4 + ETH_FCS_LEN) -+ -+/* Get the MTU for this port */ -+static u32 sparx5_mtu_get(struct sparx5_port *port) -+{ -+ struct sparx5 *sparx5 = port->sparx5; -+ const struct sparx5_ops *ops = sparx5->data->ops; -+ u32 val; -+ -+ /* We always set 2G5 or RGMII MTU, so there is no point in trying to -+ * read high-speed MAC MTU here -+ */ -+ if (ops->is_port_rgmii(port->portno)) { -+ u32 idx = ops->get_port_dev_index(sparx5, port->portno); -+ val = spx5_rd(sparx5, DEVRGMII_MAC_MAXLEN_CFG(idx)); -+ return DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN_GET(val); -+ } else { -+ val = spx5_rd(sparx5, DEV2G5_MAC_MAXLEN_CFG(port->portno)); -+ return DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(val); -+ } -+} -+ -+/* Set the MTU for this port. */ -+static void sparx5_mtu_set(struct sparx5_port *port, u32 new_mtu) -+{ -+ struct sparx5 *sparx5 = port->sparx5; -+ const struct sparx5_ops *ops; -+ u32 idx, hw_mtu; -+ -+ ops = sparx5->data->ops; -+ idx = ops->get_port_dev_index(sparx5, port->portno); -+ hw_mtu = SPX5_HW_MTU(new_mtu); -+ -+ pr_debug("Setting MTU to: %u for portno (idx: %u): %u\n", new_mtu, -+ port->portno, idx); -+ -+ /* All port modules have a 2g5 shadow device (and DEV2G5 is indexed -+ * by port number). Except the RGMII ports -+ */ -+ if (!ops->is_port_rgmii(port->portno)) -+ spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(hw_mtu), -+ DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, sparx5, -+ DEV2G5_MAC_MAXLEN_CFG(port->portno)); -+ -+ if (ops->is_port_rgmii(port->portno)) -+ spx5_rmw(DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN_SET(hw_mtu), -+ DEVRGMII_MAC_MAXLEN_CFG_MAX_LEN, sparx5, -+ DEVRGMII_MAC_MAXLEN_CFG(idx)); -+ else if (ops->is_port_2g5(port->portno)) -+ return; /* Already configured. */ -+ else if (ops->is_port_5g(port->portno)) -+ spx5_rmw(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(hw_mtu), -+ DEV5G_MAC_MAXLEN_CFG_MAX_LEN, sparx5, -+ DEV5G_MAC_MAXLEN_CFG(idx)); -+ else if (ops->is_port_10g(port->portno)) -+ spx5_rmw(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(hw_mtu), -+ DEV10G_MAC_MAXLEN_CFG_MAX_LEN, sparx5, -+ DEV10G_MAC_MAXLEN_CFG(idx)); -+ else -+ spx5_rmw(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(hw_mtu), -+ DEV25G_MAC_MAXLEN_CFG_MAX_LEN, sparx5, -+ DEV25G_MAC_MAXLEN_CFG(idx)); -+} -+ -+u32 sparx5_mtu_max(struct sparx5 *sparx5) -+{ -+ u32 mtu_max = 0; -+ -+ for (int i = 0; i < sparx5->data->consts->n_ports; i++) { -+ struct sparx5_port *port = sparx5->ports[i]; -+ u32 mtu; -+ -+ if (!port) -+ continue; -+ -+ mtu = sparx5_mtu_get(port) + IFH_LEN_BYTES + -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + -+ VLAN_HLEN * 2 + XDP_PACKET_HEADROOM; -+ -+ if (mtu > mtu_max) -+ mtu_max = mtu; -+ } -+ -+ return mtu_max; -+} -+ -+static int sparx5_mtu_fdma_set(struct sparx5 *sparx5) -+{ -+ const struct sparx5_ops *ops = sparx5->data->ops; -+ u32 mtu_max = sparx5_mtu_max(sparx5); -+ -+ /* We might not be using FDMA */ -+ if (sparx5->fdma_irq <= 0) -+ return 0; -+ -+ /* No need to restart FDMA if the MTU reflects the buffer size */ -+ if (mtu_max == sparx5->tx.max_mtu) -+ return 0; -+ -+ return ops->fdma_resize(sparx5); -+} -+ -+int sparx5_mtu_change(struct net_device *dev, int new_mtu) -+{ -+ struct sparx5_port *port = netdev_priv(dev); -+ struct sparx5 *sparx5 = port->sparx5; -+ int err, orig_mtu = dev->mtu; -+ -+ /* Write MTU to hardware */ -+ sparx5_mtu_set(port, new_mtu); -+ -+ err = sparx5_mtu_fdma_set(sparx5); -+ if (err) { -+ sparx5_mtu_set(port, orig_mtu); -+ return err; -+ } -+ -+ /* Let the stack know */ -+ WRITE_ONCE(dev->mtu, new_mtu); -+ -+ return 0; -+} diff --git a/target/linux/microchipsw/patches-6.12/128-net-sparx5-add-MTU-change.patch b/target/linux/microchipsw/patches-6.12/128-net-sparx5-add-MTU-change.patch deleted file mode 100644 index d628ac8914..0000000000 --- a/target/linux/microchipsw/patches-6.12/128-net-sparx5-add-MTU-change.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 466d22c9d3bdb2feda284c582d4f183879fc57ad Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 24 Mar 2026 12:26:51 +0100 -Subject: [PATCH 128/130] net: sparx5: add MTU change - -Add the required SparX-5 specific code to change the MTU. - -Signed-off-by: Robert Marko ---- - .../ethernet/microchip/sparx5/sparx5_fdma.c | 52 +++++++++++++++++++ - .../ethernet/microchip/sparx5/sparx5_main.c | 2 + - .../ethernet/microchip/sparx5/sparx5_main.h | 1 + - 3 files changed, 55 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c -@@ -278,6 +278,8 @@ static void sparx5_fdma_rx_init(struct s - struct fdma *fdma = &rx->fdma; - int idx; - -+ sparx5->rx.page_order = -+ round_up(sparx5->tx.max_mtu, PAGE_SIZE) / PAGE_SIZE - 1; - fdma->channel_id = channel; - fdma->n_dcbs = FDMA_DCB_MAX; - fdma->n_dbs = FDMA_RX_DCB_MAX_DBS; -@@ -403,6 +405,8 @@ int sparx5_fdma_init(struct sparx5 *spar - { - int err; - -+ sparx5->tx.max_mtu = sparx5->data->ops->get_mtu(sparx5); -+ - /* Reset FDMA state */ - spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); - spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); -@@ -504,3 +508,51 @@ int sparx5_fdma_stop(struct sparx5 *spar - - return 0; - } -+ -+int sparx5_fdma_resize(struct sparx5 *sparx5) -+{ -+ u32 old_mtu = sparx5->tx.max_mtu; -+ struct fdma tx_fdma_old = {0}; -+ struct fdma rx_fdma_old = {0}; -+ int err; -+ -+ memcpy(&tx_fdma_old, &sparx5->tx.fdma, sizeof(struct fdma)); -+ memcpy(&rx_fdma_old, &sparx5->rx.fdma, sizeof(struct fdma)); -+ -+ sparx5_fdma_stop(sparx5); -+ -+ err = sparx5_fdma_init(sparx5); -+ if (err) -+ goto restore; -+ -+ fdma_free_phys(&rx_fdma_old); -+ fdma_free_phys(&tx_fdma_old); -+ -+ goto start; -+ -+restore: -+ -+ /* At this point, the FDMA engine is stopped and the stack is not -+ * calling us for xmit. Restore the old MTU and rx,tx buffers and -+ * restart the engine. -+ */ -+ -+ sparx5->tx.max_mtu = old_mtu; -+ memcpy(&sparx5->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); -+ memcpy(&sparx5->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); -+ -+ /* Old buffers have to be re-initialized. */ -+ -+ fdma_dcbs_init(&sparx5->rx.fdma, -+ FDMA_DCB_INFO_DATAL(sparx5->rx.fdma.db_size), -+ FDMA_DCB_STATUS_INTR); -+ -+ fdma_dcbs_init(&sparx5->tx.fdma, -+ FDMA_DCB_INFO_DATAL(sparx5->tx.fdma.db_size), -+ FDMA_DCB_STATUS_DONE); -+ -+start: -+ sparx5_fdma_start(sparx5); -+ -+ return err; -+} ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c -@@ -1108,6 +1108,8 @@ static const struct sparx5_ops sparx5_op - .fdma_deinit = &sparx5_fdma_deinit, - .fdma_poll = &sparx5_fdma_napi_callback, - .fdma_xmit = &sparx5_fdma_xmit, -+ .fdma_resize = &sparx5_fdma_resize, -+ .get_mtu = &sparx5_mtu_max, - }; - - static const struct sparx5_match_data sparx5_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h -@@ -472,6 +472,7 @@ int sparx5_fdma_xmit(struct sparx5 *spar - irqreturn_t sparx5_fdma_handler(int irq, void *args); - void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma); - void sparx5_fdma_injection_mode(struct sparx5 *sparx5); -+int sparx5_fdma_resize(struct sparx5 *sparx5); - - /* sparx5_mactable.c */ - void sparx5_mact_pull_work(struct work_struct *work); diff --git a/target/linux/microchipsw/patches-6.12/129-net-lan969x-add-MTU-change.patch b/target/linux/microchipsw/patches-6.12/129-net-lan969x-add-MTU-change.patch deleted file mode 100644 index ef89cacd04..0000000000 --- a/target/linux/microchipsw/patches-6.12/129-net-lan969x-add-MTU-change.patch +++ /dev/null @@ -1,126 +0,0 @@ -From b73c8d9fe87d3e35dc09faca85d5a5f9ee8e3f6c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 24 Mar 2026 12:30:45 +0100 -Subject: [PATCH 129/130] net: lan969x: add MTU change - -Add the LAN969x specific code for MTU change. - -Signed-off-by: Robert Marko ---- - .../microchip/sparx5/lan969x/lan969x.c | 2 + - .../microchip/sparx5/lan969x/lan969x.h | 1 + - .../microchip/sparx5/lan969x/lan969x_fdma.c | 60 ++++++++++++++++++- - 3 files changed, 61 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c -@@ -354,6 +354,8 @@ static const struct sparx5_ops lan969x_o - .fdma_deinit = &lan969x_fdma_deinit, - .fdma_poll = &lan969x_fdma_napi_poll, - .fdma_xmit = &lan969x_fdma_xmit, -+ .fdma_resize = lan969x_fdma_resize, -+ .get_mtu = &sparx5_mtu_max, - }; - - const struct sparx5_match_data lan969x_desc = { ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h -@@ -78,5 +78,6 @@ int lan969x_fdma_deinit(struct sparx5 *s - int lan969x_fdma_napi_poll(struct napi_struct *napi, int weight); - int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, - struct net_device *dev); -+int lan969x_fdma_resize(struct sparx5 *sparx5); - - #endif ---- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c -+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c -@@ -154,7 +154,7 @@ static int lan969x_fdma_rx_alloc(struct - int err; - - struct page_pool_params pp_params = { -- .order = 0, -+ .order = rx->page_order, - .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, - .pool_size = fdma->n_dcbs * fdma->n_dbs, - .nid = NUMA_NO_NODE, -@@ -209,12 +209,14 @@ static void lan969x_fdma_rx_init(struct - { - struct fdma *fdma = &sparx5->rx.fdma; - -+ sparx5->rx.page_order = -+ round_up(sparx5->tx.max_mtu, PAGE_SIZE) / PAGE_SIZE - 1; - fdma->channel_id = FDMA_XTR_CHANNEL; - fdma->n_dcbs = FDMA_DCB_MAX; - fdma->n_dbs = 1; - fdma->priv = sparx5; - fdma->size = fdma_get_size(fdma); -- fdma->db_size = PAGE_SIZE; -+ fdma->db_size = PAGE_SIZE << sparx5->rx.page_order; - fdma->ops.dataptr_cb = &lan969x_fdma_rx_dataptr_cb; - fdma->ops.nextptr_cb = &fdma_nextptr_cb; - -@@ -359,6 +361,8 @@ int lan969x_fdma_init(struct sparx5 *spa - struct sparx5_rx *rx = &sparx5->rx; - int err; - -+ sparx5->tx.max_mtu = sparx5->data->ops->get_mtu(sparx5); -+ - lan969x_fdma_rx_init(sparx5); - lan969x_fdma_tx_init(sparx5); - sparx5_fdma_injection_mode(sparx5); -@@ -404,3 +408,55 @@ int lan969x_fdma_deinit(struct sparx5 *s - - return 0; - } -+ -+int lan969x_fdma_resize(struct sparx5 *sparx5) -+{ -+ struct page_pool *page_pool_old = sparx5->rx.page_pool; -+ u32 old_mtu = sparx5->tx.max_mtu; -+ struct fdma tx_fdma_old = {0}; -+ struct fdma rx_fdma_old = {0}; -+ int err; -+ -+ memcpy(&tx_fdma_old, &sparx5->tx.fdma, sizeof(struct fdma)); -+ memcpy(&rx_fdma_old, &sparx5->rx.fdma, sizeof(struct fdma)); -+ -+ sparx5_fdma_stop(sparx5); -+ lan969x_fdma_free_pages(&sparx5->rx); -+ -+ err = lan969x_fdma_init(sparx5); -+ if (err) -+ goto restore; -+ -+ fdma_free_coherent(sparx5->dev, &rx_fdma_old); -+ fdma_free_coherent(sparx5->dev, &tx_fdma_old); -+ page_pool_destroy(page_pool_old); -+ -+ goto start; -+ -+restore: -+ -+ /* At this point, the FDMA engine is stopped and the stack is not -+ * calling us for xmit. Restore the old MTU and rx,tx buffers and -+ * restart the engine. -+ */ -+ -+ sparx5->tx.max_mtu = old_mtu; -+ sparx5->rx.page_pool = page_pool_old; -+ memcpy(&sparx5->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); -+ memcpy(&sparx5->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); -+ -+ /* Old buffers have to be re-initialized. */ -+ -+ fdma_dcbs_init(&sparx5->rx.fdma, -+ FDMA_DCB_INFO_DATAL(sparx5->rx.fdma.db_size), -+ FDMA_DCB_STATUS_INTR); -+ -+ fdma_dcbs_init(&sparx5->tx.fdma, -+ FDMA_DCB_INFO_DATAL(sparx5->tx.fdma.db_size), -+ FDMA_DCB_STATUS_DONE); -+ -+start: -+ sparx5_fdma_start(sparx5); -+ -+ return err; -+} diff --git a/target/linux/microchipsw/patches-6.12/130-net-sparx5-wire-in-MTU-change.patch b/target/linux/microchipsw/patches-6.12/130-net-sparx5-wire-in-MTU-change.patch deleted file mode 100644 index 678b601342..0000000000 --- a/target/linux/microchipsw/patches-6.12/130-net-sparx5-wire-in-MTU-change.patch +++ /dev/null @@ -1,33 +0,0 @@ -From aa92b8a004be460d68aa671c3f8e98373496b199 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 24 Mar 2026 12:32:39 +0100 -Subject: [PATCH 130/130] net: sparx5: wire in MTU change - -Now that both generic and chip specific MTU code is in place, add the -required netdev OP to trigger the MTU change. - -Signed-off-by: Robert Marko ---- - drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c -@@ -259,6 +259,7 @@ static const struct net_device_ops sparx - .ndo_setup_tc = sparx5_port_setup_tc, - .ndo_hwtstamp_get = sparx5_port_hwtstamp_get, - .ndo_hwtstamp_set = sparx5_port_hwtstamp_set, -+ .ndo_change_mtu = sparx5_mtu_change, - }; - - bool sparx5_netdevice_check(const struct net_device *dev) -@@ -279,6 +280,9 @@ struct net_device *sparx5_create_netdev( - ndev->hw_features |= NETIF_F_HW_TC; - ndev->features |= NETIF_F_HW_TC; - -+ /* The MAC supports frame lengths of up to 14,000 bytes */ -+ ndev->max_mtu = 14000; -+ - SET_NETDEV_DEV(ndev, sparx5->dev); - spx5_port = netdev_priv(ndev); - spx5_port->ndev = ndev; From c8aa9beb4379f7e742350d44a0c150e98c99e2cd Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Wed, 18 Mar 2026 17:49:56 +0800 Subject: [PATCH 35/46] mediatek: add GL.iNET GL-MT3600BE support Hardware specification: SoC: MediaTek MT7987A 4x A53 Flash: 512 MB SPI-NAND RAM: 512MB DDR4 Ethernet: 2x 2.5GbE (built-in + RTL8221B) WiFi: MediaTek MT7990 USB: 1x USB 3.0 port Button: Mode, Reset Power: Type-C PD 5/9/12V Flash instructions: 1. Power on the device with 'reset' key pressed for 5s 2. Set static IP on your PC: IP 192.168.1.10/24, GW 192.168.1.1 3. Visit http://192.168.1.1 and upload sysupgrade.bin Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/22476 Signed-off-by: Hauke Mehrtens --- .../dts/mt7987a-glinet-gl-mt3600be.dts | 292 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 1 + target/linux/mediatek/image/filogic.mk | 21 ++ 3 files changed, 314 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7987a-glinet-gl-mt3600be.dts diff --git a/target/linux/mediatek/dts/mt7987a-glinet-gl-mt3600be.dts b/target/linux/mediatek/dts/mt7987a-glinet-gl-mt3600be.dts new file mode 100644 index 0000000000..784e134fff --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-glinet-gl-mt3600be.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2026 Tianling Shen + */ + +/dts-v1/; +#include +#include + +#include "mt7987a.dtsi" + +/ { + model = "GL.iNet GL-MT3600BE"; + compatible = "glinet,gl-mt3600be", "mediatek,mt7987a", "mediatek,mt7987"; + + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_status_white; + led-failsafe = &led_status_blue; + led-running = &led_status_blue; + led-upgrade = &led_status_blue; + }; + + chosen { + bootargs = "console=ttyS0,115200n1 earlycon=uart8250,mmio32,0x11000000 pci=pcie_bus_perf"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_status_blue: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 48 GPIO_ACTIVE_LOW>; + }; + + led_status_white: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 49 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-mode { + label = "mode"; + linux,code = ; + linux,input-type = ; + gpios = <&pio 3 GPIO_ACTIVE_HIGH>; + debounce-interval = <10>; + }; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; + + fan_3p3v: regulator-fan-3p3v { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + regulator-name = "fan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&pio 14 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_vbus"; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&fan { + fan-supply = <&fan_3p3v>; + interrupt-parent = <&pio>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + pwms = <&pwm 1 50000 0>; + status = "okay"; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_4000 0>; + nvmem-cell-names = "mac-address"; + phy-handle = <&phy7>; + phy-mode = "2500base-x"; + status = "okay"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_4000 1>; + nvmem-cell-names = "mac-address"; + phy-handle = <&phy15>; + phy-mode = "internal"; + status = "okay"; +}; + +&mdio { + reset-delay-us = <10000>; + reset-gpios = <&pio 0 GPIO_ACTIVE_LOW>; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupt-parent = <&pio>; + interrupts = <41 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 42 GPIO_ACTIVE_LOW>; + }; + + phy15: phy@f { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + reset-gpios = <&pio 38 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + mt7990@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + device_type = "pci"; + + ieee80211-freq-limit = <2400000 2500000>, + <5170000 5835000>; + + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + + band@0 { + reg = <0>; + nvmem-cells = <&macaddr_factory_4006 0>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + reg = <1>; + nvmem-cells = <&macaddr_factory_4006 1>; + nvmem-cell-names = "mac-address"; + }; + }; + }; +}; + +&pio { + pwm1_pins: pwm1-pins { + mux { + function = "pwm"; + groups = "pwm1_0"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pins>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <256>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x400000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1e00>; + }; + + macaddr_factory_4000: macaddr@4000 { + compatible = "mac-base"; + reg = <0x4000 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_4006: macaddr@4006 { + compatible = "mac-base"; + reg = <0x4006 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x200000>; + read-only; + }; + + partition@780000 { + label = "log"; + reg = <0x780000 0x40000>; + read-only; + }; + + partition@7c0000 { + label = "CFG"; + reg = <0x7c0000 0x40000>; + read-only; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x1d800000>; + compatible = "linux,ubi"; + }; + }; + }; +}; + +&ssusb { + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&tphyu3port0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 2d5bc24164..9fa03a8edc 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -142,6 +142,7 @@ mediatek_setup_interfaces() glinet,gl-mt2500|\ glinet,gl-mt2500-airoha|\ glinet,gl-mt3000|\ + glinet,gl-mt3600be|\ glinet,gl-x3000|\ glinet,gl-xe3000|\ openembed,som7981|\ diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 77c8055d60..c75301c111 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -1654,6 +1654,27 @@ define Device/glinet_gl-mt3000 endef TARGET_DEVICES += glinet_gl-mt3000 +define Device/glinet_gl-mt3600be + DEVICE_VENDOR := GL.iNet + DEVICE_MODEL := GL-MT3600BE + DEVICE_DTS := mt7987a-glinet-gl-mt3600be + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := mt7987-2p5g-phy-firmware kmod-mt7990-firmware \ + kmod-hwmon-pwmfan kmod-usb3 + KERNEL = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd + KERNEL_IN_UBI := 1 + KERNEL_LOADADDR := 0x40000000 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 483328k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += glinet_gl-mt3600be + define Device/glinet_gl-mt6000 DEVICE_VENDOR := GL.iNet DEVICE_MODEL := GL-MT6000 From 771e06352f5ab71d29868f5d68d1f27a8b35aed8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Seitz?= Date: Sun, 24 Aug 2025 06:51:11 +0200 Subject: [PATCH 36/46] mediatek: filogic: Add new Router model ZBT-Z8106AX-S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Device support for zbt-z8106ax-s Specifications: SoC: MediaTek MT7981B RAM: 256MiB Flash: Winbond SPI-NAND 128 MiB Switch: 1 WAN, 4 LAN (Gigabit) MediaTek MT7531 Buttons: Reset Power: DC 12V 1A WiFi: MT7981B 2.4Ghz & 5Ghz USB 3 M2 slot to hold LTE modem 1 nano SIM slot (user controllable) Hardware watchdog (confirmed to work) Router comes in a plastic tower with all antennas internal. - 4 antennas for LTE 4G/5G communication - 2 antennas for Wifi 2.4 GHz - 2 antennas for Wifi 5 GHz Led Layout: Power (green, user controllable, default set to OpenWrt Status) Mobile (green, user controllable) WLAN 2.4G (green, user controllable) WLAN 5G (green, user controllable) WAN (amber, user controllable, set to show eth1) LAN1 (amber, hardware controlled) LAN2 (amber, hardware controlled) LAN3 (amber, hardware controlled) LAN4 (amber, hardware controlled) SIM Slot: Controlled via exported GPIO named SIM. echo "0" > /sys/class/gpio/sim/value - turns off sim slot labelled SIM echo "1" > /sys/class/gpio/sim/value - turns on sim slot labelled SIM --- Installation: A. Through U-Boot menu: - Prepare your connecting computer to use a static IP in network 192.168.1.0/24 like a) 192.168.1.10 netmask 255.255.255.0 (legacy notation) b) 192.168.1.10/24 (CIDR notation) - Power down the router and hold in the Reset button. - While holding in the button power up the router again. - Hold the button in for 10 seconds and then release. - Use your browser to go to 192.168.1.1 - If you see a GUI allowing for flashing firmware then you got the right spot. - Upload the **Factory** image file. Note: U-Boot GUI it can be used to recover from an incorrect firmware flash. B. Through OpenWrt Dashboard: If your router comes with OpenWrt preinstalled (modified by vendor), you can easily upgrade by going to the dashboard (192.168.1.1) and then navigate to "System" -> "Backup/Flash firmware" Flash OpenWRT firmware. Important: Take care to deselect (untick) option "keep settings". Settings done by vendor are incompatible with versions 24.10 or 25.12. MAC Addresses: MAC Addresses were found in Factory partition: offset 0x4 F8:5E:3C:xx:xx:aa --> Router Label -2 offset 0xa F8:5E:3C:xx:xx:bb --> Router Label -1 offset 0x24 F8:5E:3C:xx:xx:cc --> Router Label +1 offset 0x2a F8:5E:3C:xx:xx:yy --> printed on Router Label Hardware Watchdog: Device features a GPIO controlled hardware watchdog. Verfied by removing procd controlled watchdog and seeing device rebooting. --- Notes: The zbt-z8106ax-s could be ordered from vendor with a variety of modems. Mine came with a 4G LTE modem Quectel EC200A. Quectel firmware was at EC200AEUHAR01A30M16. Choices for ordering with 5G LTE were available. Modem communication is set to ethernet control mode (ECM) by vendor. Package modemmanager works fine with Quectel EC200A. You may also decide to use FUjR/Qmodem github repository to have it manage LTE modem. Please take note that internal switch port named lan5 isn't wired to LTE modem in model S as opposed to model T. Just removing lan5 from DTS did cause unwanted reboots whenever a cable is plugged into LAN ports 1-4. Disabling port lan5 in DTS however works fine. No unwanted reboots due to plug/unplug cable into any lan or wan port. Signed-off-by: Jörg Seitz Link: https://github.com/openwrt/openwrt/pull/22912 Signed-off-by: Hauke Mehrtens --- .../dts/mt7981b-zbtlink-zbt-z8106ax-s.dts | 16 ++++++++++++++++ .../dts/mt7981b-zbtlink-zbt-z8106ax.dtsi | 2 +- .../filogic/base-files/etc/board.d/01_leds | 1 + .../filogic/base-files/etc/board.d/02_network | 3 ++- .../base-files/etc/board.d/03_gpio_switches | 1 + target/linux/mediatek/image/filogic.mk | 18 ++++++++++++++++++ 6 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax-s.dts diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax-s.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax-s.dts new file mode 100644 index 0000000000..3c5d1bfa1f --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax-s.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "mt7981b-zbtlink-zbt-z8106ax.dtsi" + +/ { + model = "Zbtlink ZBT-Z8106AX-S"; + compatible = "zbtlink,zbt-z8106ax-s", "mediatek,mt7981b"; +}; + +&port_4 { + /* The 4th port must be defined but isn't usable in model S, so we set it to disabled. */ + status = "disabled"; +}; + diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax.dtsi b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax.dtsi index 07e49b1013..8a4d06d53b 100644 --- a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax.dtsi +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax.dtsi @@ -189,7 +189,7 @@ label = "lan4"; }; - port@4 { + port_4: port@4 { reg = <4>; label = "wwan"; }; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 97684d232b..82df17d87f 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -330,6 +330,7 @@ zbtlink,zbt-z8103ax|\ zbtlink,zbt-z8103ax-c) ucidef_set_led_netdev "wan" "wan" "green:wan" "eth1" "link tx rx" ;; +zbtlink,zbt-z8106ax-s|\ zbtlink,zbt-z8106ax-t) ucidef_set_led_netdev "wan" "wan" "amber:wan" "eth1" "link tx rx" ucidef_set_led_netdev "mobile" "mobile" "green:mobile" "wwan" "link tx rx" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 9fa03a8edc..2a47c12063 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -76,7 +76,8 @@ mediatek_setup_interfaces() unielec,u7981-01*|\ wavlink,wl-wn536ax6-a|\ zbtlink,zbt-z8102ax|\ - zbtlink,zbt-z8102ax-v2) + zbtlink,zbt-z8102ax-v2|\ + zbtlink,zbt-z8106ax-s) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth1" ;; zbtlink,zbt-z8106ax-t) diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches b/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches index 336f5ba60d..0820bd97c8 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches @@ -21,6 +21,7 @@ zbtlink,zbt-z8102ax-v2) ucidef_add_gpio_switch "sim1" "SIM 1" "sim1" "1" ucidef_add_gpio_switch "sim2" "SIM 2" "sim2" "1" ;; +zbtlink,zbt-z8106ax-s|\ zbtlink,zbt-z8106ax-t) ucidef_add_gpio_switch "4g" "Power modem" "4g" "1" ucidef_add_gpio_switch "sim" "SIM" "sim" "1" diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index c75301c111..0112da0484 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -3449,6 +3449,24 @@ define Device/zbtlink_zbt-z8103ax-c endef TARGET_DEVICES += zbtlink_zbt-z8103ax-c +define Device/zbtlink_zbt-z8106ax-s + DEVICE_VENDOR := Zbtlink + DEVICE_MODEL := ZBT-Z8106AX-S + SUPPORTED_DEVICES += zbtlink,z8106ax-2sim + DEVICE_DTS := mt7981b-zbtlink-zbt-z8106ax-s + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option + KERNEL_IN_UBI := 1 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += zbtlink_zbt-z8106ax-s + define Device/zbtlink_zbt-z8106ax-t DEVICE_VENDOR := Zbtlink DEVICE_MODEL := ZBT-Z8106AX-T From 80a3c35d9e09a09b1f67732ae3a537781f888936 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 13:09:07 +0200 Subject: [PATCH 37/46] realtek: eth: convert rteth_XXXX_hw_stop() to regmap Use regmap in the following functions - rteth_838x_hw_stop() - rteth_839x_hw_stop() - rteth_930x_hw_stop() - rteth_931x_hw_stop() Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../drivers/net/ethernet/rtl838x_eth.c | 32 +++++++++++-------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index 599c5cf29c..fb7fa4e91b 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -730,33 +730,39 @@ static int rteth_open(struct net_device *ndev) static void rteth_838x_hw_stop(struct rteth_ctrl *ctrl) { - /* Block all ports */ - sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0)); - sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1)); - sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0); + u32 val; + + /* Block all ports. TODO: this is an unprotected table access */ + regmap_write(ctrl->map, RTL838X_TBL_ACCESS_DATA_0(0), 0x3000000); + regmap_write(ctrl->map, RTL838X_TBL_ACCESS_DATA_0(1), 0x0); + regmap_write(ctrl->map, RTL838X_TBL_ACCESS_CTRL_0, 1 << 15 | 2 << 12); /* Disable FAST_AGE_OUT otherwise flush will hang */ - sw_w32_mask(BIT(23), 0, RTL838X_L2_CTRL_1); + regmap_clear_bits(ctrl->map, RTL838X_L2_CTRL_1, BIT(23)); /* Flush L2 address cache */ for (int i = 0; i <= ctrl->r->cpu_port; i++) { - sw_w32(BIT(26) | BIT(23) | i << 5, ctrl->r->l2_tbl_flush_ctrl); - do { } while (sw_r32(ctrl->r->l2_tbl_flush_ctrl) & BIT(26)); + regmap_write(ctrl->map, ctrl->r->l2_tbl_flush_ctrl, BIT(26) | BIT(23) | i << 5); + regmap_read_poll_timeout(ctrl->map, ctrl->r->l2_tbl_flush_ctrl, + val, !(val & BIT(26)), 100, 100000); } /* CPU-Port: Link down */ - sw_w32(0x6192C, ctrl->r->mac_force_mode_ctrl); + regmap_write(ctrl->map, ctrl->r->mac_force_mode_ctrl, 0x6192C); } static void rteth_839x_hw_stop(struct rteth_ctrl *ctrl) { + u32 val; + /* Flush L2 address cache */ for (int i = 0; i <= ctrl->r->cpu_port; i++) { - sw_w32(BIT(28) | BIT(25) | i << 5, ctrl->r->l2_tbl_flush_ctrl); - do { } while (sw_r32(ctrl->r->l2_tbl_flush_ctrl) & BIT(28)); + regmap_write(ctrl->map, ctrl->r->l2_tbl_flush_ctrl, BIT(28) | BIT(25) | i << 5); + regmap_read_poll_timeout(ctrl->map, ctrl->r->l2_tbl_flush_ctrl, + val, !(val & BIT(28)), 100, 100000); } - sw_w32(0x75, ctrl->r->mac_force_mode_ctrl); + regmap_write(ctrl->map, ctrl->r->mac_force_mode_ctrl, 0x75); } static void rteth_930x_hw_stop(struct rteth_ctrl *ctrl) @@ -764,7 +770,7 @@ static void rteth_930x_hw_stop(struct rteth_ctrl *ctrl) /* TODO: L2 flush needed */ /* CPU-Port: Link down */ - sw_w32_mask(0x3, 0, ctrl->r->mac_force_mode_ctrl); + regmap_clear_bits(ctrl->map, ctrl->r->mac_force_mode_ctrl, 0x3); } static void rteth_931x_hw_stop(struct rteth_ctrl *ctrl) @@ -772,7 +778,7 @@ static void rteth_931x_hw_stop(struct rteth_ctrl *ctrl) /* TODO: L2 flush needed */ /* CPU-Port: Link down */ - sw_w32_mask(BIT(0) | BIT(9), 0, ctrl->r->mac_force_mode_ctrl); + regmap_clear_bits(ctrl->map, ctrl->r->mac_force_mode_ctrl, BIT(0) | BIT(9)); } static void rteth_hw_stop(struct rteth_ctrl *ctrl) From 01024036969a3df5c11bd53a14e3c5d223930c23 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 13:26:49 +0200 Subject: [PATCH 38/46] realtek: eth: more regmap refactoring Convert rteth_start_xmit() and rteth_hw_stop() to regmap. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../files-6.18/drivers/net/ethernet/rtl838x_eth.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index fb7fa4e91b..5739fdae66 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -784,10 +784,10 @@ static void rteth_931x_hw_stop(struct rteth_ctrl *ctrl) static void rteth_hw_stop(struct rteth_ctrl *ctrl) { /* Disable RX/TX from/to CPU-port */ - sw_w32_mask(0x3, 0, ctrl->r->mac_l2_port_ctrl); + regmap_clear_bits(ctrl->map, ctrl->r->mac_l2_port_ctrl, 0x3); /* Disable traffic */ - sw_w32_mask(ctrl->r->tx_rx_enable, 0, ctrl->r->dma_if_ctrl); + regmap_clear_bits(ctrl->map, ctrl->r->dma_if_ctrl, ctrl->r->tx_rx_enable); mdelay(200); /* Test, whether this is needed */ /* family specific stop */ @@ -797,7 +797,7 @@ static void rteth_hw_stop(struct rteth_ctrl *ctrl) rteth_disable_all_irqs(ctrl); /* Disable TX/RX DMA */ - sw_w32(0x00000000, ctrl->r->dma_if_ctrl); + regmap_write(ctrl->map, ctrl->r->dma_if_ctrl, 0); mdelay(200); } @@ -993,11 +993,11 @@ static int rteth_start_xmit(struct sk_buff *skb, struct net_device *netdev) * bug, where the hardware sometimes reads empty values from the register. Work around * that with a poll that checks if TX/RX is enabled in the register. */ - if (read_poll_timeout(sw_r32, val, val & ctrl->r->tx_rx_enable, - 0, 5000, false, ctrl->r->dma_if_ctrl)) + if (regmap_read_poll_timeout(ctrl->map, ctrl->r->dma_if_ctrl, + val, val & ctrl->r->tx_rx_enable, 0, 5000)) dev_warn_once(dev, "DMA interface ctrl register read failed\n"); - sw_w32(val | RTETH_TX_TRIGGER(ctrl, ring), ctrl->r->dma_if_ctrl); + regmap_write(ctrl->map, ctrl->r->dma_if_ctrl, val | RTETH_TX_TRIGGER(ctrl, ring)); netdev->stats.tx_packets++; netdev->stats.tx_bytes += len; From 62e0f63aa33681409bae8ac544616873ce985dca Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 13:34:46 +0200 Subject: [PATCH 39/46] realtek: eth: convert link up/down to regmap Make use of regmap in rteth_mac_link_down and rteth_mac_link_up. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index 5739fdae66..2bbe93b48e 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -1114,7 +1114,7 @@ static void rteth_mac_link_down(struct phylink_config *config, pr_debug("In %s\n", __func__); /* Stop TX/RX to port */ - sw_w32_mask(0x03, 0, ctrl->r->mac_l2_port_ctrl); + regmap_clear_bits(ctrl->map, ctrl->r->mac_l2_port_ctrl, 0x3); } static void rteth_mac_link_up(struct phylink_config *config, @@ -1127,7 +1127,7 @@ static void rteth_mac_link_up(struct phylink_config *config, pr_debug("In %s\n", __func__); /* Restart TX/RX to port */ - sw_w32_mask(0, 0x03, ctrl->r->mac_l2_port_ctrl); + regmap_set_bits(ctrl->map, ctrl->r->mac_l2_port_ctrl, 0x3); } static void rteth_set_mac_hw(struct net_device *dev, u8 *mac) From fb874fcef791c253be3708db807ffef7f7a1eb86 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 13:49:39 +0200 Subject: [PATCH 40/46] realtek: eth: convert mac functions to regmap Besides converting some functions to regmap do some minor refactoring for rteth_931x_init_mac(). - Use dev_err() instead of classic print functions - Harmonize ALE_INIT error handling. ALE_INIT_2 has the same logic as the other registers. The reset is finished as soon as the register is completely zero. - From testing 100ms poll timeout seems to be sufficient Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../drivers/net/ethernet/rtl838x_eth.c | 65 ++++++++++++------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index 2bbe93b48e..178089ea27 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -1142,8 +1142,8 @@ static void rteth_set_mac_hw(struct net_device *dev, u8 *mac) for (int i = 0; i < RTETH_MAX_MAC_REGS; i++) if (ctrl->r->mac_reg[i]) { - sw_w32(mac_hi, ctrl->r->mac_reg[i]); - sw_w32(mac_lo, ctrl->r->mac_reg[i] + 4); + regmap_write(ctrl->map, ctrl->r->mac_reg[i], mac_hi); + regmap_write(ctrl->map, ctrl->r->mac_reg[i] + 4, mac_lo); } spin_unlock_irqrestore(&ctrl->lock, flags); @@ -1169,12 +1169,12 @@ static int rteth_838x_init_mac(struct rteth_ctrl *ctrl) { pr_info("%s\n", __func__); /* fix timer for EEE */ - sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); - sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); + regmap_write(ctrl->map, RTL838X_EEE_TX_TIMER_GIGA_CTRL, 0x5001411); + regmap_write(ctrl->map, RTL838X_EEE_TX_TIMER_GELITE_CTRL, 0x5001417); /* Init VLAN. TODO: Understand what is being done, here */ for (int i = 0; i <= 28; i++) - sw_w32(0, 0xd57c + i * 0x80); + regmap_write(ctrl->map, 0xd57c + i * 0x80, 0); return 0; } @@ -1192,33 +1192,52 @@ static int rteth_930x_init_mac(struct rteth_ctrl *ctrl) static int rteth_931x_init_mac(struct rteth_ctrl *ctrl) { - pr_info("In %s\n", __func__); + struct device *dev = &ctrl->pdev->dev; + unsigned int val; + int ret; /* Initialize Encapsulation memory and wait until finished */ - sw_w32(0x1, RTL931X_MEM_ENCAP_INIT); - do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1); - pr_info("%s: init ENCAP done\n", __func__); + regmap_write(ctrl->map, RTL931X_MEM_ENCAP_INIT, 0x1); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_ENCAP_INIT, + val, !(val & 1), 0, 100000); + if (ret) + dev_err(dev, "ENCAP init timeout\n"); - /* Initialize Managemen Information Base memory and wait until finished */ - sw_w32(0x1, RTL931X_MEM_MIB_INIT); - do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1); - pr_info("%s: init MIB done\n", __func__); + /* Initialize Management Information Base memory and wait until finished */ + regmap_write(ctrl->map, RTL931X_MEM_MIB_INIT, 0x1); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_MIB_INIT, + val, !(val & 1), 0, 100000); + if (ret) + dev_err(dev, "MIB init timeout\n"); /* Initialize ACL (PIE) memory and wait until finished */ - sw_w32(0x1, RTL931X_MEM_ACL_INIT); - do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1); - pr_info("%s: init ACL done\n", __func__); + regmap_write(ctrl->map, RTL931X_MEM_ACL_INIT, 0x1); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_ACL_INIT, + val, !(val & 1), 0, 100000); + if (ret) + dev_err(dev, "ACL init timeout\n"); /* Initialize ALE memory and wait until finished */ - sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0); - do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0)); - sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1); - sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2); - do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff); - pr_info("%s: init ALE done\n", __func__); + regmap_write(ctrl->map, RTL931X_MEM_ALE_INIT_0, 0xffffffff); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_ALE_INIT_0, + val, !val, 0, 100000); + if (ret) + dev_err(dev, "ALE_0 init timeout\n"); + + regmap_write(ctrl->map, RTL931X_MEM_ALE_INIT_1, 0x7f); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_ALE_INIT_1, + val, !val, 0, 100000); + if (ret) + dev_err(dev, "ALE_1 init timeout\n"); + + regmap_write(ctrl->map, RTL931X_MEM_ALE_INIT_2, 0x7ff); + ret = regmap_read_poll_timeout(ctrl->map, RTL931X_MEM_ALE_INIT_2, + val, !val, 0, 100000); + if (ret) + dev_err(dev, "ALE_2 init timeout\n"); /* Enable ESD auto recovery */ - sw_w32(0x1, RTL931X_MDX_CTRL_RSVD); + regmap_write(ctrl->map, RTL931X_MDX_CTRL_RSVD, 0x1); return 0; } From 4e927d77b4a6d57cb5d3afcff8656c4e4d4229fe Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 20:13:45 +0200 Subject: [PATCH 41/46] realtek: eth: convert set_features() to regmap Use regmap_assign_bits() for conversion and much simpler code. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../drivers/net/ethernet/rtl838x_eth.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index 178089ea27..484f162bb3 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -1272,12 +1272,8 @@ static int rteth_83xx_set_features(struct net_device *dev, netdev_features_t fea { struct rteth_ctrl *ctrl = netdev_priv(dev); - if ((features ^ dev->features) & NETIF_F_RXCSUM) { - if (!(features & NETIF_F_RXCSUM)) - sw_w32_mask(BIT(3), 0, ctrl->r->mac_l2_port_ctrl); - else - sw_w32_mask(0, BIT(3), ctrl->r->mac_l2_port_ctrl); - } + if ((features ^ dev->features) & NETIF_F_RXCSUM) + regmap_assign_bits(ctrl->map, ctrl->r->mac_l2_port_ctrl, BIT(3), features & NETIF_F_RXCSUM); return 0; } @@ -1286,12 +1282,8 @@ static int rteth_93xx_set_features(struct net_device *dev, netdev_features_t fea { struct rteth_ctrl *ctrl = netdev_priv(dev); - if ((features ^ dev->features) & NETIF_F_RXCSUM) { - if (!(features & NETIF_F_RXCSUM)) - sw_w32_mask(BIT(4), 0, ctrl->r->mac_l2_port_ctrl); - else - sw_w32_mask(0, BIT(4), ctrl->r->mac_l2_port_ctrl); - } + if ((features ^ dev->features) & NETIF_F_RXCSUM) + regmap_assign_bits(ctrl->map, ctrl->r->mac_l2_port_ctrl, BIT(4), features & NETIF_F_RXCSUM); return 0; } From eb4b4b3107546f217d5adf9ec811efab8399d403 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Thu, 23 Apr 2026 20:26:49 +0200 Subject: [PATCH 42/46] realtek: eth: convert eth_probe() to regmap Remove the last sw() macros from the ethernet driver. With this drop the required include line. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/23067 Signed-off-by: Hauke Mehrtens --- .../drivers/net/ethernet/rtl838x_eth.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c index 484f162bb3..e50cc68fa2 100644 --- a/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c @@ -23,7 +23,6 @@ #include #include -#include #include "rtl838x_eth.h" #define RTETH_OWN_CPU 1 @@ -1576,12 +1575,17 @@ static int rteth_probe(struct platform_device *pdev) if (is_valid_ether_addr(mac_addr)) { rteth_set_mac_hw(dev, mac_addr); } else { - mac_addr[0] = (sw_r32(ctrl->r->mac_reg[0]) >> 8) & 0xff; - mac_addr[1] = sw_r32(ctrl->r->mac_reg[0]) & 0xff; - mac_addr[2] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 24) & 0xff; - mac_addr[3] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 16) & 0xff; - mac_addr[4] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 8) & 0xff; - mac_addr[5] = sw_r32(ctrl->r->mac_reg[0] + 4) & 0xff; + u32 mac_hi, mac_lo; + + regmap_read(ctrl->map, ctrl->r->mac_reg[0], &mac_hi); + regmap_read(ctrl->map, ctrl->r->mac_reg[0] + 4, &mac_lo); + + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; } dev_addr_set(dev, mac_addr); /* if the address is invalid, use a random value */ From 793ceff1494e7dea8503699f3e5bf48dacccd7c4 Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Sat, 25 Apr 2026 19:40:59 -0600 Subject: [PATCH 43/46] modules: amazon-ena: fix ptp dependency Going from 6.12 to 6.18 I see breakage with a missing dependency that drivers/net/ethernet/amazon/ena/ena_netdev.c has on ptp.ko. Signed-off-by: Philip Prindeville Link: https://github.com/openwrt/openwrt/pull/23098 Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/netdevices.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index d5106e4203..0d62534535 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -2475,7 +2475,7 @@ $(eval $(call KernelPackage,lan743x)) define KernelPackage/amazon-ena SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Elastic Network Adapter (for Amazon AWS) - DEPENDS:=@TARGET_x86_64||TARGET_armsr + DEPENDS:=@TARGET_x86_64||TARGET_armsr +LINUX_6_18:kmod-ptp KCONFIG:=CONFIG_ENA_ETHERNET FILES:=$(LINUX_DIR)/drivers/net/ethernet/amazon/ena/ena.ko AUTOLOAD:=$(call AutoLoad,12,ena) From c271123724fc03ce646fb9d79fb439d01becaada Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 27 Apr 2026 01:46:57 +0100 Subject: [PATCH 44/46] generic: 6.18: fix MediaTek USXGMII driver LINK_INBAND_ENABLE isn't valid for 5GBase-R/10GBase-R modes which by definition don't support any in-band an. Correctly report LINK_INBAND_DISABLE to fix 10G fiber SFP modules no longer working. While at it also get rid of downstream pn-swap properties in favor of using the upstream schema. Signed-off-by: Daniel Golle --- ...pcs-add-bindings-for-MediaTek-USXGMI.patch | 13 ++-- ...-add-driver-for-MediaTek-USXGMII-PCS.patch | 69 ++++++++++++++++--- ...pcs-mtk_usxgmii-add-polarity-control.patch | 65 ----------------- 3 files changed, 68 insertions(+), 79 deletions(-) delete mode 100644 target/linux/mediatek/patches-6.18/736-net-pcs-mtk_usxgmii-add-polarity-control.patch diff --git a/target/linux/generic/pending-6.18/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch b/target/linux/generic/pending-6.18/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch index 46694c8534..3bee2f2c6c 100644 --- a/target/linux/generic/pending-6.18/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch +++ b/target/linux/generic/pending-6.18/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch @@ -1,7 +1,7 @@ -From 029c59b9e92776ed1b8f586055d5813132e32f47 Mon Sep 17 00:00:00 2001 +From 3bc50ced1c42f0a31173eb65a61307d657109382 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 12 Dec 2023 03:47:31 +0000 -Subject: [PATCH 2/4] dt-bindings: net: pcs: add bindings for MediaTek USXGMII +Subject: [PATCH 1/2] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS MediaTek's USXGMII can be found in the MT7988 SoC. We need to access @@ -12,13 +12,13 @@ interface modes are also available. Signed-off-by: Daniel Golle --- - .../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++ - 1 file changed, 60 insertions(+) + .../bindings/net/pcs/mediatek,usxgmii.yaml | 63 +++++++++++++++++++ + 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml -@@ -0,0 +1,60 @@ +@@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- @@ -63,6 +63,9 @@ Signed-off-by: Daniel Golle + - clocks + - resets + ++allOf: ++ - $ref: /schemas/phy/phy-common-props.yaml# ++ +additionalProperties: false + +examples: diff --git a/target/linux/generic/pending-6.18/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch b/target/linux/generic/pending-6.18/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch index 83336476d4..385c5c924e 100644 --- a/target/linux/generic/pending-6.18/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch +++ b/target/linux/generic/pending-6.18/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch @@ -1,7 +1,7 @@ -From c33cd256420ed08ffbedf39971882acc60dc184e Mon Sep 17 00:00:00 2001 +From e9d2999f5d9d8e1b895350c569e930918b41ce92 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 12 Dec 2023 03:47:47 +0000 -Subject: [PATCH 3/4] net: pcs: add driver for MediaTek USXGMII PCS +Subject: [PATCH 2/2] net: pcs: add driver for MediaTek USXGMII PCS Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting USXGMII, 10GBase-R and 5GBase-R interface modes. @@ -9,11 +9,11 @@ USXGMII, 10GBase-R and 5GBase-R interface modes. Signed-off-by: Daniel Golle --- MAINTAINERS | 2 + - drivers/net/pcs/Kconfig | 12 + + drivers/net/pcs/Kconfig | 13 + drivers/net/pcs/Kconfig.orig | 55 ++++ drivers/net/pcs/Makefile | 1 + - drivers/net/pcs/pcs-mtk-usxgmii.c | 440 ++++++++++++++++++++++++++++++ - 5 files changed, 510 insertions(+) + drivers/net/pcs/pcs-mtk-usxgmii.c | 490 ++++++++++++++++++++++++++++++ + 5 files changed, 561 insertions(+) create mode 100644 drivers/net/pcs/Kconfig.orig create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c @@ -31,7 +31,7 @@ Signed-off-by: Daniel Golle M: Daniel Golle --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig -@@ -33,6 +33,18 @@ config PCS_MTK_LYNXI +@@ -33,6 +33,19 @@ config PCS_MTK_LYNXI This module provides helpers to phylink for managing the LynxI PCS which is part of MediaTek's SoC and Ethernet switch ICs. @@ -39,6 +39,7 @@ Signed-off-by: Daniel Golle + tristate "MediaTek USXGMII PCS" + select FWNODE_PCS + select PCS_MTK_LYNXI ++ select PHY_COMMON_PROPS + select PHYLINK + imply PHY_MTK_PEXTP + help @@ -118,7 +119,7 @@ Signed-off-by: Daniel Golle obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o --- /dev/null +++ b/drivers/net/pcs/pcs-mtk-usxgmii.c -@@ -0,0 +1,440 @@ +@@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. @@ -135,6 +136,7 @@ Signed-off-by: Daniel Golle +#include +#include +#include ++#include +#include +#include +#include @@ -176,6 +178,12 @@ Signed-off-by: Daniel Golle +#define USXGMII_LPA GENMASK(15, 0) +#define USXGMII_LPA_LATCH BIT(31) + ++/* Register to control SerDes lane polarity */ ++#define RG_PHY_TOP_CTRL0 0x82c ++#define USXGMII_PN_SWAP_MASK GENMASK(1, 0) ++#define USXGMII_PN_SWAP_RX BIT(1) ++#define USXGMII_PN_SWAP_TX BIT(0) ++ +/* Register to read PCS link status */ +#define RG_PCS_RX_STATUS0 0x904 +#define RG_PCS_RX_STATUS_UPDATE BIT(16) @@ -187,6 +195,8 @@ Signed-off-by: Daniel Golle + * @base: IO memory to access PCS hardware + * @clk: Pointer to USXGMII clk + * @reset: Pointer to USXGMII reset control ++ * @fwnode: Firmware node of the PCS, used to look up ++ * rx-polarity / tx-polarity properties + * @interface: Currently selected interface mode + * @neg_mode: Currently used phylink neg_mode + * @node: List node @@ -198,6 +208,7 @@ Signed-off-by: Daniel Golle + struct clk *clk; + struct reset_control *reset; + struct phy *xfi_tphy; ++ struct fwnode_handle *fwnode; + phy_interface_t interface; + unsigned int neg_mode; + struct list_head node; @@ -232,6 +243,36 @@ Signed-off-by: Daniel Golle + mdelay(10); +} + ++static int mtk_usxgmii_config_polarity(struct mtk_usxgmii_pcs *mpcs, ++ phy_interface_t interface) ++{ ++ unsigned int pol; ++ u32 val = 0; ++ int ret; ++ ++ if (!mpcs->fwnode) ++ return 0; ++ ++ ret = phy_get_rx_polarity(mpcs->fwnode, phy_modes(interface), ++ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), ++ PHY_POL_NORMAL, &pol); ++ if (ret) ++ return ret; ++ if (pol == PHY_POL_INVERT) ++ val |= USXGMII_PN_SWAP_RX; ++ ++ ret = phy_get_tx_polarity(mpcs->fwnode, phy_modes(interface), ++ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), ++ PHY_POL_NORMAL, &pol); ++ if (ret) ++ return ret; ++ if (pol == PHY_POL_INVERT) ++ val |= USXGMII_PN_SWAP_TX; ++ ++ mtk_m32(mpcs, RG_PHY_TOP_CTRL0, USXGMII_PN_SWAP_MASK, val); ++ return 0; ++} ++ +static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, + phy_interface_t interface, + const unsigned long *advertising, @@ -240,6 +281,7 @@ Signed-off-by: Daniel Golle + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); + unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; + bool mode_changed = false; ++ int ret; + + if (interface == PHY_INTERFACE_MODE_USXGMII) { + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE; @@ -278,6 +320,10 @@ Signed-off-by: Daniel Golle + phy_reset(mpcs->xfi_tphy); + mtk_usxgmii_reset(mpcs); + ++ ret = mtk_usxgmii_config_polarity(mpcs, interface); ++ if (ret) ++ return ret; ++ + /* Setup USXGMII AN ctrl */ + mtk_m32(mpcs, RG_PCS_AN_CTRL0, + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, @@ -467,11 +513,13 @@ Signed-off-by: Daniel Golle + phy_interface_t interface) +{ + switch (interface) { -+ case PHY_INTERFACE_MODE_5GBASER: -+ case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_USXGMII: + return LINK_INBAND_ENABLE; + ++ case PHY_INTERFACE_MODE_5GBASER: ++ case PHY_INTERFACE_MODE_10GBASER: ++ return LINK_INBAND_DISABLE; ++ + default: + return 0; + } @@ -505,6 +553,7 @@ Signed-off-by: Daniel Golle + mpcs->pcs.poll = true; + mpcs->interface = PHY_INTERFACE_MODE_NA; + mpcs->neg_mode = -1; ++ mpcs->fwnode = fwnode_handle_get(dev_fwnode(dev)); + + __set_bit(PHY_INTERFACE_MODE_5GBASER, mpcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, mpcs->pcs.supported_interfaces); @@ -538,6 +587,8 @@ Signed-off-by: Daniel Golle + rtnl_lock(); + phylink_release_pcs(&mpcs->pcs); + rtnl_unlock(); ++ ++ fwnode_handle_put(mpcs->fwnode); +}; + +static const struct of_device_id mtk_usxgmii_of_mtable[] = { diff --git a/target/linux/mediatek/patches-6.18/736-net-pcs-mtk_usxgmii-add-polarity-control.patch b/target/linux/mediatek/patches-6.18/736-net-pcs-mtk_usxgmii-add-polarity-control.patch deleted file mode 100644 index 092cd607e2..0000000000 --- a/target/linux/mediatek/patches-6.18/736-net-pcs-mtk_usxgmii-add-polarity-control.patch +++ /dev/null @@ -1,65 +0,0 @@ -From ddfae94a14bf0fc301505da75825dfe473525a33 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 29 Oct 2024 13:40:11 +0100 -Subject: [PATCH] mediatek: add support for swapping the polarity on usxgmii interfaces - -This patch comes from the MTK SDK. - -Signed-off-by: John Crispin ---- ---- a/drivers/net/pcs/pcs-mtk-usxgmii.c -+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c -@@ -55,6 +55,12 @@ - #define USXGMII_LPA GENMASK(15, 0) - #define USXGMII_LPA_LATCH BIT(31) - -+/* Register to control PCS polarity */ -+#define RG_PHY_TOP_CTRL0 0x82C -+#define USXGMII_PN_SWAP_MASK GENMASK(1, 0) -+#define USXGMII_PN_SWAP_RX BIT(1) -+#define USXGMII_PN_SWAP_TX BIT(0) -+ - /* Register to read PCS link status */ - #define RG_PCS_RX_STATUS0 0x904 - #define RG_PCS_RX_STATUS_UPDATE BIT(16) -@@ -78,6 +84,7 @@ struct mtk_usxgmii_pcs { - struct reset_control *reset; - struct phy *xfi_tphy; - phy_interface_t interface; -+ unsigned int polarity; - unsigned int neg_mode; - struct list_head node; - }; -@@ -157,6 +164,10 @@ static int mtk_usxgmii_pcs_config(struct - phy_reset(mpcs->xfi_tphy); - mtk_usxgmii_reset(mpcs); - -+ /* Configure the interface polarity */ -+ mtk_m32(mpcs, RG_PHY_TOP_CTRL0, -+ USXGMII_PN_SWAP_MASK, mpcs->polarity); -+ - /* Setup USXGMII AN ctrl */ - mtk_m32(mpcs, RG_PCS_AN_CTRL0, - USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, -@@ -369,6 +380,7 @@ static const struct phylink_pcs_ops mtk_ - static int mtk_usxgmii_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; - struct mtk_usxgmii_pcs *mpcs; - - mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL); -@@ -379,6 +391,13 @@ static int mtk_usxgmii_probe(struct plat - if (IS_ERR(mpcs->base)) - return PTR_ERR(mpcs->base); - -+ if (of_property_read_bool(np->parent, "mediatek,pnswap")) -+ mpcs->polarity = USXGMII_PN_SWAP_TX | USXGMII_PN_SWAP_RX; -+ else if (of_property_read_bool(np, "mediatek,pnswap-tx")) -+ mpcs->polarity = USXGMII_PN_SWAP_TX; -+ else if (of_property_read_bool(np, "mediatek,pnswap-rx")) -+ mpcs->polarity = USXGMII_PN_SWAP_RX; -+ - mpcs->dev = dev; - mpcs->pcs.ops = &mtk_usxgmii_pcs_ops; - mpcs->pcs.poll = true; From be0a49cfe8c72fa714a3a78a2aeb030065b54651 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 27 Apr 2026 01:50:44 +0100 Subject: [PATCH 45/46] mediatek: filogic: arcadyan-mozart: fix polarity properties Use the upstream properties to describe the USXGMII PCS polarity as the downstream mediatek,pnswap{,-rx,tx} was dropped. This board was the only user. Signed-off-by: Daniel Golle --- target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts b/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts index 420bd53b69..41bb4415f7 100644 --- a/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts +++ b/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts @@ -5,6 +5,7 @@ #include #include #include +#include / { compatible = "arcadyan,mozart", "mediatek,mt7988a"; @@ -71,11 +72,11 @@ }; &usxgmiisys0 { - mediatek,pnswap-rx; + rx-polarity = ; }; &usxgmiisys1 { - mediatek,pnswap-rx; + rx-polarity = ; }; &mdio_bus { From 10ca4886c4a40946d3553912682b918fa78966b1 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 27 Apr 2026 01:52:38 +0100 Subject: [PATCH 46/46] generic: 6.18: add and fix support for Aquantia PHYs Add support for Aquantia CUX3410 and fix/sync support for the AQR112 variants. Signed-off-by: Daniel Golle --- ...hy-aquantia-enable-AQR112-and-AQR412.patch | 8 +- ...aquantia-fix-system-side-protocol-mi.patch | 2 +- ...ntia-add-PHY_IDs-for-AQR112-variants.patch | 80 +++++++++----- ...phy-aquantia-add-support-for-CUX3410.patch | 102 ++++++++++++++++++ 4 files changed, 161 insertions(+), 31 deletions(-) create mode 100644 target/linux/generic/pending-6.18/715-net-phy-aquantia-add-support-for-CUX3410.patch diff --git a/target/linux/generic/hack-6.18/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-6.18/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch index 5e2d7a21ab..cc45abfef1 100644 --- a/target/linux/generic/hack-6.18/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch +++ b/target/linux/generic/hack-6.18/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch @@ -15,7 +15,7 @@ Signed-off-by: Alex Marginean --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -116,6 +116,29 @@ +@@ -120,6 +120,29 @@ #define AQR107_OP_IN_PROG_SLEEP 1000 #define AQR107_OP_IN_PROG_TIMEOUT 100000 @@ -45,7 +45,7 @@ Signed-off-by: Alex Marginean static int aqr107_get_sset_count(struct phy_device *phydev) { return AQR107_SGMII_STAT_SZ; -@@ -250,6 +273,51 @@ static int aqr_config_aneg(struct phy_de +@@ -264,6 +287,51 @@ static int aqr_config_aneg(struct phy_de return genphy_c45_check_and_restart_aneg(phydev, changed); } @@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean static int aqr_config_intr(struct phy_device *phydev) { bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -@@ -1338,7 +1406,7 @@ static struct phy_driver aqr_driver[] = +@@ -1356,7 +1424,7 @@ static struct phy_driver aqr_driver[] = .name = "Aquantia AQR112", .probe = aqr107_probe, .config_init = aqr_gen3_config_init, @@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean .config_intr = aqr_config_intr, .handle_interrupt = aqr_handle_interrupt, .get_tunable = aqr107_get_tunable, -@@ -1364,7 +1432,7 @@ static struct phy_driver aqr_driver[] = +@@ -1382,7 +1450,7 @@ static struct phy_driver aqr_driver[] = .name = "Aquantia AQR412", .probe = aqr107_probe, .config_init = aqr_gen3_config_init, diff --git a/target/linux/generic/hack-6.18/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-6.18/723-net-phy-aquantia-fix-system-side-protocol-mi.patch index a6b3828b98..74d3970d2c 100644 --- a/target/linux/generic/hack-6.18/723-net-phy-aquantia-fix-system-side-protocol-mi.patch +++ b/target/linux/generic/hack-6.18/723-net-phy-aquantia-fix-system-side-protocol-mi.patch @@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -306,10 +306,16 @@ static int aqr_config_aneg_set_prot(stru +@@ -320,10 +320,16 @@ static int aqr_config_aneg_set_prot(stru phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, aquantia_syscfg[if_type].start_rate); diff --git a/target/linux/generic/hack-6.18/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.18/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch index e13d1fd392..297f8b7366 100644 --- a/target/linux/generic/hack-6.18/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch +++ b/target/linux/generic/hack-6.18/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch @@ -12,52 +12,80 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -34,6 +34,8 @@ - #define PHY_ID_AQR115 0x31c31c63 - #define PHY_ID_AQR115C 0x31c31c33 - #define PHY_ID_AQR813 0x31c31cb2 +@@ -26,6 +26,8 @@ + #define PHY_ID_AQR111 0x03a1b610 + #define PHY_ID_AQR111B0 0x03a1b612 + #define PHY_ID_AQR112 0x03a1b662 +#define PHY_ID_AQR112C 0x03a1b790 +#define PHY_ID_AQR112R 0x31c31d12 - - #define MDIO_PHYXS_VEND_PROV2 0xc441 - #define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3) -@@ -1634,6 +1636,30 @@ static struct phy_driver aqr_driver[] = - .inband_caps = aqr_gen2_inband_caps, + #define PHY_ID_AQR412 0x03a1b6f2 + #define PHY_ID_AQR412C 0x03a1b712 + #define PHY_ID_AQR113 0x31c31c40 +@@ -1452,6 +1454,58 @@ static struct phy_driver aqr_driver[] = .config_inband = aqr_gen2_config_inband, }, -+{ + { + PHY_ID_MATCH_MODEL(PHY_ID_AQR112C), + .name = "Aquantia AQR112C", + .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg, ++ .config_init = aqr_gen3_config_init, ++ .config_aneg = aqr_config_aneg_set_prot, + .config_intr = aqr_config_intr, + .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+ .get_sset_count = aqr107_get_sset_count, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr_gen1_suspend, ++ .resume = aqr_gen1_resume, ++ .read_status = aqr_gen2_read_status, ++ .get_rate_matching = aqr_gen2_get_rate_matching, ++ .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++ .led_brightness_set = aqr_phy_led_brightness_set, ++ .led_hw_is_supported = aqr_phy_led_hw_is_supported, ++ .led_hw_control_set = aqr_phy_led_hw_control_set, ++ .led_hw_control_get = aqr_phy_led_hw_control_get, ++ .led_polarity_set = aqr_phy_led_polarity_set, ++ .inband_caps = aqr_gen2_inband_caps, ++ .config_inband = aqr_gen2_config_inband, +}, +{ + PHY_ID_MATCH_MODEL(PHY_ID_AQR112R), + .name = "Aquantia AQR112R", + .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg_set_prot, ++ .config_init = aqr_gen3_config_init, ++ .config_aneg = aqr_config_aneg_set_prot, + .config_intr = aqr_config_intr, + .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+ .get_sset_count = aqr107_get_sset_count, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr_gen1_suspend, ++ .resume = aqr_gen1_resume, ++ .read_status = aqr_gen2_read_status, ++ .get_rate_matching = aqr_gen2_get_rate_matching, ++ .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++ .led_brightness_set = aqr_phy_led_brightness_set, ++ .led_hw_is_supported = aqr_phy_led_hw_is_supported, ++ .led_hw_control_set = aqr_phy_led_hw_control_set, ++ .led_hw_control_get = aqr_phy_led_hw_control_get, ++ .led_polarity_set = aqr_phy_led_polarity_set, ++ .inband_caps = aqr_gen2_inband_caps, ++ .config_inband = aqr_gen2_config_inband, +}, - }; - - module_phy_driver(aqr_driver); -@@ -1657,6 +1683,8 @@ static const struct mdio_device_id __may - { PHY_ID_MATCH_MODEL(PHY_ID_AQR115) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, ++{ + PHY_ID_MATCH_MODEL(PHY_ID_AQR412), + .name = "Aquantia AQR412", + .probe = aqr107_probe, +@@ -1693,6 +1747,8 @@ static const struct mdio_device_id __may + { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) }, - { } - }; - + { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR412C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, diff --git a/target/linux/generic/pending-6.18/715-net-phy-aquantia-add-support-for-CUX3410.patch b/target/linux/generic/pending-6.18/715-net-phy-aquantia-add-support-for-CUX3410.patch new file mode 100644 index 0000000000..33069f2836 --- /dev/null +++ b/target/linux/generic/pending-6.18/715-net-phy-aquantia-add-support-for-CUX3410.patch @@ -0,0 +1,102 @@ +From c52f17573b48bdb09be946ba5d70c206ef9b2ab0 Mon Sep 17 00:00:00 2001 +From: Chad Monroe +Date: Fri, 11 Oct 2024 16:41:37 -0700 +Subject: [PATCH] net: phy: aquantia: add support for CUX3410 + +Add support for Marvell CUX3410. This PHY is nearly identical to +the AQR113C but without MACsec, SyncE and PTP support. + +Signed-off-by: Chad Monroe +--- + drivers/net/phy/aquantia/aquantia_main.c | 45 ++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -34,6 +34,7 @@ + #define PHY_ID_AQR115 0x31c31c63 + #define PHY_ID_AQR115C 0x31c31c33 + #define PHY_ID_AQR813 0x31c31cb2 ++#define PHY_ID_CUX3410 0x31c31dd3 + + #define MDIO_PHYXS_VEND_PROV2 0xc441 + #define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3) +@@ -50,6 +51,9 @@ + #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 + #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 + ++#define MDIO_PHYXS_TX_RSVD_VEND_PROV2 0xc441 ++#define MDIO_PHYXS_TX_RSVD_VEND_PROV2_ANEG BIT(3) ++ + #define MDIO_AN_VEND_PROV 0xc400 + #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) + #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) +@@ -195,6 +199,16 @@ static int aqr_set_mdix(struct phy_devic + MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val); + } + ++static int aqr107_config_usx_aneg_en(struct phy_device *phydev) ++{ ++ u16 val; ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_TX_RSVD_VEND_PROV2); ++ val |= MDIO_PHYXS_TX_RSVD_VEND_PROV2_ANEG; ++ ++ return phy_write_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_TX_RSVD_VEND_PROV2, val); ++} ++ + static int aqr_config_aneg(struct phy_device *phydev) + { + bool changed = false; +@@ -806,6 +820,10 @@ static int aqr_gen1_config_init(struct p + if (ret) + return ret; + ++ ret = aqr107_config_usx_aneg_en(phydev); ++ if (ret) ++ phydev_err(phydev, "USX autonegotiation disabled, ret: %d\n", ret); ++ + ret = aqr107_config_mdi(phydev); + if (ret) + return ret; +@@ -1560,6 +1578,32 @@ static struct phy_driver aqr_driver[] = + .inband_caps = aqr_gen2_inband_caps, + .config_inband = aqr_gen2_config_inband, + }, ++{ ++ PHY_ID_MATCH_MODEL(PHY_ID_CUX3410), ++ .name = "Aquantia CUX3410", ++ .probe = aqr107_probe, ++ .get_rate_matching = aqr_gen2_get_rate_matching, ++ .config_init = aqr_gen4_config_init, ++ .config_aneg = aqr_config_aneg, ++ .config_intr = aqr_config_intr, ++ .handle_interrupt = aqr_handle_interrupt, ++ .read_status = aqr_gen2_read_status, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr_gen1_suspend, ++ .resume = aqr_gen1_resume, ++ .get_sset_count = aqr107_get_sset_count, ++ .get_strings = aqr107_get_strings, ++ .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++ .led_brightness_set = aqr_phy_led_brightness_set, ++ .led_hw_is_supported = aqr_phy_led_hw_is_supported, ++ .led_hw_control_set = aqr_phy_led_hw_control_set, ++ .led_hw_control_get = aqr_phy_led_hw_control_get, ++ .led_polarity_set = aqr_phy_led_polarity_set, ++ .inband_caps = aqr_gen2_inband_caps, ++ .config_inband = aqr_gen2_config_inband, ++}, + }; + + module_phy_driver(aqr_driver); +@@ -1583,6 +1627,7 @@ static const struct mdio_device_id __may + { PHY_ID_MATCH_MODEL(PHY_ID_AQR115) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, ++ { PHY_ID_MATCH_MODEL(PHY_ID_CUX3410) }, + { } + }; +