From 4f107d768aa560b323ac215f974aabd409fb763f Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 10 Mar 2026 17:05:16 -0700 Subject: [PATCH 01/88] bcm53xx: mr26: fix nvmem MAC override I wrongly added the wifi devices to the pcie nodes and not the bridge nodes as they were not present at the time. Fixes: 58056df ("bcm53xx: backport nvmem mac for meraki mr26") Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/22369 Signed-off-by: Robert Marko --- .../051-ARM-dts-meraki-mr26-wifi-MACs-in-dts.patch | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/bcm53xx/patches-6.12/051-ARM-dts-meraki-mr26-wifi-MACs-in-dts.patch b/target/linux/bcm53xx/patches-6.12/051-ARM-dts-meraki-mr26-wifi-MACs-in-dts.patch index fd31438cdb..579d18bb96 100644 --- a/target/linux/bcm53xx/patches-6.12/051-ARM-dts-meraki-mr26-wifi-MACs-in-dts.patch +++ b/target/linux/bcm53xx/patches-6.12/051-ARM-dts-meraki-mr26-wifi-MACs-in-dts.patch @@ -25,7 +25,7 @@ Signed-off-by: Rosen Penev status = "disabled"; }; -+&pcie0 { ++&pcie_bridge0 { + wifi@0,0 { + reg = <0x0000 0 0 0 0>; + compatible = "brcm,bcm43431"; @@ -34,7 +34,7 @@ Signed-off-by: Rosen Penev + }; +}; + -+&pcie1 { ++&pcie_bridge1 { + wifi@0,0 { + reg = <0x0000 0 0 0 0>; + compatible = "brcm,bcm43431"; @@ -43,7 +43,7 @@ Signed-off-by: Rosen Penev + }; +}; + -+&pcie2 { ++&pcie_bridge2 { + wifi@0,0 { + reg = <0x0000 0 0 0 0>; + compatible = "brcm,bcm43428"; From ab0872a734dd96f898d01fef14ccd503c283460b Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 11 Mar 2026 17:29:51 +0000 Subject: [PATCH 02/88] procd: update to Git HEAD (2026-03-11) 129b729f757c service: fix use-after-free in per-instance set_data handler Signed-off-by: Felix Fietkau --- package/system/procd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index 1c1b520ffe..c6142ebd40 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git -PKG_MIRROR_HASH:=123c54964fd8048931002bd74181335dfcbff8ed949af2055e367e03180fe287 -PKG_SOURCE_DATE:=2026-02-20 -PKG_SOURCE_VERSION:=2881a59f304326cf0a71c849738d052ba317b4cb +PKG_MIRROR_HASH:=523ab499a2b09270db5498e543b7661fd8db98371c8baaf6bcd6082cd73377c4 +PKG_SOURCE_DATE:=2026-03-11 +PKG_SOURCE_VERSION:=129b729f757ce625cf39601d24d97f4d92db7a7e CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 From 48b8ff890b94e3dd0b717aeb3eb2bdb3b68d316c Mon Sep 17 00:00:00 2001 From: John Audia Date: Tue, 10 Mar 2026 16:22:39 -0400 Subject: [PATCH 03/88] linux-firmware: update to 20260309 % git log --no-merges --pretty=oneline --abbrev-commit 20260110...20260309 6d5c4e499d32 mediatek MT7922: update bluetooth firmware to 20260224103448 e426f99ddbe6 linux-firmware: update firmware for MT7922 WiFi device 21d670224ad1 cirrus: cs42l45: Add CS42L45 SDCA codec firmware for Dell laptops bfebfc16a8b3 cirrus: cs35l63: Add firmware for Cirrus CS35L63 for various Dell laptops cf2d1a574838 linux-firmware: Remove duplicate fw and Rename Lenovo ISH LNLM firmware files accordingly b9e372cffcb0 amdgpu: DMCUB updates for various ASICs 397e9a13dbb4 linux-firmware: Add firmware file for Intel BlazarIGfp2 core b251087087e8 QCA: Update Bluetooth QCA6698 firmware to 2.1.2-00069 f58642691280 qcom: Update CDSP firmware for QCM6490 platform f4fccdeaa58a linux-firmware: add firmware for Lontium LT8713SX DP hub 822ba35b15b1 linux-firmware: qcom: sync audioreach firmwares from v1.0.2 build 6b986839e4bc qcom: update ADSP, CDSP firmware for sm8750 platform eb48837f8acc qcom: update ADSP dtb.mbn for glymur platform 87768b59c878 qca: Update Bluetooth WCN6750 1.1.3-00105 firmware to 1.1.3-00106 64330a97f0f2 QCA: Update Bluetooth WCN6856 firmware 2.1.0-00659 to 2.1.0-00665 bcc17f274d19 amdgpu: update PSP 13.0.14 firmware bed8b292d199 amdgpu: update GC 9.4.4 firmware 40518428a964 amdgpu: update PSP 13.0.5 firmware 6f3948e1a80f amdgpu: update GC 10.3.6 firmware c5c71a6b42ef amdgpu: update PSP 13.0.0 kicker firmware 936b64f49831 amdgpu: update VCN 4.0.0 firmware ca25e8cea638 amdgpu: update PSP 13.0.0 firmware 652378d0d156 amdgpu: update GC 11.0.0 firmware ca31625e94c9 amdgpu: update SDMA 6.1.3 firmware d1b9b7263627 amdgpu: update PSP 14.0.5 firmware ab1f658c787b amdgpu: update GC 11.5.3 firmware 58b10704da49 amdgpu: update beige goby firmware 127e3755fe43 amdgpu: update SDMA 6.1.2 firmware a7669eb10e78 amdgpu: update PSP 14.0.4 firmware e2d3b43db975 amdgpu: update GC 11.5.2 firmware c0bec6f13e3f amdgpu: update dimgrey cavefish firmware 7ab313a9f169 amdgpu: update vangogh firmware 60bd7581c608 amdgpu: update navy flounder firmware 6237f479d99e amdgpu: update PSP 13.0.11 firmware 29ffce4483d3 amdgpu: update GC 11.0.4 firmware 8746dc896220 amdgpu: update VCN 4.0.2 firmware afe6f8da8aec amdgpu: update SDMA 6.0.1 firmware f940f4540549 amdgpu: update PSP 13.0.4 firmware 4e47f7fa71fb amdgpu: update GC 11.0.1 firmware f789bb032a9c amdgpu: update sienna cichlid firmware 48f3c77d8f79 amdgpu: update navi14 firmware 2d7345645d59 amdgpu: update green sardine firmware 31d1b0dd5396 amdgpu: update VCN 4.0.6 firmware 212257aad62c amdgpu: update SDMA 6.1.1 firmware 28dd17d1d31b amdgpu: update PSP 14.0.1 firmware dea4e8a3376c amdgpu: update GC 11.5.1 firmware 8669af2dd952 amdgpu: update VCN 5.0.0 firmware 7177f2135df7 amdgpu: update SMU 14.0.3 firmware 2a0af58da356 amdgpu: update PSP 14.0.3 firmware 1dd31ea90f7f amdgpu: update GC 12.0.1 firmware 4db65e675ed0 amdgpu: update VPE 6.1.0 firmware 4b81a4817629 amdgpu: update VCN 4.0.5 firmware d23903078c5f amdgpu: update SDMA 6.1.0 firmware dea480a1b32b amdgpu: update PSP 14.0.0 firmware de99d0fd70ca amdgpu: update GC 11.5.0 firmware 683aace3644f amdgpu: update navi12 firmware eba8a69fb7b6 amdgpu: update SMU 14.0.2 firmware b39b4a98582b amdgpu: update PSP 14.0.2 firmware 37e9adcb709d amdgpu: update GC 12.0.0 firmware aaca282a05b6 amdgpu: update renoir firmware 18461c2329d1 amdgpu: update navi10 firmware 4773307708e9 amdgpu: update VCN 4.0.4 firmware 897d73a7b650 amdgpu: update SDMA 6.0.2 firmware 1d4fdf2cbdc4 amdgpu: update PSP 13.0.7 firmware 1d5d7a62ebff amdgpu: update GC 11.0.2 firmware ffbc28980e23 amdgpu: update VCN 4.0.3 firmware 138597a4e0bd amdgpu: update PSP 13.0.6 firmware 19e0d4624bdb amdgpu: update GC 9.4.3 firmware a9004d5a0ba4 amdgpu: update yellow carp firmware b5d25d858b7e amdgpu: update PSP 13.0.10 firmware c6feb53895f6 amdgpu: update GC 11.0.3 firmware 95c430cdd81a amdgpu: update VCN 5.0.1 firmware ad7910db6e83 amdgpu: update PSP 13.0.12 firmware e7f955441b97 amdgpu: update GC 9.5.0 firmware 1d609638b772 linux-firmware:Renaming the file back for HP EliteBook X Flip G1i 26668fabcfea linux-firmware:Renaming the file back for HP EliteBook X Flip G1i 49cf497556b9 linux-firmware:Renaming the file back for HP EliteBook X Flip G1i 58cf579b98c0 amdnpu: Restore old NPU firmware for compatibility 4aaa9c557e90 cirrus: cs42l45: Add CS42L45 SDCA codec firmware for Dell laptops feba387aac8f lenovo: remove obsolete ish_lnlm_53c4ffad_2a17559f.bin firmware df954d275a07 linux-firmware: update firmware for MT7902 BT device edc18bd4dc29 linux-firmware: update firmware for MT7902 WiFi device 30a139cb6561 qcom: vpu: fix SC7280 VPU Gen2 firmware and add compatibility symlink 65c7ff3ec808 amdgpu: DMCUB updates for various ASICs 6a24a5a92c32 qcom: Update DSP firmware for qcs8300 platform 39f04545b26f cirrus: cs35l41: Add Firmware for ASUS Zenbook Laptop using CS35L41 HDA 664f8b6adeba qcom: Update DSP firmware for sa8775p platform bed52d78bc0c amdgpu: DMCUB updates for various ASICs 342ce02256f3 rtw89: 8851b: add format-1 for fw v0.29.41.5 with fw elements 4a216696655b rtw89: 8852a: add format-1 for fw v0.13.36.2 with fw elements 0579ff05d882 rtw89: 8852bt: add regd and diag_mac and update txpwr to R09 af193c46b6bd rtw89: 8852b: update txpwr element to R43 81eae19b21a0 rtw89: 8852b: add format-2 with v0.29.29.15 and fw elements 1cfed3e213c5 Revert "rtw89: 8852b: update fw to v0.29.128.0 with format suffix -2" 86725d7351e8 xe: Update GUC to v70.58.0 for LNL, BMG, PTL cbd0f9753754 ath11k: WCN6855 hw2.0: update board-2.bin 65a3c868b360 ath11k: QCA6390 hw2.0: update board-2.bin 0364daaa28a2 qcom: Add gpu firmwares for Glymur chipset 6c1e2562f626 amdgpu: DMCUB updates for various ASICs 2bb21553d510 qcom: vpu: add video firmware for Glymur 8fafd2481eed qcom: add QUPv3 firmware for x1e80100 platform fd38db51a2a6 Bluetooth: Add symbolic links for Intel Solar JfP2/1 firmware variants 07b822cc556d Bluetooth: Add symbolic links for Intel Solar firmware variants 1b902aa966e4 Bluetooth: Add symbolic links for Intel Pulsar firmware variants 949dba8936ab Bluetooth: Add symbolic links for Intel AX201 firmware variants 81a99dba039a ath10k: WCN3990 hw1.0: update board-2.bin b69afa29d3f6 qcom: add ADSP, CDSP firmware for glymur platform 4e83a67a5637 ASoC: tas2783: Add Firmware files for tas2783A 87972e133405 linux-firmware: Update firmware file for Intel Solar core a693bc58e2ac mediatek MT7921: update bluetooth firmware to 20251223091725 fbf93476b789 rtl_bt: Update RTL8822C BT USB and UART firmware to 0x0673 a712a43ff2c0 ath12k: WCN7850 hw2.0: update board-2.bin ec76089d563e ath12k: QCN9274 hw2.0: update to WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1 49df41843d27 ath11k: WCN6855 hw2.0: update board-2.bin fd8bdffeabe4 ath11k: QCA6698AQ hw2.1: update board-2.bin af03e44a2029 WHENCE: Correct 2 trailing whitespaces 1043c0303910 linux-firmware: Add firmware for airoha-npu-7581 driver used for MT7990 offloading f18b40ebf5e8 linux-firmware: Add Dell ISH firmware for Intel panther lake systems 9a727f07bc60 amdgpu: DMCUB updates for various ASICs fb1cfb1989ea linux-firmware: update Aeonsemi AS21x1x firmware to 1.9.1 0fa5e69a0d9e rtl_nic: add firmware rtl8125cp-1 for RTL8125cp dfff492a66a0 ice: update DDP LAG package to 1.3.2.0 db024df1e153 cirrus: cs35l56: Add WHENCE links for 17aa233c spkid0 firmware a80ebbccb826 rtw89: 8922a: update REGD R73-R08, txpwr R46 and element of diag MAC f9c84ebaefbf rtw89: 8852c: update REGD R73-R60, txpwr R82 and element of diag MAC d8fc35003355 Update firmware for NPU PHX, STX and STX HALO a7bd257ea496 qcom: Update ADSP and add CDSP firmware for qcs6490-radxa-dragon-q6a 1ccefae136c4 qcom: Remove ADSP SensorPD json for Radxa Dragon Q6A afae3262fa2f amdgpu: DMCUB updates for various ASICs ff3470eca79b intel/ish: Add Lenovo ISH firmware support for X1 and X9 systems 53ec87319d28 cirrus: cs42l45: Add CS42L45 SDCA codec firmware for Lenovo laptops 8ca12d6383d0 cirrus: cs42l45: Add CS42L45 SDCA codec firmware for Dell laptops ecf00f092a8e cirrus: cs35l57 cs35l63: Add firmware for Cirrus Amps for some Lenovo laptops d01a86bd2b35 cirrus: cs35l56 cs35l57: Add and update firmware for some Dell laptops e22074558beb Intel IPU7: Update firmware binary for Panther Lake a80dabbc28fa linux-firmware: update firmware for MT7921 WiFi device 1e2c15348485 amdgpu: DMCUB updates for various ASICs 9e79ce04180f linux-firmware: Add firmware file for Intel ScorpiusGfp2 core f401a31ab5ba linux-firmware: Update firmware file for Intel Scorpius core 6be3bd6cc295 linux-firmware: Update firmware file for Intel BlazarIGfP core 99a2479f94e1 linux-firmware: Update firmware file for Intel BlazarI core 9bf06b2bdf74 linux-firmware: Update firmware file for Intel BlazarU-HrPGfP core 40a812ce5880 linux-firmware: Update firmware file for Intel BlazarU core 634af751cc56 rtl_bt: Update RTL8852BT/RTL8852BE-VT BT USB FW to 0x06EB_C65F 4cc877a7c241 linux-firmware: Add firmware for airoha-npu-7583 driver 9a9285ce9b44 iwlwifi: add Bz/Sc FW for core102-56 release 579ca4320f6b iwlwifi: Add Hr/Gf firmware for core102-56 release 90af9c636906 iwlwifi: update ty/So/Ma firmwares for core102-56 release 05a6a40bbba8 xe: Add GSC 105.0.2.1301 for PTL 087f9b0a8d23 mediatek: rename MT8188 SCP firmware a438fce32e0e qcom: Update DSP firmware for QCM6490 platform bfc1d7433ddd linux-firmware: qcom: sync audioreach firmwares from v1.0.1 build Build system: x86/64 Build-tested: x86/64-glibc Run-tested: Intel N150 based system Signed-off-by: John Audia Link: https://github.com/openwrt/openwrt/pull/22364 Signed-off-by: Christian Marangi --- package/firmware/linux-firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index dfb8cb10e1..871d450f5f 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20260221 +PKG_VERSION:=20260309 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=bd19acc4c1a02548e09d3df67f987fe6e378df735bab138c1d9e917962056d94 +PKG_HASH:=c74cc6f562b58ad5bc6b2b00a61abc29c9e49e06126e7ba34fbca9928e07a96c PKG_MAINTAINER:=Felix Fietkau From 1f30a3288d336941478ff7d25faf7efb377ca0cb Mon Sep 17 00:00:00 2001 From: Eric Fahlgren Date: Wed, 11 Mar 2026 13:16:34 -0700 Subject: [PATCH 04/88] build: reject non-matching artifacts Check for malformed artifact names before dereferencing them. Fixes: https://github.com/openwrt/openwrt/commit/5816d883ff3884ae96c3293b316f6d56c099eee0 Signed-off-by: Eric Fahlgren Link: https://github.com/openwrt/openwrt/pull/22385 Signed-off-by: Robert Marko --- scripts/json_overview_image_info.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/scripts/json_overview_image_info.py b/scripts/json_overview_image_info.py index c8d0e0ad45..0449bb56d7 100755 --- a/scripts/json_overview_image_info.py +++ b/scripts/json_overview_image_info.py @@ -36,8 +36,9 @@ def add_artifact(artifact, prefix="openwrt-"): output[artifact] = {} for file in files: file = str(file.name) - arch = re.match(r".*Linux-([^.]*)\.", file).group(1) - output[artifact][arch] = file + arch = re.match(r".*Linux-([^.]*)\.", file) + if arch: + output[artifact][arch.group(1)] = file for json_file in work_dir.glob("*.json"): From 369bb6aa5491ba55ed69e94ff362a9ab1cfa7ce4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 12 Nov 2025 13:10:50 +0100 Subject: [PATCH 05/88] microchipsw: tactical-1000: rename ports Rename the network ports so they match the information printed on the case. Signed-off-by: Robert Marko --- .../microchipsw/dts/lan9696-tactical-1000.dts | 29 +++++++++++++++++++ .../lan969x/base-files/etc/board.d/02_network | 2 +- .../lib/preinit/04_set_netdev_label | 15 ++++++++++ ...arx5-lan969x-populate-netdev-of_node.patch | 26 +++++++++++++++++ 4 files changed, 71 insertions(+), 1 deletion(-) create mode 100755 target/linux/microchipsw/lan969x/base-files/lib/preinit/04_set_netdev_label create mode 100644 target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch diff --git a/target/linux/microchipsw/dts/lan9696-tactical-1000.dts b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts index 1ee1d3ab55..4aeadc7fd2 100644 --- a/target/linux/microchipsw/dts/lan9696-tactical-1000.dts +++ b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts @@ -585,6 +585,7 @@ phy-mode = "qsgmii"; phys = <&serdes 0>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan4"; }; port1: port@1 { @@ -593,6 +594,7 @@ phy-mode = "qsgmii"; phys = <&serdes 0>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan3"; }; port2: port@2 { @@ -601,6 +603,7 @@ phy-mode = "qsgmii"; phys = <&serdes 0>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan2"; }; port3: port@3 { @@ -609,6 +612,7 @@ phy-mode = "qsgmii"; phys = <&serdes 0>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan1"; }; port4: port@4 { @@ -617,6 +621,7 @@ phy-mode = "qsgmii"; phys = <&serdes 1>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan8"; }; port5: port@5 { @@ -625,6 +630,7 @@ phy-mode = "qsgmii"; phys = <&serdes 1>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan7"; }; port6: port@6 { @@ -633,6 +639,7 @@ phy-mode = "qsgmii"; phys = <&serdes 1>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan6"; }; port7: port@7 { @@ -641,6 +648,7 @@ phy-mode = "qsgmii"; phys = <&serdes 1>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan5"; }; port8: port@8 { @@ -649,6 +657,7 @@ phy-mode = "qsgmii"; phys = <&serdes 2>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan12"; }; port9: port@9 { @@ -657,6 +666,7 @@ phy-mode = "qsgmii"; phys = <&serdes 2>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan11"; }; port10: port@10 { @@ -665,6 +675,7 @@ phy-mode = "qsgmii"; phys = <&serdes 2>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan10"; }; port11: port@11 { @@ -673,6 +684,7 @@ phy-mode = "qsgmii"; phys = <&serdes 2>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan9"; }; port12: port@12 { @@ -681,6 +693,7 @@ phy-mode = "qsgmii"; phys = <&serdes 3>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan16"; }; port13: port@13 { @@ -689,6 +702,7 @@ phy-mode = "qsgmii"; phys = <&serdes 3>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan15"; }; port14: port@14 { @@ -697,6 +711,7 @@ phy-mode = "qsgmii"; phys = <&serdes 3>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan14"; }; port15: port@15 { @@ -705,6 +720,7 @@ phy-mode = "qsgmii"; phys = <&serdes 3>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan13"; }; port16: port@16 { @@ -713,6 +729,7 @@ phy-mode = "qsgmii"; phys = <&serdes 4>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan20"; }; port17: port@17 { @@ -721,6 +738,7 @@ phy-mode = "qsgmii"; phys = <&serdes 4>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan19"; }; port18: port@18 { @@ -729,6 +747,7 @@ phy-mode = "qsgmii"; phys = <&serdes 4>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan18"; }; port19: port@19 { @@ -737,6 +756,7 @@ phy-mode = "qsgmii"; phys = <&serdes 4>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan17"; }; port20: port@20 { @@ -745,6 +765,7 @@ phy-mode = "qsgmii"; phys = <&serdes 5>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan24"; }; port21: port@21 { @@ -753,6 +774,7 @@ phy-mode = "qsgmii"; phys = <&serdes 5>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan23"; }; port22: port@22 { @@ -761,6 +783,7 @@ phy-mode = "qsgmii"; phys = <&serdes 5>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan22"; }; port23: port@23 { @@ -769,6 +792,7 @@ phy-mode = "qsgmii"; phys = <&serdes 5>; microchip,bandwidth = <1000>; + openwrt,netdev-name = "lan21"; }; port24: port@24 { @@ -779,6 +803,7 @@ managed = "in-band-status"; microchip,bandwidth = <10000>; microchip,sd-sgpio = <24>; + openwrt,netdev-name = "sfp1"; }; port25: port@25 { @@ -789,6 +814,7 @@ managed = "in-band-status"; microchip,bandwidth = <10000>; microchip,sd-sgpio = <28>; + openwrt,netdev-name = "sfp2"; }; port26: port@26 { @@ -799,6 +825,7 @@ managed = "in-band-status"; microchip,bandwidth = <10000>; microchip,sd-sgpio = <32>; + openwrt,netdev-name = "sfp3"; }; port27: port@27 { @@ -809,6 +836,7 @@ managed = "in-band-status"; microchip,bandwidth = <10000>; microchip,sd-sgpio = <36>; + openwrt,netdev-name = "sfp4"; }; port29: port@29 { @@ -817,6 +845,7 @@ phy-handle = <&phy3>; phy-mode = "rgmii-id"; microchip,bandwidth = <1000>; + openwrt,netdev-name = "mgmt"; }; }; }; diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network index fcf03f88a3..726207d833 100644 --- a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network @@ -9,7 +9,7 @@ lan969x_setup_interfaces() case "$board" in microchip,ev23x71a|\ novarq,tactical-1000) - lan_list=$(ls -1 -v -d /sys/class/net/eth* | xargs -n1 basename | xargs) + lan_list=$(ls -1 -v -d /sys/class/net/eth* /sys/class/net/lan* /sys/class/net/sfp* /sys/class/net/mgmt* | xargs -n1 basename | xargs) ucidef_set_interface_lan "$lan_list" ;; *) diff --git a/target/linux/microchipsw/lan969x/base-files/lib/preinit/04_set_netdev_label b/target/linux/microchipsw/lan969x/base-files/lib/preinit/04_set_netdev_label new file mode 100755 index 0000000000..2042d56315 --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/lib/preinit/04_set_netdev_label @@ -0,0 +1,15 @@ +set_netdev_labels() { + local dir + local label + local netdev + + for dir in /sys/class/net/*; do + [ -r "$dir/of_node/openwrt,netdev-name" ] || continue + read -r label < "$dir/of_node/openwrt,netdev-name" + netdev="${dir##*/}" + [ "$netdev" = "$label" ] && continue + ip link set "$netdev" name "$label" + done +} + +boot_hook_add preinit_main set_netdev_labels diff --git a/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch b/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch new file mode 100644 index 0000000000..d1eccda589 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0097-v6.19-net-sparx5-lan969x-populate-netdev-of_node.patch @@ -0,0 +1,26 @@ +From fc6aa0e470e092873eddb213d996a8beee86bf4d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 10 Nov 2025 13:42:53 +0100 +Subject: [PATCH] net: sparx5/lan969x: populate netdev of_node + +Populate of_node for the port netdevs, to make the individual ports +of_nodes available in sysfs. + +Signed-off-by: Robert Marko +Link: https://patch.msgid.link/20251110124342.199216-1-robert.marko@sartura.hr +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -396,6 +396,8 @@ static int sparx5_create_port(struct spa + + spx5_port->phylink = phylink; + ++ spx5_port->ndev->dev.of_node = spx5_port->of_node; ++ + return 0; + } + From b4df523754e8364fcab92db2e2724a6146495a0c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 26 Feb 2026 15:04:21 +0100 Subject: [PATCH 06/88] microchipsw: backport fix for ets qdisc offload Backport upstream fix for ets qdisc offloading. Signed-off-by: Robert Marko --- ...9x-fix-DWRR-cost-max-to-match-hardwa.patch | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch diff --git a/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch b/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch new file mode 100644 index 0000000000..27c4a31912 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch @@ -0,0 +1,38 @@ +From 6c28aa8dfdf24f554d4c5d4ff7d723a95360d94a Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Tue, 10 Feb 2026 14:44:01 +0100 +Subject: [PATCH] net: sparx5/lan969x: fix DWRR cost max to match hardware + register width + +DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth +across traffic classes based on per-queue cost values, where lower cost +means higher bandwidth share. + +The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware +register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only +5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to +compute cost values that silently overflow via FIELD_PREP, resulting +in incorrect scheduling weights. + +Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width. + +Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc") +Signed-off-by: Daniel Machon +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_qos.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h +@@ -35,7 +35,7 @@ + #define SPX5_SE_BURST_UNIT 4096 + + /* Dwrr */ +-#define SPX5_DWRR_COST_MAX 63 ++#define SPX5_DWRR_COST_MAX 31 + + struct sparx5_shaper { + u32 mode; From 55f1f2c1c447f87f904ccaf67747a41a355766b3 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 12 Mar 2026 11:05:40 +0100 Subject: [PATCH 07/88] microchipsw: lan969x: tactical-1000: fix SFP I2C buses SFP I2C buses for ports 1 and 3 were swapped as order changed on production boards. So, swap them around to fix SFP 1 and 3 failed to read EEPROM errors. Fixes: 29b3d929a610 ("microchipsw: lan969x: add Novarq Tactical 1000") Signed-off-by: Robert Marko --- target/linux/microchipsw/dts/lan9696-tactical-1000.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/microchipsw/dts/lan9696-tactical-1000.dts b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts index 4aeadc7fd2..6f70b3d5e1 100644 --- a/target/linux/microchipsw/dts/lan9696-tactical-1000.dts +++ b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts @@ -58,7 +58,7 @@ <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; settle-time-us = <100>; - i2c_sfp0: i2c@0 { + i2c_sfp2: i2c@0 { reg = <0x0>; }; @@ -66,7 +66,7 @@ reg = <0x1>; }; - i2c_sfp2: i2c@2 { + i2c_sfp0: i2c@2 { reg = <0x2>; }; From 8a7eb57ab8366045d7e1470c003827391e37684b Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 12 Mar 2026 20:27:17 +0100 Subject: [PATCH 08/88] umdns: update to Git HEAD (2026-02-06) a52cdb354d13 dns: validate IPv4 record addresses b798c24205b5 dns: validate IPv6 record addresses a3dcb4adc635 dns: validate reverse dns query name lengths Signed-off-by: Jonas Gorski --- package/network/services/umdns/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/services/umdns/Makefile b/package/network/services/umdns/Makefile index f1d04d559b..d2e6d18dd5 100644 --- a/package/network/services/umdns/Makefile +++ b/package/network/services/umdns/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_URL=$(PROJECT_GIT)/project/mdnsd.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-10-04 -PKG_SOURCE_VERSION:=2f75344fd0cc848558bf2ea3a94c0bf8b903ff89 -PKG_MIRROR_HASH:=ca03392a39e3e38b276514d4627bab25093cf873abf361352c82dfec0c4bdc93 +PKG_SOURCE_DATE:=2026-02-06 +PKG_SOURCE_VERSION:=a52cdb354d13c179150d2ba26f9f8a51d418b43d +PKG_MIRROR_HASH:=64d6b454aefd208881a130ec0d503e690375565ed3de0171a8c70f5d1a4a25bf PKG_MAINTAINER:=John Crispin PKG_LICENSE:=LGPL-2.1 From 1d63b427ba6e88b999ffcd0c1d6fcdcce23dda57 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 13 Mar 2026 00:04:05 +0100 Subject: [PATCH 09/88] libubox: update to Git HEAD (2026-03-13) 815633847cd3 CMakeLists.txt: remove -Werror=format-nonliteral Signed-off-by: Hauke Mehrtens --- package/libs/libubox/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/libubox/Makefile b/package/libs/libubox/Makefile index ebe01cbe64..d0d1c2570d 100644 --- a/package/libs/libubox/Makefile +++ b/package/libs/libubox/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/libubox.git -PKG_MIRROR_HASH:=fb43a86d13bbbf16d47358caa2fe7eec3b802e3a57ba5142520add159469c927 -PKG_SOURCE_DATE:=2026-02-13 -PKG_SOURCE_VERSION:=1aa36ee774c8db4d7a396903e0d2e1fb79ee8bf1 +PKG_MIRROR_HASH:=55b2298ea74bb4c7267e4b615d442aeff601e0de88ec0e641e4c40eed8454e85 +PKG_SOURCE_DATE:=2026-03-13 +PKG_SOURCE_VERSION:=815633847cd32ffe6da28943cbeb37edc88265c8 PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE)) CMAKE_INSTALL:=1 From e65d3f9052e6fb34b1da669a3a338d9981c4c35d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 13 Mar 2026 10:10:45 +0100 Subject: [PATCH 10/88] qca-nss-dp: update to Git HEAD (2026-03-13) 22fb70661799 fix flex array not at end of struct 6a5c4716ca25 convert memcpy + ETH_GSTRING_LEN to ethtool_puts Signed-off-by: Robert Marko --- package/kernel/qca-nss-dp/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/kernel/qca-nss-dp/Makefile b/package/kernel/qca-nss-dp/Makefile index 4d90281731..b85a6aee0e 100644 --- a/package/kernel/qca-nss-dp/Makefile +++ b/package/kernel/qca-nss-dp/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_URL:=https://github.com/openwrt/qca-nss-dp.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-11-24 -PKG_SOURCE_VERSION:=19c51af0c5be0afcbd57a9e0e50928759d7d08da -PKG_MIRROR_HASH:=96aafb7c8f09ecde036ed706535111368874b06cd412a7b9df950415e5b4b334 +PKG_SOURCE_DATE:=2026-03-13 +PKG_SOURCE_VERSION:=6a5c4716ca258d67202fc7964c9294dfefa3ccfa +PKG_MIRROR_HASH:=5f9a9a44f91842492d8c9038670379011b90e68fda7af291b2bdd81889a9ea1a PKG_BUILD_PARALLEL:=1 PKG_FLAGS:=nonshared From 873120b4ffaf17ad8d72e4e654a6d9657d34a9cb Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 12 Mar 2026 20:45:58 +0100 Subject: [PATCH 11/88] ipq40xx: wr-1: fix WLAN LEDs labels Restore the lost band label. Fixes: 502ac21e8fde ("ipq40xx: drop redundant label with new LED color/function format") Signed-off-by: Tomasz Maciej Nowak --- target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts index f9daf3f32d..a6c3af8b92 100644 --- a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts +++ b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts @@ -46,14 +46,14 @@ wlan2g { gpios = <&tlmm 1 GPIO_ACTIVE_LOW>; color = ; - function = LED_FUNCTION_WLAN; + function = LED_FUNCTION_WLAN_2GHZ; linux,default-trigger = "phy0tpt"; }; wlan5g { gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; color = ; - function = LED_FUNCTION_WLAN; + function = LED_FUNCTION_WLAN_5GHZ; linux,default-trigger = "phy1tpt"; }; }; From f93dd5ecde6ca3ce646200f515479f86efc0a76e Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 12 Mar 2026 20:45:59 +0100 Subject: [PATCH 12/88] ipq40xx: wr-1: remove TODO The MAC address is sourced from U-Boot environment. Signed-off-by: Tomasz Maciej Nowak --- target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts index a6c3af8b92..b3fb85714e 100644 --- a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts +++ b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts @@ -11,7 +11,6 @@ compatible = "pakedge,wr-1"; aliases { - // TODO: Verify if the ethernet0 alias is needed ethernet0 = &gmac; label-mac-device = &gmac; led-boot = &led_power; From a11b33eb3fa343d9726a8bfc8cb058f964921925 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 12 Mar 2026 20:46:00 +0100 Subject: [PATCH 13/88] ipq40xx: wr-1: wire up switch LEDs This will allow controlling them from sysfs. Signed-off-by: Tomasz Maciej Nowak --- .../linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts index b3fb85714e..6fb90b6627 100644 --- a/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts +++ b/target/linux/ipq40xx/dts/qcom-ipq4018-wr-1.dts @@ -176,6 +176,80 @@ status = "okay"; }; +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + default-state = "keep"; + }; + }; +}; + +ðphy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + default-state = "keep"; + }; + }; +}; + +ðphy2 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; +}; + +ðphy3 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + }; +}; + +ðphy4 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; +}; + &gmac { status = "okay"; }; From a654fa7fe4f1a3a244543cb0ba73f4c9a0acd872 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 12 Mar 2026 20:44:50 +0100 Subject: [PATCH 14/88] ipq40xx: wrtq-329acn: remove ethernet alias The mac addresses are sourced from ART partition. Signed-off-by: Tomasz Maciej Nowak --- target/linux/ipq40xx/dts/qcom-ipq4018-wrtq-329acn.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/linux/ipq40xx/dts/qcom-ipq4018-wrtq-329acn.dts b/target/linux/ipq40xx/dts/qcom-ipq4018-wrtq-329acn.dts index 8b5bf7a051..bacf6753d7 100644 --- a/target/linux/ipq40xx/dts/qcom-ipq4018-wrtq-329acn.dts +++ b/target/linux/ipq40xx/dts/qcom-ipq4018-wrtq-329acn.dts @@ -9,11 +9,6 @@ model = "Luma Home WRTQ-329ACN"; compatible = "luma,wrtq-329acn"; - aliases { - // TODO: Verify if the ethernet0 alias is needed - ethernet0 = &gmac; - }; - i2c-gpio { compatible = "i2c-gpio"; sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; From d85a33283151dba230e359332c0fff09d072546f Mon Sep 17 00:00:00 2001 From: Matt Merhar Date: Thu, 5 Mar 2026 22:05:40 -0500 Subject: [PATCH 15/88] mac80211: ath12k: backport thermal sensor support This is nearly identical to what landed in ath-next for v7.1, aside from resolving a couple conflicts. A separate patch has been added to replace CONFIG_THERMAL with CPTCFG_ATH12K_THERMAL so the setting may be enabled via menuconfig (as is done with ath10k and ath11k). Note that at this stage, throttling has not been implemented upstream, hence the slight change in wording versus existing options. Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1 Link: https://patch.msgid.link/20260223132622.43464-1-maharaja.kennadyrajan@oss.qualcomm.com Signed-off-by: Matt Merhar Link: https://github.com/openwrt/openwrt/pull/22280 Signed-off-by: Robert Marko --- package/kernel/mac80211/ath.mk | 13 +- ...49-wifi-ath11k-fix-monitor-rx-pktlen.patch | 6 +- ...dd-basic-hwmon-temperature-reporting.patch | 380 ++++++++++++++++++ ...k-control-thermal-support-via-symbol.patch | 62 +++ ...support-for-loading-EEPROM-from-user.patch | 2 +- 5 files changed, 457 insertions(+), 6 deletions(-) create mode 100644 package/kernel/mac80211/patches/ath12k/001-v7.1-wifi-ath12k-add-basic-hwmon-temperature-reporting.patch create mode 100644 package/kernel/mac80211/patches/ath12k/300-ath12k-control-thermal-support-via-symbol.patch diff --git a/package/kernel/mac80211/ath.mk b/package/kernel/mac80211/ath.mk index 35c36954e5..9adb8914cd 100644 --- a/package/kernel/mac80211/ath.mk +++ b/package/kernel/mac80211/ath.mk @@ -13,6 +13,7 @@ PKG_CONFIG_DEPENDS += \ CONFIG_ATH10K_LEDS \ CONFIG_ATH10K_THERMAL \ CONFIG_ATH11K_THERMAL \ + CONFIG_ATH12K_THERMAL \ CONFIG_ATH_USER_REGD ifdef CONFIG_PACKAGE_MAC80211_DEBUGFS @@ -59,6 +60,7 @@ config-$(CONFIG_ATH9K_UBNTHSR) += ATH9K_UBNTHSR config-$(CONFIG_ATH10K_LEDS) += ATH10K_LEDS config-$(CONFIG_ATH10K_THERMAL) += ATH10K_THERMAL config-$(CONFIG_ATH11K_THERMAL) += ATH11K_THERMAL +config-$(CONFIG_ATH12K_THERMAL) += ATH12K_THERMAL config-$(call config_package,ath9k-htc) += ATH9K_HTC config-$(call config_package,ath10k,regular) += ATH10K ATH10K_PCI @@ -368,7 +370,8 @@ define KernelPackage/ath12k URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath12k DEPENDS+= @PCI_SUPPORT +kmod-ath +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT \ +kmod-crypto-michael-mic +kmod-qrtr-mhi \ - +kmod-qcom-qmi-helpers +@DRIVER_11BE_SUPPORT + +kmod-qcom-qmi-helpers +@DRIVER_11BE_SUPPORT \ + +ATH12K_THERMAL:kmod-hwmon-core +ATH12K_THERMAL:kmod-thermal FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath12k/ath12k.ko AUTOLOAD:=$(call AutoProbe,ath12k) endef @@ -378,6 +381,14 @@ This module adds support for Qualcomm Technologies 802.11be family of chipsets with PCI bus. endef +define KernelPackage/ath12k/config + + config ATH12K_THERMAL + bool "Enable ath12k thermal sensor support" + depends on PACKAGE_kmod-ath12k + +endef + define KernelPackage/carl9170 $(call KernelPackage/mac80211/Default) TITLE:=Driver for Atheros AR9170 USB sticks diff --git a/package/kernel/mac80211/patches/ath11k/949-wifi-ath11k-fix-monitor-rx-pktlen.patch b/package/kernel/mac80211/patches/ath11k/949-wifi-ath11k-fix-monitor-rx-pktlen.patch index 98d0db137c..638d2dc7e2 100644 --- a/package/kernel/mac80211/patches/ath11k/949-wifi-ath11k-fix-monitor-rx-pktlen.patch +++ b/package/kernel/mac80211/patches/ath11k/949-wifi-ath11k-fix-monitor-rx-pktlen.patch @@ -22,10 +22,8 @@ This patch: This targets monitor capture length correctness only and keeps the fix scoped to the monitor RX delivery path. -Index: backports-6.18.7/drivers/net/wireless/ath/ath11k/dp_rx.c -=================================================================== ---- backports-6.18.7.orig/drivers/net/wireless/ath/ath11k/dp_rx.c -+++ backports-6.18.7/drivers/net/wireless/ath/ath11k/dp_rx.c +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c @@ -4931,8 +4931,13 @@ ath11k_dp_rx_mon_merg_msdus(struct ath11 } diff --git a/package/kernel/mac80211/patches/ath12k/001-v7.1-wifi-ath12k-add-basic-hwmon-temperature-reporting.patch b/package/kernel/mac80211/patches/ath12k/001-v7.1-wifi-ath12k-add-basic-hwmon-temperature-reporting.patch new file mode 100644 index 0000000000..f861283ca7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/001-v7.1-wifi-ath12k-add-basic-hwmon-temperature-reporting.patch @@ -0,0 +1,380 @@ +From 151322bccdbdb132f5a73cc8ad5d3ab89b90ed52 Mon Sep 17 00:00:00 2001 +From: Maharaja Kennadyrajan +Date: Mon, 23 Feb 2026 18:56:22 +0530 +Subject: wifi: ath12k: add basic hwmon temperature reporting + +Add initial thermal support by wiring up a per-radio (pdev) hwmon temperature +sensor backed by the existing WMI pdev temperature command and event. +When userspace reads the sysfs file temp1_input, the driver sends +WMI_PDEV_GET_TEMPERATURE_CMDID (tag WMI_TAG_PDEV_GET_TEMPERATURE_CMD) and waits +for the corresponding WMI_PDEV_TEMPERATURE_EVENTID +(tag WMI_TAG_PDEV_TEMPERATURE_EVENT) to get the temperature and pdev_id. + +Export the reported value in millidegrees Celsius as required by hwmon. +The temperature reported is per-radio (pdev). In a multi-radio wiphy under a +single phy, a separate hwmon device is created for each radio. + +Sample command and output: +$ cat /sys/devices/pci0000:00/.../ieee80211/phyX/hwmonY/temp1_input +$ 50000 + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1 +Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 + +Co-developed-by: Aishwarya R +Signed-off-by: Aishwarya R +Signed-off-by: Maharaja Kennadyrajan +Reviewed-by: Vasanthakumar Thiagarajan +Link: https://patch.msgid.link/20260223132622.43464-1-maharaja.kennadyrajan@oss.qualcomm.com +Signed-off-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/Makefile | 1 + + drivers/net/wireless/ath/ath12k/core.c | 13 ++++ + drivers/net/wireless/ath/ath12k/core.h | 3 + + drivers/net/wireless/ath/ath12k/mac.c | 4 + + drivers/net/wireless/ath/ath12k/thermal.c | 124 ++++++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath12k/thermal.h | 40 ++++++++++ + drivers/net/wireless/ath/ath12k/wmi.c | 57 +++++++------- + 7 files changed, 211 insertions(+), 31 deletions(-) + create mode 100644 drivers/net/wireless/ath/ath12k/thermal.c + create mode 100644 drivers/net/wireless/ath/ath12k/thermal.h + +--- a/drivers/net/wireless/ath/ath12k/core.c ++++ b/drivers/net/wireless/ath/ath12k/core.c +@@ -857,11 +857,22 @@ static int ath12k_core_pdev_create(struc + return ret; + } + ++ ret = ath12k_thermal_register(ab); ++ if (ret) { ++ ath12k_err(ab, "could not register thermal device: %d\n", ret); ++ goto err_dp_pdev_free; ++ } ++ + return 0; ++ ++err_dp_pdev_free: ++ ath12k_dp_pdev_free(ab); ++ return ret; + } + + static void ath12k_core_pdev_destroy(struct ath12k_base *ab) + { ++ ath12k_thermal_unregister(ab); + ath12k_dp_pdev_free(ab); + } + +@@ -1350,6 +1361,7 @@ static int ath12k_core_reconfigure_on_cr + int ret, total_vdev; + + mutex_lock(&ab->core_lock); ++ ath12k_thermal_unregister(ab); + ath12k_dp_pdev_free(ab); + ath12k_ce_cleanup_pipes(ab); + ath12k_wmi_detach(ab); +@@ -1491,6 +1503,7 @@ static void ath12k_core_pre_reconfigure_ + complete(&ar->vdev_delete_done); + complete(&ar->bss_survey_done); + complete_all(&ar->regd_update_completed); ++ complete_all(&ar->thermal.wmi_sync); + + wake_up(&ar->dp.tx_empty_waitq); + idr_for_each(&ar->txmgmt_idr, +--- a/drivers/net/wireless/ath/ath12k/core.h ++++ b/drivers/net/wireless/ath/ath12k/core.h +@@ -34,6 +34,7 @@ + #include "wow.h" + #include "debugfs_htt_stats.h" + #include "coredump.h" ++#include "thermal.h" + + #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) + +@@ -846,6 +847,8 @@ struct ath12k { + + s8 max_allowed_tx_power; + struct ath12k_pdev_rssi_offsets rssi_info; ++ ++ struct ath12k_thermal thermal; + }; + + struct ath12k_hw { +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -14057,6 +14057,10 @@ static void ath12k_mac_setup(struct ath1 + init_completion(&ar->mlo_setup_done); + init_completion(&ar->completed_11d_scan); + init_completion(&ar->regd_update_completed); ++ init_completion(&ar->thermal.wmi_sync); ++ ++ ar->thermal.temperature = 0; ++ ar->thermal.hwmon_dev = NULL; + + INIT_DELAYED_WORK(&ar->scan.timeout, ath12k_scan_timeout_work); + wiphy_work_init(&ar->scan.vdev_clean_wk, ath12k_scan_vdev_clean_work); +--- a/drivers/net/wireless/ath/ath12k/Makefile ++++ b/drivers/net/wireless/ath/ath12k/Makefile +@@ -30,6 +30,7 @@ ath12k-$(CPTCFG_ATH12K_TRACING) += trace + ath12k-$(CONFIG_PM) += wow.o + ath12k-$(CPTCFG_ATH12K_COREDUMP) += coredump.o + ath12k-$(CPTCFG_NL80211_TESTMODE) += testmode.o ++ath12k-$(CONFIG_THERMAL) += thermal.o + + # for tracing framework to find trace.h + CFLAGS_trace.o := -I$(src) +--- /dev/null ++++ b/drivers/net/wireless/ath/ath12k/thermal.c +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: BSD-3-Clause-Clear ++/* ++ * Copyright (c) 2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "core.h" ++#include "debug.h" ++ ++static ssize_t ath12k_thermal_temp_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct ath12k *ar = dev_get_drvdata(dev); ++ unsigned long time_left; ++ int ret, temperature; ++ ++ guard(wiphy)(ath12k_ar_to_hw(ar)->wiphy); ++ ++ if (ar->ah->state != ATH12K_HW_STATE_ON) ++ return -ENETDOWN; ++ ++ reinit_completion(&ar->thermal.wmi_sync); ++ ret = ath12k_wmi_send_pdev_temperature_cmd(ar); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to read temperature %d\n", ret); ++ return ret; ++ } ++ ++ if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) ++ return -ESHUTDOWN; ++ ++ time_left = wait_for_completion_timeout(&ar->thermal.wmi_sync, ++ ATH12K_THERMAL_SYNC_TIMEOUT_HZ); ++ if (!time_left) { ++ ath12k_warn(ar->ab, "failed to synchronize thermal read\n"); ++ return -ETIMEDOUT; ++ } ++ ++ spin_lock_bh(&ar->data_lock); ++ temperature = ar->thermal.temperature; ++ spin_unlock_bh(&ar->data_lock); ++ ++ /* display in millidegree celsius */ ++ return sysfs_emit(buf, "%d\n", temperature * 1000); ++} ++ ++void ath12k_thermal_event_temperature(struct ath12k *ar, int temperature) ++{ ++ spin_lock_bh(&ar->data_lock); ++ ar->thermal.temperature = temperature; ++ spin_unlock_bh(&ar->data_lock); ++ complete_all(&ar->thermal.wmi_sync); ++} ++ ++static SENSOR_DEVICE_ATTR_RO(temp1_input, ath12k_thermal_temp, 0); ++ ++static struct attribute *ath12k_hwmon_attrs[] = { ++ &sensor_dev_attr_temp1_input.dev_attr.attr, ++ NULL, ++}; ++ATTRIBUTE_GROUPS(ath12k_hwmon); ++ ++int ath12k_thermal_register(struct ath12k_base *ab) ++{ ++ struct ath12k *ar; ++ int i, j, ret; ++ ++ if (!IS_REACHABLE(CONFIG_HWMON)) ++ return 0; ++ ++ for (i = 0; i < ab->num_radios; i++) { ++ ar = ab->pdevs[i].ar; ++ if (!ar) ++ continue; ++ ++ ar->thermal.hwmon_dev = ++ hwmon_device_register_with_groups(&ar->ah->hw->wiphy->dev, ++ "ath12k_hwmon", ar, ++ ath12k_hwmon_groups); ++ if (IS_ERR(ar->thermal.hwmon_dev)) { ++ ret = PTR_ERR(ar->thermal.hwmon_dev); ++ ar->thermal.hwmon_dev = NULL; ++ ath12k_err(ar->ab, "failed to register hwmon device: %d\n", ++ ret); ++ for (j = i - 1; j >= 0; j--) { ++ ar = ab->pdevs[j].ar; ++ if (!ar) ++ continue; ++ ++ hwmon_device_unregister(ar->thermal.hwmon_dev); ++ ar->thermal.hwmon_dev = NULL; ++ } ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++void ath12k_thermal_unregister(struct ath12k_base *ab) ++{ ++ struct ath12k *ar; ++ int i; ++ ++ if (!IS_REACHABLE(CONFIG_HWMON)) ++ return; ++ ++ for (i = 0; i < ab->num_radios; i++) { ++ ar = ab->pdevs[i].ar; ++ if (!ar) ++ continue; ++ ++ if (ar->thermal.hwmon_dev) { ++ hwmon_device_unregister(ar->thermal.hwmon_dev); ++ ar->thermal.hwmon_dev = NULL; ++ } ++ } ++} +--- /dev/null ++++ b/drivers/net/wireless/ath/ath12k/thermal.h +@@ -0,0 +1,40 @@ ++/* SPDX-License-Identifier: BSD-3-Clause-Clear */ ++/* ++ * Copyright (c) 2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. ++ */ ++ ++#ifndef _ATH12K_THERMAL_ ++#define _ATH12K_THERMAL_ ++ ++#define ATH12K_THERMAL_SYNC_TIMEOUT_HZ (5 * HZ) ++ ++struct ath12k_thermal { ++ struct completion wmi_sync; ++ ++ /* temperature value in Celsius degree protected by data_lock. */ ++ int temperature; ++ struct device *hwmon_dev; ++}; ++ ++#if IS_REACHABLE(CONFIG_THERMAL) ++int ath12k_thermal_register(struct ath12k_base *ab); ++void ath12k_thermal_unregister(struct ath12k_base *ab); ++void ath12k_thermal_event_temperature(struct ath12k *ar, int temperature); ++#else ++static inline int ath12k_thermal_register(struct ath12k_base *ab) ++{ ++ return 0; ++} ++ ++static inline void ath12k_thermal_unregister(struct ath12k_base *ab) ++{ ++} ++ ++static inline void ath12k_thermal_event_temperature(struct ath12k *ar, ++ int temperature) ++{ ++} ++ ++#endif ++#endif /* _ATH12K_THERMAL_ */ +--- a/drivers/net/wireless/ath/ath12k/wmi.c ++++ b/drivers/net/wireless/ath/ath12k/wmi.c +@@ -6674,31 +6674,6 @@ static int ath12k_pull_peer_assoc_conf_e + return 0; + } + +-static int +-ath12k_pull_pdev_temp_ev(struct ath12k_base *ab, struct sk_buff *skb, +- const struct wmi_pdev_temperature_event *ev) +-{ +- const void **tb; +- int ret; +- +- tb = ath12k_wmi_tlv_parse_alloc(ab, skb, GFP_ATOMIC); +- if (IS_ERR(tb)) { +- ret = PTR_ERR(tb); +- ath12k_warn(ab, "failed to parse tlv: %d\n", ret); +- return ret; +- } +- +- ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT]; +- if (!ev) { +- ath12k_warn(ab, "failed to fetch pdev temp ev"); +- kfree(tb); +- return -EPROTO; +- } +- +- kfree(tb); +- return 0; +-} +- + static void ath12k_wmi_op_ep_tx_credits(struct ath12k_base *ab) + { + /* try to send pending beacons first. they take priority */ +@@ -8713,25 +8688,45 @@ static void + ath12k_wmi_pdev_temperature_event(struct ath12k_base *ab, + struct sk_buff *skb) + { ++ const struct wmi_pdev_temperature_event *ev; + struct ath12k *ar; +- struct wmi_pdev_temperature_event ev = {}; ++ const void **tb; ++ int temp; ++ u32 pdev_id; + +- if (ath12k_pull_pdev_temp_ev(ab, skb, &ev) != 0) { +- ath12k_warn(ab, "failed to extract pdev temperature event"); ++ tb = ath12k_wmi_tlv_parse_alloc(ab, skb, GFP_ATOMIC); ++ if (IS_ERR(tb)) { ++ ath12k_warn(ab, "failed to parse tlv: %ld\n", PTR_ERR(tb)); + return; + } + ++ ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT]; ++ if (!ev) { ++ ath12k_warn(ab, "failed to fetch pdev temp ev\n"); ++ kfree(tb); ++ return; ++ } ++ ++ temp = a_sle32_to_cpu(ev->temp); ++ pdev_id = le32_to_cpu(ev->pdev_id); ++ ++ kfree(tb); ++ + ath12k_dbg(ab, ATH12K_DBG_WMI, +- "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id); ++ "pdev temperature ev temp %d pdev_id %u\n", ++ temp, pdev_id); + + rcu_read_lock(); + +- ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev.pdev_id)); ++ ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); + if (!ar) { +- ath12k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id); ++ ath12k_warn(ab, "invalid pdev id %u in pdev temperature ev\n", ++ pdev_id); + goto exit; + } + ++ ath12k_thermal_event_temperature(ar, temp); ++ + exit: + rcu_read_unlock(); + } diff --git a/package/kernel/mac80211/patches/ath12k/300-ath12k-control-thermal-support-via-symbol.patch b/package/kernel/mac80211/patches/ath12k/300-ath12k-control-thermal-support-via-symbol.patch new file mode 100644 index 0000000000..8d7e2d8cc5 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/300-ath12k-control-thermal-support-via-symbol.patch @@ -0,0 +1,62 @@ +From b6a3bb1561e98980b24f08bffe91327b29091c82 Mon Sep 17 00:00:00 2001 +From: Matt Merhar +Date: Wed, 4 Mar 2026 22:07:15 -0500 +Subject: [PATCH] ath12k: control thermal support via symbol + +As is already done for ath10k and ath11k, add a new ATH12K_THERMAL +symbol to decouple the enablement of thermal support from +CONFIG_THERMAL. + +Signed-off-by: Matt Merhar +--- + drivers/net/wireless/ath/ath12k/Kconfig | 7 +++++++ + drivers/net/wireless/ath/ath12k/Makefile | 2 +- + drivers/net/wireless/ath/ath12k/thermal.h | 2 +- + local-symbols | 1 + + 4 files changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/Kconfig ++++ b/drivers/net/wireless/ath/ath12k/Kconfig +@@ -61,3 +61,10 @@ config ATH12K_COREDUMP + + If unsure, say Y to make it easier to debug problems. But if + dump collection not required choose N. ++ ++config ATH12K_THERMAL ++ bool "ath12k thermal sensor support" ++ depends on ATH12K ++ depends on THERMAL ++ help ++ Enable ath12k thermal sensor support. +--- a/drivers/net/wireless/ath/ath12k/Makefile ++++ b/drivers/net/wireless/ath/ath12k/Makefile +@@ -30,7 +30,7 @@ ath12k-$(CPTCFG_ATH12K_TRACING) += trace + ath12k-$(CONFIG_PM) += wow.o + ath12k-$(CPTCFG_ATH12K_COREDUMP) += coredump.o + ath12k-$(CPTCFG_NL80211_TESTMODE) += testmode.o +-ath12k-$(CONFIG_THERMAL) += thermal.o ++ath12k-$(CPTCFG_ATH12K_THERMAL) += thermal.o + + # for tracing framework to find trace.h + CFLAGS_trace.o := -I$(src) +--- a/drivers/net/wireless/ath/ath12k/thermal.h ++++ b/drivers/net/wireless/ath/ath12k/thermal.h +@@ -17,7 +17,7 @@ struct ath12k_thermal { + struct device *hwmon_dev; + }; + +-#if IS_REACHABLE(CONFIG_THERMAL) ++#if IS_REACHABLE(CPTCFG_ATH12K_THERMAL) + int ath12k_thermal_register(struct ath12k_base *ab); + void ath12k_thermal_unregister(struct ath12k_base *ab); + void ath12k_thermal_event_temperature(struct ath12k *ar, int temperature); +--- a/local-symbols ++++ b/local-symbols +@@ -170,6 +170,7 @@ ATH12K_DEBUG= + ATH12K_DEBUGFS= + ATH12K_TRACING= + ATH12K_COREDUMP= ++ATH12K_THERMAL= + WLAN_VENDOR_ATMEL= + AT76C50X_USB= + WLAN_VENDOR_BROADCOM= diff --git a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch b/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch index 3dfeedfede..ac9e2060bb 100644 --- a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch +++ b/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch @@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi --- a/local-symbols +++ b/local-symbols -@@ -336,6 +336,7 @@ RT2X00_LIB_FIRMWARE= +@@ -337,6 +337,7 @@ RT2X00_LIB_FIRMWARE= RT2X00_LIB_CRYPTO= RT2X00_LIB_LEDS= RT2X00_LIB_DEBUGFS= From 63e0c890385154fd910d8935b0147e2be8e43765 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 14 Dec 2025 15:44:01 -0800 Subject: [PATCH 16/88] treewide: constify mdio_bus In generic, there's a backport from 6.14 that makes this change. Do so in downstream locations as well. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/21167 Signed-off-by: Robert Marko --- target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c | 2 +- target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c | 2 +- target/linux/mediatek/files/drivers/net/phy/en8801sc.c | 2 +- ...1-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch | 2 +- .../files-6.12/drivers/net/phy/realtek/realtek_multiport.c | 2 +- target/linux/siflower/files-6.12/drivers/net/phy/siflower.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c index a1eb2c1614..8c142afee6 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c @@ -310,7 +310,7 @@ static struct phy_driver rtk_phy_drivers[] = { module_phy_driver(rtk_phy_drivers); -static struct mdio_device_id __maybe_unused rtk_phy_tbl[] = { +static const struct mdio_device_id __maybe_unused rtk_phy_tbl[] = { { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N) }, { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B) }, { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264) }, diff --git a/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c b/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c index 7fab0854ef..cf10b7a9a8 100644 --- a/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c +++ b/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c @@ -255,7 +255,7 @@ static struct phy_driver an8855_driver[] = { module_phy_driver(an8855_driver); -static struct mdio_device_id __maybe_unused an8855_tbl[] = { +static const struct mdio_device_id __maybe_unused an8855_tbl[] = { { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) }, { } }; diff --git a/target/linux/mediatek/files/drivers/net/phy/en8801sc.c b/target/linux/mediatek/files/drivers/net/phy/en8801sc.c index 08774e3b88..301b76c9a6 100644 --- a/target/linux/mediatek/files/drivers/net/phy/en8801sc.c +++ b/target/linux/mediatek/files/drivers/net/phy/en8801sc.c @@ -1109,7 +1109,7 @@ static struct phy_driver Airoha_driver[] = { module_phy_driver(Airoha_driver); -static struct mdio_device_id __maybe_unused Airoha_tbl[] = { +static const struct mdio_device_id __maybe_unused Airoha_tbl[] = { { EN8801SC_PHY_ID, 0x0ffffff0 }, { } }; diff --git a/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch b/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch index 1c61aaf4ae..ff7aa40f53 100644 --- a/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch +++ b/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch @@ -386,7 +386,7 @@ Signed-off-by: Sky Huang + +module_phy_driver(mtk_2p5gephy_driver); + -+static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { ++static const struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x00339c00) }, + { } +}; diff --git a/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c b/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c index 6704f31a2b..3074e57858 100644 --- a/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c +++ b/target/linux/realtek/files-6.12/drivers/net/phy/realtek/realtek_multiport.c @@ -695,7 +695,7 @@ static struct phy_driver rtl83xx_phy_driver[] = { module_phy_driver(rtl83xx_phy_driver); -static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = { +static const struct mdio_device_id __maybe_unused rtl83xx_tbl[] = { { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214_OR_8218) }, { } }; diff --git a/target/linux/siflower/files-6.12/drivers/net/phy/siflower.c b/target/linux/siflower/files-6.12/drivers/net/phy/siflower.c index 22acb5b67e..9a82e2178c 100644 --- a/target/linux/siflower/files-6.12/drivers/net/phy/siflower.c +++ b/target/linux/siflower/files-6.12/drivers/net/phy/siflower.c @@ -865,7 +865,7 @@ static struct phy_driver sf_phy_drivers[] = { /* for linux 4.x */ module_phy_driver(sf_phy_drivers); -static struct mdio_device_id __maybe_unused siflower_phy_tbl[] = { +static const struct mdio_device_id __maybe_unused siflower_phy_tbl[] = { { SF1211F_PHY_ID, SIFLOWER_PHY_ID_MASK }, { SF1240_PHY_ID, SIFLOWER_PHY_ID_MASK }, {}, From 08d2c0514f0e75b8ef3d9f7fe2ef796ed95c4643 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 8 Feb 2026 14:12:02 -0800 Subject: [PATCH 17/88] trelay: use struct_size helper in allocation Makes it clear that the allocation is dealing with a flex array member. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/21960 Signed-off-by: Robert Marko --- package/kernel/trelay/src/trelay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/trelay/src/trelay.c b/package/kernel/trelay/src/trelay.c index 8b3bef2a8e..32ac623afe 100644 --- a/package/kernel/trelay/src/trelay.c +++ b/package/kernel/trelay/src/trelay.c @@ -152,7 +152,7 @@ static int trelay_do_add(char *name, char *devn1, char *devn2) struct trelay *tr, *tr1; int ret; - tr = kzalloc(sizeof(*tr) + strlen(name) + 1, GFP_KERNEL); + tr = kzalloc(struct_size(tr, name, strlen(name) + 1), GFP_KERNEL); if (!tr) return -ENOMEM; From 3f6d2868ff2390b1290dea1cb6ea0b4f97585f46 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 19 Feb 2026 16:57:29 -0800 Subject: [PATCH 18/88] kernel: netdevices: add KSZ9477 DSA switch support This adds kernel packages for the Microchip KSZ9477 switch family. The core package has a target specific dependency as the ksz9477 driver enables DCB which grows the kernel size and can negatively impact other targets. Signed-off-by: Tim Harvey Link: https://github.com/openwrt/openwrt/pull/22257 Signed-off-by: Robert Marko --- package/kernel/linux/modules/netdevices.mk | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index 4c57b878f5..3dc28952d5 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -705,6 +705,64 @@ endef $(eval $(call KernelPackage,dsa-b53-mdio)) + +define KernelPackage/dsa-ksz9477 + SUBMENU:=$(NETWORK_DEVICES_MENU) + TITLE:=Microchip KSZ9477 family managed switch DSA support + DEPENDS:=@TARGET_imx_cortexa53 +kmod-dsa +kmod-dsa-notag +kmod-phy-micrel +kmod-regmap-core + KCONFIG:= \ + CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON \ + CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=n \ + CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=n \ + CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=n \ + CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=n \ + CONFIG_NET_DSA_TAG_KSZ=y + FILES:= \ + $(LINUX_DIR)/drivers/net/dsa/microchip/ksz_switch.ko \ + $(LINUX_DIR)/net/dsa/tag_ksz.ko + AUTOLOAD:=$(call AutoProbe,ksz_switch) +endef + +define KernelPackage/dsa-ksz9477/description + Microchip KSZ9477 family managed switch support. Note that this should be target + specific as the driver enables DCB which grows the static kernel code. +endef + +$(eval $(call KernelPackage,dsa-ksz9477)) + + +define KernelPackage/dsa-ksz9477-i2c + SUBMENU:=$(NETWORK_DEVICES_MENU) + TITLE:=Microchip KSZ9477 family managed switch DSA support via I2C + DEPENDS:=+kmod-dsa-ksz9477 +kmod-regmap-i2c + KCONFIG:=CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C + FILES:= $(LINUX_DIR)/drivers/net/dsa/microchip/ksz9477_i2c.ko + AUTOLOAD:=$(call AutoProbe,ksz9477_i2c) +endef + +define KernelPackage/dsa-ksz9477-i2c/description + Microchip KSZ9477 family managed switch support via I2C +endef + +$(eval $(call KernelPackage,dsa-ksz9477-i2c)) + + +define KernelPackage/dsa-ksz9477-spi + SUBMENU:=$(NETWORK_DEVICES_MENU) + TITLE:=Microchip KSZ9477 family managed switch DSA support via SPI + DEPENDS:=+kmod-dsa-ksz9477 +kmod-regmap-spi + KCONFIG:=CONFIG_NET_DSA_MICROCHIP_KSZ_SPI + FILES:= $(LINUX_DIR)/drivers/net/dsa/microchip/ksz_spi.ko + AUTOLOAD:=$(call AutoProbe,ksz_spi) +endef + +define KernelPackage/dsa-ksz9477-spi/description + Microchip KSZ9477 family managed switch support via SPI +endef + +$(eval $(call KernelPackage,dsa-ksz9477-spi)) + + define KernelPackage/dsa-mv88e6060 SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Marvell MV88E6060 DSA Switch From 626c67caca0c5ebd8d89a2c21c45ade7ce4d2f80 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 19 Feb 2026 17:01:48 -0800 Subject: [PATCH 19/88] imx: cortexa53: remove KSZ9477 static driver The KSZ9477 driver was added to the cortexa53 kernel to support the Gateworks Venice product family which has a board with this switch. Now that the kmod-dsa-ksz9477 driver is available as a package remove the static configuration ad add the package. This resolves an issue caused by having the switch driver static and the PHY driver as a module such that the PHY driver was not registered early enough to be used causing some errata to not be worked around. Signed-off-by: Tim Harvey Link: https://github.com/openwrt/openwrt/pull/22120 Link: https://github.com/openwrt/openwrt/pull/22257 Signed-off-by: Robert Marko --- target/linux/imx/cortexa53/config-default | 5 ----- target/linux/imx/image/cortexa53.mk | 3 ++- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/linux/imx/cortexa53/config-default b/target/linux/imx/cortexa53/config-default index 95757ef9e9..3a946c7647 100644 --- a/target/linux/imx/cortexa53/config-default +++ b/target/linux/imx/cortexa53/config-default @@ -108,11 +108,6 @@ CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MODULES_USE_ELF_RELA=y CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI is not set -CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=y -CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y -# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set -CONFIG_NET_DSA_TAG_KSZ=y CONFIG_NOP_USB_XCEIV=y CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y diff --git a/target/linux/imx/image/cortexa53.mk b/target/linux/imx/image/cortexa53.mk index 378bf67a62..2a33d328e6 100644 --- a/target/linux/imx/image/cortexa53.mk +++ b/target/linux/imx/image/cortexa53.mk @@ -74,7 +74,8 @@ define Device/gateworks_venice kmod-hwmon-gsc kmod-rtc-ds1672 kmod-eeprom-at24 \ kmod-gpio-button-hotplug kmod-leds-gpio kmod-pps-gpio \ kmod-lan743x kmod-sky2 kmod-iio-st_accel-i2c \ - kmod-can kmod-can-flexcan kmod-can-mcp251x + kmod-can kmod-can-flexcan kmod-can-mcp251x \ + kmod-dsa-ksz9477-i2c IMAGES := img.gz IMAGE/img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata endef From 5ba55feb108d07ad1287b9cead155dfa35890ca3 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 13 Mar 2026 23:15:18 +0000 Subject: [PATCH 20/88] procd: update to git HEAD 58eb263 instance: don't print error in case cgroups are disabled 9baf019 instance: use positive error numbers for strerror() Signed-off-by: Daniel Golle --- package/system/procd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index c6142ebd40..139503147f 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git -PKG_MIRROR_HASH:=523ab499a2b09270db5498e543b7661fd8db98371c8baaf6bcd6082cd73377c4 -PKG_SOURCE_DATE:=2026-03-11 -PKG_SOURCE_VERSION:=129b729f757ce625cf39601d24d97f4d92db7a7e +PKG_MIRROR_HASH:=8bd86938479609045e1ceebed904e4f5cb96fdb38220d41c3579b7e764fbb05b +PKG_SOURCE_DATE:=2026-03-13 +PKG_SOURCE_VERSION:=58eb263d5abe03f8c1280bdfa65a3b052614215d CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 From 8ef564bcda6dcd1052ea2065601b9d7be3a49fee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Van=C4=9Bk?= Date: Mon, 2 Mar 2026 20:36:29 +0100 Subject: [PATCH 21/88] kernel: add patch for YT8821 address collision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This minimalistic patch should ensure that the Cudy M3000 with the Motorcomm PHY works reliably. The patch is not upstreamable into the mainline kernel. However, it could be sufficient as a simple stop-gap measure until some other solution is found. Link: https://forum.openwrt.org/t/cudy-m3000-with-motorcomm-phy-how-to-fix-it/247083?u=linuxtardis Signed-off-by: Jakub Vaněk Link: https://github.com/openwrt/openwrt/pull/22259 Signed-off-by: Hauke Mehrtens --- ...comm-yt8821-bus-collision-workaround.patch | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 target/linux/generic/hack-6.12/755-net-phy-motorcomm-yt8821-bus-collision-workaround.patch diff --git a/target/linux/generic/hack-6.12/755-net-phy-motorcomm-yt8821-bus-collision-workaround.patch b/target/linux/generic/hack-6.12/755-net-phy-motorcomm-yt8821-bus-collision-workaround.patch new file mode 100644 index 0000000000..28c4c702b3 --- /dev/null +++ b/target/linux/generic/hack-6.12/755-net-phy-motorcomm-yt8821-bus-collision-workaround.patch @@ -0,0 +1,85 @@ +From 63161fb6353493c648a260244f6ac7eca65fd48e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jakub=20Van=C4=9Bk?= +Date: Mon, 2 Mar 2026 20:31:37 +0100 +Subject: [PATCH] net: phy: Work around MDIO collisions in the YT8821 driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Cudy M3000 router suffers from a MDIO bus collision: +- The MT7981B internal gigabit PHY listens on address 0. +- The Motorcomm YT8821 is strapped to listen on address 1, + but it initially also listens on address 0 (Motorcomm + incorrectly considers that address a broadcast address). + +Without this patch, the YT8821 reacts to MDIO commands intended +for the internal gigabit PHY and that makes it work unreliably. +The YT8821 state somehow gets corrupted by the commands for the MT7981 +(e.g. we get 100Mbps speeds on gigabit links). + +This dirty workaround resets the PHY to cancel out any earlier +YT8821 register corruption and then it disables the address 0 +as soon as possible. This should make the YT8821 work reliably. + +BEWARE though: the PHY will be reset only if the device tree +node that defines the PHY carries the reset-gpios attribute. +The PHY will not be reset if the reset GPIO is either on the MDIO +bus node or is not defined at all. This might not always be a problem -- +some routers do not require the PHY to be reset (e.g. Cudy WR3000H, +where there likely is less communication with the MT7981B PHY, +and so the YT8821 PHY works reasonably well there even without this patch). + +This patch also does not address the possible MDIO bus collisions +when the MT7981B PHY driver initially configures that PHY and invokes +some read transactions on the bus. I am hoping that the MT7981B MDIO +bus controller gives priority to the internal PHY and so it would +not be affected by these collisions. However, I don't have anything +to base this on apart from it "seeming to be working okay". + +This patch is unlikely to be mergeable into the mainline kernel. +Upstream has strongly indicated that they would prefer this problem +to be resolved by the platform bootloader (e.g. U-Boot), see +- https://lore.kernel.org/all/d3bb9c36-5a0e-4339-901d-2dd21bdba395@gmail.com/ +- https://lore.kernel.org/all/20260228232241.1274236-1-linuxtardis@gmail.com/ + +Signed-off-by: Jakub Vaněk +--- + drivers/net/phy/motorcomm.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -214,6 +214,9 @@ + #define YT8521_RC1R_RGMII_2_100_NS 14 + #define YT8521_RC1R_RGMII_2_250_NS 15 + ++#define YTPHY_MDIO_ADDRESS_CONTROL_REG 0xA005 ++#define YTPHY_MACR_EN_PHY_ADDR_0 BIT(6) ++ + #define YTPHY_MISC_CONFIG_REG 0xA006 + #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) + #define YTPHY_MCR_FIBER_1000BX (0x1 << 0) +@@ -2659,6 +2662,23 @@ static int yt8821_config_init(struct phy + int ret; + u16 set; + ++ /* Hard-reset the PHY to clear out any register corruption ++ * from preceding MDIO bus conflicts. ++ */ ++ phy_device_reset(phydev, 1); ++ ++ /* Deassert the reset GPIO under the MDIO bus lock to make ++ * sure that nothing will communicate on the bus until we ++ * disable the broadcast address in the YT8821. ++ */ ++ phy_lock_mdio_bus(phydev); ++ phy_device_reset(phydev, 0); ++ ret = ytphy_modify_ext(phydev, ++ YTPHY_MDIO_ADDRESS_CONTROL_REG, ++ YTPHY_MACR_EN_PHY_ADDR_0, ++ 0); ++ phy_unlock_mdio_bus(phydev); ++ + if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) + mode = YT8821_CHIP_MODE_FORCE_BX2500; + From 45b51ebaff51d2a49d149e9011717abb1b032683 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Van=C4=9Bk?= Date: Mon, 2 Mar 2026 21:14:28 +0100 Subject: [PATCH 22/88] mediatek: filogic: add support for Cudy M3000 w/ YT8821 PHY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware is very close the the Cudy M3000 v1 (see commit 20e4a18feb3f). However, the Motorcomm YT8821 PHY is tricky to support because of a MDIO address collision within the router. Specification: - MT7981BA CPU: dual-core ARM Cortex-A53 @ 1.3 GHz - 256 MiB RAM - 128 MiB SPI NAND - Ethernet: - 1x 1GbE LAN port driven by the internal MT7981 PHY - 1x 2.5GbE WAN port driven by the Motorcomm YT8821 - WiFi: - MT7981BA 2.4 GHz WiFi with 2x2:2 MIMO - MT7981BA 5 GHz WiFi with 2x3:2 MIMO - Buttons: Reset, WPS - LED: 1x combined red/white How to know if you have the a router with the YT8821 PHY: - Boot the router into the vendor's firmware. Go to Diagnostic Tools -> System Log. Try searching for "rtl8221b". - If there are some matches, you have the Cudy M3000 router with the Realtek PHY and you should NOT use the device defined in this commit. Instead, you should use the device defined in mt7981b-cudy-m3000-v1.dts. - If there are no matches, try searching for "yt8821". If that matches something, you have the Cudy M3000 with the Motorcomm PHY and you should use this device tree (mt7981b-cudy-m3000-v2-yt8821.dts). - If even the yt8821 string did not match anything, then something is wrong. Rebooting the router might help (the system log would be refreshed). Installation via the Cudy web UI: - Download the signed intermediary firmware from https://drive.google.com/drive/folders/1BKVarlwlNxf7uJUtRhuMGUqeCa5KpMnj - Flash the intermediary firmware using the Cudy web UI - Connect a PC/laptop to the "1Gbps LAN" port - Open http://192.168.1.1 in your browser, log in (the password should be empty) - Flash your desired OpenWrt firmware via LuCI - The router should reboot into the desired firmware How to access UART (citing from 20e4a18feb3f): - remove rubber ring on the bottom - remove screws - pull up the cylinder, maybe help by push on an ethernet socket with a screwdriver - remove the (3) screws holding the board in the frame - remove the board from the frame to get to the screws for the silver, flat heat shield - remove the (3) screws holding the heat shield - solder UART pins to the back of the board - make sure to have the pins point out on side with the black, finned heat spread - the markings for the pins are going to be below the silver heat shield - Vcc is not needed - the UART parameters are 115200 baud, 8n1 Installation via UART (citing from 20e4a18feb3f): - attach an Ethernet cable to the "1Gbps LAN" port on the router - hold the reset button while powering the router - press CTRL-C or wait for the timeout to get to the U-Boot prompt - prepare a TFTP server on the network to supply ..-initramfs-kernel.bin - use 'tftpboot 0x46000000 ..-initramfs-kernel.bin' in the U-Boot shell to pull the image (change the file name accordingly) - boot the image using 'bootm 0x46000000' - push the ..-sysupgrade to the router using your preferred method - perform the upgrade with 'sysupgrade -n' Signed-off-by: Jakub Vaněk Link: https://github.com/openwrt/openwrt/pull/22259 Signed-off-by: Hauke Mehrtens --- .../lib/preinit/05_set_preinit_iface | 1 + .../mediatek/dts/mt7981b-cudy-m3000-v1.dts | 192 +---------------- .../dts/mt7981b-cudy-m3000-v2-yt8821.dts | 22 ++ .../mediatek/dts/mt7981b-cudy-m3000.dtsi | 195 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 1 + target/linux/mediatek/image/filogic.mk | 22 ++ 7 files changed, 244 insertions(+), 190 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7981b-cudy-m3000-v2-yt8821.dts create mode 100644 target/linux/mediatek/dts/mt7981b-cudy-m3000.dtsi diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface index 174baa407d..40b9a926c2 100644 --- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface +++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface @@ -2,6 +2,7 @@ set_preinit_iface() { case $(board_name) in bazis,ax3000wm|\ cudy,m3000-v1|\ + cudy,m3000-v2-yt8821|\ cudy,tr3000-256mb-v1|\ cudy,tr3000-v1|\ cudy,tr3000-v1-ubootmod|\ diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts index 5cbd683418..05e7d57045 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -2,106 +2,15 @@ /dts-v1/; -#include "mt7981b.dtsi" +#include "mt7981b-cudy-m3000.dtsi" / { model = "Cudy M3000 v1"; compatible = "cudy,m3000-v1", "mediatek,mt7981"; - - aliases { - label-mac-device = &gmac0; - led-boot = &led_status; - led-failsafe = &led_status; - led-running = &led_status; - led-upgrade = &led_status; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_status: internet-white { - function = LED_FUNCTION_WAN_ONLINE; - color = ; - gpios = <&pio 10 GPIO_ACTIVE_LOW>; - }; - - internet-red { - function = LED_FUNCTION_WAN_ONLINE; - color = ; - gpios = <&pio 4 GPIO_ACTIVE_LOW>; - }; - - wan { - function = LED_FUNCTION_WAN; - color = ; - gpios = <&pio 5 GPIO_ACTIVE_LOW>; - }; - - lan { - function = LED_FUNCTION_LAN; - color = ; - gpios = <&pio 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - phy-handle = <&rtl8221b_phy>; - - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_bdinfo_de00 0>; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&int_gbe_phy>; - - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_bdinfo_de00 1>; - }; }; &mdio_bus { - rtl8221b_phy: ethernet-phy@1 { + wan_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <1>; reset-assert-us = <100000>; @@ -111,100 +20,3 @@ interrupt-parent = <&pio>; }; }; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x0000000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x0180000 0x0200000>; - read-only; - }; - - bdinfo: partition@380000 { - label = "bdinfo"; - reg = <0x0380000 0x0040000>; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_bdinfo_de00: macaddr@de00 { - #nvmem-cell-cells = <1>; - compatible = "mac-base"; - reg = <0xde00 0x6>; - }; - }; - }; - - partition@3c0000 { - label = "FIP"; - reg = <0x03c0000 0x0200000>; - read-only; - }; - - partition@5c0000 { - label = "ubi"; - reg = <0x05c0000 0x4000000>; - }; - }; - }; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = ; - bias-pull-up = ; - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = ; - bias-pull-down = ; - }; - }; -}; - -&wifi { - status = "okay"; - mediatek,mtd-eeprom = <&factory 0x0>; -}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v2-yt8821.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v2-yt8821.dts new file mode 100644 index 0000000000..0922b318e1 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v2-yt8821.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981b-cudy-m3000.dtsi" + +/ { + model = "Cudy M3000 v2 with Motorcomm YT8821"; + compatible = "cudy,m3000-v2-yt8821", "mediatek,mt7981"; +}; + +&mdio_bus { + wan_phy: ethernet-phy@1 { + compatible = "ethernet-phy-id4f51.ea19"; + reg = <1>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&pio>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000.dtsi b/target/linux/mediatek/dts/mt7981b-cudy-m3000.dtsi new file mode 100644 index 0000000000..c6fa571e86 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + aliases { + label-mac-device = &gmac0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: internet-white { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + internet-red { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&wan_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 1>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x0180000 0x0200000>; + read-only; + }; + + bdinfo: partition@380000 { + label = "bdinfo"; + reg = <0x0380000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + #nvmem-cell-cells = <1>; + compatible = "mac-base"; + reg = <0xde00 0x6>; + }; + }; + }; + + partition@3c0000 { + label = "FIP"; + reg = <0x03c0000 0x0200000>; + read-only; + }; + + partition@5c0000 { + label = "ubi"; + reg = <0x05c0000 0x4000000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&wifi { + status = "okay"; + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 848492a75e..dca52e4c20 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -130,6 +130,7 @@ mediatek_setup_interfaces() ;; bazis,ax3000wm|\ cudy,m3000-v1|\ + cudy,m3000-v2-yt8821|\ cudy,tr3000-256mb-v1|\ cudy,tr3000-v1|\ cudy,tr3000-v1-ubootmod|\ diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 5950a590a8..7d5811e6e0 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -92,6 +92,7 @@ case "$board" in cudy,ap3000wall-v1|\ cudy,ap3000-v1|\ cudy,m3000-v1|\ + cudy,m3000-v2-yt8821|\ cudy,re3000-v1|\ cudy,tr3000-256mb-v1|\ cudy,tr3000-v1|\ diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index e37f536594..3d2eee88a5 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -1147,6 +1147,28 @@ define Device/cudy_m3000-v1 endef TARGET_DEVICES += cudy_m3000-v1 +define Device/cudy_m3000-v2-yt8821 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := M3000 + DEVICE_VARIANT := v2 with Motorcomm YT8821 + DEVICE_DTS := mt7981b-cudy-m3000-v2-yt8821 + DEVICE_DTS_DIR := ../dts + SUPPORTED_DEVICES += R37 + DEVICE_DTS_LOADADDR := 0x44000000 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-phy-motorcomm +endef +TARGET_DEVICES += cudy_m3000-v2-yt8821 + define Device/cudy_re3000-v1 DEVICE_VENDOR := Cudy DEVICE_MODEL := RE3000 From 51abd131d1acaaf7f7eb487376309ce52b814f81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Van=C4=9Bk?= Date: Tue, 3 Mar 2026 22:41:28 +0100 Subject: [PATCH 23/88] mediatek: filogic: rename Cudy M3000 v1 to v1/v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Cudy M3000 v1/v2 seem to have mostly identical hardware. The M3000 v1 OpenWrt images work on the M3000 v2 (excluding the v2 parts with a different PHY). Cudy also distributes one firmware image that supports both routers. Rename the human-readable device variant to "v1/v2" to match this. Don't change the compatible property as that hooks into the attended sysupgrade process. The recent flash and PHY changes don't seem to be related to the v1/v2 split. There exist M3000 v2 with the Realtek PHY, see e.g. https://github.com/openwrt/openwrt/pull/21584#issuecomment-3864992555 Signed-off-by: Jakub Vaněk Link: https://github.com/openwrt/openwrt/pull/22259 Signed-off-by: Hauke Mehrtens --- target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts | 2 +- target/linux/mediatek/image/filogic.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts index 05e7d57045..885437e49a 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -5,7 +5,7 @@ #include "mt7981b-cudy-m3000.dtsi" / { - model = "Cudy M3000 v1"; + model = "Cudy M3000 v1/v2"; compatible = "cudy,m3000-v1", "mediatek,mt7981"; }; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 3d2eee88a5..29c8c3d657 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -1128,7 +1128,7 @@ TARGET_DEVICES += cudy_ap3000-v1 define Device/cudy_m3000-v1 DEVICE_VENDOR := Cudy DEVICE_MODEL := M3000 - DEVICE_VARIANT := v1 + DEVICE_VARIANT := v1/v2 DEVICE_DTS := mt7981b-cudy-m3000-v1 DEVICE_DTS_DIR := ../dts SUPPORTED_DEVICES += R37 From 087204922612f164b462098e4b7d4399cfea6c80 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Fri, 6 Mar 2026 13:59:06 +0100 Subject: [PATCH 24/88] realtek: enable U-Boot env NVMEM layout for missing targets Allow to convert MAC adddresses for all devices to NVMEM in the future. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22302 Signed-off-by: Robert Marko --- target/linux/realtek/rtl839x/config-6.12 | 1 + target/linux/realtek/rtl930x_nand/config-6.12 | 1 + target/linux/realtek/rtl931x_nand/config-6.12 | 1 + 3 files changed, 3 insertions(+) diff --git a/target/linux/realtek/rtl839x/config-6.12 b/target/linux/realtek/rtl839x/config-6.12 index 300d5a6a9a..c515afbf8a 100644 --- a/target/linux/realtek/rtl839x/config-6.12 +++ b/target/linux/realtek/rtl839x/config-6.12 @@ -191,6 +191,7 @@ CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y diff --git a/target/linux/realtek/rtl930x_nand/config-6.12 b/target/linux/realtek/rtl930x_nand/config-6.12 index 5fa736be1f..473fa91b30 100644 --- a/target/linux/realtek/rtl930x_nand/config-6.12 +++ b/target/linux/realtek/rtl930x_nand/config-6.12 @@ -179,6 +179,7 @@ CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y diff --git a/target/linux/realtek/rtl931x_nand/config-6.12 b/target/linux/realtek/rtl931x_nand/config-6.12 index 19797397b4..1642286ca7 100644 --- a/target/linux/realtek/rtl931x_nand/config-6.12 +++ b/target/linux/realtek/rtl931x_nand/config-6.12 @@ -190,6 +190,7 @@ CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NR_CPUS=4 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y From 59f1fe1205563b4eafbc78a12f8b402b496cc2ce Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Fri, 6 Mar 2026 13:30:39 +0100 Subject: [PATCH 25/88] realtek: dts: convert LGS3xxC to NVMEM These devices contain a single MAC address in the U-Boot environment. Set it as eth0 and label MAC in device tree. To maintain the current state, the 02_network script still sets individual port MAC addresses and the bridge MAC address. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22302 Signed-off-by: Robert Marko --- .../realtek/base-files/etc/board.d/02_network | 6 +++--- .../linux/realtek/dts/rtl8380_linksys_lgs310c.dts | 15 +++++++++++++++ .../dts/rtl93xx_linksys_lgs3xxc_nand_common.dtsi | 14 ++++++++++++++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network index 7fccc77f58..21c949380f 100644 --- a/target/linux/realtek/base-files/etc/board.d/02_network +++ b/target/linux/realtek/base-files/etc/board.d/02_network @@ -53,6 +53,9 @@ realtek_setup_macs() case $board in edgecore,ecs4100-12ph|\ + linksys,lgs310c|\ + linksys,lgs328c|\ + linksys,lgs352c|\ netgear,gs108t-v3|\ netgear,gs110tpp-v1|\ netgear,gs110tup-v1|\ @@ -117,9 +120,6 @@ realtek_setup_macs() hasivo,s1100w-8xgt-se|\ inaba,aml2-17gp|\ iodata,bsh-g24mb|\ - linksys,lgs310c|\ - linksys,lgs328c|\ - linksys,lgs352c|\ netgear,gs750e|\ panasonic,m16eg-pn28160k|\ panasonic,m24eg-pn28240k|\ diff --git a/target/linux/realtek/dts/rtl8380_linksys_lgs310c.dts b/target/linux/realtek/dts/rtl8380_linksys_lgs310c.dts index f0980b9af4..4ce6e97b95 100644 --- a/target/linux/realtek/dts/rtl8380_linksys_lgs310c.dts +++ b/target/linux/realtek/dts/rtl8380_linksys_lgs310c.dts @@ -11,6 +11,7 @@ model = "Linksys LGS310C"; aliases { + label-mac-device = ðernet0; led-boot = &led_power; led-failsafe = &led_fault; led-running = &led_power; @@ -84,6 +85,12 @@ }; }; + +ðernet0 { + nvmem-cells = <&macaddr_ubootenv_ethaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &mdio_aux { status = "okay"; @@ -122,6 +129,14 @@ partition@80000 { label = "u-boot-env"; reg = <0x00080000 0x10000>; + + nvmem-layout { + compatible = "u-boot,env"; + + macaddr_ubootenv_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + }; }; partition@90000 { label = "u-boot-env2"; diff --git a/target/linux/realtek/dts/rtl93xx_linksys_lgs3xxc_nand_common.dtsi b/target/linux/realtek/dts/rtl93xx_linksys_lgs3xxc_nand_common.dtsi index 8fd5615c99..e452d87061 100644 --- a/target/linux/realtek/dts/rtl93xx_linksys_lgs3xxc_nand_common.dtsi +++ b/target/linux/realtek/dts/rtl93xx_linksys_lgs3xxc_nand_common.dtsi @@ -6,6 +6,7 @@ / { aliases { + label-mac-device = ðernet0; led-boot = &led_power; led-failsafe = &led_fault; led-running = &led_power; @@ -89,6 +90,11 @@ status = "okay"; }; +ðernet0 { + nvmem-cells = <&macaddr_ubootenv_ethaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi0 { status = "okay"; flash@0 { @@ -109,6 +115,14 @@ partition@e0000 { label = "u-boot-env"; reg = <0xe0000 0x10000>; + + nvmem-layout { + compatible = "u-boot,env"; + + macaddr_ubootenv_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + }; }; partition@f0000 { label = "u-boot-env2"; From 0d04e03385f3b37d5a3a1f5b8a33d988b034ebfa Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 9 Mar 2026 19:21:54 +0100 Subject: [PATCH 26/88] realtek: eth: drop pcs handling The ethernet driver configures the SoC internal network card on its own. There are no special serdes or other layers in between. So there is no need for pcs handling in the driver. Drop that. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22347 Signed-off-by: Robert Marko --- .../drivers/net/ethernet/rtl838x_eth.c | 106 ------------ .../drivers/net/ethernet/rtl838x_eth.h | 160 ------------------ 2 files changed, 266 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c index 32d45dd95b..fcd7fccfff 100644 --- a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c @@ -150,7 +150,6 @@ struct rteth_ctrl { struct rtl838x_rx_q rx_qs[RTETH_RX_RINGS]; struct phylink *phylink; struct phylink_config phylink_config; - struct phylink_pcs pcs; const struct rteth_config *r; u32 lastEvent; /* receive handling */ @@ -1078,74 +1077,6 @@ static void rteth_mac_config(struct phylink_config *config, pr_info("In %s, mode %x\n", __func__, mode); } -static void rteth_pcs_an_restart(struct phylink_pcs *pcs) -{ - struct rteth_ctrl *ctrl = container_of(pcs, struct rteth_ctrl, pcs); - - /* This works only on RTL838x chips */ - if (ctrl->r->family_id != RTL8380_FAMILY_ID) - return; - - pr_debug("In %s\n", __func__); - /* Restart by disabling and re-enabling link */ - sw_w32(0x6192D, ctrl->r->mac_force_mode_ctrl); - mdelay(20); - sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl); -} - -static void rteth_pcs_get_state(struct phylink_pcs *pcs, - struct phylink_link_state *state) -{ - u32 speed; - struct rteth_ctrl *ctrl = container_of(pcs, struct rteth_ctrl, pcs); - int port = ctrl->r->cpu_port; - - pr_info("In %s\n", __func__); - - state->link = ctrl->r->get_mac_link_sts(port) ? 1 : 0; - state->duplex = ctrl->r->get_mac_link_dup_sts(port) ? 1 : 0; - - pr_info("%s link status is %d\n", __func__, state->link); - speed = ctrl->r->get_mac_link_spd_sts(port); - switch (speed) { - case 0: - state->speed = SPEED_10; - break; - case 1: - state->speed = SPEED_100; - break; - case 2: - state->speed = SPEED_1000; - break; - case 5: - state->speed = SPEED_2500; - break; - case 6: - state->speed = SPEED_5000; - break; - case 4: - state->speed = SPEED_10000; - break; - default: - state->speed = SPEED_UNKNOWN; - break; - } - - state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); - if (ctrl->r->get_mac_rx_pause_sts(port)) - state->pause |= MLO_PAUSE_RX; - if (ctrl->r->get_mac_tx_pause_sts(port)) - state->pause |= MLO_PAUSE_TX; -} - -static int rteth_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, - phy_interface_t interface, - const unsigned long *advertising, - bool permit_pause_to_mac) -{ - return 0; -} - static void rteth_mac_link_down(struct phylink_config *config, unsigned int mode, phy_interface_t interface) @@ -1318,15 +1249,6 @@ static int rteth_93xx_set_features(struct net_device *dev, netdev_features_t fea return 0; } -static struct phylink_pcs *rteth_mac_select_pcs(struct phylink_config *config, - phy_interface_t interface) -{ - struct net_device *dev = to_net_dev(config->dev); - struct rteth_ctrl *ctrl = netdev_priv(dev); - - return &ctrl->pcs; -} - static int rteth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data) { struct dsa_switch *ds; @@ -1376,11 +1298,6 @@ static const struct rteth_config rteth_838x_cfg = { .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size, .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr, .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, - .get_mac_link_sts = rtl838x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts, .mac_reg = { RTETH_838X_MAC_ADDR_CTRL, RTETH_838X_MAC_ADDR_CTRL_ALE, RTETH_838X_MAC_ADDR_CTRL_MAC }, @@ -1425,11 +1342,6 @@ static const struct rteth_config rteth_839x_cfg = { .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size, .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr, .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, - .get_mac_link_sts = rtl839x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts, .mac_reg = { RTETH_839X_MAC_ADDR_CTRL }, .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, .update_counter = rteth_83xx_update_counter, @@ -1473,11 +1385,6 @@ static const struct rteth_config rteth_930x_cfg = { .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size, .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr, .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0, - .get_mac_link_sts = rtl930x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts, .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL }, .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, .update_counter = rteth_93xx_update_counter, @@ -1521,11 +1428,6 @@ static const struct rteth_config rteth_931x_cfg = { .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size, .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr, .rst_glb_ctrl = RTL931X_RST_GLB_CTRL, - .get_mac_link_sts = rtldsa_931x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts, .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL }, .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, .update_counter = rteth_93xx_update_counter, @@ -1536,14 +1438,7 @@ static const struct rteth_config rteth_931x_cfg = { .netdev_ops = &rteth_931x_netdev_ops, }; -static const struct phylink_pcs_ops rteth_pcs_ops = { - .pcs_get_state = rteth_pcs_get_state, - .pcs_an_restart = rteth_pcs_an_restart, - .pcs_config = rteth_pcs_config, -}; - static const struct phylink_mac_ops rteth_mac_ops = { - .mac_select_pcs = rteth_mac_select_pcs, .mac_config = rteth_mac_config, .mac_link_down = rteth_mac_link_down, .mac_link_up = rteth_mac_link_up, @@ -1678,7 +1573,6 @@ static int rtl838x_eth_probe(struct platform_device *pdev) return -EINVAL; } - ctrl->pcs.ops = &rteth_pcs_ops; ctrl->phylink_config.dev = &dev->dev; ctrl->phylink_config.type = PHYLINK_NETDEV; ctrl->phylink_config.mac_capabilities = diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h index 8559139963..ea6ccddea7 100644 --- a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h +++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h @@ -112,34 +112,6 @@ #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) -/* MAC-side link state handling */ -#define RTL838X_MAC_LINK_STS (0xa188) -#define RTL839X_MAC_LINK_STS (0x0390) -#define RTL930X_MAC_LINK_STS (0xCB10) -#define RTL931X_MAC_LINK_STS (0x0ec0) - -#define RTL838X_MAC_LINK_SPD_STS (0xa190) -#define RTL839X_MAC_LINK_SPD_STS (0x03a0) -#define RTL930X_MAC_LINK_SPD_STS (0xCB18) -#define RTL931X_MAC_LINK_SPD_STS (0x0ed0) - -#define RTL838X_MAC_LINK_DUP_STS (0xa19c) -#define RTL839X_MAC_LINK_DUP_STS (0x03b0) -#define RTL930X_MAC_LINK_DUP_STS (0xCB28) -#define RTL931X_MAC_LINK_DUP_STS (0x0ef0) - -/* TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR??? */ - -#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) -#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) -#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C) -#define RTL931X_MAC_TX_PAUSE_STS (0x0ef8) - -#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) -#define RTL839X_MAC_RX_PAUSE_STS (0xCB30) -#define RTL930X_MAC_RX_PAUSE_STS (0xC2F8) -#define RTL931X_MAC_RX_PAUSE_STS (0x0f00) - #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) @@ -261,133 +233,6 @@ inline int rtl931x_dma_if_rx_ring_cntr(int i) return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); } -inline u32 rtl838x_get_mac_link_sts(int port) -{ - return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port)); -} - -inline u32 rtl839x_get_mac_link_sts(int p) -{ - return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_link_sts(int port) -{ - u32 link = sw_r32(RTL930X_MAC_LINK_STS); - - link = sw_r32(RTL930X_MAC_LINK_STS); - pr_info("%s link state is %08x\n", __func__, link); - return link & BIT(port); -} - -inline u32 rtldsa_931x_get_mac_link_sts(int port) -{ - unsigned int reg = RTL931X_MAC_LINK_STS + (port / 32) * 4; - u32 mask = BIT(port % 32); - u32 link; - - link = sw_r32(reg); - link = sw_r32(reg); - - return (link & mask); -} - -inline u32 rtl838x_get_mac_link_dup_sts(int port) -{ - return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port)); -} - -inline u32 rtl839x_get_mac_link_dup_sts(int p) -{ - return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_link_dup_sts(int port) -{ - return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port)); -} - -inline u32 rtl931x_get_mac_link_dup_sts(int p) -{ - return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl838x_get_mac_link_spd_sts(int port) -{ - int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 16) << 1; - return (speed & 0x3); -} - -inline u32 rtl839x_get_mac_link_spd_sts(int port) -{ - int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 16) << 1; - return (speed & 0x3); -} - -inline u32 rtl930x_get_mac_link_spd_sts(int port) -{ - int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 8) << 2; - return (speed & 0xf); -} - -inline u32 rtl931x_get_mac_link_spd_sts(int port) -{ - int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 8) << 2; - return (speed & 0xf); -} - -inline u32 rtl838x_get_mac_rx_pause_sts(int port) -{ - return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl839x_get_mac_rx_pause_sts(int p) -{ - return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_rx_pause_sts(int port) -{ - return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl931x_get_mac_rx_pause_sts(int p) -{ - return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl838x_get_mac_tx_pause_sts(int port) -{ - return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl839x_get_mac_tx_pause_sts(int p) -{ - return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_tx_pause_sts(int port) -{ - return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl931x_get_mac_tx_pause_sts(int p) -{ - return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - struct p_hdr; struct dsa_tag; struct rteth_ctrl; @@ -414,11 +259,6 @@ struct rteth_config { int (*dma_if_rx_ring_size)(int ring); int (*dma_if_rx_ring_cntr)(int ring); int rst_glb_ctrl; - u32 (*get_mac_link_sts)(int port); - u32 (*get_mac_link_dup_sts)(int port); - u32 (*get_mac_link_spd_sts)(int port); - u32 (*get_mac_rx_pause_sts)(int port); - u32 (*get_mac_tx_pause_sts)(int port); u32 mac_reg[RTETH_MAX_MAC_REGS]; int l2_tbl_flush_ctrl; void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio); From 681eb446cfcba99965f626e27fcad1476ff9e4e3 Mon Sep 17 00:00:00 2001 From: Paul Spooren Date: Sat, 14 Mar 2026 18:58:52 +0100 Subject: [PATCH 27/88] package: bump odhcpd to latest HEAD 2026-03-12 * 13cec01 dhcpv6-ia: dhcpv6_log_ia_addr(): parse return of snprintf Signed-off-by: Paul Spooren --- package/network/services/odhcpd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/services/odhcpd/Makefile b/package/network/services/odhcpd/Makefile index 70c860fbef..bf40208fc3 100644 --- a/package/network/services/odhcpd/Makefile +++ b/package/network/services/odhcpd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git -PKG_MIRROR_HASH:=89af53f1b6db61a5cc31eb39713f52eaa521e3ed3da12a742ad55b0bd8e5c248 -PKG_SOURCE_DATE:=2026-01-19 -PKG_SOURCE_VERSION:=13ef483716a504378b223d668c2482c93a804336 +PKG_MIRROR_HASH:=389d840185dabe2d872dc9751da3cee0a4a3570c8dc6f89c71c9b6a456ba6d90 +PKG_SOURCE_DATE:=2026-03-12 +PKG_SOURCE_VERSION:=13cec018c0d9bd452f4cb5e583c52fdf206cdc31 PKG_MAINTAINER:=Álvaro Fernández Rojas PKG_LICENSE:=GPL-2.0 From 2c2cea8864db209a2ed8a12421be10b27732990d Mon Sep 17 00:00:00 2001 From: Paul Spooren Date: Sat, 14 Mar 2026 19:00:52 +0100 Subject: [PATCH 28/88] package: update jsonfilter to latest HEAD 2026-03-12 * e3f6a41 main: exit 1 when showing the usage * b17c31f main: exit 1 on getopt() errors * e086664 lexer: fix a minor memleak in jp_get_token()/match_token() * e5a07f4 main: defer processing until options are processed * afe72ad main: usage spell fixes Signed-off-by: Paul Spooren --- package/utils/jsonfilter/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/utils/jsonfilter/Makefile b/package/utils/jsonfilter/Makefile index d057dadd76..d0aea0d92a 100644 --- a/package/utils/jsonfilter/Makefile +++ b/package/utils/jsonfilter/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/jsonpath.git -PKG_SOURCE_DATE:=2025-10-04 -PKG_SOURCE_VERSION:=f4fe702d0e8d9f8704b42f5d5c10950470ada231 -PKG_MIRROR_HASH:=799b630107aedb5bfd4b0494af82843f803759324140cce89256b479124d5b1c +PKG_SOURCE_DATE:=2026-03-12 +PKG_SOURCE_VERSION:=e086664e6a570630e8feba889482f174a9a8715e +PKG_MIRROR_HASH:=e00e8f5ca44d156284375a32e03529c29fdaeac1cbd276c214879aaa0a502548 CMAKE_INSTALL:=1 PKG_MAINTAINER:=Jo-Philipp Wich From 4cc753e9b78c53e87007318eedc5384d9ab929a1 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Mon, 23 Feb 2026 21:17:51 +0000 Subject: [PATCH 29/88] realtek: pcs: bring PLL definitions into shape Bring the PLL definitions into a proper shape. While there was already a definition for the PLL type, a generic PLL speed definition was missing. Introduce such a definition and adjust the naming of the existing PLL type definition to have a better distinction and avoid conflicts. The definitions can and should be used to make the CMU/PLL configuration more generic and reduce the need for variant-specific definitions. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 60 +++++++++++-------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 9a83d3fae9..119ec66e1a 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -153,9 +153,16 @@ enum rtpcs_port_media { }; enum rtpcs_sds_pll_type { - RTPCS_SDS_PLL_RING, - RTPCS_SDS_PLL_LC, - RTPCS_SDS_PLL_END, + RTPCS_SDS_PLL_TYPE_RING, + RTPCS_SDS_PLL_TYPE_LC, + RTPCS_SDS_PLL_TYPE_END, +}; + +enum rtpcs_sds_pll_speed { + RTPCS_SDS_PLL_SPD_1000, + RTPCS_SDS_PLL_SPD_2500, + RTPCS_SDS_PLL_SPD_10000, + RTPCS_SDS_PLL_SPD_END, }; enum rtpcs_chip_version { @@ -1251,9 +1258,9 @@ static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds */ pll_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit); - *pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_LC : RTPCS_SDS_PLL_RING; + *pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_TYPE_LC : RTPCS_SDS_PLL_TYPE_RING; - sbit = *pll == RTPCS_SDS_PLL_LC ? 8 : 12; + sbit = *pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; *speed = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); } @@ -1261,7 +1268,7 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ int speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - int sbit = pll == RTPCS_SDS_PLL_LC ? 8 : 12; + int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; int pbit = (sds == even_sds) ? 4 : 6; int pll_val; @@ -1270,10 +1277,10 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ (speed != RTSDS_930X_PLL_10000)) return -EINVAL; - if (pll >= RTPCS_SDS_PLL_END) + if (pll >= RTPCS_SDS_PLL_TYPE_END) return -EINVAL; - if ((pll == RTPCS_SDS_PLL_RING) && (speed == RTSDS_930X_PLL_10000)) + if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTSDS_930X_PLL_10000)) return -EINVAL; /* @@ -1282,7 +1289,7 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ * always activate both. */ - pll_val = pll == RTPCS_SDS_PLL_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING; + pll_val = pll == RTPCS_SDS_PLL_TYPE_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING; rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll_val); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, speed); @@ -1304,7 +1311,7 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) */ rtpcs_930x_sds_get_pll_data(sds, &pll, &speed); - bit = pll == RTPCS_SDS_PLL_LC ? 2 : 0; + bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, @@ -1418,19 +1425,20 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, return -ENOTSUPP; if (!neighbor_mode) - pll = speed == RTSDS_930X_PLL_10000 ? RTPCS_SDS_PLL_LC : RTPCS_SDS_PLL_RING; + pll = speed == RTSDS_930X_PLL_10000 ? RTPCS_SDS_PLL_TYPE_LC + : RTPCS_SDS_PLL_TYPE_RING; else if (speed == neighbor_speed) { speed_changed = false; pll = neighbor_pll; - } else if (neighbor_pll == RTPCS_SDS_PLL_RING) - pll = RTPCS_SDS_PLL_LC; + } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) + pll = RTPCS_SDS_PLL_TYPE_LC; else if (speed == RTSDS_930X_PLL_10000) { pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", __func__, sds->id, nb_sds->id); - rtpcs_930x_sds_reconfigure_pll(nb_sds, RTPCS_SDS_PLL_RING); - pll = RTPCS_SDS_PLL_LC; + rtpcs_930x_sds_reconfigure_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); + pll = RTPCS_SDS_PLL_TYPE_LC; } else - pll = RTPCS_SDS_PLL_RING; + pll = RTPCS_SDS_PLL_TYPE_RING; rtpcs_930x_sds_set_pll_data(sds, pll, speed); @@ -1438,7 +1446,7 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, rtpcs_930x_sds_reset_cmu(sds); pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, - pll == RTPCS_SDS_PLL_LC ? "LC" : "ring", hw_mode); + pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); return 0; } @@ -3363,27 +3371,27 @@ static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo return 0; case RTPCS_SDS_MODE_QSGMII: - pll_type = RTPCS_SDS_PLL_RING; + pll_type = RTPCS_SDS_PLL_TYPE_RING; force_pll_spd = false; break; case RTPCS_SDS_MODE_1000BASEX: - pll_type = RTPCS_SDS_PLL_RING; + pll_type = RTPCS_SDS_PLL_TYPE_RING; force_pll_spd = false; break; /* case MII_1000BX100BX_AUTO: - pll_type = RTPCS_SDS_PLL_RING; + pll_type = RTPCS_SDS_PLL_TYPE_RING; force_pll_spd = false; break; */ case RTPCS_SDS_MODE_SGMII: - pll_type = RTPCS_SDS_PLL_RING; + pll_type = RTPCS_SDS_PLL_TYPE_RING; force_pll_spd = false; break; case RTPCS_SDS_MODE_2500BASEX: - pll_type = RTPCS_SDS_PLL_RING; + pll_type = RTPCS_SDS_PLL_TYPE_RING; force_pll_spd = true; break; @@ -3405,10 +3413,10 @@ static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo } pr_info("%s: pll_type %s cmu_page %x force_pll_spd %d even_sds %d sds %d\n", - __func__, pll_type == RTPCS_SDS_PLL_LC ? "LC" : "ring", cmu_page, force_pll_spd, - even_sds->id, sds->id); + __func__, pll_type == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", cmu_page, + force_pll_spd, even_sds->id, sds->id); - if (pll_type == RTPCS_SDS_PLL_RING) { + if (pll_type == RTPCS_SDS_PLL_TYPE_RING) { rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x0); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 2, 0x3); @@ -3418,7 +3426,7 @@ static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo force_lc_mode_val_bit, 0x0); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 12, 12, 0x1); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, force_pll_spd ? 0x1 : 0x0); - } else if (pll_type == RTPCS_SDS_PLL_LC) { + } else if (pll_type == RTPCS_SDS_PLL_TYPE_LC) { rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x1); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 1, 0, 0x3); From 681e2882c4cbf88f20f3d5b2505c672216994790 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Mon, 23 Feb 2026 21:44:37 +0000 Subject: [PATCH 30/88] realtek: pcs: rtl930x: use generic PLL speed definition Make use of the generic PLL speed definition in the current CMU/PLL configuration code for RTL930x. Assign explicit values to the field of the PLL speed enum to tie these fields to the values that are used in the register fields. This allows to simplify the code a bit. Setting the actual speed selector for RTL930x was found to be similar to RTL931x despite of different values being used since the LSB is always 1. According to the SDK this seems to be a force bit while the other bits are the actual value/selector that is being forced. For RTL930x, separate the speed selection to be able to use that as common behavior for both variants later. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 51 ++++++++++--------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 119ec66e1a..12a333635d 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -98,9 +98,6 @@ #define RTPCS_930X_SDS_SUBMODE_USXGMII_SX 0x0 #define RTPCS_930X_SDS_SUBMODE_USXGMII_QX 0x2 -#define RTSDS_930X_PLL_1000 0x1 -#define RTSDS_930X_PLL_10000 0x5 -#define RTSDS_930X_PLL_2500 0x3 #define RTPCS_930X_PLL_LC 0x3 #define RTPCS_930X_PLL_RING 0x1 @@ -159,9 +156,9 @@ enum rtpcs_sds_pll_type { }; enum rtpcs_sds_pll_speed { - RTPCS_SDS_PLL_SPD_1000, - RTPCS_SDS_PLL_SPD_2500, - RTPCS_SDS_PLL_SPD_10000, + RTPCS_SDS_PLL_SPD_1000 = 0, + RTPCS_SDS_PLL_SPD_2500 = 1, + RTPCS_SDS_PLL_SPD_10000 = 2, RTPCS_SDS_PLL_SPD_END, }; @@ -1246,11 +1243,11 @@ static void rtpcs_930x_sds_rx_reset(struct rtpcs_serdes *sds, } static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll, - int *speed) + enum rtpcs_sds_pll_speed *speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit, pbit = (sds == even_sds) ? 4 : 6; - int pll_val; + int pll_val, speed_val; /* * PLL data is shared between adjacent SerDes in the even lane. Each SerDes defines @@ -1261,26 +1258,27 @@ static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds *pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_TYPE_LC : RTPCS_SDS_PLL_TYPE_RING; sbit = *pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; - *speed = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); + speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); } static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, - int speed) + enum rtpcs_sds_pll_speed speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; int pbit = (sds == even_sds) ? 4 : 6; int pll_val; - if ((speed != RTSDS_930X_PLL_1000) && - (speed != RTSDS_930X_PLL_2500) && - (speed != RTSDS_930X_PLL_10000)) + if (speed >= RTPCS_SDS_PLL_SPD_END) return -EINVAL; if (pll >= RTPCS_SDS_PLL_TYPE_END) return -EINVAL; - if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTSDS_930X_PLL_10000)) + if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000)) return -EINVAL; /* @@ -1292,7 +1290,9 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ pll_val = pll == RTPCS_SDS_PLL_TYPE_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING; rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll_val); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, speed); + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); return 0; } @@ -1301,8 +1301,9 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int reset_sequence[4] = { 3, 2, 3, 1 }; + enum rtpcs_sds_pll_speed speed; enum rtpcs_sds_pll_type pll; - int speed, i, bit; + int i, bit; /* * After the PLL speed has changed, the CMU must take over the new values. The models @@ -1365,8 +1366,9 @@ static void rtpcs_930x_sds_set_power(struct rtpcs_serdes *sds, bool on) static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) { + enum rtpcs_sds_pll_speed speed; enum rtpcs_sds_pll_type tmp; - int mode, speed; + int mode; mode = __rtpcs_930x_sds_get_ip_mode(sds); rtpcs_930x_sds_get_pll_data(sds, &tmp, &speed); @@ -1388,9 +1390,10 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) { struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds); + enum rtpcs_sds_pll_speed speed, neighbor_speed; enum rtpcs_sds_pll_type pll, neighbor_pll; - int speed, neighbor_speed, neighbor_mode; bool speed_changed = true; + int neighbor_mode; /* * A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate @@ -1416,23 +1419,23 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, if ((hw_mode == RTPCS_SDS_MODE_1000BASEX) || (hw_mode == RTPCS_SDS_MODE_SGMII)) - speed = RTSDS_930X_PLL_1000; + speed = RTPCS_SDS_PLL_SPD_1000; else if (hw_mode == RTPCS_SDS_MODE_2500BASEX) - speed = RTSDS_930X_PLL_2500; + speed = RTPCS_SDS_PLL_SPD_2500; else if (hw_mode == RTPCS_SDS_MODE_10GBASER) - speed = RTSDS_930X_PLL_10000; + speed = RTPCS_SDS_PLL_SPD_10000; else return -ENOTSUPP; if (!neighbor_mode) - pll = speed == RTSDS_930X_PLL_10000 ? RTPCS_SDS_PLL_TYPE_LC - : RTPCS_SDS_PLL_TYPE_RING; + pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC + : RTPCS_SDS_PLL_TYPE_RING; else if (speed == neighbor_speed) { speed_changed = false; pll = neighbor_pll; } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) pll = RTPCS_SDS_PLL_TYPE_LC; - else if (speed == RTSDS_930X_PLL_10000) { + else if (speed == RTPCS_SDS_PLL_SPD_10000) { pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", __func__, sds->id, nb_sds->id); rtpcs_930x_sds_reconfigure_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); From 55139cebbeeb1d526b9ed6341d7ace0a2ba0cb05 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Mon, 23 Feb 2026 22:10:45 +0000 Subject: [PATCH 31/88] realtek: pcs: rtl930x: use generic PLL type definition Make use of the generic PLL type definition in the current CMU/PLL configuration code for RTL930x. Assign explicit values to the fields of the PLL type enum to tie these fields to the values that are used in the register fields. This allows to simplify the code a bit. Selecting the PLL to use for a SerDes shares some similarities between RTL930x and RTL931x. While the location of the selector in the registers is placed different, similar underlying bit semantics are used. This allows to reuse the same plain values for both. RTL930x uses a force bit and a selector bit, RTL931x at least uses the selector bit with the same values for ring and LC PLL. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 12a333635d..f3796c984a 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -98,9 +98,6 @@ #define RTPCS_930X_SDS_SUBMODE_USXGMII_SX 0x0 #define RTPCS_930X_SDS_SUBMODE_USXGMII_QX 0x2 -#define RTPCS_930X_PLL_LC 0x3 -#define RTPCS_930X_PLL_RING 0x1 - /* Registers of the internal SerDes of the 9310 */ #define RTPCS_931X_MAC_GROUP0_1_CTRL (0x13a4) #define RTPCS_931X_MAC_GROUP2_3_CTRL (0x13a8) @@ -150,8 +147,8 @@ enum rtpcs_port_media { }; enum rtpcs_sds_pll_type { - RTPCS_SDS_PLL_TYPE_RING, - RTPCS_SDS_PLL_TYPE_LC, + RTPCS_SDS_PLL_TYPE_RING = 0, + RTPCS_SDS_PLL_TYPE_LC = 1, RTPCS_SDS_PLL_TYPE_END, }; @@ -1255,7 +1252,9 @@ static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds */ pll_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit); - *pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_TYPE_LC : RTPCS_SDS_PLL_TYPE_RING; + + /* bit 0 is force-bit, bit 1 is PLL selector */ + *pll = (enum rtpcs_sds_pll_type)(pll_val >> 1); sbit = *pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); @@ -1270,7 +1269,6 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; int pbit = (sds == even_sds) ? 4 : 6; - int pll_val; if (speed >= RTPCS_SDS_PLL_SPD_END) return -EINVAL; @@ -1287,9 +1285,10 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ * always activate both. */ - pll_val = pll == RTPCS_SDS_PLL_TYPE_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING; rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll_val); + + /* bit 0 is force-bit, bit 1 is PLL selector */ + rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); /* bit 0 is force-bit, bits [3:1] are speed selector */ rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); From c41356933050a7c2d9bc6f144644bdefeefd43be Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 00:14:12 +0000 Subject: [PATCH 32/88] realtek: pcs: rtl930x: split pll config Split up PLL configuration of RTL930x in the two distinct actions of configuring the PLL itself (aka setting its speed, etc.) and selecting which PLL is used by a SerDes. It was found that for both RTL930x and RTL931x, PLL configuration can be combined while selecting the PLL a SerDes uses differs and needs to be implemented variant-specific. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 79 ++++++++++++++----- 1 file changed, 58 insertions(+), 21 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index f3796c984a..80d4d46bd5 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -1239,36 +1239,56 @@ static void rtpcs_930x_sds_rx_reset(struct rtpcs_serdes *sds, rtpcs_sds_write_bits(sds, page, 0x15, 4, 4, 0x0); } -static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll, +static int rtpcs_930x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int pbit = (sds == even_sds) ? 4 : 6; + int pll_sel; + + pll_sel = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit); + if (pll_sel < 0) + return pll_sel; + + /* bit 0 is force-bit, bit 1 is PLL selector */ + *pll = (enum rtpcs_sds_pll_type)(pll_sel >> 1); + return 0; +} + +static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, enum rtpcs_sds_pll_speed *speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - int sbit, pbit = (sds == even_sds) ? 4 : 6; - int pll_val, speed_val; + int sbit, speed_val; /* * PLL data is shared between adjacent SerDes in the even lane. Each SerDes defines * what PLL it needs (ring or LC) while the PLL itself stores the current speed. */ - pll_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit); - - /* bit 0 is force-bit, bit 1 is PLL selector */ - *pll = (enum rtpcs_sds_pll_type)(pll_val >> 1); - - sbit = *pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); /* bit 0 is force-bit, bits [3:1] are speed selector */ *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); } +static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int pbit = (sds == even_sds) ? 4 : 6; + + /* Selecting the PLL a SerDes is done in the even lane register */ + + /* bit 0 is force-bit, bit 1 is PLL selector */ + return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); +} + static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, enum rtpcs_sds_pll_speed speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; - int pbit = (sds == even_sds) ? 4 : 6; if (speed >= RTPCS_SDS_PLL_SPD_END) return -EINVAL; @@ -1287,9 +1307,6 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); - /* bit 0 is force-bit, bit 1 is PLL selector */ - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); - /* bit 0 is force-bit, bits [3:1] are speed selector */ rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); @@ -1300,9 +1317,8 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int reset_sequence[4] = { 3, 2, 3, 1 }; - enum rtpcs_sds_pll_speed speed; enum rtpcs_sds_pll_type pll; - int i, bit; + int ret, i, bit; /* * After the PLL speed has changed, the CMU must take over the new values. The models @@ -1310,7 +1326,10 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) * to flipping two bits in a special sequence. */ - rtpcs_930x_sds_get_pll_data(sds, &pll, &speed); + ret = rtpcs_930x_sds_get_pll_select(sds, &pll); + if (ret < 0) + return; + bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) @@ -1366,11 +1385,16 @@ static void rtpcs_930x_sds_set_power(struct rtpcs_serdes *sds, bool on) static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) { enum rtpcs_sds_pll_speed speed; - enum rtpcs_sds_pll_type tmp; - int mode; + enum rtpcs_sds_pll_type old_pll; + int mode, ret; mode = __rtpcs_930x_sds_get_ip_mode(sds); - rtpcs_930x_sds_get_pll_data(sds, &tmp, &speed); + + ret = rtpcs_930x_sds_get_pll_select(sds, &old_pll); + if (ret < 0) + return; + + rtpcs_930x_sds_get_pll_data(sds, old_pll, &speed); rtpcs_930x_sds_set_power(sds, false); __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); @@ -1378,6 +1402,10 @@ static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_ rtpcs_930x_sds_set_pll_data(sds, pll, speed); rtpcs_930x_sds_reset_cmu(sds); + ret = rtpcs_930x_sds_set_pll_select(sds, sds->hw_mode, pll); + if (ret < 0) + return; + __rtpcs_930x_sds_set_ip_mode(sds, mode); if (rtpcs_930x_sds_wait_clock_ready(sds)) pr_err("%s: SDS %d could not sync clock\n", __func__, sds->id); @@ -1392,7 +1420,7 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_speed speed, neighbor_speed; enum rtpcs_sds_pll_type pll, neighbor_pll; bool speed_changed = true; - int neighbor_mode; + int neighbor_mode, ret; /* * A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate @@ -1414,7 +1442,12 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, */ neighbor_mode = __rtpcs_930x_sds_get_ip_mode(nb_sds); - rtpcs_930x_sds_get_pll_data(nb_sds, &neighbor_pll, &neighbor_speed); + + ret = rtpcs_930x_sds_get_pll_select(sds, &neighbor_pll); + if (ret < 0) + return ret; + + rtpcs_930x_sds_get_pll_data(nb_sds, neighbor_pll, &neighbor_speed); if ((hw_mode == RTPCS_SDS_MODE_1000BASEX) || (hw_mode == RTPCS_SDS_MODE_SGMII)) @@ -1447,6 +1480,10 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, if (speed_changed) rtpcs_930x_sds_reset_cmu(sds); + ret = rtpcs_930x_sds_set_pll_select(sds, hw_mode, pll); + if (ret < 0) + return ret; + pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); From 130d8d6b5197795a15c4caf11af49caa6f470371 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 11:58:14 +0000 Subject: [PATCH 33/88] realtek: pcs: add generic mode-to-pll-speed mapper Add a mapper function to infer the to-be-selected PLL speed from the desired SerDes hardware mode. This avoids having similar logic in each CMU implementation. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 40 ++++++++++++++----- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 80d4d46bd5..5e1ca2584e 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -516,6 +516,34 @@ static void rtpcs_generic_sds_restart_autoneg(struct rtpcs_serdes *sds) rtpcs_sds_write_field(sds, &sds->regs->an_restart, 0x1); } +static int rtpcs_sds_select_pll_speed(enum rtpcs_sds_mode hw_mode, enum rtpcs_sds_pll_speed *speed) +{ + switch (hw_mode) { + case RTPCS_SDS_MODE_1000BASEX: + case RTPCS_SDS_MODE_SGMII: + case RTPCS_SDS_MODE_QSGMII: + *speed = RTPCS_SDS_PLL_SPD_1000; + break; + case RTPCS_SDS_MODE_2500BASEX: + *speed = RTPCS_SDS_PLL_SPD_2500; + break; + case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + *speed = RTPCS_SDS_PLL_SPD_10000; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + /* Variant-specific functions */ /* RTL838X */ @@ -1449,15 +1477,9 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, rtpcs_930x_sds_get_pll_data(nb_sds, neighbor_pll, &neighbor_speed); - if ((hw_mode == RTPCS_SDS_MODE_1000BASEX) || - (hw_mode == RTPCS_SDS_MODE_SGMII)) - speed = RTPCS_SDS_PLL_SPD_1000; - else if (hw_mode == RTPCS_SDS_MODE_2500BASEX) - speed = RTPCS_SDS_PLL_SPD_2500; - else if (hw_mode == RTPCS_SDS_MODE_10GBASER) - speed = RTPCS_SDS_PLL_SPD_10000; - else - return -ENOTSUPP; + ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); + if (ret < 0) + return ret; if (!neighbor_mode) pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC From 6f06dbf7dd5d6a5e1cc063fbf88b155d0cee09ca Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 12:11:18 +0000 Subject: [PATCH 34/88] realtek: pcs: rtl930x: move CMU reset into PLL config Move resetting the CMU into the PLL configuration itself where the speed is set. Since this operation is not dependent of the target SerDes and only needs to be called if the speed changed, it fits better there. Though the call was guarded with a 'speed_changed' before, this also applies to actually changing the speed. This was done before anyway, even if the speed value hasn't really changed. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 53 +++++++++---------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 5e1ca2584e..8f0474911a 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -1312,6 +1312,29 @@ static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); } +static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int reset_sequence[4] = { 3, 2, 3, 1 }; + enum rtpcs_sds_pll_type pll; + int bit, i, ret; + + /* + * After the PLL speed has changed, the CMU must take over the new values. The models + * of the Otto platform have different reset sequences. Luckily it always boils down + * to flipping two bits in a special sequence. + */ + ret = rtpcs_930x_sds_get_pll_select(sds, &pll); + if (ret < 0) + return; + + bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; + + for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) + rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, + reset_sequence[i]); +} + static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, enum rtpcs_sds_pll_speed speed) { @@ -1338,33 +1361,10 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ /* bit 0 is force-bit, bits [3:1] are speed selector */ rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); + rtpcs_930x_sds_reset_cmu(sds); return 0; } -static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) -{ - struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - int reset_sequence[4] = { 3, 2, 3, 1 }; - enum rtpcs_sds_pll_type pll; - int ret, i, bit; - - /* - * After the PLL speed has changed, the CMU must take over the new values. The models - * of the Otto platform have different reset sequences. Luckily it always boils down - * to flipping two bits in a special sequence. - */ - - ret = rtpcs_930x_sds_get_pll_select(sds, &pll); - if (ret < 0) - return; - - bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; - - for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) - rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, - reset_sequence[i]); -} - static int rtpcs_930x_sds_wait_clock_ready(struct rtpcs_serdes *sds) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); @@ -1428,7 +1428,6 @@ static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_ __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); rtpcs_930x_sds_set_pll_data(sds, pll, speed); - rtpcs_930x_sds_reset_cmu(sds); ret = rtpcs_930x_sds_set_pll_select(sds, sds->hw_mode, pll); if (ret < 0) @@ -1497,10 +1496,8 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, } else pll = RTPCS_SDS_PLL_TYPE_RING; - rtpcs_930x_sds_set_pll_data(sds, pll, speed); - if (speed_changed) - rtpcs_930x_sds_reset_cmu(sds); + rtpcs_930x_sds_set_pll_data(sds, pll, speed); ret = rtpcs_930x_sds_set_pll_select(sds, hw_mode, pll); if (ret < 0) From c4a3a0723bff0d099ea806285ed0efce21460444 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 17:05:28 +0000 Subject: [PATCH 35/88] realtek: pcs: rtl930x: fix naming and error handling Fix naming of several functions to better reflect what they are doing. While at it, also improve the error handling a lot, changing the return type from void to int and actually returning errors. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 74 ++++++++++++------- 1 file changed, 48 insertions(+), 26 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 8f0474911a..93459f2c4a 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -1282,8 +1282,8 @@ static int rtpcs_930x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd return 0; } -static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, - enum rtpcs_sds_pll_speed *speed) +static int rtpcs_930x_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed *speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit, speed_val; @@ -1295,9 +1295,12 @@ static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); + if (speed_val < 0) + return speed_val; /* bit 0 is force-bit, bits [3:1] are speed selector */ *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); + return 0; } static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, @@ -1312,7 +1315,7 @@ static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); } -static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) +static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int reset_sequence[4] = { 3, 2, 3, 1 }; @@ -1326,20 +1329,25 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) */ ret = rtpcs_930x_sds_get_pll_select(sds, &pll); if (ret < 0) - return; + return ret; bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; - for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) - rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, - reset_sequence[i]); + for (i = 0; i < ARRAY_SIZE(reset_sequence); i++) { + ret = rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit, + reset_sequence[i]); + if (ret < 0) + return ret; + } + return 0; } -static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, - enum rtpcs_sds_pll_speed speed) +static int rtpcs_930x_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed speed) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + int ret; if (speed >= RTPCS_SDS_PLL_SPD_END) return -EINVAL; @@ -1356,13 +1364,16 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_ * always activate both. */ - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); + if (ret < 0) + return ret; /* bit 0 is force-bit, bits [3:1] are speed selector */ - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); + if (ret < 0) + return ret; - rtpcs_930x_sds_reset_cmu(sds); - return 0; + return rtpcs_930x_sds_reset_cmu(sds); } static int rtpcs_930x_sds_wait_clock_ready(struct rtpcs_serdes *sds) @@ -1410,7 +1421,7 @@ static void rtpcs_930x_sds_set_power(struct rtpcs_serdes *sds, bool on) rtpcs_sds_write_bits(sds, 0x20, 0x00, 5, 4, rx_enable); } -static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) +static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) { enum rtpcs_sds_pll_speed speed; enum rtpcs_sds_pll_type old_pll; @@ -1420,27 +1431,32 @@ static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_ ret = rtpcs_930x_sds_get_pll_select(sds, &old_pll); if (ret < 0) - return; + return ret; - rtpcs_930x_sds_get_pll_data(sds, old_pll, &speed); + ret = rtpcs_930x_sds_get_pll_config(sds, old_pll, &speed); + if (ret < 0) + return ret; rtpcs_930x_sds_set_power(sds, false); __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); - rtpcs_930x_sds_set_pll_data(sds, pll, speed); + ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; ret = rtpcs_930x_sds_set_pll_select(sds, sds->hw_mode, pll); if (ret < 0) - return; + return ret; __rtpcs_930x_sds_set_ip_mode(sds, mode); if (rtpcs_930x_sds_wait_clock_ready(sds)) pr_err("%s: SDS %d could not sync clock\n", __func__, sds->id); rtpcs_930x_sds_set_power(sds, true); + return 0; } -static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, +static int rtpcs_930x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) { struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds); @@ -1474,7 +1490,9 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, if (ret < 0) return ret; - rtpcs_930x_sds_get_pll_data(nb_sds, neighbor_pll, &neighbor_speed); + ret = rtpcs_930x_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed); + if (ret < 0) + return ret; ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); if (ret < 0) @@ -1491,13 +1509,16 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, else if (speed == RTPCS_SDS_PLL_SPD_10000) { pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", __func__, sds->id, nb_sds->id); - rtpcs_930x_sds_reconfigure_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); + ret = rtpcs_930x_sds_reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); + if (ret < 0) + return ret; + pll = RTPCS_SDS_PLL_TYPE_LC; } else pll = RTPCS_SDS_PLL_TYPE_RING; if (speed_changed) - rtpcs_930x_sds_set_pll_data(sds, pll, speed); + ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed); ret = rtpcs_930x_sds_set_pll_select(sds, hw_mode, pll); if (ret < 0) @@ -1506,7 +1527,7 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds, pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); - return 0; + return ret; } static void rtpcs_930x_sds_reset_state_machine(struct rtpcs_serdes *sds) @@ -1598,9 +1619,10 @@ static int rtpcs_930x_sds_set_ip_mode(struct rtpcs_serdes *sds, if (hw_mode == RTPCS_SDS_MODE_OFF) return 0; - if (rtpcs_930x_sds_config_pll(sds, hw_mode)) - pr_err("%s: SDS %d could not configure PLL for mode %d\n", __func__, - sds->id, hw_mode); + ret = rtpcs_930x_sds_config_cmu(sds, hw_mode); + if (ret < 0) + pr_err("%s: SDS %d could not configure PLL for mode %d: %d\n", __func__, + sds->id, hw_mode, ret); ret = __rtpcs_930x_sds_set_ip_mode(sds, mode_val); if (ret < 0) From 8e29b78726b4a87d2bb9124ced33658f9cf6a138 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 18:22:45 +0000 Subject: [PATCH 36/88] realtek: pcs: add CMU management SerDes ops Add new SerDes ops for CMU management to be able to share common behavior of CMU configuration for RTL930x and RTL931x while still covering variant specifics. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 93459f2c4a..9767bd8e14 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -179,6 +179,14 @@ struct rtpcs_serdes_ops { int (*set_autoneg)(struct rtpcs_serdes *sds, unsigned int neg_mode, const unsigned long *advertising); void (*restart_autoneg)(struct rtpcs_serdes *sds); + + /* CMU management */ + int (*get_pll_select)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll); + int (*set_pll_select)(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll); + int (*reset_cmu)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); + /* online reconfiguration of a running SerDes to another PLL */ + int (*reconfigure_to_pll)(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll); }; struct rtpcs_sds_reg_field { From eccb5c6fa1cd0266bfa28601d614ac00a7b8a9a2 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 21:22:05 +0000 Subject: [PATCH 37/88] realtek: pcs: make rtl930x CMU config generic Generalize the RTL930x CMU configuration to support RTL931x as well. Both implementations differ only in minor details, allowing them to share common code and avoid duplication. Affected functions are moved up in the code to the 93xx common area and slightly renamed. Existing variant-specific functions are adjusted too and assigned to the previously added SerDes operation hooks. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 274 +++++++++--------- 1 file changed, 137 insertions(+), 137 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 9767bd8e14..70e8f37eb3 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -1119,6 +1119,135 @@ static int rtpcs_93xx_init_serdes_common(struct rtpcs_ctrl *ctrl) return 0; } +static int rtpcs_93xx_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed *speed) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int sbit, speed_val; + + /* + * PLL config is shared between adjacent SerDes in the even lane. Each SerDes defines + * what PLL it needs (ring or LC) while the PLL itself stores the current speed. + */ + + sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); + if (speed_val < 0) + return speed_val; + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); + return 0; +} + +static int rtpcs_93xx_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, + enum rtpcs_sds_pll_speed speed) +{ + struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); + int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; + int ret; + + if (speed >= RTPCS_SDS_PLL_SPD_END) + return -EINVAL; + + if (pll >= RTPCS_SDS_PLL_TYPE_END) + return -EINVAL; + + if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000)) + return -EINVAL; + + /* + * A SerDes clock can either be taken from the low speed ring PLL or the high speed + * LC PLL. As it is unclear if disabling PLLs has any positive or negative effect, + * always activate both. + */ + + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); + if (ret < 0) + return ret; + + /* bit 0 is force-bit, bits [3:1] are speed selector */ + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); + if (ret < 0) + return ret; + + if (sds->ops->reset_cmu) + ret = sds->ops->reset_cmu(sds, pll); + + return ret; +} + +static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) +{ + struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds); + enum rtpcs_sds_pll_speed speed, neighbor_speed; + enum rtpcs_sds_pll_type pll, neighbor_pll; + bool speed_changed = true; + int ret; + + /* + * A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate + * signals of 1.25G and 3.125G for link speeds of 1G/2.5G. A high speed LC PLL can + * additionally generate a 10.3125G signal for 10G speeds. To drive the pair at different + * speeds each SerDes must use its own PLL. But what if the SerDess attached to the ring + * PLL suddenly needs 10G but the LC PLL is running at 1G? To avoid reconfiguring the + * "partner" SerDes we must choose wisely what assignment serves the current needs. The + * logic boils down to the following rules: + * + * - Use ring PLL for slow 1G speeds + * - Use LC PLL for fast 10G speeds + * - For 2.5G prefer ring over LC PLL + * + * However, when we want to configure 10G speed while the other SerDes is already using + * the LC PLL for a slower speed, there is no way to avoid reconfiguration. Note that + * this can even happen when the other SerDes is not actually in use, because changing + * the state of a SerDes back to RTL930X_SDS_OFF is not (yet) implemented. + */ + + ret = nb_sds->ops->get_pll_select(nb_sds, &neighbor_pll); + if (ret < 0) + return ret; + + ret = rtpcs_93xx_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed); + if (ret < 0) + return ret; + + ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); + if (ret < 0) + return ret; + + if (nb_sds->hw_mode == RTPCS_SDS_MODE_OFF) + pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC + : RTPCS_SDS_PLL_TYPE_RING; + else if (speed == neighbor_speed) { + speed_changed = false; + pll = neighbor_pll; + } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) + pll = RTPCS_SDS_PLL_TYPE_LC; + else if (speed == RTPCS_SDS_PLL_SPD_10000) { + pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", + __func__, sds->id, nb_sds->id); + ret = nb_sds->ops->reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); + if (ret < 0) + return ret; + + pll = RTPCS_SDS_PLL_TYPE_LC; + } else + pll = RTPCS_SDS_PLL_TYPE_RING; + + if (speed_changed) + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + + ret = sds->ops->set_pll_select(sds, hw_mode, pll); + if (ret < 0) + return ret; + + pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, + pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); + + return ret; +} + /* RTL930X */ /* @@ -1290,27 +1419,6 @@ static int rtpcs_930x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd return 0; } -static int rtpcs_930x_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, - enum rtpcs_sds_pll_speed *speed) -{ - struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - int sbit, speed_val; - - /* - * PLL data is shared between adjacent SerDes in the even lane. Each SerDes defines - * what PLL it needs (ring or LC) while the PLL itself stores the current speed. - */ - - sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; - speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit); - if (speed_val < 0) - return speed_val; - - /* bit 0 is force-bit, bits [3:1] are speed selector */ - *speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1); - return 0; -} - static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, enum rtpcs_sds_pll_type pll) { @@ -1323,11 +1431,10 @@ static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0)); } -static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) +static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); int reset_sequence[4] = { 3, 2, 3, 1 }; - enum rtpcs_sds_pll_type pll; int bit, i, ret; /* @@ -1335,9 +1442,6 @@ static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) * of the Otto platform have different reset sequences. Luckily it always boils down * to flipping two bits in a special sequence. */ - ret = rtpcs_930x_sds_get_pll_select(sds, &pll); - if (ret < 0) - return ret; bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0; @@ -1350,40 +1454,6 @@ static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds) return 0; } -static int rtpcs_930x_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll, - enum rtpcs_sds_pll_speed speed) -{ - struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12; - int ret; - - if (speed >= RTPCS_SDS_PLL_SPD_END) - return -EINVAL; - - if (pll >= RTPCS_SDS_PLL_TYPE_END) - return -EINVAL; - - if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000)) - return -EINVAL; - - /* - * A SerDes clock can either be taken from the low speed ring PLL or the high speed - * LC PLL. As it is unclear if disabling PLLs has any positive or negative effect, - * always activate both. - */ - - ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); - if (ret < 0) - return ret; - - /* bit 0 is force-bit, bits [3:1] are speed selector */ - ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0)); - if (ret < 0) - return ret; - - return rtpcs_930x_sds_reset_cmu(sds); -} - static int rtpcs_930x_sds_wait_clock_ready(struct rtpcs_serdes *sds) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); @@ -1441,14 +1511,14 @@ static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpc if (ret < 0) return ret; - ret = rtpcs_930x_sds_get_pll_config(sds, old_pll, &speed); + ret = rtpcs_93xx_sds_get_pll_config(sds, old_pll, &speed); if (ret < 0) return ret; rtpcs_930x_sds_set_power(sds, false); __rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF); - ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed); + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); if (ret < 0) return ret; @@ -1464,80 +1534,6 @@ static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpc return 0; } -static int rtpcs_930x_sds_config_cmu(struct rtpcs_serdes *sds, - enum rtpcs_sds_mode hw_mode) -{ - struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds); - enum rtpcs_sds_pll_speed speed, neighbor_speed; - enum rtpcs_sds_pll_type pll, neighbor_pll; - bool speed_changed = true; - int neighbor_mode, ret; - - /* - * A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate - * signals of 1.25G and 3.125G for link speeds of 1G/2.5G. A high speed LC PLL can - * additionally generate a 10.3125G signal for 10G speeds. To drive the pair at different - * speeds each SerDes must use its own PLL. But what if the SerDess attached to the ring - * PLL suddenly needs 10G but the LC PLL is running at 1G? To avoid reconfiguring the - * "partner" SerDes we must choose wisely what assignment serves the current needs. The - * logic boils down to the following rules: - * - * - Use ring PLL for slow 1G speeds - * - Use LC PLL for fast 10G speeds - * - For 2.5G prefer ring over LC PLL - * - * However, when we want to configure 10G speed while the other SerDes is already using - * the LC PLL for a slower speed, there is no way to avoid reconfiguration. Note that - * this can even happen when the other SerDes is not actually in use, because changing - * the state of a SerDes back to RTL930X_SDS_OFF is not (yet) implemented. - */ - - neighbor_mode = __rtpcs_930x_sds_get_ip_mode(nb_sds); - - ret = rtpcs_930x_sds_get_pll_select(sds, &neighbor_pll); - if (ret < 0) - return ret; - - ret = rtpcs_930x_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed); - if (ret < 0) - return ret; - - ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); - if (ret < 0) - return ret; - - if (!neighbor_mode) - pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC - : RTPCS_SDS_PLL_TYPE_RING; - else if (speed == neighbor_speed) { - speed_changed = false; - pll = neighbor_pll; - } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) - pll = RTPCS_SDS_PLL_TYPE_LC; - else if (speed == RTPCS_SDS_PLL_SPD_10000) { - pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", - __func__, sds->id, nb_sds->id); - ret = rtpcs_930x_sds_reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); - if (ret < 0) - return ret; - - pll = RTPCS_SDS_PLL_TYPE_LC; - } else - pll = RTPCS_SDS_PLL_TYPE_RING; - - if (speed_changed) - ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed); - - ret = rtpcs_930x_sds_set_pll_select(sds, hw_mode, pll); - if (ret < 0) - return ret; - - pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, - pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); - - return ret; -} - static void rtpcs_930x_sds_reset_state_machine(struct rtpcs_serdes *sds) { rtpcs_sds_write_bits(sds, 0x06, 0x02, 12, 12, 0x01); /* SM_RESET bit */ @@ -1627,7 +1623,7 @@ static int rtpcs_930x_sds_set_ip_mode(struct rtpcs_serdes *sds, if (hw_mode == RTPCS_SDS_MODE_OFF) return 0; - ret = rtpcs_930x_sds_config_cmu(sds, hw_mode); + ret = rtpcs_93xx_sds_config_cmu(sds, hw_mode); if (ret < 0) pr_err("%s: SDS %d could not configure PLL for mode %d: %d\n", __func__, sds->id, hw_mode, ret); @@ -4300,6 +4296,10 @@ static const struct rtpcs_serdes_ops rtpcs_930x_sds_ops = { .xsg_write = rtpcs_930x_sds_op_xsg_write, .set_autoneg = rtpcs_93xx_sds_set_autoneg, .restart_autoneg = rtpcs_generic_sds_restart_autoneg, + .get_pll_select = rtpcs_930x_sds_get_pll_select, + .set_pll_select = rtpcs_930x_sds_set_pll_select, + .reset_cmu = rtpcs_930x_sds_reset_cmu, + .reconfigure_to_pll = rtpcs_930x_sds_reconfigure_to_pll, }; static const struct rtpcs_sds_regs rtpcs_930x_sds_regs = { From 7c7bdd803f3af46b77acc21d17573f4bb50f6eec Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 21:32:24 +0000 Subject: [PATCH 38/88] realtek: pcs: rtl93xx: slightly improve CMU config Do some slight improvements to the generic CMU configuration for RTL93xx. This covers several points: - update comments to the current reality - add fast path to avoid issues and unneeded calls - use cached mode value instead of register read Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 61 +++++++++++-------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 70e8f37eb3..198794f1fe 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -1161,7 +1161,6 @@ static int rtpcs_93xx_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sd * LC PLL. As it is unclear if disabling PLLs has any positive or negative effect, * always activate both. */ - ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf); if (ret < 0) return ret; @@ -1186,24 +1185,39 @@ static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo int ret; /* - * A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate - * signals of 1.25G and 3.125G for link speeds of 1G/2.5G. A high speed LC PLL can - * additionally generate a 10.3125G signal for 10G speeds. To drive the pair at different - * speeds each SerDes must use its own PLL. But what if the SerDess attached to the ring - * PLL suddenly needs 10G but the LC PLL is running at 1G? To avoid reconfiguring the - * "partner" SerDes we must choose wisely what assignment serves the current needs. The - * logic boils down to the following rules: + * A SerDes pair on RTL93xx is driven by a shared CMU with two PLLs: * - * - Use ring PLL for slow 1G speeds - * - Use LC PLL for fast 10G speeds - * - For 2.5G prefer ring over LC PLL + * - a low speed ring PLL which can generate signals of 1.25G and 3.125G for link + * speeds of 1G/2.5G + * - a high speed LC PLL which can additionally generate a 10.3125G signal for + * 10G link speeds * - * However, when we want to configure 10G speed while the other SerDes is already using - * the LC PLL for a slower speed, there is no way to avoid reconfiguration. Note that - * this can even happen when the other SerDes is not actually in use, because changing - * the state of a SerDes back to RTL930X_SDS_OFF is not (yet) implemented. + * To drive the pair at different speeds, each SerDes must use its own PLL and we + * must wisely assign the PLLs to the SerDes based on their needs. The logic boils + * down to the following rules: + * + * - use ring PLL for slow 1G speeds + * - use LC PLL for fast 10G speeds + * - for 2.5G prefer ring over LC PLL + * + * For the case that we want to configure 10G speed but the LC PLL is already used + * by the neighbor SerDes and running with a slower speed, there's no way to avoid + * reconfiguration. The neighbor SerDes is reconfigured online to the ring PLL. */ + if (hw_mode == RTPCS_SDS_MODE_OFF) + return 0; + + ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); + if (ret < 0) + return ret; + + if (nb_sds->hw_mode == RTPCS_SDS_MODE_OFF) { + pll = (speed == RTPCS_SDS_PLL_SPD_10000) ? RTPCS_SDS_PLL_TYPE_LC + : RTPCS_SDS_PLL_TYPE_RING; + goto pll_setup; + } + ret = nb_sds->ops->get_pll_select(nb_sds, &neighbor_pll); if (ret < 0) return ret; @@ -1212,14 +1226,7 @@ static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo if (ret < 0) return ret; - ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); - if (ret < 0) - return ret; - - if (nb_sds->hw_mode == RTPCS_SDS_MODE_OFF) - pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC - : RTPCS_SDS_PLL_TYPE_RING; - else if (speed == neighbor_speed) { + if (speed == neighbor_speed) { speed_changed = false; pll = neighbor_pll; } else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING) @@ -1227,6 +1234,7 @@ static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo else if (speed == RTPCS_SDS_PLL_SPD_10000) { pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n", __func__, sds->id, nb_sds->id); + ret = nb_sds->ops->reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING); if (ret < 0) return ret; @@ -1235,8 +1243,12 @@ static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo } else pll = RTPCS_SDS_PLL_TYPE_RING; - if (speed_changed) +pll_setup: + if (speed_changed) { ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; + } ret = sds->ops->set_pll_select(sds, hw_mode, pll); if (ret < 0) @@ -1244,7 +1256,6 @@ static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id, pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode); - return ret; } From 7a1e66e7f1d07a4a5dae7e9f009fcb1b1c1e72e4 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 24 Feb 2026 22:00:43 +0000 Subject: [PATCH 39/88] realtek: pcs: rtl931x: improve CMU page mapping Improve the RTL931x mapper to infer the CMU page from the hardware mode by replace unneeded with useful comments, returning a better error code and dropping irrelevant parts. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 29 ++++++++++--------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 198794f1fe..f93715a46d 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -3427,21 +3427,24 @@ static int rtpcs_931x_sds_cmu_page_get(enum rtpcs_sds_mode hw_mode) { switch (hw_mode) { case RTPCS_SDS_MODE_SGMII: - case RTPCS_SDS_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */ - return 0x24; - case RTPCS_SDS_MODE_2500BASEX: /* MII_2500Base_X: */ - return 0x28; -/* case MII_HISGMII_5G: */ -/* return 0x2a; */ + case RTPCS_SDS_MODE_1000BASEX: + return 0x24; /* ANA_1G */ + case RTPCS_SDS_MODE_2500BASEX: + return 0x28; /* ANA_3G */ case RTPCS_SDS_MODE_QSGMII: - return 0x2a; /* Code also has 0x34 */ -/* case MII_RXAUI_LITE: */ -/* return 0x2c; */ - case RTPCS_SDS_MODE_XSGMII: /* MII_XSGMII */ - case RTPCS_SDS_MODE_10GBASER: /* MII_10GR */ - return 0x2e; + return 0x2a; /* ANA_5G/6G */ + // return 0x34; + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: + case RTPCS_SDS_MODE_USXGMII_10GDXGMII: + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_USXGMII_5GSXGMII: + case RTPCS_SDS_MODE_USXGMII_5GDXGMII: + case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: + case RTPCS_SDS_MODE_10GBASER: + return 0x2e; /* ANA_10G */ default: - return -EINVAL; + return -ENOTSUPP; } } From 3f17f15bd5aefed934bfbd71e3a9933eb39f2588 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Fri, 27 Feb 2026 08:59:00 +0000 Subject: [PATCH 40/88] realtek: pcs: rtl931x: use generic CMU configuration The current CMU setup was just copied and slightly adjusted from the SDK, lacks functionality and logic and doesn't cover all cases we need (same in the SDK due to multiple reasons). The existing implementation for RTL930x covers all that and can be reused for RTL931x. Previous patches made this generic and now we can add the remaining missing pieces to actually use it for RTL931x. This only includes implementations for the few variant-specific actions within the implementation, linking them properly and calling the CMU configuration. Drop the old CMU code for RTL931x then since it's not needed anymore. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 158 +++++++++--------- 1 file changed, 79 insertions(+), 79 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index f93715a46d..41809982bc 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -3448,95 +3448,92 @@ static int rtpcs_931x_sds_cmu_page_get(enum rtpcs_sds_mode hw_mode) } } -static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) +static int rtpcs_931x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll) +{ + int cmu_page, pll_sel; + + cmu_page = rtpcs_931x_sds_cmu_page_get(sds->hw_mode); + if (cmu_page < 0) + return cmu_page; + + pll_sel = rtpcs_sds_read_bits(sds, cmu_page, 0x7, 15, 15); + if (pll_sel < 0) + return pll_sel; + + *pll = (enum rtpcs_sds_pll_type)pll_sel; + return 0; +} + +static int rtpcs_931x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode, + enum rtpcs_sds_pll_type pll) { struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds); - u32 force_lc_mode_bit, force_lc_mode_val_bit; - enum rtpcs_sds_pll_type pll_type; /* SDK calls this cmu_type */ - bool force_pll_spd; - int cmu_page = 0; - - switch (hw_mode) { - case RTPCS_SDS_MODE_OFF: - case RTPCS_SDS_MODE_XSGMII: - case RTPCS_SDS_MODE_10GBASER: - case RTPCS_SDS_MODE_USXGMII_10GSXGMII: - case RTPCS_SDS_MODE_USXGMII_10GDXGMII: - case RTPCS_SDS_MODE_USXGMII_10GQXGMII: - case RTPCS_SDS_MODE_USXGMII_5GSXGMII: - case RTPCS_SDS_MODE_USXGMII_5GDXGMII: - case RTPCS_SDS_MODE_USXGMII_2_5GSXGMII: - return 0; - - case RTPCS_SDS_MODE_QSGMII: - pll_type = RTPCS_SDS_PLL_TYPE_RING; - force_pll_spd = false; - break; - - case RTPCS_SDS_MODE_1000BASEX: - pll_type = RTPCS_SDS_PLL_TYPE_RING; - force_pll_spd = false; - break; - -/* case MII_1000BX100BX_AUTO: - pll_type = RTPCS_SDS_PLL_TYPE_RING; - force_pll_spd = false; - break; */ - - case RTPCS_SDS_MODE_SGMII: - pll_type = RTPCS_SDS_PLL_TYPE_RING; - force_pll_spd = false; - break; - - case RTPCS_SDS_MODE_2500BASEX: - pll_type = RTPCS_SDS_PLL_TYPE_RING; - force_pll_spd = true; - break; - - default: - pr_info("SerDes %d mode is invalid\n", sds->id); - return -EINVAL; - } + int cmu_page, ret, val; + int frc_lc_mode_bit; cmu_page = rtpcs_931x_sds_cmu_page_get(hw_mode); if (cmu_page < 0) - return -EINVAL; + return cmu_page; - if (sds == even_sds) { - force_lc_mode_bit = 4; - force_lc_mode_val_bit = 5; - } else { - force_lc_mode_bit = 6; - force_lc_mode_val_bit = 7; - } + /* + * bits [5:4] (even) / [7:6] (odd) are used by RTL930x as selector. The selector + * for RTL931x SerDes is in the CMU page of each SerDes, depending on the hardware + * mode. + * + * Here, the SDK calls them 'frc_lc_mode' and 'frc_lc_mode_val'. However, they don't + * seem to have any effect and thus their purpose is unknown. So just set them as + * the SDK does. + */ + val = (pll == RTPCS_SDS_PLL_TYPE_LC) ? 0x3 : 0x1; + frc_lc_mode_bit = (sds == even_sds) ? 4 : 6; + ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, frc_lc_mode_bit + 1, + frc_lc_mode_bit, val); + if (ret < 0) + return ret; - pr_info("%s: pll_type %s cmu_page %x force_pll_spd %d even_sds %d sds %d\n", - __func__, pll_type == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", cmu_page, - force_pll_spd, even_sds->id, sds->id); + return rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, pll); +} - if (pll_type == RTPCS_SDS_PLL_TYPE_RING) { - rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x0); +static int rtpcs_931x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll) +{ + enum rtpcs_sds_pll_type tmp_pll; + enum rtpcs_sds_pll_speed speed; + enum rtpcs_sds_mode tmp_mode; + int ret; - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 2, 0x3); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_bit, - force_lc_mode_bit, 0x1); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_val_bit, - force_lc_mode_val_bit, 0x0); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 12, 12, 0x1); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, force_pll_spd ? 0x1 : 0x0); - } else if (pll_type == RTPCS_SDS_PLL_TYPE_LC) { - rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x1); + /* assume we always reconfigure to the other PLL */ + tmp_pll = (pll == RTPCS_SDS_PLL_TYPE_LC) ? RTPCS_SDS_PLL_TYPE_RING : RTPCS_SDS_PLL_TYPE_LC; - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 1, 0, 0x3); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_bit, - force_lc_mode_bit, 0x1); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_val_bit, - force_lc_mode_val_bit, 0x1); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 8, 8, 0x1); - rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 11, 9, force_pll_spd ? 0x1 : 0x0); - } + ret = rtpcs_93xx_sds_get_pll_config(sds, tmp_pll, &speed); + if (ret < 0) + return ret; - return 0; + tmp_mode = sds->hw_mode; + + /* turn off SerDes for reconfiguration */ + ret = rtpcs_931x_sds_power(sds, false); + if (ret < 0) + return ret; + + ret = rtpcs_931x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF); + if (ret < 0) + return ret; + + /* reconfigure to other PLL */ + ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed); + if (ret < 0) + return ret; + + ret = rtpcs_931x_sds_set_pll_select(sds, sds->hw_mode, pll); + if (ret < 0) + return ret; + + /* turn on SerDes again */ + ret = rtpcs_931x_sds_set_mode(sds, tmp_mode); + if (ret < 0) + return ret; + + return rtpcs_931x_sds_power(sds, true); } static int rtpcs_931x_sds_cmu_band_set(struct rtpcs_serdes *sds, @@ -3865,7 +3862,7 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds, if (ret < 0) return ret; - ret = rtpcs_931x_sds_config_cmu(sds, hw_mode); + ret = rtpcs_93xx_sds_config_cmu(sds, hw_mode); if (ret < 0) return ret; @@ -4350,6 +4347,9 @@ static const struct rtpcs_serdes_ops rtpcs_931x_sds_ops = { .xsg_write = rtpcs_931x_sds_op_xsg_write, .set_autoneg = rtpcs_93xx_sds_set_autoneg, .restart_autoneg = rtpcs_generic_sds_restart_autoneg, + .get_pll_select = rtpcs_931x_sds_get_pll_select, + .set_pll_select = rtpcs_931x_sds_set_pll_select, + .reconfigure_to_pll = rtpcs_931x_sds_reconfigure_to_pll, }; static const struct rtpcs_sds_regs rtpcs_931x_sds_regs = { From 3c3e56afca1e2b2c3e0c091da77bc9774c788ae3 Mon Sep 17 00:00:00 2001 From: Fabrice Fontaine Date: Fri, 13 Mar 2026 20:57:11 +0100 Subject: [PATCH 41/88] tools/expat: fix PKG_CPE_ID cpe:/a:libexpat_project:libexpat is the correct CPE ID for expat: https://nvd.nist.gov/products/cpe/search/results?keyword=cpe:2.3:a:libexpat_project:libexpat Fixes: ff59f3f4bdb56c779579aaa11b815f4c83abbac5 (tools/expat: fix PKG_CPE_ID) Signed-off-by: Fabrice Fontaine Link: https://github.com/openwrt/openwrt/pull/22406 Signed-off-by: Hauke Mehrtens --- tools/expat/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/expat/Makefile b/tools/expat/Makefile index 37d3d113b9..7ad86b08f9 100644 --- a/tools/expat/Makefile +++ b/tools/expat/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=expat -PKG_CPE_ID:=cpe:/a:libexpat:libexpat +PKG_CPE_ID:=cpe:/a:libexpat_project:libexpat PKG_VERSION:=2.7.4 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz From f2699cce13fdfb7fac57aad4a59bcd0c63b77014 Mon Sep 17 00:00:00 2001 From: Semih Baskan Date: Wed, 11 Mar 2026 18:05:57 +0300 Subject: [PATCH 42/88] mediatek: filogic: tplink-be450: fix RTL8261N reset timing, add missing WLAN button, fix memory size - Fix RTL8261N 10GbE PHY `reset-deassert-us` from 100ms to 221ms to meet datasheet minimum SMI-ready timing (t7 >= 150ms), fixing intermittent boot stalls caused by MDIO bus instability - Add missing WLAN toggle button (GPIO 34) present in stock firmware but absent from OpenWrt DTS - Fix memory size from 1 GB to the actual 512 MB Fix 1: The RTL8261N 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us), but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a minimum **SMI-ready time of 150ms** after nRESET release before the MDIO (SMI) bus can be used. With only 100ms, the kernel attempts MDIO bus access before the RTL8261N's SMI interface is stable. Since the RTL8261N (mdio-bus:00) and the internal MT7988 2.5GbE PHY (mdio-bus:0f) share the same MDIO bus, a not-yet-ready RTL8261N disrupts all MDIO traffic, causing the 2.5GbE PHY firmware loading (`mt798x_2p5ge_phy_config_init`) to stall. Observed symptoms on warm reboot: - Sometimes `mt798x_2p5ge_phy_config_init` hangs for 5+ minutes or indefinitely - RCU CPU stalls (`rcu: INFO: rcu_sched detected stalls on CPUs`) - mt7996e WiFi chip message timeouts cascading to `chip full reset failed` - System appears hung with only power LED blinking slowly UART serial log evidence (warm reboot with 100ms): ``` [ 73.041756] rcu: INFO: rcu_sched self-detected stall on CPU [ 73.048341] rcu: 2-....: (8 ticks this GP) [ 73.061641] pc : mt798x_2p5ge_phy_config_init+0x258/0xbb0 [ 73.061653] lr : mt798x_2p5ge_phy_config_init+0x238/0xbb0 ... [ 334.771280] MediaTek MT7988 2.5GbE PHY mdio-bus:0f: Firmware date code: 2024/10/30 ``` The 2.5GbE PHY firmware loading, which normally takes ~3 seconds, took **325 seconds** due to MDIO bus instability. In the worst case, the system never recovers. GPL DTS uses 221ms (`reset-deassert-us = <221000>`), providing 71ms of margin above the 150ms datasheet minimum. All MediaTek MT7988 reference board DTS files in the GPL use this same 221ms value. Fix 2: Missing WLAN button (GPIO 34) The BE450 has a physical WLAN toggle button on GPIO 34, defined in the stock TP-Link GPL DTS but missing from the OpenWrt DTS. Without this definition, the button is non-functional under OpenWrt. The pin name for GPIO 34 in the MT7988 pinctrl is `SPI2_MISO`, confirmed by the kernel pinctrl driver (`pinctrl-mt7988.c`: `MT7988_PIN(34, "SPI2_MISO")`) and the official devicetree binding (`mediatek,mt7988-pinctrl.yaml`). Note: GPIO 34 is also used by the BE450's First U-Boot as a recovery button (web recovery 192.168.1.1). Registering it in the DTS ensures the kernel claims the pin. Fix 3: Incorrect memory size in DTS The OpenWrt DTS declares 1 GB (`0x40000000`) of RAM, but the BE450 has 512 MB (`0x20000000`). Run tested. Signed-off-by: Semih Baskan Link: https://github.com/openwrt/openwrt/pull/22386 Signed-off-by: Hauke Mehrtens --- .../mediatek/dts/mt7988d-tplink-be450.dts | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target/linux/mediatek/dts/mt7988d-tplink-be450.dts b/target/linux/mediatek/dts/mt7988d-tplink-be450.dts index c594f81db1..d40f70e941 100644 --- a/target/linux/mediatek/dts/mt7988d-tplink-be450.dts +++ b/target/linux/mediatek/dts/mt7988d-tplink-be450.dts @@ -27,7 +27,7 @@ }; memory@40000000 { - reg = <0x0 0x40000000 0x0 0x40000000>; + reg = <0x0 0x40000000 0x0 0x20000000>; device_type = "memory"; }; @@ -69,6 +69,12 @@ linux,code = ; gpios = <&pio 14 GPIO_ACTIVE_LOW>; }; + + wifi { + label = "wlan"; + linux,code = ; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + }; }; gpio-leds { @@ -121,7 +127,7 @@ gpios = <&pio 68 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_USB; - }; + }; }; }; @@ -148,7 +154,6 @@ spi_nand: spi_nand@0 { compatible = "spi-nand"; - reg = <0>; spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; @@ -156,7 +161,7 @@ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; spi-cal-datalen = <7>; spi-cal-enable; - spi-cal-mode = "read-data"; + spi-cal-mode = "read-data"; spi-max-frequency = <52000000>; spi-rx-bus-width = <4>; @@ -240,7 +245,7 @@ reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>; reset-assert-us = <100000>; - reset-deassert-us = <100000>; + reset-deassert-us = <221000>; }; }; @@ -323,8 +328,8 @@ &pio { button_pins: button-pins { - pins = "GPIO_RESET", "GPIO_WPS"; - bias-disable; /* bias-disable */ + pins = "GPIO_RESET", "GPIO_WPS", "SPI2_MISO"; + bias-disable; }; mdio0_pins: mdio0-pins { @@ -361,11 +366,11 @@ }; enable-usb-power { - gpio-hog; - gpios = <32 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "USB power"; - }; + gpio-hog; + gpios = <32 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "USB power"; + }; }; &ssusb1 { From 65f2b060a3ad990bfcc6d2b7db4e5e023d50e483 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 12 Jun 2024 13:57:58 -0700 Subject: [PATCH 43/88] ramips: h3x,tx180x: use nvmem for uboot-env Removes deprecated userspace handling. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/14182 Signed-off-by: Robert Marko --- target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi | 18 ++++++++++++++++++ .../mt7621/base-files/etc/board.d/02_network | 7 ------- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi index 1520aaf5b1..31347723cf 100644 --- a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi +++ b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi @@ -8,6 +8,7 @@ / { aliases { + label-mac-device = &gmac1; led-boot = &led_status_amber; led-failsafe = &led_status_green; led-running = &led_status_green; @@ -52,10 +53,18 @@ }; }; +&gmac0 { + nvmem-cells = <&macaddr_uboot_ethaddr 1>; + nvmem-cell-names = "mac-address"; +}; + &gmac1 { status = "okay"; label = "wan"; phy-handle = <ðphy4>; + + nvmem-cells = <&macaddr_uboot_ethaddr 0>; + nvmem-cell-names = "mac-address"; }; ðphy4 { @@ -84,6 +93,15 @@ partition@80000 { label = "u-boot-env"; reg = <0x0080000 0x0080000>; + + nvmem-layout { + compatible = "u-boot,env"; + env-size = <0x20000>; + + macaddr_uboot_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + }; }; partition@100000 { diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 18e979df61..493811893b 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -270,13 +270,6 @@ ramips_setup_macs() wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) label_mac=$wan_mac ;; - h3c,tx1800-plus|\ - h3c,tx1801-plus|\ - h3c,tx1806) - label_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) - lan_mac=$(macaddr_add "$label_mac" 1) - wan_mac=$label_mac - ;; iodata,wnpr2600g) wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) label_mac=$wan_mac From 8dd95cc6b532af599a2ad0b92b3a53371832a3a4 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 12 Jun 2024 14:03:49 -0700 Subject: [PATCH 44/88] ramips: iptime,t5004: use nvmem for ubootenv Userspace handling is deprecated. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/14182 Signed-off-by: Robert Marko --- target/linux/ramips/dts/mt7621_iptime_t5004.dts | 17 +++++++++++++++++ .../mt7621/base-files/etc/board.d/02_network | 4 ---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_iptime_t5004.dts b/target/linux/ramips/dts/mt7621_iptime_t5004.dts index 4a7f9aaaa1..19c72884b4 100644 --- a/target/linux/ramips/dts/mt7621_iptime_t5004.dts +++ b/target/linux/ramips/dts/mt7621_iptime_t5004.dts @@ -55,6 +55,15 @@ partition@80000 { label = "u-boot-env"; reg = <0x80000 0xc0000>; + + nvmem-layout { + compatible = "u-boot,env"; + env-size = <0x1000>; + + macaddr_uboot_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; + }; }; partition@140000 { @@ -85,10 +94,18 @@ }; }; +&gmac0 { + nvmem-cells = <&macaddr_uboot_ethaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &gmac1 { status = "okay"; label = "wan"; phy-handle = <ðphy0>; + + nvmem-cells = <&macaddr_uboot_ethaddr 1>; + nvmem-cell-names = "mac-address"; }; ðphy0 { diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 493811893b..c6e440b8e9 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -274,10 +274,6 @@ ramips_setup_macs() wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) label_mac=$wan_mac ;; - iptime,t5004) - lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ;; jdcloud,re-sp-01b) lan_mac=$(mtd_get_mac_ascii config mac) wan_mac=$lan_mac From d7178cdd6ea5badfdce8686b27fd6a3ab575a9cd Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 16 Jun 2024 16:25:24 -0700 Subject: [PATCH 45/88] ramips: edimax,rx21s: use nvmem for ethaddr Userspace handling is deprecated. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/14182 Signed-off-by: Robert Marko --- .../linux/ramips/dts/mt7621_edimax_rx21s.dtsi | 19 +++++++++++++++++++ .../mt7621/base-files/etc/board.d/02_network | 1 - 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi index 8e7652cac7..3a235070bf 100644 --- a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi +++ b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi @@ -78,6 +78,13 @@ label = "u-boot-env"; reg = <0x30000 0x10000>; read-only; + + nvmem-layout { + compatible = "u-boot,env"; + + macaddr_uboot_ethaddr: ethaddr { + }; + }; }; partition@40000 { @@ -160,21 +167,33 @@ port@1 { status = "okay"; label = "lan4"; + + nvmem-cells = <&macaddr_uboot_ethaddr>; + nvmem-cell-names = "mac-address"; }; port@2 { status = "okay"; label = "lan3"; + + nvmem-cells = <&macaddr_uboot_ethaddr>; + nvmem-cell-names = "mac-address"; }; port@3 { status = "okay"; label = "lan2"; + + nvmem-cells = <&macaddr_uboot_ethaddr>; + nvmem-cell-names = "mac-address"; }; port@4 { status = "okay"; label = "lan1"; + + nvmem-cells = <&macaddr_uboot_ethaddr>; + nvmem-cell-names = "mac-address"; }; }; }; diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index c6e440b8e9..c16196e1c0 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -261,7 +261,6 @@ ramips_setup_macs() ;; edimax,ra21s|\ edimax,rg21s) - lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) ;; elecom,wrc-2533ghbk2-t|\ From beca714ce5d69494038b6d7d034a3265400312fe Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 10 Mar 2026 22:14:32 -0700 Subject: [PATCH 46/88] ramips: elecom,wrc-2533ghbk: use nvmem for mac addresses Userspace handling is deprecated. Since the u-boot ethaddr variable is quoted, we cannot use it. Use mac-base instead to specify in dts. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/14182 Signed-off-by: Robert Marko --- .../ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi | 15 +++++++++++++++ .../mt7621/base-files/etc/board.d/02_network | 6 ------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi index cdb94dcdc1..545a2031b8 100644 --- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi +++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi @@ -12,6 +12,7 @@ led-failsafe = &led_power; led-running = &led_power; led-upgrade = &led_power; + label-mac-device = &gmac1; }; leds { @@ -109,6 +110,12 @@ reg = <0x0 0x4da8>; }; + macaddr_factory_4: mac-address@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + eeprom_factory_8000: eeprom@8000 { reg = <0x8000 0x4da8>; }; @@ -118,10 +125,18 @@ }; }; +&gmac0 { + nvmem-cells = <&eeprom_factory_0 (-1)>; + nvmem-cell-names = "mac-address"; +}; + &gmac1 { status = "okay"; label = "wan"; phy-handle = <ðphy0>; + + nvmem-cells = <&eeprom_factory_0 (-2)>; + nvmem-cell-names = "mac-address"; }; ðphy0 { diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index c16196e1c0..25a8beecfe 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -263,12 +263,6 @@ ramips_setup_macs() edimax,rg21s) wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) ;; - elecom,wrc-2533ghbk2-t|\ - elecom,wrc-2533ghbk-i) - lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) - wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) - label_mac=$wan_mac - ;; iodata,wnpr2600g) wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr) label_mac=$wan_mac From 53f477f03431b917c99d7cec6d31698a39388b03 Mon Sep 17 00:00:00 2001 From: Kenneth Kasilag Date: Fri, 13 Mar 2026 10:32:19 +0000 Subject: [PATCH 47/88] airoha: automatically refresh patches CI is currently failing due to these four patches. Automatically refreshed with `make target/linux/refresh`. Signed-off-by: Kenneth Kasilag Link: https://github.com/openwrt/openwrt/pull/22399 Signed-off-by: Robert Marko --- ...3-pinctrl-airoha-Add-support-for-EN7581-SoC.patch | 2 +- ...net-phy-add-PHY_DETACH_NO_HW_RESET-PHY-flag.patch | 2 +- ...7.0-net-airoha-npu-Init-BA-memory-region-if.patch | 4 +--- ...a-npu-Add-the-capability-to-read-firmware-n.patch | 12 +++++------- 4 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/linux/airoha/patches-6.12/034-01-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch b/target/linux/airoha/patches-6.12/034-01-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch index 1bb0f61062..ceb58a1b00 100644 --- a/target/linux/airoha/patches-6.12/034-01-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch +++ b/target/linux/airoha/patches-6.12/034-01-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch @@ -29,7 +29,7 @@ Signed-off-by: Linus Walleij --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18198,6 +18198,13 @@ F: drivers/pinctrl/ +@@ -18204,6 +18204,13 @@ F: drivers/pinctrl/ F: include/dt-bindings/pinctrl/ F: include/linux/pinctrl/ diff --git a/target/linux/airoha/patches-6.12/801-01-net-phy-add-PHY_DETACH_NO_HW_RESET-PHY-flag.patch b/target/linux/airoha/patches-6.12/801-01-net-phy-add-PHY_DETACH_NO_HW_RESET-PHY-flag.patch index 5a4533378b..0c273f000f 100644 --- a/target/linux/airoha/patches-6.12/801-01-net-phy-add-PHY_DETACH_NO_HW_RESET-PHY-flag.patch +++ b/target/linux/airoha/patches-6.12/801-01-net-phy-add-PHY_DETACH_NO_HW_RESET-PHY-flag.patch @@ -107,7 +107,7 @@ Signed-off-by: Christian Marangi module_phy_driver(as21xxx_drivers); --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -2074,7 +2074,8 @@ void phy_detach(struct phy_device *phyde +@@ -2069,7 +2069,8 @@ void phy_detach(struct phy_device *phyde device_release_driver(&phydev->mdio.dev); /* Assert the reset signal */ diff --git a/target/linux/airoha/patches-6.12/910-01-v7.0-net-airoha-npu-Init-BA-memory-region-if.patch b/target/linux/airoha/patches-6.12/910-01-v7.0-net-airoha-npu-Init-BA-memory-region-if.patch index 793229e162..9283e18de6 100644 --- a/target/linux/airoha/patches-6.12/910-01-v7.0-net-airoha-npu-Init-BA-memory-region-if.patch +++ b/target/linux/airoha/patches-6.12/910-01-v7.0-net-airoha-npu-Init-BA-memory-region-if.patch @@ -13,11 +13,9 @@ Signed-off-by: Jakub Kicinski drivers/net/ethernet/airoha/airoha_npu.c | 8 ++++++++ 1 file changed, 8 insertions(+) -diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c -index 22f72c14606599..a56b3780bb627c 100644 --- a/drivers/net/ethernet/airoha/airoha_npu.c +++ b/drivers/net/ethernet/airoha/airoha_npu.c -@@ -519,6 +519,14 @@ static int airoha_npu_wlan_init_memory(struct airoha_npu *npu) +@@ -519,6 +519,14 @@ static int airoha_npu_wlan_init_memory(s if (err) return err; diff --git a/target/linux/airoha/patches-6.12/910-02-v7.0-net-airoha-npu-Add-the-capability-to-read-firmware-n.patch b/target/linux/airoha/patches-6.12/910-02-v7.0-net-airoha-npu-Add-the-capability-to-read-firmware-n.patch index b626840ee6..e5586b7f1b 100644 --- a/target/linux/airoha/patches-6.12/910-02-v7.0-net-airoha-npu-Add-the-capability-to-read-firmware-n.patch +++ b/target/linux/airoha/patches-6.12/910-02-v7.0-net-airoha-npu-Add-the-capability-to-read-firmware-n.patch @@ -20,8 +20,6 @@ Signed-off-by: Jakub Kicinski drivers/net/ethernet/airoha/airoha_npu.c | 46 ++++++++++++++++++++---- 1 file changed, 40 insertions(+), 6 deletions(-) -diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c -index a56b3780bb627c..89f22f3f47dc56 100644 --- a/drivers/net/ethernet/airoha/airoha_npu.c +++ b/drivers/net/ethernet/airoha/airoha_npu.c @@ -16,6 +16,8 @@ @@ -33,7 +31,7 @@ index a56b3780bb627c..89f22f3f47dc56 100644 #define NPU_AN7583_FIRMWARE_DATA "airoha/an7583_npu_data.bin" #define NPU_AN7583_FIRMWARE_RV32 "airoha/an7583_npu_rv32.bin" #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000 -@@ -195,18 +197,18 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id, +@@ -195,18 +197,18 @@ static int airoha_npu_send_msg(struct ai } static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr, @@ -56,7 +54,7 @@ index a56b3780bb627c..89f22f3f47dc56 100644 ret = -E2BIG; goto out; } -@@ -218,6 +220,28 @@ static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr, +@@ -218,6 +220,28 @@ out: return ret; } @@ -83,9 +81,9 @@ index a56b3780bb627c..89f22f3f47dc56 100644 +} + static int airoha_npu_run_firmware(struct device *dev, void __iomem *base, - struct resource *res) + struct reserved_mem *rmem) { -@@ -233,14 +257,22 @@ static int airoha_npu_run_firmware(struct device *dev, void __iomem *base, +@@ -233,14 +257,22 @@ static int airoha_npu_run_firmware(struc if (IS_ERR(addr)) return PTR_ERR(addr); @@ -110,7 +108,7 @@ index a56b3780bb627c..89f22f3f47dc56 100644 } static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance) -@@ -790,6 +822,8 @@ module_platform_driver(airoha_npu_driver); +@@ -791,6 +823,8 @@ module_platform_driver(airoha_npu_driver MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA); MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32); From d755c49f7a8a2bf33527a6aa6c4aa52c5c7c1324 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 14 May 2025 11:47:23 -0500 Subject: [PATCH 48/88] qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible Originally, the .compatible string for EAP623-Outdoor HD tried to shorten the "-outdoor" to "od". However, this naming was inconsistent with the existing "eap610-outdoor". As "od" is not a common shorthand, spell out the complete word: "eap623-outdoor-hd-v1". Fixes: 5dbf93c8c5 ("ipq60xx: add support for TP-Link EAP623-Outdoor HD v1") Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18804 Signed-off-by: Robert Marko --- .../uboot-tools/uboot-envtools/files/qualcommax_ipq60xx | 8 +++++++- .../arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts} | 2 +- target/linux/qualcommax/image/ipq60xx.mk | 4 ++-- .../qualcommax/ipq60xx/base-files/etc/board.d/02_network | 4 ++-- .../base-files/etc/hotplug.d/firmware/11-ath11k-caldata | 2 +- .../ipq60xx/base-files/lib/preinit/09_mount_factory_data | 2 +- .../qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh | 2 +- 7 files changed, 15 insertions(+), 9 deletions(-) rename target/linux/qualcommax/{dts/ipq6018-eap623od-hd-v1.dts => files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts} (97%) diff --git a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx index 14e8950feb..f7eb07147f 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx +++ b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx @@ -7,6 +7,12 @@ touch /etc/config/ubootenv board=$(board_name) +ubootenv_add_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" +} + case "$board" in 8devices,mango-dvk|\ 8devices,mango-dvk-sfp|\ @@ -25,7 +31,7 @@ netgear,wax214|\ netgear,wax610|\ netgear,wax610y|\ tplink,eap610-outdoor|\ -tplink,eap623od-hd-v1|\ +tplink,eap623-outdoor-hd-v1|\ tplink,eap620-hd-v3|\ tplink,eap625-outdoor-hd-v1) ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000" diff --git a/target/linux/qualcommax/dts/ipq6018-eap623od-hd-v1.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts similarity index 97% rename from target/linux/qualcommax/dts/ipq6018-eap623od-hd-v1.dts rename to target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts index f54593a08b..3aaa32e827 100644 --- a/target/linux/qualcommax/dts/ipq6018-eap623od-hd-v1.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts @@ -12,7 +12,7 @@ / { model = "TP-Link EAP623-Outdoor HD V1.0"; - compatible = "tplink,eap623od-hd-v1", "qcom,ipq6018"; + compatible = "tplink,eap623-outdoor-hd-v1", "qcom,ipq6018"; aliases { serial0 = &blsp1_uart3; diff --git a/target/linux/qualcommax/image/ipq60xx.mk b/target/linux/qualcommax/image/ipq60xx.mk index bef95ecd4c..5319dfc00f 100644 --- a/target/linux/qualcommax/image/ipq60xx.mk +++ b/target/linux/qualcommax/image/ipq60xx.mk @@ -252,7 +252,7 @@ define Device/tplink_eap610-outdoor endef TARGET_DEVICES += tplink_eap610-outdoor -define Device/tplink_eap623od-hd-v1 +define Device/tplink_eap623-outdoor-hd-v1 $(call Device/FitImage) $(call Device/UbiFit) DEVICE_VENDOR := TP-Link @@ -266,7 +266,7 @@ define Device/tplink_eap623od-hd-v1 IMAGE/web-ui-factory.bin := append-ubi | tplink-image-2022 TPLINK_SUPPORT_STRING := SupportList:\r\nEAP623-Outdoor HD(TP-Link|UN|AX1800-D):1.0\r\n endef -TARGET_DEVICES += tplink_eap623od-hd-v1 +TARGET_DEVICES += tplink_eap623-outdoor-hd-v1 define Device/tplink_eap625-outdoor-hd-v1 $(call Device/FitImage) diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network index 67ac532602..558c68dacc 100644 --- a/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network +++ b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network @@ -41,8 +41,8 @@ ipq60xx_setup_interfaces() netgear,wax610|\ netgear,wax610y|\ tplink,eap610-outdoor|\ - tplink,eap623od-hd-v1|\ tplink,eap620-hd-v3|\ + tplink,eap623-outdoor-hd-v1|\ tplink,eap625-outdoor-hd-v1) ucidef_set_interface_lan "lan" "dhcp" ;; @@ -70,7 +70,7 @@ ipq60xx_setup_macs() ;; tplink,eap610-outdoor|\ tplink,eap620-hd-v3|\ - tplink,eap623od-hd-v1|\ + tplink,eap623-outdoor-hd-v1|\ tplink,eap625-outdoor-hd-v1) label_mac=$(get_mac_binary /tmp/factory_data/default-mac 0) lan_mac=$label_mac diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index 77587aeca4..14ab459e66 100644 --- a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -70,7 +70,7 @@ case "$FIRMWARE" in ath11k_set_macflag ;; tplink,eap610-outdoor|\ - tplink,eap623od-hd-v1|\ + tplink,eap623-outdoor-hd-v1|\ tplink,eap625-outdoor-hd-v1) caldata_from_file "/tmp/factory_data/radio" 0 0x10000 label_mac=$(get_mac_binary /tmp/factory_data/default-mac 0) diff --git a/target/linux/qualcommax/ipq60xx/base-files/lib/preinit/09_mount_factory_data b/target/linux/qualcommax/ipq60xx/base-files/lib/preinit/09_mount_factory_data index 09ca32f08c..fbd294f333 100644 --- a/target/linux/qualcommax/ipq60xx/base-files/lib/preinit/09_mount_factory_data +++ b/target/linux/qualcommax/ipq60xx/base-files/lib/preinit/09_mount_factory_data @@ -9,7 +9,7 @@ preinit_mount_factory_data() { case $(board_name) in tplink,eap610-outdoor|\ tplink,eap620-hd-v3|\ - tplink,eap623od-hd-v1|\ + tplink,eap623-outdoor-hd-v1|\ tplink,eap625-outdoor-hd-v1) mtd_path=$(find_mtd_chardev "factory_data") ubiattach --dev-path="$mtd_path" --devn=1 diff --git a/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh index 789f88c4bf..3cfd935431 100644 --- a/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh @@ -205,7 +205,7 @@ platform_do_upgrade() { ;; tplink,eap610-outdoor|\ tplink,eap620-hd-v3|\ - tplink,eap623od-hd-v1|\ + tplink,eap623-outdoor-hd-v1|\ tplink,eap625-outdoor-hd-v1) tplink_do_upgrade "$1" ;; From 38635ffd330713f3187d7633225b815d0570c6f5 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Thu, 15 May 2025 08:48:30 -0500 Subject: [PATCH 49/88] qualcommax: ipq60xx: eap6xx-outdoor: use yellow for LED color As I was looking at the differences between EAP610, 623, and 625 Outdoor, I realized that the quick-start guide of all of the devices mentions a yellow and green LED. Thus rename the "amber" led to "yellow", and adjust its color ID accordingly. Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18804 Signed-off-by: Robert Marko --- .../qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi b/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi index 0a551e73ca..cefdcde311 100644 --- a/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi +++ b/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi @@ -14,9 +14,9 @@ aliases { serial0 = &blsp1_uart3; led-boot = &led_sys_green; - led-failsafe = &led_sys_amber; + led-failsafe = &led_sys_yellow; led-running = &led_sys_green; - led-upgrade = &led_sys_amber; + led-upgrade = &led_sys_yellow; }; chosen { @@ -37,9 +37,9 @@ leds { compatible = "gpio-leds"; - led_sys_amber: led-0 { + led_sys_yellow: led-0 { function = "system"; - color = ; + color = ; gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; }; From e288cf24518471c0289ccc31a4122657e9767ab2 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 14 May 2025 12:49:26 -0500 Subject: [PATCH 50/88] qualcommax: ipq60xx: unify eap6xx device trees The EAP625 and EAP623 are extremely similar. The only difference in the vendor's device tree is that EAP625 also enables USB and UART2. Use the eap6xx dtsi instead of writing out a full devicetree. The EAP623 uses the same RTL8211F as the 625 and 610. Since this is a gigabit PHY, it is okay to change the ess mac mode from SGMII_PLUS to SGMII. This is now consistent across all three devices. Move the 'realtek,clkout-disable' and 'realtek,aldps-enable' PHY properties to the common dtsi, as they work well on all three devices. Reflect the remaining differences in the eap625 dts. Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18804 Signed-off-by: Robert Marko --- .../dts/ipq6018-tplink-eap6xx-outdoor.dtsi | 2 + .../dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts | 137 +----------------- 2 files changed, 6 insertions(+), 133 deletions(-) diff --git a/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi b/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi index cefdcde311..9ab252ef37 100644 --- a/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi +++ b/target/linux/qualcommax/dts/ipq6018-tplink-eap6xx-outdoor.dtsi @@ -115,6 +115,8 @@ rtl8211f_4: ethernet-phy@4 { reg = <4>; + realtek,clkout-disable; + realtek,aldps-enable; }; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts index 3aaa32e827..a474c2043f 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts @@ -3,145 +3,16 @@ /dts-v1/; -#include "ipq6018.dtsi" -#include "ipq6018-cp-cpu.dtsi" -#include "ipq6018-ess.dtsi" -#include -#include -#include +#include "ipq6018-tplink-eap6xx-outdoor.dtsi" / { model = "TP-Link EAP623-Outdoor HD V1.0"; compatible = "tplink,eap623-outdoor-hd-v1", "qcom,ipq6018"; - - aliases { - serial0 = &blsp1_uart3; - led-boot = &led_sys_green; - led-failsafe = &led_sys_yellow; - led-running = &led_sys_green; - led-upgrade = &led_sys_yellow; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs-append = " root=/dev/ubiblock0_1"; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_sys_green: led-0 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - }; - - led_sys_yellow: led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; - }; - }; }; -&blsp1_uart3 { - pinctrl-0 = <&serial_3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tlmm { - mdio_pins: mdio-pins { - mdc { - pins = "gpio64"; - function = "mdc"; - drive-strength = <8>; - bias-pull-up; - }; - - mdio { - pins = "gpio65"; - function = "mdio"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - phy_pins: phy-reset-pin { - pins = "gpio77"; - function = "gpio"; - bias-pull-up; - }; -}; - -&mdio { - status = "okay"; - reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; - reset-delay-us = <10000>; - reset-post-delay-us = <50000>; - pinctrl-0 = <&mdio_pins>, <&phy_pins>; - pinctrl-names = "default"; - - rtl8211f: ethernet-phy@4 { - reg = <4>; - - realtek,clkout-disable; - realtek,aldps-enable; - }; -}; - -&switch { - status = "okay"; - switch_lan_bmp = ; /* lan port bitmap */ - switch_mac_mode1 = ; /* mac mode for uniphy instance0*/ - - qcom,port_phyinfo { - port@5 { - port_id = <5>; - phy_address = <4>; - port_mac_sel = "QGMAC_PORT"; - }; - }; -}; - -&edma { - status = "okay"; -}; - -&dp5 { - status = "okay"; - phy-handle = <&rtl8211f>; - phy-mode = "sgmii"; - label = "lan"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; +&led_sys_yellow { + function = LED_FUNCTION_STATUS; + gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; }; &wifi { From 815200231514c5c6d83f9e497d230d34bd3ff2ac Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 14 May 2025 13:12:53 -0500 Subject: [PATCH 51/88] qualcommax: ipq60xx: unify common make rules for eap6xx The main difference between EAP610, 623, and 625 is the device name, support string, and the BDF package. Move the others to a common Device/tplink_eap6xx-common in order to highlight the common aspects. Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18804 Signed-off-by: Robert Marko --- target/linux/qualcommax/image/ipq60xx.mk | 36 +++++++++--------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/linux/qualcommax/image/ipq60xx.mk b/target/linux/qualcommax/image/ipq60xx.mk index 5319dfc00f..e56e404a8e 100644 --- a/target/linux/qualcommax/image/ipq60xx.mk +++ b/target/linux/qualcommax/image/ipq60xx.mk @@ -234,17 +234,22 @@ define Device/qihoo_360v6 endef TARGET_DEVICES += qihoo_360v6 -define Device/tplink_eap610-outdoor +define Device/tplink_eap6xx-common $(call Device/FitImage) $(call Device/UbiFit) DEVICE_VENDOR := TP-Link - DEVICE_MODEL := EAP610-Outdoor BLOCKSIZE := 128k PAGESIZE := 2048 SOC := ipq6018 - DEVICE_PACKAGES := ipq-wifi-tplink_eap610-outdoor + DEVICE_PACKAGES := kmod-phy-realtek IMAGES += web-ui-factory.bin IMAGE/web-ui-factory.bin := append-ubi | tplink-image-2022 +endef + +define Device/tplink_eap610-outdoor + $(call Device/tplink_eap6xx-common) + DEVICE_MODEL := EAP610-Outdoor + DEVICE_PACKAGES += ipq-wifi-tplink_eap610-outdoor TPLINK_SUPPORT_STRING := SupportList:\r\n \ EAP610-Outdoor(TP-Link|UN|AX1800-D):1.0\r\n \ EAP610-Outdoor(TP-Link|JP|AX1800-D):1.0\r\n \ @@ -253,32 +258,19 @@ endef TARGET_DEVICES += tplink_eap610-outdoor define Device/tplink_eap623-outdoor-hd-v1 - $(call Device/FitImage) - $(call Device/UbiFit) - DEVICE_VENDOR := TP-Link + $(call Device/tplink_eap6xx-common) DEVICE_MODEL := EAP623-Outdoor HD DEVICE_VARIANT := v1 - BLOCKSIZE := 128k - PAGESIZE := 2048 - SOC := ipq6018 - DEVICE_PACKAGES := ipq-wifi-tplink_eap623-outdoor-hd-v1 kmod-phy-realtek - IMAGES += web-ui-factory.bin - IMAGE/web-ui-factory.bin := append-ubi | tplink-image-2022 + DEVICE_PACKAGES += ipq-wifi-tplink_eap623-outdoor-hd-v1 TPLINK_SUPPORT_STRING := SupportList:\r\nEAP623-Outdoor HD(TP-Link|UN|AX1800-D):1.0\r\n endef TARGET_DEVICES += tplink_eap623-outdoor-hd-v1 define Device/tplink_eap625-outdoor-hd-v1 - $(call Device/FitImage) - $(call Device/UbiFit) - DEVICE_VENDOR := TP-Link - DEVICE_MODEL := EAP625-Outdoor HD v1 and v1.6 - BLOCKSIZE := 128k - PAGESIZE := 2048 - SOC := ipq6018 - DEVICE_PACKAGES := ipq-wifi-tplink_eap625-outdoor-hd-v1 - IMAGES += web-ui-factory.bin - IMAGE/web-ui-factory.bin := append-ubi | tplink-image-2022 + $(call Device/tplink_eap6xx-common) + DEVICE_MODEL := EAP625-Outdoor HD + DEVICE_VARIANT := v1 + DEVICE_PACKAGES += ipq-wifi-tplink_eap625-outdoor-hd-v1 TPLINK_SUPPORT_STRING := SupportList:\r\n \ EAP625-Outdoor HD(TP-Link|UN|AX1800-D):1.0\r\n \ EAP625-Outdoor HD(TP-Link|CA|AX1800-D):1.0\r\n \ From c23b9256f00bda5df0690a2569886c9148bf8fa6 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Mon, 9 Mar 2026 22:56:12 +0100 Subject: [PATCH 52/88] mediatek: replace patches with upstream version No functional changes intended. Signed-off-by: Aleksander Jan Bajkowski Link: https://github.com/openwrt/openwrt/pull/22350 Signed-off-by: Hauke Mehrtens --- ...k-mt7988-Add-xsphy-for-ssusb0-pcie2.patch} | 7 +- ...ediatek-mt7988a-bpi-r4-enable-xsphy.patch} | 4 +- ...-mediatek-mt7988-add-spi-controllers.patch | 112 --------------- ...-mediatek-mt7988-add-spi-controllers.patch | 69 +++++++++ ...move-uart0-and-spi1-pins-to-soc-dtsi.patch | 133 ------------------ ...ek-mt7988-move-uart0-and-spi1-pins-t.patch | 90 ++++++++++++ ...m64-dts-mediatek-mt7988-add-cci-node.patch | 128 ----------------- ...m64-dts-mediatek-mt7988-add-cci-node.patch | 86 +++++++++++ ...8-add-phy-calibration-efuse-subnodes.patch | 85 ----------- ...ek-mt7988-add-phy-calibration-efuse-.patch | 42 ++++++ ...7988a-bpi-r4-Add-fan-and-coolingmaps.patch | 98 ------------- ...ek-mt7988a-bpi-r4-Add-fan-and-coolin.patch | 59 ++++++++ ...k-mt7988a-bpi-r4-configure-spi-nodes.patch | 99 ------------- ...tek-mt7988a-bpi-r4-configure-spi-node.patc | 55 ++++++++ ...7988a-bpi-r4-add-proc-supply-for-cci.patch | 68 --------- ...ek-mt7988a-bpi-r4-add-proc-supply-fo.patch | 28 ++++ 16 files changed, 436 insertions(+), 727 deletions(-) rename target/linux/mediatek/patches-6.12/{171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch => 171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch} (89%) rename target/linux/mediatek/patches-6.12/{172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch => 172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch} (82%) delete mode 100644 target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch create mode 100644 target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch delete mode 100644 target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch create mode 100644 target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch delete mode 100644 target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch create mode 100644 target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch delete mode 100644 target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch create mode 100644 target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch delete mode 100644 target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch create mode 100644 target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch delete mode 100644 target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch create mode 100644 target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc delete mode 100644 target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch create mode 100644 target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch diff --git a/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch b/target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch similarity index 89% rename from target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch rename to target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch index fac060ef16..18f1ddc5bf 100644 --- a/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch +++ b/target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch @@ -1,14 +1,15 @@ -From 1861c63ba7bb7f8a5145d4ceabcf346f274da61f Mon Sep 17 00:00:00 2001 +From 2400b24dfecea9a628f63089bf7eeb9a43b91021 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 22 Apr 2025 15:24:30 +0200 -Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for - ssusb0/pcie2 +Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2 First usb and third pcie controller on mt7988 need a xs-phy to work properly. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch b/target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch similarity index 82% rename from target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch rename to target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch index da26a93eb7..d02bca2b4e 100644 --- a/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch +++ b/target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch @@ -1,4 +1,4 @@ -From d326d21a44fbc48663840316c35524002029fbb1 Mon Sep 17 00:00:00 2001 +From bb5872c4b6cb0a8687b424b9970b2c3cca2ededd Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 22 Apr 2025 15:24:31 +0200 Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy @@ -7,6 +7,8 @@ Enable XS-Phy on Bananapi R4 for pcie2. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20250422132438.15735-9-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- diff --git a/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch deleted file mode 100644 index a0557ab966..0000000000 --- a/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch +++ /dev/null @@ -1,112 +0,0 @@ -From patchwork Sun May 11 14:19:20 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084127 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers -Date: Sun, 11 May 2025 16:19:20 +0200 -Message-ID: <20250511141942.10284-5-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: 5110cbfc-28b8-49e4-b9da-560d0bd630a5 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add SPI controllers for mt7988. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ - 1 file changed, 45 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -311,6 +311,51 @@ - status = "disabled"; - }; - -+ spi0: spi@11007000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11007000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI0>, -+ <&infracfg CLK_INFRA_66M_SPI0_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@11008000 { -+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; -+ reg = <0 0x11008000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI1>, -+ <&infracfg CLK_INFRA_66M_SPI1_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@11009000 { -+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; -+ reg = <0 0x11009000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_104M_SPI2_BCK>, -+ <&infracfg CLK_INFRA_66M_SPI2_HCK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", -+ "hclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts-ap"; - #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch new file mode 100644 index 0000000000..d634671ab5 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch @@ -0,0 +1,69 @@ +From bf7c2ce439ca811dc1697b4bc19ab57bd8f13be3 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 16 May 2025 20:01:35 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988: add spi controllers + +Add SPI controllers for mt7988. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -311,6 +311,51 @@ + status = "disabled"; + }; + ++ spi0: spi@11007000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11007000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI0>, ++ <&infracfg CLK_INFRA_66M_SPI0_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@11008000 { ++ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; ++ reg = <0 0x11008000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI1>, ++ <&infracfg CLK_INFRA_66M_SPI1_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@11009000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11009000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI2_BCK>, ++ <&infracfg CLK_INFRA_66M_SPI2_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts-ap"; + #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch b/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch deleted file mode 100644 index 7dbc1e4286..0000000000 --- a/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch +++ /dev/null @@ -1,133 +0,0 @@ -From patchwork Sun May 11 14:19:21 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084155 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 - pins to soc dtsi -Date: Sun, 11 May 2025 16:19:21 +0200 -Message-ID: <20250511141942.10284-6-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: 730e5bd4-362e-4c00-a35e-0ec77e8f4691 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -In order to use uart0 or spi1 there is only 1 possible pin definition -so move them to soc dtsi to reuse them in other boards and avoiding -conflict if defined twice. - -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ - 2 files changed, 18 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -328,13 +328,6 @@ - }; - }; - -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0"; -- }; -- }; -- - snfi_pins: snfi-pins { - mux { - function = "flash"; -@@ -356,13 +349,6 @@ - }; - }; - -- spi1_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1"; -- }; -- }; -- - spi2_pins: spi2-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -209,6 +209,20 @@ - "pcie_wake_n3_0"; - }; - }; -+ -+ spi1_pins: spi1-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1"; -+ }; -+ }; -+ -+ uart0_pins: uart0-pins { -+ mux { -+ function = "uart"; -+ groups = "uart0"; -+ }; -+ }; - }; - - pwm: pwm@10048000 { -@@ -244,6 +258,8 @@ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - -@@ -338,6 +354,8 @@ - "hclk"; - #address-cells = <1>; - #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - diff --git a/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch b/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch new file mode 100644 index 0000000000..54d829c7d9 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch @@ -0,0 +1,90 @@ +From b9ebd166b006f77cef4530b4bf4a291a112da4f2 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 16 May 2025 20:01:36 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc + dtsi + +In order to use uart0 or spi1 there is only 1 possible pin definition +so move them to soc dtsi to reuse them in other boards and avoiding +conflict if defined twice. + +Suggested-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20250516180147.10416-7-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ + 2 files changed, 18 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -328,13 +328,6 @@ + }; + }; + +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0"; +- }; +- }; +- + snfi_pins: snfi-pins { + mux { + function = "flash"; +@@ -356,13 +349,6 @@ + }; + }; + +- spi1_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1"; +- }; +- }; +- + spi2_pins: spi2-pins { + mux { + function = "spi"; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -209,6 +209,20 @@ + "pcie_wake_n3_0"; + }; + }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; + }; + + pwm: pwm@10048000 { +@@ -244,6 +258,8 @@ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; + status = "disabled"; + }; + +@@ -338,6 +354,8 @@ + "hclk"; + #address-cells = <1>; + #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + diff --git a/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch deleted file mode 100644 index 915c45caeb..0000000000 --- a/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch +++ /dev/null @@ -1,128 +0,0 @@ -From patchwork Sun May 11 14:19:22 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084106 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node -Date: Sun, 11 May 2025 16:19:22 +0200 -Message-ID: <20250511141942.10284-7-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: beeb7784-23fa-410f-9e58-cc51116d869e -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -Add cci devicetree node for cpu frequency scaling. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -12,6 +12,35 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ cci: cci { -+ compatible = "mediatek,mt8183-cci"; -+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, -+ <&topckgen CLK_TOP_XTAL>; -+ clock-names = "cci", "intermediate"; -+ operating-points-v2 = <&cci_opp>; -+ }; -+ -+ cci_opp: opp-table-cci { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ opp-480000000 { -+ opp-hz = /bits/ 64 <480000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-660000000 { -+ opp-hz = /bits/ 64 <660000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <850000>; -+ }; -+ opp-1080000000 { -+ opp-hz = /bits/ 64 <1080000000>; -+ opp-microvolt = <900000>; -+ }; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -25,6 +54,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { -@@ -36,6 +66,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { -@@ -47,6 +78,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { -@@ -58,6 +90,7 @@ - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; -+ mediatek,cci = <&cci>; - }; - - cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch new file mode 100644 index 0000000000..42a4aed2e2 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch @@ -0,0 +1,86 @@ +From 0cbdb6d04689f8c05074e348c8e0a42b229ef9a3 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 6 Jul 2025 15:22:03 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988: add cci node + +Add cci devicetree node for cpu frequency scaling. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20250706132213.20412-9-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -12,6 +12,35 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ cci: cci { ++ compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; ++ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cci", "intermediate"; ++ operating-points-v2 = <&cci_opp>; ++ }; ++ ++ cci_opp: opp-table-cci { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-480000000 { ++ opp-hz = /bits/ 64 <480000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-660000000 { ++ opp-hz = /bits/ 64 <660000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1080000000 { ++ opp-hz = /bits/ 64 <1080000000>; ++ opp-microvolt = <900000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -25,6 +54,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { +@@ -36,6 +66,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { +@@ -47,6 +78,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { +@@ -58,6 +90,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch b/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch deleted file mode 100644 index dc6df8ee57..0000000000 --- a/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From patchwork Sun May 11 14:19:23 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084124 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration - efuse subnodes -Date: Sun, 11 May 2025 16:19:23 +0200 -Message-ID: <20250511141942.10284-8-linux@fw-web.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> -References: <20250511141942.10284-1-linux@fw-web.de> -MIME-Version: 1.0 -X-Mail-ID: b7327c0d-db13-43b6-8ec5-709b71d19c3b -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -From: Frank Wunderlich - -MT7988 contains buildin mt753x switch which needs calibration data from -efuse. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -702,6 +702,22 @@ - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; -+ -+ phy_calibration_p0: calib@940 { -+ reg = <0x940 0x10>; -+ }; -+ -+ phy_calibration_p1: calib@954 { -+ reg = <0x954 0x10>; -+ }; -+ -+ phy_calibration_p2: calib@968 { -+ reg = <0x968 0x10>; -+ }; -+ -+ phy_calibration_p3: calib@97c { -+ reg = <0x97c 0x10>; -+ }; - }; - - clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch b/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch new file mode 100644 index 0000000000..b657e221f6 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch @@ -0,0 +1,42 @@ +From e4950b016c727feb0c39ad12cfcb6182c9ef3814 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 16 May 2025 20:01:38 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988: add phy calibration efuse + subnodes + +MT7988 contains buildin mt753x switch which needs calibration data from +efuse. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20250516180147.10416-9-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -702,6 +702,22 @@ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; ++ ++ phy_calibration_p0: calib@940 { ++ reg = <0x940 0x10>; ++ }; ++ ++ phy_calibration_p1: calib@954 { ++ reg = <0x954 0x10>; ++ }; ++ ++ phy_calibration_p2: calib@968 { ++ reg = <0x968 0x10>; ++ }; ++ ++ phy_calibration_p3: calib@97c { ++ reg = <0x97c 0x10>; ++ }; + }; + + clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch b/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch deleted file mode 100644 index 4e3d4ae8c0..0000000000 --- a/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch +++ /dev/null @@ -1,98 +0,0 @@ -From patchwork Sun May 11 14:26:50 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084133 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and - coolingmaps -Date: Sun, 11 May 2025 16:26:50 +0200 -Message-ID: <20250511142655.11007-1-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -Add Fan and cooling maps for Bananpi-R4 board. - -Signed-off-by: Frank Wunderlich ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -12,6 +12,15 @@ - stdout-path = "serial0:115200n8"; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ -+ cooling-levels = <0 80 128 255>; -+ #cooling-cells = <2>; -+ pwms = <&pwm 0 50000>; -+ status = "okay"; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; -@@ -73,6 +82,26 @@ - type = "active"; - }; - }; -+ -+ cooling-maps { -+ map-cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 3 3>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ map-cpu-active-med { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_med>; -+ }; -+ -+ map-cpu-active-low { -+ /* active: set fan to cooling level 0 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ }; - }; - - &i2c0 { diff --git a/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch b/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch new file mode 100644 index 0000000000..9b616cebd1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch @@ -0,0 +1,59 @@ +From 0f63e96e2ab422d1d35def1da75d3df299bf503e Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 16 May 2025 20:01:41 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps + +Add Fan and cooling maps for Bananapi-R4 board. + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20250516180147.10416-12-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -12,6 +12,15 @@ + stdout-path = "serial0:115200n8"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ ++ cooling-levels = <0 80 128 255>; ++ #cooling-cells = <2>; ++ pwms = <&pwm 0 50000>; ++ status = "okay"; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; +@@ -73,6 +82,26 @@ + type = "active"; + }; + }; ++ ++ cooling-maps { ++ map-cpu-active-high { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 3 3>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ map-cpu-active-med { ++ /* active: set fan to cooling level 1 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_med>; ++ }; ++ ++ map-cpu-active-low { ++ /* active: set fan to cooling level 0 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ }; + }; + + &i2c0 { diff --git a/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch b/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch deleted file mode 100644 index c5c5e83e92..0000000000 --- a/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch +++ /dev/null @@ -1,99 +0,0 @@ -From patchwork Sun May 11 14:26:51 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084136 -Received: from frank-u24 ([194.15.84.99]) by mail.gmx.net (mrgmx104 - [212.227.17.168]) with ESMTPSA (Nemesis) id 1MD9XF-1u5YvB0cIj-00FOt5; Sun, 11 - May 2025 16:27:04 +0200 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure - spi-nodes -Date: Sun, 11 May 2025 16:26:51 +0200 -Message-ID: <20250511142655.11007-2-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> -References: <20250511142655.11007-1-frank-w@public-files.de> -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -Configure and enable SPI nodes on Bananapi R4 board. - -Signed-off-by: Frank Wunderlich ---- - .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -401,6 +401,38 @@ - status = "okay"; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ -+ spi_nand: flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&spi1 { -+ status = "okay"; -+}; -+ -+&spi_nand { -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x200000>; -+ read-only; -+ }; -+ }; -+}; -+ - &ssusb1 { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc b/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc new file mode 100644 index 0000000000..cffc02226b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc @@ -0,0 +1,55 @@ +From 6b7642e9d095d33d8034b8b396a2de9e5ecb25a7 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 16 May 2025 20:01:42 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes + +Configure and enable SPI nodes on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20250516180147.10416-13-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -401,6 +401,38 @@ + status = "okay"; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; ++ ++&spi1 { ++ status = "okay"; ++}; ++ ++&spi_nand { ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x200000>; ++ read-only; ++ }; ++ }; ++}; ++ + &ssusb1 { + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch b/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch deleted file mode 100644 index f692a6f1c4..0000000000 --- a/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch +++ /dev/null @@ -1,68 +0,0 @@ -From patchwork Sun May 11 14:26:52 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 14084137 -From: Frank Wunderlich -To: Andrew Lunn , - Vladimir Oltean , - "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Matthias Brugger , - AngeloGioacchino Del Regno -Subject: [PATCH v1 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add - proc-supply for cci -Date: Sun, 11 May 2025 16:26:52 +0200 -Message-ID: <20250511142655.11007-3-frank-w@public-files.de> -X-Mailer: git-send-email 2.43.0 -In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> -References: <20250511142655.11007-1-frank-w@public-files.de> -MIME-Version: 1.0 -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, Landen Chao , - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , - netdev@vger.kernel.org, Sean Wang , - Daniel Golle , linux-kernel@vger.kernel.org, - DENG Qingfang , linux-mediatek@lists.infradead.org, - Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, - Felix Fietkau -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - -CCI requires proc-supply. Add it on board level. - -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi -@@ -40,6 +40,10 @@ - }; - }; - -+&cci { -+ proc-supply = <&rt5190_buck3>; -+}; -+ - &cpu0 { - proc-supply = <&rt5190_buck3>; - }; diff --git a/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch new file mode 100644 index 0000000000..68858e76b0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch @@ -0,0 +1,28 @@ +From b5a4ad957114b59a74b3e3f598ae0785dd86cd32 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 6 Jul 2025 15:22:06 +0200 +Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci + +CCI requires proc-supply. Add it on board level. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20250706132213.20412-12-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -40,6 +40,10 @@ + }; + }; + ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &cpu0 { + proc-supply = <&rt5190_buck3>; + }; From 51cb7b6e641205a4408b88683d31d68a8ea1f867 Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Tue, 10 Mar 2026 20:35:36 +0100 Subject: [PATCH 53/88] uboot-fritz4040: update to Git HEAD (2026-03-08) 056376fc703f Replace custom bool definitions with Signed-off-by: Til Kaiser Link: https://github.com/openwrt/openwrt/pull/22361 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-fritz4040/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/boot/uboot-fritz4040/Makefile b/package/boot/uboot-fritz4040/Makefile index 7997d35fdf..671d937fb3 100644 --- a/package/boot/uboot-fritz4040/Makefile +++ b/package/boot/uboot-fritz4040/Makefile @@ -10,9 +10,9 @@ include $(INCLUDE_DIR)/kernel.mk PKG_SOURCE_URL:=https://github.com/chunkeey/FritzBox-4040-UBOOT PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=6909090cb82db96f8ef0cd211ca91e87d69a07fc -PKG_SOURCE_DATE:=2026-03-04 -PKG_MIRROR_HASH:=741da058f24e559befff1f2d28d057dbfe9b3a6af67e60191cbefdbacc9143bb +PKG_SOURCE_VERSION:=056376fc703f2af0b93d673bf8ab4184689c5403 +PKG_SOURCE_DATE:=2026-03-08 +PKG_MIRROR_HASH:=1d7e4fe9116dc9378ee5569b48a1ce7bd41a8138928905010ebe79b8771c39dc PKG_RELEASE:=1 From 2a7cb484e958c2bb9196d6ef9a2362cd16ed0996 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 14 Mar 2026 21:48:58 +0100 Subject: [PATCH 54/88] mac80211: ath11k: make the M3 dump memory not defined a debug message There is no point in printing the missing M3 memory dump adress message on each boot under the warning level, as not all boards need it at all. So, degrate it to a debug print with QMI mask. Signed-off-by: Robert Marko --- .../931-wifi-ath11k-Support-to-assign-m3-dump-memory.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/mac80211/patches/ath11k/931-wifi-ath11k-Support-to-assign-m3-dump-memory.patch b/package/kernel/mac80211/patches/ath11k/931-wifi-ath11k-Support-to-assign-m3-dump-memory.patch index 77c92fd777..128ac8105e 100644 --- a/package/kernel/mac80211/patches/ath11k/931-wifi-ath11k-Support-to-assign-m3-dump-memory.patch +++ b/package/kernel/mac80211/patches/ath11k/931-wifi-ath11k-Support-to-assign-m3-dump-memory.patch @@ -16,7 +16,7 @@ Signed-off-by: Ziyang Huang break; + case M3_DUMP_REGION_TYPE: + if (of_property_read_u32(dev->of_node, "qcom,m3-dump-addr", &addr)) { -+ ath11k_warn(ab, "qmi fail to get qcom,m3-dump-addr, ignore m3 dump mem req\n"); ++ ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi fail to get qcom,m3-dump-addr, ignore m3 dump mem req\n"); + break; + } + From 518d711461334954e529b6199b9c6dcc2df24145 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Fri, 19 Dec 2025 23:20:48 +0800 Subject: [PATCH 55/88] tools/zlib: update to 1.3.2 Release Notes: https://github.com/madler/zlib/blob/v1.3.2/ChangeLog We also switch package tarball source to GitHub repository releases to avoid package hash mismatch after the zstd upgrade. The 900-* patch was suppressed by the upstream commit 15ba5055a935 ("CMake: Adapt pkgconfig-file to the GnuInstallDirs layout.") Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/21228 Signed-off-by: Hauke Mehrtens --- tools/zlib/Makefile | 9 ++-- ...karound-elfutils-link-error-on-MacOS.patch | 52 +++++++++++++++++++ .../900-overridable-pc-exec-prefix.patch | 14 ----- 3 files changed, 56 insertions(+), 19 deletions(-) create mode 100644 tools/zlib/patches/0001-deflate-workaround-elfutils-link-error-on-MacOS.patch delete mode 100644 tools/zlib/patches/900-overridable-pc-exec-prefix.patch diff --git a/tools/zlib/Makefile b/tools/zlib/Makefile index 09c0aa6f71..cea344ae5e 100644 --- a/tools/zlib/Makefile +++ b/tools/zlib/Makefile @@ -8,13 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=zlib -PKG_VERSION:=1.3.1 +PKG_VERSION:=1.3.2 PKG_RELEASE:=1 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/madler/zlib -PKG_SOURCE_VERSION:=51b7f2abdade71cd9bb0e7a373ef2610ec6f9daf -PKG_MIRROR_HASH:=6558577038f4839057fad93afb295bf32e84dc9bd2c33512d40a5eab6d4889ef +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://github.com/madler/zlib/releases/download/v$(PKG_VERSION) +PKG_HASH:=d7a0654783a4da529d1bb793b7ad9c3318020af77667bcae35f95d0e42a792f3 PKG_LICENSE:=Zlib PKG_LICENSE_FILES:=LICENSE diff --git a/tools/zlib/patches/0001-deflate-workaround-elfutils-link-error-on-MacOS.patch b/tools/zlib/patches/0001-deflate-workaround-elfutils-link-error-on-MacOS.patch new file mode 100644 index 0000000000..0b46e7aaff --- /dev/null +++ b/tools/zlib/patches/0001-deflate-workaround-elfutils-link-error-on-MacOS.patch @@ -0,0 +1,52 @@ +From 18a6dfff79b6357aada21bec506442ed96bb34da Mon Sep 17 00:00:00 2001 +From: Shiji Yang +Date: Thu, 5 Mar 2026 00:13:35 +0800 +Subject: [PATCH] deflate: workaround elfutils link error on MacOS + +duplicate symbol '_crc32' in: + /Volumes/OpenWrt/openwrt/build_dir/host/elfutils-0.192/libdw/libdw.a[392](crc32.o) + /Volumes/OpenWrt/openwrt/staging_dir/host/lib/libz.a[3](crc32.o) + +Signed-off-by: Shiji Yang +--- + deflate.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/deflate.c ++++ b/deflate.c +@@ -970,12 +970,21 @@ local void flush_pending(z_streamp strm) + /* =========================================================================== + * Update the header CRC with the bytes s->pending_buf[beg..s->pending - 1]. + */ ++#if defined(__APPLE__) ++#define HCRC_UPDATE(beg) \ ++ do { \ ++ if (s->gzhead->hcrc && s->pending > (beg)) \ ++ strm->adler = crc32(strm->adler, s->pending_buf + (beg), \ ++ s->pending - (beg)); \ ++ } while (0) ++#else + #define HCRC_UPDATE(beg) \ + do { \ + if (s->gzhead->hcrc && s->pending > (beg)) \ + strm->adler = crc32_z(strm->adler, s->pending_buf + (beg), \ + s->pending - (beg)); \ + } while (0) ++#endif + + /* ========================================================================= */ + int ZEXPORT deflate(z_streamp strm, int flush) { +@@ -1108,8 +1117,13 @@ int ZEXPORT deflate(z_streamp strm, int + put_byte(s, (s->gzhead->extra_len >> 8) & 0xff); + } + if (s->gzhead->hcrc) ++#if defined(__APPLE__) ++ strm->adler = crc32(strm->adler, s->pending_buf, ++ s->pending); ++#else + strm->adler = crc32_z(strm->adler, s->pending_buf, + s->pending); ++#endif + s->gzindex = 0; + s->status = EXTRA_STATE; + } diff --git a/tools/zlib/patches/900-overridable-pc-exec-prefix.patch b/tools/zlib/patches/900-overridable-pc-exec-prefix.patch deleted file mode 100644 index 4f1e376c90..0000000000 --- a/tools/zlib/patches/900-overridable-pc-exec-prefix.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/zlib.pc.cmakein -+++ b/zlib.pc.cmakein -@@ -1,8 +1,8 @@ - prefix=@CMAKE_INSTALL_PREFIX@ - exec_prefix=@CMAKE_INSTALL_PREFIX@ --libdir=@INSTALL_LIB_DIR@ --sharedlibdir=@INSTALL_LIB_DIR@ --includedir=@INSTALL_INC_DIR@ -+libdir=${prefix}/lib -+sharedlibdir=${prefix}/lib -+includedir=${prefix}/include - - Name: zlib - Description: zlib compression library From 9413a3d96d27b8b28bb2118568d60b9aa5685ae6 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Fri, 19 Dec 2025 23:59:05 +0800 Subject: [PATCH 56/88] zlib: update to 1.3.2 Release Notes: https://github.com/madler/zlib/blob/v1.3.2/ChangeLog We also switch package tarball source to GitHub repository releases to avoid package hash mismatch after the zstd upgrade. The 005-* patch was suppressed by the upstream commit 15ba5055a935 ("CMake: Adapt pkgconfig-file to the GnuInstallDirs layout.") This patch also adjust the zlib.pc file path as it was changed in the latest release. The mipsel_24kc 'zlib' package size will increase by about 1 kB. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/21228 Signed-off-by: Hauke Mehrtens --- package/libs/zlib/Makefile | 13 ++--- ...rcefiles-in-patch-002-to-buildsystem.patch | 57 +++++++++---------- .../005-relative-pkg-config-paths.patch | 14 ----- 3 files changed, 32 insertions(+), 52 deletions(-) delete mode 100644 package/libs/zlib/patches/005-relative-pkg-config-paths.patch diff --git a/package/libs/zlib/Makefile b/package/libs/zlib/Makefile index 87a5715f89..b192b6dcf7 100644 --- a/package/libs/zlib/Makefile +++ b/package/libs/zlib/Makefile @@ -8,13 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=zlib -PKG_VERSION:=1.3.1 +PKG_VERSION:=1.3.2 PKG_RELEASE:=1 -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/madler/zlib -PKG_SOURCE_VERSION:=51b7f2abdade71cd9bb0e7a373ef2610ec6f9daf -PKG_MIRROR_HASH:=6558577038f4839057fad93afb295bf32e84dc9bd2c33512d40a5eab6d4889ef +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=https://github.com/madler/zlib/releases/download/v$(PKG_VERSION) +PKG_HASH:=d7a0654783a4da529d1bb793b7ad9c3318020af77667bcae35f95d0e42a792f3 PKG_LICENSE:=Zlib PKG_LICENSE_FILES:=LICENSE @@ -71,7 +70,7 @@ define Build/InstallDev $(CP) $(PKG_INSTALL_DIR)/usr/lib/libz.{a,so*} \ $(1)/usr/lib/ mkdir -p $(1)/usr/lib/pkgconfig - $(CP) $(PKG_INSTALL_DIR)/usr/share/pkgconfig/zlib.pc \ + $(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/zlib.pc \ $(1)/usr/lib/pkgconfig/ endef @@ -91,7 +90,7 @@ define Package/zlib-dev/install $(INSTALL_DIR) $(1)/usr/lib $(CP) $(PKG_INSTALL_DIR)/usr/lib/libz.a $(1)/usr/lib/ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig - $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/pkgconfig/zlib.pc \ + $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/zlib.pc \ $(1)/usr/lib/pkgconfig/ endef diff --git a/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch b/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch index 5181dcf419..582e48245e 100644 --- a/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch +++ b/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch @@ -1,9 +1,9 @@ --- a/CMakeLists.txt +++ b/CMakeLists.txt -@@ -93,34 +93,67 @@ set(ZLIB_PUBLIC_HDRS - ${CMAKE_CURRENT_BINARY_DIR}/zconf.h - zlib.h - ) +@@ -121,33 +121,64 @@ configure_file(${zlib_BINARY_DIR}/zconf. + + set(ZLIB_PUBLIC_HDRS ${zlib_BINARY_DIR}/zconf.h zlib.h) + -set(ZLIB_PRIVATE_HDRS - crc32.h - deflate.h @@ -13,8 +13,20 @@ - inflate.h - inftrees.h - trees.h -- zutil.h --) +- zutil.h) ++if(ARMv8) ++ set(ZLIB_PRIVATE_HDRS ++ crc32.h ++ deflate.h ++ gzguts.h ++ inffast.h ++ inffixed.h ++ inflate.h ++ inftrees.h ++ trees.h ++ zutil.h ++ contrib/arm/chunkcopy.h) + -set(ZLIB_SRCS - adler32.c - compress.c @@ -30,22 +42,7 @@ - inffast.c - trees.c - uncompr.c -- zutil.c --) -+ -+if(ARMv8) -+ set(ZLIB_PRIVATE_HDRS -+ crc32.h -+ deflate.h -+ gzguts.h -+ inffast.h -+ inffixed.h -+ inflate.h -+ inftrees.h -+ trees.h -+ zutil.h -+ contrib/arm/chunkcopy.h -+ ) +- zutil.c) + set(ZLIB_SRCS + adler32.c + compress.c @@ -61,9 +58,8 @@ + contrib/arm/inffast.c + trees.c + uncompr.c -+ zutil.c -+ ) -+ else() ++ zutil.c) ++else() + set(ZLIB_PRIVATE_HDRS + crc32.h + deflate.h @@ -73,8 +69,8 @@ + inflate.h + inftrees.h + trees.h -+ zutil.h -+ ) ++ zutil.h) ++ + set(ZLIB_SRCS + adler32.c + compress.c @@ -90,9 +86,8 @@ + inffast.c + trees.c + uncompr.c -+ zutil.c -+ ) ++ zutil.c) +endif() - if(NOT MINGW) - set(ZLIB_DLL_SRCS + if(WIN32) + set(zlib_static_suffix "s") diff --git a/package/libs/zlib/patches/005-relative-pkg-config-paths.patch b/package/libs/zlib/patches/005-relative-pkg-config-paths.patch deleted file mode 100644 index c86d19b412..0000000000 --- a/package/libs/zlib/patches/005-relative-pkg-config-paths.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/zlib.pc.cmakein -+++ b/zlib.pc.cmakein -@@ -1,8 +1,8 @@ - prefix=@CMAKE_INSTALL_PREFIX@ - exec_prefix=@CMAKE_INSTALL_PREFIX@ --libdir=@INSTALL_LIB_DIR@ --sharedlibdir=@INSTALL_LIB_DIR@ --includedir=@INSTALL_INC_DIR@ -+libdir=${exec_prefix}/lib -+sharedlibdir=${exec_prefix}/lib -+includedir=${prefix}/include - - Name: zlib - Description: zlib compression library From bda9db304943a0107c1e79ecd1ed6bbcab0088f4 Mon Sep 17 00:00:00 2001 From: Jan Kantert Date: Sun, 1 Mar 2026 00:09:19 +0100 Subject: [PATCH 57/88] realtek: use 50kHz I2C for SFPs on Xikestor SKS8300-8X Some 10G optics showed random "module transmit fault indicated" due to I2C read errors on ONTi ONT-S508CL-8S/XikeStor SKS8300-8X switches. The same modules work with the original firmware and on other Linux based devices. There seems to be some differences in how we talk to those modules using I2C in OpenWRT. To fix this this patch adds support for 50kHz I2C speed on SFPs and enables that for XikeStor/Onti devices. Since SFPs only transmit very few bytes this should not have any real downsides. This patch configures I2C to use 50kHz clock in the DTS for the affected devices. For it to work it requires a change in the RTL9300 I2C driver. This can be safely merged without the kernel change (but will not work in that case as it will fall back to 100kHz). Signed-off-by: Jan Kantert Link: https://github.com/openwrt/openwrt/pull/22210 Signed-off-by: Hauke Mehrtens --- target/linux/realtek/dts/rtl9303_xikestor_sks8300-8x.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/linux/realtek/dts/rtl9303_xikestor_sks8300-8x.dts b/target/linux/realtek/dts/rtl9303_xikestor_sks8300-8x.dts index bced9eb22c..acc96092df 100644 --- a/target/linux/realtek/dts/rtl9303_xikestor_sks8300-8x.dts +++ b/target/linux/realtek/dts/rtl9303_xikestor_sks8300-8x.dts @@ -147,27 +147,35 @@ /* SDA0-7 correspond to GPIO9-16 */ i2c0: i2c@0 { reg = <0>; + clock-frequency = <50000>; }; i2c1: i2c@1 { reg = <1>; + clock-frequency = <50000>; }; i2c2: i2c@2 { reg = <2>; + clock-frequency = <50000>; }; i2c3: i2c@3 { reg = <3>; + clock-frequency = <50000>; }; i2c4: i2c@4 { reg = <4>; + clock-frequency = <50000>; }; i2c5: i2c@5 { reg = <5>; + clock-frequency = <50000>; }; i2c6: i2c@6 { reg = <6>; + clock-frequency = <50000>; }; i2c7: i2c@7 { reg = <7>; + clock-frequency = <50000>; }; }; From e4624d308ee91c598507ea801b618b93f6793917 Mon Sep 17 00:00:00 2001 From: John Audia Date: Sun, 15 Feb 2026 05:25:59 -0500 Subject: [PATCH 58/88] intel-microcode: update to 20260210 Changelog: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260210-rev1 Build system: x86/64 Build-tested: x86/64-glibc Run-tested: x86/64-glibc (Intel N150) Signed-off-by: John Audia Link: https://github.com/openwrt/openwrt/pull/22035 Signed-off-by: Hauke Mehrtens --- package/firmware/intel-microcode/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/intel-microcode/Makefile b/package/firmware/intel-microcode/Makefile index 224c878dd6..d09eaf80ec 100644 --- a/package/firmware/intel-microcode/Makefile +++ b/package/firmware/intel-microcode/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=intel-microcode -PKG_VERSION:=20251111 +PKG_VERSION:=20260210 PKG_RELEASE:=1 PKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).1.tar.xz PKG_SOURCE_URL:=@DEBIAN/pool/non-free-firmware/i/intel-microcode/ -PKG_HASH:=9b6d11cf851dbe483d3afe73e93049263f06b2f93c78a5f7b0068fb2f7ea3411 +PKG_HASH:=4d8654f4f6c7d14f496bcfcb097522d2825282eb8ea27605d882092371d66a76 PKG_BUILD_DIR:=$(BUILD_DIR)/intel-microcode-3.$(PKG_VERSION).1 PKG_CPE_ID:=cpe:/a:intel:microcode From bb7f4f97c7dfb3fca085ca5306f82e8ab4ddee5c Mon Sep 17 00:00:00 2001 From: John Audia Date: Sun, 8 Mar 2026 07:58:25 -0400 Subject: [PATCH 59/88] intel-microcode: update to 20260227 Changelog: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260227 Build system: x86/64 Build-tested: x86/64-glibc Run-tested: x86/64-glibc (Intel N150) Signed-off-by: John Audia Link: https://github.com/openwrt/openwrt/pull/22035 Signed-off-by: Hauke Mehrtens --- package/firmware/intel-microcode/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/intel-microcode/Makefile b/package/firmware/intel-microcode/Makefile index d09eaf80ec..afbd8efac5 100644 --- a/package/firmware/intel-microcode/Makefile +++ b/package/firmware/intel-microcode/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=intel-microcode -PKG_VERSION:=20260210 +PKG_VERSION:=20260227 PKG_RELEASE:=1 PKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).1.tar.xz PKG_SOURCE_URL:=@DEBIAN/pool/non-free-firmware/i/intel-microcode/ -PKG_HASH:=4d8654f4f6c7d14f496bcfcb097522d2825282eb8ea27605d882092371d66a76 +PKG_HASH:=15289edaaa2db7976e005628027f16d19945f1eab1bb2d5dd44133cd06c4ad25 PKG_BUILD_DIR:=$(BUILD_DIR)/intel-microcode-3.$(PKG_VERSION).1 PKG_CPE_ID:=cpe:/a:intel:microcode From 42fcfe535c82b3b5edd735c1c5632418c66fb199 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Wed, 4 Mar 2026 08:13:25 +0100 Subject: [PATCH 60/88] realtek: dsa: add MAC_LINK_STS to config structure This register will be needed to provide a generic irq handler. Add it to the configuration structure of the driver. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22273 Signed-off-by: Hauke Mehrtens --- .../linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c | 1 + .../linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h | 1 + .../linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c | 1 + .../linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c | 1 + .../linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c | 1 + 5 files changed, 5 insertions(+) diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c index 650b46db14..f9756dcc7e 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c @@ -1845,6 +1845,7 @@ const struct rtldsa_config rtldsa_838x_cfg = { .vlan_set_tagged = rtl838x_vlan_set_tagged, .vlan_set_untagged = rtl838x_vlan_set_untagged, .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .mac_link_sts = RTL838X_MAC_LINK_STS, .vlan_profile_get = rtldsa_838x_vlan_profile_get, .vlan_profile_dump = rtldsa_838x_vlan_profile_dump, .vlan_profile_setup = rtl838x_vlan_profile_setup, diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h index 0843676e93..acdc40f048 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h @@ -1444,6 +1444,7 @@ struct rtldsa_config { void (*set_static_move_action)(int port, bool forward); int (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]); void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); + int mac_link_sts; int (*mac_force_mode_ctrl)(int port); int (*mac_port_ctrl)(int port); int (*l2_port_new_salrn)(int port); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c index 9f0196c371..a4bd5a914e 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c @@ -1800,6 +1800,7 @@ const struct rtldsa_config rtldsa_839x_cfg = { .stp_get = rtldsa_839x_stp_get, .stp_set = rtl839x_stp_set, .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .mac_link_sts = RTL839X_MAC_LINK_STS, .mac_port_ctrl = rtl839x_mac_port_ctrl, .l2_port_new_salrn = rtl839x_l2_port_new_salrn, .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd, diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c index c86b28a45b..b258f05ba7 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c @@ -2861,6 +2861,7 @@ const struct rtldsa_config rtldsa_930x_cfg = { .set_vlan_egr_filter = rtl930x_set_egr_filter, .stp_get = rtldsa_930x_stp_get, .stp_set = rtl930x_stp_set, + .mac_link_sts = RTL930X_MAC_LINK_STS, .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl, .mac_port_ctrl = rtl930x_mac_port_ctrl, .l2_port_new_salrn = rtl930x_l2_port_new_salrn, diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c index 3a2a0f5121..fbefb3c79b 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c @@ -2008,6 +2008,7 @@ const struct rtldsa_config rtldsa_931x_cfg = { .stp_get = rtldsa_931x_stp_get, .stp_set = rtl931x_stp_set, .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl, + .mac_link_sts = RTL931X_MAC_LINK_STS, .mac_port_ctrl = rtl931x_mac_port_ctrl, .l2_port_new_salrn = rtl931x_l2_port_new_salrn, .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd, From 056176cde1cabb7b38dd57bedfcdd480769bf7d7 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Wed, 4 Mar 2026 19:16:23 +0100 Subject: [PATCH 61/88] realtek: dsa: consolidate switch_irq() The dsa irq handler works always in the same way for all SoCs. - Read register ISR_PORT_LINK_STS_CHG to determine the ports that triggered the irq. - Write the read value back to the register to confirm the irq - Read link status via MAC_LINK_STS - Trigger dsa_port_phylink_mac_change() for each changed port Currently each SoC has its own implementation. Drop that in favour of a generic implementation that makes use of the existing bit register read/write helpers. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22273 Signed-off-by: Hauke Mehrtens --- .../drivers/net/dsa/rtl83xx/common.c | 41 +++++++++++-------- .../drivers/net/dsa/rtl83xx/rtl838x.c | 24 ----------- .../drivers/net/dsa/rtl83xx/rtl839x.c | 24 ----------- .../drivers/net/dsa/rtl83xx/rtl83xx.h | 5 --- .../drivers/net/dsa/rtl83xx/rtl930x.c | 23 ----------- .../drivers/net/dsa/rtl83xx/rtl931x.c | 31 -------------- 6 files changed, 23 insertions(+), 125 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c index 59c1444e6e..3f98a20f95 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c @@ -1532,6 +1532,27 @@ static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, v return NOTIFY_DONE; } +static irqreturn_t rtldsa_switch_irq(int irq, void *dev_id) +{ + struct rtl838x_switch_priv *priv; + struct dsa_switch *ds = dev_id; + u64 link, ports; + + priv = ds->priv; + ports = priv->r->get_port_reg_le(priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg_le(ports, priv->r->isr_port_link_sts_chg); + + /* read latched */ + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + + for (int port = 0; port < priv->cpu_port; port++) + if (ports & BIT_ULL(port)) + dsa_port_phylink_mac_change(ds, port, link & BIT_ULL(port)); + + return IRQ_HANDLED; +} + /* * TODO: This check is usually built into the DSA initialization functions. After carving * out the mdio driver from the ethernet driver, there are two drivers that must be loaded @@ -1699,24 +1720,8 @@ static int rtl83xx_sw_probe(struct platform_device *pdev) priv->link_state_irq = platform_get_irq(pdev, 0); pr_info("LINK state irq: %d\n", priv->link_state_irq); - switch (priv->family_id) { - case RTL8380_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl838x_switch_irq, - IRQF_SHARED, "rtl838x-link-state", priv->ds); - break; - case RTL8390_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl839x_switch_irq, - IRQF_SHARED, "rtl839x-link-state", priv->ds); - break; - case RTL9300_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtldsa_930x_switch_irq, - IRQF_SHARED, "rtl930x-link-state", priv->ds); - break; - case RTL9310_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl931x_switch_irq, - IRQF_SHARED, "rtl931x-link-state", priv->ds); - break; - } + err = request_irq(priv->link_state_irq, rtldsa_switch_irq, + IRQF_SHARED, "rtldsa-link-state", priv->ds); if (err) { dev_err(dev, "Error setting up switch interrupt.\n"); /* Need to free allocated switch here */ diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c index f9756dcc7e..4cdcfc50a5 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c @@ -1898,27 +1898,3 @@ const struct rtldsa_config rtldsa_838x_cfg = { .lag_set_port_members = rtldsa_838x_lag_set_port_members, .lag_setup_algomask = rtldsa_83xx_lag_setup_algomask, }; - -irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL838X_ISR_GLB_SRC); - u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); - u32 link; - - /* Clear status */ - sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports); - - for (int i = 0; i < 28; i++) { - if (ports & BIT(i)) { - link = sw_r32(RTL838X_MAC_LINK_STS); - if (link & BIT(i)) - dsa_port_phylink_mac_change(ds, i, true); - else - dsa_port_phylink_mac_change(ds, i, false); - } - } - - return IRQ_HANDLED; -} diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c index a4bd5a914e..3fab93ac69 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c @@ -708,30 +708,6 @@ static void rtl839x_set_static_move_action(int port, bool forward) RTL839X_L2_PORT_STATIC_MV_ACT(port)); } -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL839X_ISR_GLB_SRC); - u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG); - u64 link; - - /* Clear status */ - rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports); - - for (int i = 0; i < RTL839X_CPU_PORT; i++) { - if (ports & BIT_ULL(i)) { - link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS); - if (link & BIT_ULL(i)) - dsa_port_phylink_mac_change(ds, i, true); - else - dsa_port_phylink_mac_change(ds, i, false); - } - } - - return IRQ_HANDLED; -} - static void rtldsa_839x_vlan_profile_dump(struct rtl838x_switch_priv *priv, int idx) { diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h index 7237aa862c..cf24ecc1be 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -159,23 +159,18 @@ int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate /* RTL838x-specific */ u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtl838x_switch_irq(int irq, void *dev_id); void rtldsa_838x_print_matrix(void); /* RTL839x-specific */ u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); void rtl839x_exec_tbl2_cmd(u32 cmd); void rtldsa_839x_print_matrix(void); /* RTL930x-specific */ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtldsa_930x_switch_irq(int irq, void *dev_id); -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); void rtldsa_930x_print_matrix(void); /* RTL931x-specific */ -irqreturn_t rtl931x_switch_irq(int irq, void *dev_id); void rtldsa_931x_print_matrix(void); int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c index b258f05ba7..1c428814bb 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c @@ -1112,29 +1112,6 @@ void rtl9300_dump_debug(void) ); } -irqreturn_t rtldsa_930x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - struct rtl838x_switch_priv *priv = ds->priv; - unsigned long ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG); - unsigned int i; - u32 link; - - /* Clear status */ - sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG); - - /* Read the register twice because of issues with latency at least - * with the external RTL8226 PHY on the XGS1210 - */ - link = sw_r32(RTL930X_MAC_LINK_STS); - link = sw_r32(RTL930X_MAC_LINK_STS); - - for_each_set_bit(i, &ports, priv->cpu_port) - dsa_port_phylink_mac_change(ds, i, link & BIT(i)); - - return IRQ_HANDLED; -} - /* Calculate both the block 0 and the block 1 hash, and return in * lower and higher word of the return value since only 12 bit of * the hash are significant diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c index fbefb3c79b..2e31c10cdc 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c @@ -462,37 +462,6 @@ static int rtldsa_931x_port_rate_police_del(struct dsa_switch *ds, int port, return 0; } -irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL931X_ISR_GLB_SRC); - u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG); - u64 link; - - /* Clear status */ - rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status, ports); - - link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); - /* Must re-read this to get correct status */ - link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); - pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link); - - for (int i = 0; i < 56; i++) { - if (ports & BIT_ULL(i)) { - if (link & BIT_ULL(i)) { - pr_debug("%s port %d up\n", __func__, i); - dsa_port_phylink_mac_change(ds, i, true); - } else { - pr_debug("%s port %d down\n", __func__, i); - dsa_port_phylink_mac_change(ds, i, false); - } - } - } - - return IRQ_HANDLED; -} - void rtldsa_931x_print_matrix(void) { struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1); From eda2630ceb7d98293fcc3cf9df1c27e1d8ed803a Mon Sep 17 00:00:00 2001 From: John Audia Date: Thu, 26 Feb 2026 17:24:56 -0500 Subject: [PATCH 62/88] wireguard-tools: bump to 20260223 % git shortlog v1.0.20250521..v1.0.20260223 Doug Freed (1): wg-quick@.service: add deps on wg-quick.target Jason A. Donenfeld (8): wg-quick: linux: use smallest mtu, not largest syncconf: account for psks removed from config file wg-quick: linux: deal with resolvconf migration more gracefully wg-quick: use addconf instead of setconf wg-quick: linux: do not unnecessarily set sysctl config: preserve const correctness syncconf: account for persistent keepalive removed from config file version: bump Robyn Kosching (1): wg-quick: pass on # comments to {Pre,Post}{Up,Down} Build system: x86/64 Build-tested: x86/64-glibc Run-tested: x86/64-glibc Signed-off-by: John Audia Link: https://github.com/openwrt/openwrt/pull/22190 Signed-off-by: Hauke Mehrtens --- package/network/utils/wireguard-tools/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/network/utils/wireguard-tools/Makefile b/package/network/utils/wireguard-tools/Makefile index b0b0ddc967..b5ebdf12cf 100644 --- a/package/network/utils/wireguard-tools/Makefile +++ b/package/network/utils/wireguard-tools/Makefile @@ -10,12 +10,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=wireguard-tools -PKG_VERSION:=1.0.20250521 +PKG_VERSION:=1.0.20260223 PKG_RELEASE:=1 PKG_SOURCE:=wireguard-tools-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://git.zx2c4.com/wireguard-tools/snapshot/ -PKG_HASH:=b6f2628b85b1b23cc06517ec9c74f82d52c4cdbd020f3dd2f00c972a1782950e +PKG_HASH:=af459827b80bfd31b83b08077f4b5843acb7d18ad9a33a2ef532d3090f291fbf PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING From acedb7e2d366a670f7196913de528db3f668a8ae Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Tue, 23 Dec 2025 20:38:31 +0100 Subject: [PATCH 63/88] realtek: support MDI swapping for RTL8226 PHY The PHY supports swapping the MDI pairs (ABCD->DCBA) to simplify board layout. On devices making use of this, it needs to be configured in the driver, otherwise the PHY won't work properly. Signed-off-by: Jan Hoffmann Link: https://github.com/openwrt/openwrt/pull/21261 Signed-off-by: Hauke Mehrtens --- ...tek-support-MDI-swapping-for-RTL8226.patch | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch diff --git a/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch b/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch new file mode 100644 index 0000000000..19d5df2202 --- /dev/null +++ b/target/linux/realtek/patches-6.12/740-net-phy-realtek-support-MDI-swapping-for-RTL8226.patch @@ -0,0 +1,190 @@ +From 672a9bfb2e01ecaf40e5b92e9cc564589ffc251d Mon Sep 17 00:00:00 2001 +From: Jan Hoffmann +Date: Tue, 23 Dec 2025 20:07:53 +0100 +Subject: [PATCH] net: phy: realtek: support MDI swapping for RTL8226 + +Add support for configuring swapping of MDI pairs (ABCD->DCBA) when the +property "enet-phy-pair-order" is specified. + +Unfortunately, no documentation about this feature is available, so the +configuration involves magic values. Only enabling MDI swapping is +supported, as it is unknown whether the patching step can be safely +reversed. + +For now, only implement it for RTL8226, where it is needed to make the +PHYs in Zyxel XGS1010-12 rev A1 work. However, parts of this code might +also be useful for other PHYs in the future: + +RTL8221B also allows to configure MDI swapping via the same register, +but does not need the additional patching step. Since it also supports +configuration via strapping pins, there might not be any need for driver +support on that PHY, though. + +The patching step itself seems to be the same which is also used by the +integrated PHY of some Realtek PCIe/USB NICs. + +Signed-off-by: Jan Hoffmann +--- + drivers/net/phy/realtek/realtek_main.c | 159 ++++++++++++++++++++++++- + 1 file changed, 158 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/realtek/realtek_main.c ++++ b/drivers/net/phy/realtek/realtek_main.c +@@ -1486,6 +1486,148 @@ static unsigned int rtl822x_inband_caps( + } + } + ++static int rtl8226_set_mdi_swap(struct phy_device *phydev, bool swap_enable) ++{ ++ u16 val = swap_enable ? BIT(5) : 0; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, 0x6a21, BIT(5), val); ++} ++ ++static int rtl8226_patch_mdi_swap(struct phy_device *phydev) ++{ ++ int ret; ++ u16 vals[4]; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd068); ++ if (ret < 0) ++ return ret; ++ ++ if (!(ret & BIT(1))) { ++ /* already swapped */ ++ return 0; ++ } ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x7, 0x1); ++ if (ret < 0) ++ return ret; ++ ++ /* swap adccal_offset */ ++ ++ for (int i = 0; i < 4; i++) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xd06a); ++ if (ret < 0) ++ return ret; ++ ++ vals[i] = ret; ++ } ++ ++ for (int i = 0; i < 4; i++) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xd068, 0x3 << 3, i << 3); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xd06a, vals[3 - i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ /* swap rg_lpf_cap_xg */ ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a); ++ if (ret < 0) ++ return ret; ++ ++ vals[0] = ret & 0x1f; ++ vals[1] = (ret >> 8) & 0x1f; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c); ++ if (ret < 0) ++ return ret; ++ ++ vals[2] = ret & 0x1f; ++ vals[3] = (ret >> 8) & 0x1f; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5a, 0x1f1f, ++ vals[3] | (vals[2] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbd5c, 0x1f1f, ++ vals[1] | (vals[0] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ /* swap rg_lpf_cap */ ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc18); ++ if (ret < 0) ++ return ret; ++ ++ vals[0] = ret & 0x1f; ++ vals[1] = (ret >> 8) & 0x1f; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a); ++ if (ret < 0) ++ return ret; ++ ++ vals[2] = ret & 0x1f; ++ vals[3] = (ret >> 8) & 0x1f; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc18, 0x1f1f, ++ vals[3] | (vals[2] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xbc1a, 0x1f1f, ++ vals[1] | (vals[0] << 8)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtl8226_config_mdi_order(struct phy_device *phydev) ++{ ++ u32 order; ++ int ret; ++ ++ ret = of_property_read_u32(phydev->mdio.dev.of_node, "enet-phy-pair-order", &order); ++ ++ /* Property not present, nothing to do */ ++ if (ret == -EINVAL) ++ return 0; ++ ++ if (ret) ++ return ret; ++ ++ /* Only enabling MDI swapping is supported */ ++ if (order != 1) ++ return -EINVAL; ++ ++ ret = rtl8226_set_mdi_swap(phydev, true); ++ if (ret) ++ return ret; ++ ++ ret = rtl8226_patch_mdi_swap(phydev); ++ return ret; ++} ++ ++static int rtl8226_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = rtl8226_config_mdi_order(phydev); ++ if (ret) ++ return ret; ++ ++ return rtl822x_config_init(phydev); ++} ++ ++ + static int rtl822xb_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) + { +@@ -2358,7 +2500,7 @@ static struct phy_driver realtek_drvs[] + .soft_reset = rtl822x_c45_soft_reset, + .get_features = rtl822x_c45_get_features, + .config_aneg = rtl822x_c45_config_aneg, +- .config_init = rtl822x_config_init, ++ .config_init = rtl8226_config_init, + .inband_caps = rtl822x_inband_caps, + .config_inband = rtl822x_config_inband, + .read_status = rtl822xb_c45_read_status, From b943db9cb2a2780e9244d10582ee873e6c01ee7f Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Tue, 23 Dec 2025 20:40:52 +0100 Subject: [PATCH 64/88] realtek: enable MDI swapping for RTL8226 where needed The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped MDI lanes. Specify this in the device tree, so the driver can configure it. With this change, the PHYs no longer require initialization by the bootloader. Signed-off-by: Jan Hoffmann Link: https://github.com/openwrt/openwrt/pull/21261 Signed-off-by: Hauke Mehrtens --- target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts | 2 ++ target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts index e0a308cdd7..513f217170 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts @@ -105,8 +105,10 @@ &phy24 { realtek,smi-address = <8>; + enet-phy-pair-order = <1>; }; &phy25 { realtek,smi-address = <9>; + enet-phy-pair-order = <1>; }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts index dc8e55b772..2f8ea1b9fa 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts @@ -10,8 +10,10 @@ &phy24 { realtek,smi-address = <8>; + enet-phy-pair-order = <1>; }; &phy25 { realtek,smi-address = <9>; + enet-phy-pair-order = <1>; }; From 2948dbebbfb2111af17c8c4152462132e4ff25d5 Mon Sep 17 00:00:00 2001 From: Yanase Yuki Date: Wed, 24 Dec 2025 17:05:38 +0900 Subject: [PATCH 65/88] mac80211: use OpenWrt mirror for b43 fw downloads lwfinger dot com seems drop-catched and now redirects to potentially unsafe website. This commit also drops no longer available 6.30 firmware. Fixes: https://github.com/openwrt/openwrt/issues/19436 Signed-off-by: Yanase Yuki Link: https://github.com/openwrt/openwrt/pull/21269 Signed-off-by: Hauke Mehrtens --- package/kernel/mac80211/broadcom.mk | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/package/kernel/mac80211/broadcom.mk b/package/kernel/mac80211/broadcom.mk index 7bc8aa6dc1..15112df4a8 100644 --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk @@ -35,14 +35,6 @@ config-$(CONFIG_PACKAGE_BRCM80211_DEBUG) += BRCMDBG config-$(CONFIG_LEDS_TRIGGERS) += B43_LEDS B43LEGACY_LEDS #Broadcom firmware -ifneq ($(CONFIG_B43_FW_6_30),) - PKG_B43_FWV4_NAME:=broadcom-wl - PKG_B43_FWV4_VERSION:=6.30.163.46 - PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).wl_apsta.o - PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2 - PKG_B43_FWV4_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/ - PKG_B43_FWV4_HASH:=a07c3b6b277833c7dbe61daa511f908cd66c5e2763eb7a0859abc36cd9335c2d -else ifneq ($(CONFIG_B43_FW_5_10),) PKG_B43_FWV4_NAME:=broadcom-wl PKG_B43_FWV4_VERSION:=5.10.56.27.3 @@ -64,7 +56,7 @@ ifneq ($(CONFIG_B43_FW_5_100_138),) PKG_B43_FWV4_VERSION:=5.100.138 PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)/linux/wl_apsta.o PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2 - PKG_B43_FWV4_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/ + PKG_B43_FWV4_SOURCE_URL:=@OPENWRT PKG_B43_FWV4_HASH:=f1e7067aac5b62b67b8b6e4c517990277804339ac16065eb13c731ff909ae46f else PKG_B43_FWV4_NAME:=broadcom-wl @@ -164,15 +156,6 @@ config PACKAGE_B43_USE_BCMA If unsure, select the this firmware. - config B43_FW_6_30 - bool "Firmware 784.2 from driver 6.30.163.46 (experimental)" - help - Newer experimental firmware for BCM43xx devices. - - This firmware is mostly untested. - - If unsure, select the "stable" firmware. - config B43_OPENFIRMWARE bool "Open FirmWare for WiFi networks" help @@ -367,7 +350,7 @@ PKG_BRCMSMAC_FW_NAME:=broadcom-wl PKG_BRCMSMAC_FW_VERSION:=5.100.138 PKG_BRCMSMAC_FW_OBJECT:=$(PKG_BRCMSMAC_FW_NAME)-$(PKG_BRCMSMAC_FW_VERSION)/linux/wl_apsta.o PKG_BRCMSMAC_FW_SOURCE:=$(PKG_BRCMSMAC_FW_NAME)-$(PKG_BRCMSMAC_FW_VERSION).tar.bz2 -PKG_BRCMSMAC_FW_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/ +PKG_BRCMSMAC_FW_SOURCE_URL:=@OPENWRT PKG_BRCMSMAC_FW_HASH:=f1e7067aac5b62b67b8b6e4c517990277804339ac16065eb13c731ff909ae46f define Download/brcmsmac From 200158208ec50eb325fea6c696ea88902c1383e5 Mon Sep 17 00:00:00 2001 From: Rustam Adilov Date: Wed, 18 Feb 2026 21:33:07 +0500 Subject: [PATCH 66/88] realtek: thermal: extend the driver to support rtl960x This commit adds support for RTL9607C / RTL8198D thermal controller. Based on the Realtek SDK code. Signed-off-by: Rustam Adilov Link: https://github.com/openwrt/openwrt/pull/22081 Signed-off-by: Hauke Mehrtens --- .../drivers/thermal/realtek-thermal.c | 45 +++++++++++++++++++ .../330-add-realtek-thernal-driver.patch | 4 +- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c b/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c index 353860b005..e2cbf0c89a 100644 --- a/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c +++ b/target/linux/realtek/files-6.12/drivers/thermal/realtek-thermal.c @@ -45,6 +45,16 @@ #define RTL9300_COMPARE_DLY_SHIFT (0) #define RTL9300_COMPARE_DLY_MASK GENMASK(RTL9300_COMPARE_DLY_SHIFT + 15, RTL9300_COMPARE_DLY_SHIFT) +#define RTL9607_THERMAL_CTRL_0 0x150 +#define RTL9607_REG_PPOW BIT(29) +#define RTL9607_THERMAL_CTRL_2 0x158 +#define RTL9607_THERMAL_CTRL_5 0x164 +#define RTL9607_THERMAL_STS_0 0x178 +#define RTL9607_TEMP_OUT_MASK GENMASK(18, 0) +#define RTL9607_TEMP_OUT_SIGN BIT(18) +#define RTL9607_TEMP_OUT_INT GENMASK(17, 10) +#define RTL9607_TEMP_OUT_FLOAT GENMASK(9, 0) + struct realtek_thermal_priv { struct regmap *regmap; bool enabled; @@ -144,6 +154,40 @@ static const struct thermal_zone_device_ops rtl9300_ops = { .get_temp = rtl9300_get_temp, }; +static void rtl9607_thermal_init(struct realtek_thermal_priv *priv) +{ + priv->enabled = !regmap_update_bits(priv->regmap, RTL9607_THERMAL_CTRL_0, RTL9607_REG_PPOW, RTL9607_REG_PPOW); +} + +static int rtl9607_get_temp(struct thermal_zone_device *tz, int *res) +{ + struct realtek_thermal_priv *priv = thermal_zone_device_priv(tz); + int offset = thermal_zone_get_offset(tz); + int slope = thermal_zone_get_slope(tz); + u32 val; + int ret; + + if (!priv->enabled) + rtl9607_thermal_init(priv); + + ret = regmap_read(priv->regmap, RTL9607_THERMAL_STS_0, &val); + if (ret) + return ret; + + /* + * The temperature sensor output consist of sign at bit 18, integer part at bits 17~10 + * and fractional point with 0.5 scaling at bits 9~0. + * For simplicity, we only care about the integer part. + */ + *res = FIELD_GET(RTL9607_TEMP_OUT_INT, val) * slope + offset; + + return 0; +} + +static const struct thermal_zone_device_ops rtl9607_ops = { + .get_temp = rtl9607_get_temp, +}; + static int realtek_thermal_probe(struct platform_device *pdev) { struct realtek_thermal_priv *priv; @@ -171,6 +215,7 @@ static const struct of_device_id realtek_sensor_ids[] = { { .compatible = "realtek,rtl8380-thermal", .data = &rtl8380_ops, }, { .compatible = "realtek,rtl8390-thermal", .data = &rtl8390_ops, }, { .compatible = "realtek,rtl9300-thermal", .data = &rtl9300_ops, }, + { .compatible = "realtek,rtl9607-thermal", .data = &rtl9607_ops, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, realtek_sensor_ids); diff --git a/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch b/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch index 055ee845d0..ab466ba6d2 100644 --- a/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch +++ b/target/linux/realtek/patches-6.12/330-add-realtek-thernal-driver.patch @@ -6,10 +6,10 @@ +config REALTEK_THERMAL + tristate "Realtek RTL838x and RTL930x thermal sensor support" -+ depends on RTL838X || RTL839X || RTL930X || COMPILE_TEST ++ depends on RTL838X || RTL839X || RTL930X || RTL960X || COMPILE_TEST + depends on THERMAL_OF + help -+ Support thermal sensor in Realtek RTL838x, RTL839x and RTL930x SoCs ++ Support thermal sensor in Realtek RTL838x, RTL839x, RTL930x and RTL960x SoCs + endif --- a/drivers/thermal/Makefile From 7824dbcab815a6fa605b6cecf94c200b9d3973f7 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sun, 15 Mar 2026 14:56:09 +0800 Subject: [PATCH 67/88] mac80211: broadcom: fix Makefile syntax error Remove unmatched endif. fixes: 2948dbebbfb2 ("mac80211: use OpenWrt mirror for b43 fw downloads") Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22430 Signed-off-by: Robert Marko --- package/kernel/mac80211/broadcom.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/package/kernel/mac80211/broadcom.mk b/package/kernel/mac80211/broadcom.mk index 15112df4a8..4cee78c5ea 100644 --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk @@ -68,7 +68,6 @@ else endif endif endif -endif ifneq ($(CONFIG_B43_OPENFIRMWARE),) PKG_B43_FWV4_NAME:=broadcom-wl PKG_B43_FWV4_VERSION:=5.2 From 36a818b41328b107022c7413d1714189b28ca2b1 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sun, 15 Mar 2026 21:05:08 +0800 Subject: [PATCH 68/88] qualcommax: move EAP623 Outdoor dts to the correct folder The device dts files were moved to the dedicated directory in commit a66e30631c87 ("qualcommax: move Device DTS to dedicated DTS directory"), which resulted in a merge conflict. Fixes: d755c49f7a8a ("qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible") Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22433 Signed-off-by: Robert Marko --- .../arm64/boot/dts/qcom => dts}/ipq6018-eap623-outdoor-hd-v1.dts | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename target/linux/qualcommax/{files/arch/arm64/boot/dts/qcom => dts}/ipq6018-eap623-outdoor-hd-v1.dts (100%) diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts b/target/linux/qualcommax/dts/ipq6018-eap623-outdoor-hd-v1.dts similarity index 100% rename from target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623-outdoor-hd-v1.dts rename to target/linux/qualcommax/dts/ipq6018-eap623-outdoor-hd-v1.dts From 1477292634451c55a47905739d3058ea4595430f Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 16 Mar 2026 00:51:04 +0100 Subject: [PATCH 69/88] jsonfilter: update to Git HEAD (2026-03-16) b17c31f8a2fd main: exit 1 on getopt() errors e3f6a4160ba2 main: exit 1 when showing the usage d67578d6b7f7 main: fix stdin parsing after option deferral b9034210bd33 main: fix multiple -e/-t expressions after option deferral Fixes: https://github.com/openwrt/openwrt/issues/22439 Signed-off-by: Hauke Mehrtens --- package/utils/jsonfilter/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/utils/jsonfilter/Makefile b/package/utils/jsonfilter/Makefile index d0aea0d92a..afe890cdad 100644 --- a/package/utils/jsonfilter/Makefile +++ b/package/utils/jsonfilter/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/jsonpath.git -PKG_SOURCE_DATE:=2026-03-12 -PKG_SOURCE_VERSION:=e086664e6a570630e8feba889482f174a9a8715e -PKG_MIRROR_HASH:=e00e8f5ca44d156284375a32e03529c29fdaeac1cbd276c214879aaa0a502548 +PKG_SOURCE_DATE:=2026-03-16 +PKG_SOURCE_VERSION:=b9034210bd331749673416c6bf389cccd4e23610 +PKG_MIRROR_HASH:=e8616b3eee53c6dd3420a7d800337e13a61e1333dfbd8551b50ab15bafd94a0e CMAKE_INSTALL:=1 PKG_MAINTAINER:=Jo-Philipp Wich From de2b830dc4ec3d2a7eab0799d7a473325efb35b4 Mon Sep 17 00:00:00 2001 From: Qingfang Deng Date: Thu, 5 Mar 2026 15:23:42 +0800 Subject: [PATCH 70/88] mvebu: select CPU_LITTLE_ENDIAN When running `make kernel_menuconfig`, CPU_BIG_ENDIAN is selected by default, resulting in a non-bootable image. Add CPU_LITTLE_ENDIAN to avoid that. Signed-off-by: Qingfang Deng Link: https://github.com/openwrt/openwrt/pull/22282 Signed-off-by: Hauke Mehrtens --- target/linux/mvebu/config-6.12 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mvebu/config-6.12 b/target/linux/mvebu/config-6.12 index 668a415b12..6bb99af885 100644 --- a/target/linux/mvebu/config-6.12 +++ b/target/linux/mvebu/config-6.12 @@ -89,6 +89,7 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_PABRT_V7=y CONFIG_CPU_PJ4B=y From 91bc5ea271881e3675af5560b1e6de48ae89dc3c Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sat, 28 Feb 2026 19:25:07 +0800 Subject: [PATCH 71/88] ramips: mt76x8: add missing clocks to PWM peripheral The upstream MediaTek PWM driver requires these clock sources to work properly. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22214 Signed-off-by: Hauke Mehrtens --- target/linux/ramips/dts/mt7628an.dtsi | 9 ++++ ...ink-mtmips-add-pwm-clocks-for-mt76x8.patch | 42 +++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi index 7c37b952f3..bf39ec307b 100644 --- a/target/linux/ramips/dts/mt7628an.dtsi +++ b/target/linux/ramips/dts/mt7628an.dtsi @@ -232,6 +232,15 @@ reg = <0x5000 0x1000>; #pwm-cells = <2>; + clocks = <&sysc MT76X8_CLK_PWM_TOP>, + <&sysc MT76X8_CLK_PWM_MAIN>, + <&sysc MT76X8_CLK_PWM_CH1>, + <&sysc MT76X8_CLK_PWM_CH2>, + <&sysc MT76X8_CLK_PWM_CH3>, + <&sysc MT76X8_CLK_PWM_CH4>; + clock-names = "top", "main", + "pwm1", "pwm2", "pwm3", "pwm4"; + pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; diff --git a/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch b/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch new file mode 100644 index 0000000000..94880f7e07 --- /dev/null +++ b/target/linux/ramips/patches-6.12/101-clk-ralink-mtmips-add-pwm-clocks-for-mt76x8.patch @@ -0,0 +1,42 @@ +From f0300b3fc74a71742eee50ac596166b5780e0df6 Mon Sep 17 00:00:00 2001 +From: Shiji Yang +Date: Tue, 24 Feb 2026 19:19:14 +0800 +Subject: [PATCH] clk: ralink: mtmips: add pwm clocks for mt76x8 + +Signed-off-by: Shiji Yang +--- + drivers/clk/ralink/clk-mtmips.c | 8 +++++++- + include/dt-bindings/clock/mediatek,mtmips-sysc.h | 6 ++++++ + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/drivers/clk/ralink/clk-mtmips.c ++++ b/drivers/clk/ralink/clk-mtmips.c +@@ -222,7 +222,13 @@ static struct mtmips_clk mt76x8_pherip_c + { CLK_PERIPH("10000d00.uart1", "periph") }, + { CLK_PERIPH("10000e00.uart2", "periph") }, + { CLK_PERIPH("10130000.mmc", "sdhc") }, +- { CLK_PERIPH("10300000.wmac", "xtal") } ++ { CLK_PERIPH("10300000.wmac", "xtal") }, ++ { CLK_PERIPH("10005000.pwm-top", "periph") }, ++ { CLK_PERIPH("10005000.pwm-main", "periph") }, ++ { CLK_PERIPH("10005000.pwm-ch1", "periph") }, ++ { CLK_PERIPH("10005000.pwm-ch2", "periph") }, ++ { CLK_PERIPH("10005000.pwm-ch3", "periph") }, ++ { CLK_PERIPH("10005000.pwm-ch4", "periph") } + }; + + static int mtmips_register_pherip_clocks(struct device_node *np, +--- a/include/dt-bindings/clock/mediatek,mtmips-sysc.h ++++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h +@@ -126,5 +126,11 @@ + #define MT76X8_CLK_UART2 15 + #define MT76X8_CLK_MMC 16 + #define MT76X8_CLK_WMAC 17 ++#define MT76X8_CLK_PWM_TOP 18 ++#define MT76X8_CLK_PWM_MAIN 19 ++#define MT76X8_CLK_PWM_CH1 20 ++#define MT76X8_CLK_PWM_CH2 21 ++#define MT76X8_CLK_PWM_CH3 22 ++#define MT76X8_CLK_PWM_CH4 23 + + #endif /* _DT_BINDINGS_CLK_MTMIPS_H */ From 4f61fe811880844d7855deda0c3b434cf7c9f309 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sat, 28 Feb 2026 19:25:29 +0800 Subject: [PATCH 72/88] ramips: mt76x8: adapt to upstream PWM driver Fix register offsets and clock sources for MT7628 hardware variant. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22214 Signed-off-by: Hauke Mehrtens --- ...set-mt7628-pwm45_fixup-flag-to-false.patch | 25 +++++++ ...-correct-mt7628-clock-source-setting.patch | 65 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch create mode 100644 target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch diff --git a/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch b/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch new file mode 100644 index 0000000000..130b877737 --- /dev/null +++ b/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch @@ -0,0 +1,25 @@ +From 2ff84ce933de37e91d132553a2555c4b4e9dedc8 Mon Sep 17 00:00:00 2001 +From: Shiji Yang +Date: Tue, 24 Feb 2026 15:32:42 +0800 +Subject: [PATCH 1/2] pwm: mediatek: set mt7628 pwm45_fixup flag to false + +According to the programing guide, mt7628 has generic register layout +like most other hardware revisions. We should not set pwm45_fixup flag +for it. + +Signed-off-by: Shiji Yang +--- + drivers/pwm/pwm-mediatek.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -324,7 +324,7 @@ static const struct pwm_mediatek_of_data + + static const struct pwm_mediatek_of_data mt7628_pwm_data = { + .num_pwms = 4, +- .pwm45_fixup = true, ++ .pwm45_fixup = false, + .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, + }; diff --git a/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch b/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch new file mode 100644 index 0000000000..498eb7fc63 --- /dev/null +++ b/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch @@ -0,0 +1,65 @@ +From 1d846d6f80f24066747dac57440c84502a8a1cd3 Mon Sep 17 00:00:00 2001 +From: Shiji Yang +Date: Tue, 24 Feb 2026 16:19:54 +0800 +Subject: [PATCH 2/2] pwm: mediatek: correct mt7628 clock source setting + +PWMCON register Bit(3) is used to configure whether to pre divide +the clock source. Most revisions clear this bit to disable frequency +division. However, mt7628 needs to set this bit. Hence, we introduce +a new clksel_fixup flag to correctly configure the clock source for +mt7628. + +Signed-off-by: Shiji Yang +--- + drivers/pwm/pwm-mediatek.c | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -21,6 +21,8 @@ + + /* PWM registers and bits definitions */ + #define PWMCON 0x00 ++#define PWMCON_CLKSEL BIT(3) ++#define PWMCON_OLD_PWM_MODE BIT(15) + #define PWMHDUR 0x04 + #define PWMLDUR 0x08 + #define PWMGDUR 0x0c +@@ -35,6 +37,7 @@ + + struct pwm_mediatek_of_data { + unsigned int num_pwms; ++ bool clksel_fixup; + bool pwm45_fixup; + bool has_ck_26m_sel; + const unsigned int *reg_offset; +@@ -141,6 +144,7 @@ static int pwm_mediatek_config(struct pw + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); + u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, + reg_thres = PWMTHRES; ++ u32 con_val; + unsigned long clk_rate; + u64 resolution; + int ret; +@@ -191,7 +195,12 @@ static int pwm_mediatek_config(struct pw + + cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); + +- pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); ++ con_val = PWMCON_OLD_PWM_MODE | clkdiv; ++ /* Set BIT(3) to disable clock division */ ++ if (pc->soc->clksel_fixup) ++ con_val |= PWMCON_CLKSEL; ++ ++ pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, con_val); + pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1); + + if (cnt_duty) { +@@ -324,6 +333,7 @@ static const struct pwm_mediatek_of_data + + static const struct pwm_mediatek_of_data mt7628_pwm_data = { + .num_pwms = 4, ++ .clksel_fixup = true, + .pwm45_fixup = false, + .has_ck_26m_sel = false, + .reg_offset = mtk_pwm_reg_offset_v1, From de8b01c0a5ccdb302cdb283a737c43ddccd44f86 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sat, 28 Feb 2026 19:26:03 +0800 Subject: [PATCH 73/88] ramips: mt76x8: add new upstream PWM driver module This is the generic PWM framework driver for Mediatek SoC. Now this module is ready for MT7628. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22214 Signed-off-by: Hauke Mehrtens --- target/linux/ramips/modules.mk | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk index 5175be85c0..a038f2f0df 100644 --- a/target/linux/ramips/modules.mk +++ b/target/linux/ramips/modules.mk @@ -27,6 +27,23 @@ endef $(eval $(call KernelPackage,mmc-mtk)) +define KernelPackage/pwm-mediatek + SUBMENU:=Other modules + TITLE:=MediaTek PWM support + DEPENDS:=@TARGET_ramips_mt76x8 + KCONFIG:= \ + CONFIG_PWM=y \ + CONFIG_PWM_MEDIATEK + FILES:=$(LINUX_DIR)/drivers/pwm/pwm-mediatek.ko + AUTOLOAD:=$(call AutoProbe,pwm-mediatek) +endef + +define KernelPackage/pwm-mediatek/description + Generic PWM framework driver for Mediatek SoC. +endef + +$(eval $(call KernelPackage,pwm-mediatek)) + define KernelPackage/pwm-mediatek-ramips SUBMENU:=Other modules TITLE:=MT7628 PWM From 4286dea96b0c2f8d929621d49584f2110de252ff Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Sat, 28 Feb 2026 19:26:47 +0800 Subject: [PATCH 74/88] ramips: mt76x8: drop downstream PWM driver support Developers no longer maintain this driver. And it has been replaced by the new upstream implementation. It's time to say goodbye. Signed-off-by: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22214 Signed-off-by: Hauke Mehrtens --- target/linux/ramips/modules.mk | 19 -- .../845-pwm-add-mediatek-support.patch | 227 ------------------ 2 files changed, 246 deletions(-) delete mode 100644 target/linux/ramips/patches-6.12/845-pwm-add-mediatek-support.patch diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk index a038f2f0df..7221636009 100644 --- a/target/linux/ramips/modules.mk +++ b/target/linux/ramips/modules.mk @@ -44,25 +44,6 @@ endef $(eval $(call KernelPackage,pwm-mediatek)) -define KernelPackage/pwm-mediatek-ramips - SUBMENU:=Other modules - TITLE:=MT7628 PWM - DEPENDS:=@(TARGET_ramips_mt76x8) - KCONFIG:= \ - CONFIG_PWM=y \ - CONFIG_PWM_MEDIATEK_RAMIPS \ - CONFIG_PWM_SYSFS=y - FILES:= \ - $(LINUX_DIR)/drivers/pwm/pwm-mediatek-ramips.ko - AUTOLOAD:=$(call AutoProbe,pwm-mediatek-ramips) -endef - -define KernelPackage/pwm-mediatek-ramips/description - Kernel modules for MediaTek Pulse Width Modulator -endef - -$(eval $(call KernelPackage,pwm-mediatek-ramips)) - define KernelPackage/sdhci-mt7620 SUBMENU:=Other modules TITLE:=MT7620 SDCI diff --git a/target/linux/ramips/patches-6.12/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-6.12/845-pwm-add-mediatek-support.patch deleted file mode 100644 index 1aa3a26e97..0000000000 --- a/target/linux/ramips/patches-6.12/845-pwm-add-mediatek-support.patch +++ /dev/null @@ -1,227 +0,0 @@ -From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:16:50 +0100 -Subject: [PATCH 52/53] pwm: add mediatek support - -Signed-off-by: John Crispin ---- - drivers/pwm/Kconfig | 9 +++ - drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 183 insertions(+) - create mode 100644 drivers/pwm/pwm-mediatek.c - ---- a/drivers/pwm/Kconfig -+++ b/drivers/pwm/Kconfig -@@ -452,6 +452,15 @@ config PWM_MICROCHIP_CORE - To compile this driver as a module, choose M here: the module - will be called pwm-microchip-core. - -+config PWM_MEDIATEK_RAMIPS -+ tristate "Mediatek PWM support" -+ depends on RALINK && OF -+ help -+ Generic PWM framework driver for Mediatek ARM SoC. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called pwm-mxs. -+ - config PWM_MXS - tristate "Freescale MXS PWM support" - depends on ARCH_MXS || COMPILE_TEST ---- a/drivers/pwm/Makefile -+++ b/drivers/pwm/Makefile -@@ -38,6 +38,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p - obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o - obj-$(CONFIG_PWM_MESON) += pwm-meson.o - obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o -+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o - obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o - obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o - obj-$(CONFIG_PWM_MXS) += pwm-mxs.o ---- /dev/null -+++ b/drivers/pwm/pwm-mediatek-ramips.c -@@ -0,0 +1,183 @@ -+/* -+ * Mediatek Pulse Width Modulator driver -+ * -+ * Copyright (C) 2015 John Crispin -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NUM_PWM 4 -+ -+/* PWM registers and bits definitions */ -+#define PWMCON 0x00 -+#define PWMHDUR 0x04 -+#define PWMLDUR 0x08 -+#define PWMGDUR 0x0c -+#define PWMWAVENUM 0x28 -+#define PWMDWIDTH 0x2c -+#define PWMTHRES 0x30 -+ -+/** -+ * struct mtk_pwm_chip - struct representing pwm chip -+ * -+ * @mmio_base: base address of pwm chip -+ * @chip: linux pwm chip representation -+ */ -+struct mtk_pwm_chip { -+ void __iomem *mmio_base; -+ struct pwm_chip chip; -+}; -+ -+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) -+{ -+ return container_of(chip, struct mtk_pwm_chip, chip); -+} -+ -+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, -+ unsigned long offset) -+{ -+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, -+ unsigned int num, unsigned long offset, -+ unsigned long val) -+{ -+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, -+ int duty_ns, int period_ns) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 resolution = 100 / 4; -+ u32 clkdiv = 0; -+ -+ while (period_ns / resolution > 8191) { -+ clkdiv++; -+ resolution *= 2; -+ } -+ -+ if (clkdiv > 7) -+ return -1; -+ -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); -+ return 0; -+} -+ -+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val |= BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+ -+ return 0; -+} -+ -+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val &= ~BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+} -+ -+static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, -+ const struct pwm_state *state) -+{ -+ int err; -+ bool enabled = pwm->state.enabled; -+ -+ if (!state->enabled) { -+ if (enabled) -+ mtk_pwm_disable(chip, pwm); -+ -+ return 0; -+ } -+ -+ err = mtk_pwm_config(pwm->chip, pwm, -+ state->duty_cycle, state->period); -+ if (err) -+ return err; -+ -+ if (!enabled) -+ err = mtk_pwm_enable(chip, pwm); -+ -+ return err; -+} -+ -+static const struct pwm_ops mtk_pwm_ops = { -+ .apply = mtk_pwm_apply, -+}; -+ -+static int mtk_pwm_probe(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc; -+ -+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); -+ if (!pc) -+ return -ENOMEM; -+ -+ pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pc->mmio_base)) -+ return PTR_ERR(pc->mmio_base); -+ -+ pc->chip.dev = pdev->dev; -+ pc->chip.ops = &mtk_pwm_ops; -+ pc->chip.npwm = NUM_PWM; -+ -+ platform_set_drvdata(pdev, pc); -+ -+ return devm_pwmchip_add(&pdev->dev, &pc->chip); -+} -+ -+static void mtk_pwm_remove(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < NUM_PWM; i++) -+ pwm_disable(&pc->chip.pwms[i]); -+} -+ -+static const struct of_device_id mtk_pwm_of_match[] = { -+ { .compatible = "mediatek,mt7628-pwm" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); -+ -+static struct platform_driver mtk_pwm_driver = { -+ .driver = { -+ .name = "mtk-pwm", -+ .of_match_table = mtk_pwm_of_match, -+ }, -+ .probe = mtk_pwm_probe, -+ .remove_new = mtk_pwm_remove, -+}; -+ -+module_platform_driver(mtk_pwm_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_ALIAS("platform:mtk-pwm"); From 97238c793b9f160be21b23b8bf39897d7f354230 Mon Sep 17 00:00:00 2001 From: Julius Schwartzenberg Date: Thu, 19 Feb 2026 19:08:59 +0100 Subject: [PATCH 75/88] ipq40xx: enable Devolo Magic 2 WiFi next Note that for working G.hn support some packages need to be extracted from the Devolo firmware. Signed-off-by: Julius Schwartzenberg Link: https://github.com/openwrt/openwrt/pull/22123 Signed-off-by: Hauke Mehrtens --- target/linux/ipq40xx/image/generic.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index ee52e1840b..c93c377954 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -392,7 +392,6 @@ define Device/devolo_magic-2-wifi-next IMAGE_SIZE := 26624k IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata - DEFAULT := n endef TARGET_DEVICES += devolo_magic-2-wifi-next From 708883c9d2c0d79100b561fda69abf897f691f2d Mon Sep 17 00:00:00 2001 From: Andrew LaMarche Date: Thu, 12 Mar 2026 13:22:03 +0000 Subject: [PATCH 76/88] airoha: an7581: fix w1700k fan script W1700K fan script is missing the #!/bin/sh /etc/rc.common shebang and requires execution bits set. Also, set the fallback to hwmon 3 instead of 5, since the new RTL PHY driver was not merged. Signed-off-by: Andrew LaMarche Link: https://github.com/openwrt/openwrt/pull/22391 Signed-off-by: Robert Marko --- target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) mode change 100644 => 100755 target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan diff --git a/target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan b/target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan old mode 100644 new mode 100755 index 0705402ea7..ab9eeca83a --- a/target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan +++ b/target/linux/airoha/an7581/base-files/etc/init.d/airoha_fan @@ -1,3 +1,4 @@ +#!/bin/sh /etc/rc.common # # Copyright (C) 2025 openwrt.org # @@ -14,7 +15,7 @@ find_nct7802() return fi done - echo "/sys/class/hwmon/hwmon5" # fallback + echo "/sys/class/hwmon/hwmon3" # fallback } boot() From 598c4b7fde1240d8d64386e4162a41270f865c30 Mon Sep 17 00:00:00 2001 From: Hannu Nyman Date: Sat, 14 Mar 2026 22:40:30 +0200 Subject: [PATCH 77/88] apk: add help text for 'apk add --force-reinstall' Add a help text for the new --force-reinstall option, so that users will actually find the new option. (Also refresh patches) Improves: 91cff1a "apk: add --force-reinstall option" Signed-off-by: Hannu Nyman Link: https://github.com/openwrt/openwrt/pull/22426 Signed-off-by: Robert Marko --- package/system/apk/Makefile | 2 +- .../apk/patches/0002-openwrt-wiki-help-link.patch | 4 +--- .../0100-add-add-force-reinstall-option.patch | 13 +++++++++++++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/package/system/apk/Makefile b/package/system/apk/Makefile index 2cea412dd5..df65bc082e 100644 --- a/package/system/apk/Makefile +++ b/package/system/apk/Makefile @@ -1,7 +1,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=apk -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git PKG_SOURCE_PROTO:=git diff --git a/package/system/apk/patches/0002-openwrt-wiki-help-link.patch b/package/system/apk/patches/0002-openwrt-wiki-help-link.patch index 587d3c79ff..dd6466709e 100644 --- a/package/system/apk/patches/0002-openwrt-wiki-help-link.patch +++ b/package/system/apk/patches/0002-openwrt-wiki-help-link.patch @@ -1,8 +1,6 @@ -diff --git a/src/genhelp_apk.lua b/src/genhelp_apk.lua -index a62e84d22ed5..a97264f6ab3c 100644 --- a/src/genhelp_apk.lua +++ b/src/genhelp_apk.lua -@@ -65,7 +65,7 @@ local function render_options(doc, out, options) +@@ -65,7 +65,7 @@ local function render_options(doc, out, end local function render_footer(doc, out) diff --git a/package/system/apk/patches/0100-add-add-force-reinstall-option.patch b/package/system/apk/patches/0100-add-add-force-reinstall-option.patch index 9d8c4c6c67..829184bea5 100644 --- a/package/system/apk/patches/0100-add-add-force-reinstall-option.patch +++ b/package/system/apk/patches/0100-add-add-force-reinstall-option.patch @@ -46,3 +46,16 @@ Signed-off-by: Felix Fietkau } r = apk_solver_commit(db, 0, world); +--- a/doc/apk-add.8.scd ++++ b/doc/apk-add.8.scd +@@ -30,6 +30,10 @@ To later upgrade or downgrade back to a + *apk add* supports the commit options described in *apk*(8), as well as the + following options: + ++*--force-reinstall* ++ Allow reinstalling already-installed packages without a version ++ change. Only the named packages are reinstalled, not dependencies. ++ + *--initdb* + Initialize a new package database. + From 7d2c244646d9caf895e5e03ea8f47f4089c2abec Mon Sep 17 00:00:00 2001 From: Kenneth Kasilag Date: Mon, 16 Mar 2026 09:25:53 +0000 Subject: [PATCH 78/88] airoha: rename kmod-pwm-an7581 to kmod-pwm-airoha Certain targets for an7581 and an7583 referred to kmod-pwm-airoha; however in the target modules makefile the module is referred to as kmod-pwm-an7581, causing buildbot to fail. Change the name of kmod-pwm-an7581 to kmod-pwm-airoha to resolve this. Signed-off-by: Kenneth Kasilag Link: https://github.com/openwrt/openwrt/pull/22445 Signed-off-by: Robert Marko --- target/linux/airoha/modules.mk | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/linux/airoha/modules.mk b/target/linux/airoha/modules.mk index cbefe38996..3a038f57d0 100644 --- a/target/linux/airoha/modules.mk +++ b/target/linux/airoha/modules.mk @@ -20,10 +20,10 @@ endef $(eval $(call KernelPackage,i2c-an7581)) -define KernelPackage/pwm-an7581 +define KernelPackage/pwm-airoha SUBMENU:=$(OTHER_MENU) - TITLE:=Airoha EN7581 PWM - DEPENDS:=@(TARGET_airoha_an7581) + TITLE:=Airoha AN7581 and AN7583 PWM + DEPENDS:=@TARGET_airoha_an7581||TARGET_airoha_an7583 KCONFIG:= \ CONFIG_PWM=y \ CONFIG_PWM_AIROHA=y \ @@ -33,10 +33,10 @@ define KernelPackage/pwm-an7581 AUTOLOAD:=$(call AutoProbe,pwm-airoha) endef -define KernelPackage/pwm-an7581/description +define KernelPackage/pwm-airoha/description Kernel module to use the PWM channel on Airoha SoC endef -$(eval $(call KernelPackage,pwm-an7581)) +$(eval $(call KernelPackage,pwm-airoha)) From 045deec7e92065d250c1884c8cd1dfcc7a4fcd5d Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 15 Mar 2026 17:47:15 +0100 Subject: [PATCH 79/88] wifi: mt76: mt7915: set mt76 specific PS flag mt76 tracks the PSM state of a sta internally with a wcid flag. TX to such clients is skipped based on the presence of this flag. This flag was not added to the PS state notify handler for MT7915 chips. Without this flag, mt76 queues pending frames to the hardware, accounting for airtime when a PSM notification is received while in a TX iteration. Set the PS flag for the STA WCID to prevent this from happening. TX gets skipped in presence of this flag. Link: https://patchwork.kernel.org/project/linux-wireless/patch/20260313112502.2026974-1-mail@david-bauer.net/ Signed-off-by: David Bauer --- package/kernel/mt76/Makefile | 2 +- ...t76-mt7915-set-mt76-specific-PS-flag.patch | 42 +++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) create mode 100644 package/kernel/mt76/patches/0001-wifi-mt76-mt7915-set-mt76-specific-PS-flag.patch diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index 5245e7868a..bedcba4275 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -1,7 +1,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mt76 -PKG_RELEASE=1 +PKG_RELEASE=2 PKG_LICENSE:=BSD-3-Clause-Clear PKG_LICENSE_FILES:= diff --git a/package/kernel/mt76/patches/0001-wifi-mt76-mt7915-set-mt76-specific-PS-flag.patch b/package/kernel/mt76/patches/0001-wifi-mt76-mt7915-set-mt76-specific-PS-flag.patch new file mode 100644 index 0000000000..b904cddf33 --- /dev/null +++ b/package/kernel/mt76/patches/0001-wifi-mt76-mt7915-set-mt76-specific-PS-flag.patch @@ -0,0 +1,42 @@ +From e78688a4f44478a9270813ac494fc548ed6b3be9 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 13 Mar 2026 12:19:37 +0100 +Subject: [PATCH] wifi: mt76: mt7915: set mt76 specific PS flag + +mt76 tracks the PSM state of a sta internally with a wcid flag. TX to +such clients is skipped based on the presence of this flag. + +This flag was not added to the PS state notify handler for MT7915 chips. +Without this flag, mt76 queues pending frames to the hardware, +accounting for airtime when a PSM notification is received while in a TX +iteration. + +Set the PS flag for the STA WCID to prevent this from happening. TX gets +skipped in presence of this flag. + +Link: https://patchwork.kernel.org/project/linux-wireless/patch/20260313112502.2026974-1-mail@david-bauer.net/ + +Signed-off-by: David Bauer +--- + mt7915/mcu.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/mt7915/mcu.c b/mt7915/mcu.c +index 6625f905..52c89d2b 100644 +--- a/mt7915/mcu.c ++++ b/mt7915/mcu.c +@@ -421,6 +421,11 @@ static void mt7915_mcu_rx_ps_sync(struct mt7915_dev *dev, struct sk_buff *skb) + if (!sta) + goto out; + ++ if (p->ps_bit) ++ set_bit(MT_WCID_FLAG_PS, &wcid->flags); ++ else ++ clear_bit(MT_WCID_FLAG_PS, &wcid->flags); ++ + ieee80211_sta_ps_transition_ni(sta, !!p->ps_bit); + + out: +-- +2.51.0 + From d405685b44c61b8d0f1ec046d58adfd8b1426893 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 16 Mar 2026 02:40:09 +0100 Subject: [PATCH 80/88] lantiq: adapt gpio-stp-xway node name to get clock The MIPS code assigns the clock node based on the device tree node name. This name was renamed with kernel 6.12.58 and v6.6.117. Adapt our out of tree device tree files to this rename to fix loading the STP GPIO driver. Without this fix the driver fails like this: ``` [ 0.320000] gpio-stp-xway 1e100bb0.stp: Failed to get clock [ 0.330000] gpio-stp-xway 1e100bb0.stp: probe with driver gpio-stp-xway failed with error -2 ``` Link: https://git.kernel.org/linus/b0d04fe6a633ada2c7bc1b5ddd011cbd85961868 Fixes: https://github.com/openwrt/openwrt/issues/21697 Co-Authored-By: Shiji Yang Link: https://github.com/openwrt/openwrt/pull/22444 Signed-off-by: Hauke Mehrtens --- target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi | 2 +- target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi index 25329745cf..fdea51192b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi @@ -314,7 +314,7 @@ }; }; - stp: stp@e100bb0 { + stp: gpio@e100bb0 { #gpio-cells = <2>; compatible = "lantiq,gpio-stp-xway"; gpio-controller; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi index 10fb8d4934..ffad822690 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -354,7 +354,7 @@ }; }; - stp: stp@e100bb0 { + stp: gpio@e100bb0 { status = "disabled"; compatible = "lantiq,gpio-stp-xway"; reg = <0xe100bb0 0x40>; From a15b224e8309fa203dcc23fe95c8cf8dd748255d Mon Sep 17 00:00:00 2001 From: Oliver Sedlbauer Date: Mon, 16 Mar 2026 10:27:38 +0100 Subject: [PATCH 81/88] ramips: mt76x8: fix bootcount init script file permissions The bootcount init script is missing the executable bit (644 instead of 755), causing the script to not be executable: /etc/preinit: line 44: /etc/init.d/bootcount: Permission denied Fixes: c3b8108a2be4 ("ramips: Add support for Xiaomi MiWiFi 3A") Signed-off-by: Oliver Sedlbauer Link: https://github.com/openwrt/openwrt/pull/22446 Signed-off-by: Hauke Mehrtens --- target/linux/ramips/mt76x8/base-files/etc/init.d/bootcount | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 target/linux/ramips/mt76x8/base-files/etc/init.d/bootcount diff --git a/target/linux/ramips/mt76x8/base-files/etc/init.d/bootcount b/target/linux/ramips/mt76x8/base-files/etc/init.d/bootcount old mode 100644 new mode 100755 From d97381aff3186fa8b655e1d3eb6584febfd80298 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Esat=20Yi=C4=9Fithan=20G=C3=96KTOPRAK?= Date: Mon, 16 Mar 2026 20:38:00 +0300 Subject: [PATCH 82/88] ramips: fix for Keenetic KN-1910 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set nand flash for KN-1910 Sysupgrade or any other method i tried (asu, owut) not working without it. Tested with a local build. Signed-off-by: Esat Yiğithan GÖKTOPRAK Link: https://github.com/openwrt/openwrt/pull/22311 Signed-off-by: Hauke Mehrtens --- target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh index a737d2f08b..981cfacd54 100644 --- a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh +++ b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh @@ -111,6 +111,7 @@ platform_do_upgrade() { iptime,ax2004m|\ iptime,t5004|\ jcg,q20|\ + keenetic,kn-1910|\ keenetic,kn-3510|\ linksys,e5600|\ linksys,e7350|\ From 02e2065203c5e6c95f88e3501644d3e6ad740f89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miika=20Sundstr=C3=B6m?= Date: Sun, 15 Mar 2026 18:40:42 +0200 Subject: [PATCH 83/88] wifi-scripts: fix [VHT160]/[VHT160-80PLUS80] usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't set vht_capab [VHT160] or [VHT160-80PLUS80] when the AP is not configured to operate in 160 MHz. Fixes an issue degrading station upload speed. Fixes: https://github.com/openwrt/openwrt/issues/22435 Signed-off-by: Miika Sundström Link: https://github.com/openwrt/openwrt/pull/22436 Signed-off-by: Hauke Mehrtens --- .../files-ucode/usr/share/ucode/wifi/hostapd.uc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc b/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc index 61570d76f2..49262c9d61 100644 --- a/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc +++ b/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc @@ -354,10 +354,10 @@ function device_htmode_append(config) { config.vht_capab += '[BF-ANTENNA-' + min(((vht_capab >> 13) & 3) + 1, config.beamformer_antennas) + ']'; /* supported Channel widths */ - if ((vht_capab & 0xc) == 8 && config.vht160 <= 2) - config.vht_capab += '[VHT160-80PLUS80]'; - else if ((vht_capab & 0xc) == 4 && config.vht160 <= 2) + if (((vht_capab & 0xc) == 4 || (vht_capab & 0xc) == 8) && config.vht160 >= 1) config.vht_capab += '[VHT160]'; + if ((vht_capab & 0xc) == 8 && config.vht160 >= 2) + config.vht_capab += '[VHT160-80PLUS80]'; /* maximum MPDU length */ if ((vht_capab & 3) > 1 && config.vht_max_mpdu >= 11454) From b37cbcf50abcbba082a3badf9983a18a4289530a Mon Sep 17 00:00:00 2001 From: Eric Fahlgren Date: Mon, 16 Mar 2026 08:26:03 -0700 Subject: [PATCH 84/88] iptables: prefer nft variants over zz-legacy Set the default variant on "iptables-nft" and "ip6tables-nft" to make them the preferred package when "iptables" is installed as a dependency. Link: https://github.com/openwrt/packages/issues/28815 Signed-off-by: Eric Fahlgren Link: https://github.com/openwrt/openwrt/pull/22448 Signed-off-by: Hauke Mehrtens --- package/network/utils/iptables/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/package/network/utils/iptables/Makefile b/package/network/utils/iptables/Makefile index 289ad8db07..4b00f3bbe0 100644 --- a/package/network/utils/iptables/Makefile +++ b/package/network/utils/iptables/Makefile @@ -10,7 +10,7 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=iptables PKG_VERSION:=1.8.10 -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE_URL:=https://netfilter.org/projects/iptables/files PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz @@ -144,6 +144,7 @@ $(call Package/iptables/Default) TITLE:=IP firewall administration tool nft DEPENDS:=+kmod-ipt-core +xtables-nft PROVIDES:=iptables + DEFAULT_VARIANT:=1 ALTERNATIVES:=\ 300:/usr/sbin/iptables:xtables-nft-multi \ 300:/usr/sbin/iptables-restore:xtables-nft-multi \ @@ -489,6 +490,7 @@ $(call Package/iptables/Default) DEPENDS:=@IPV6 +kmod-ip6tables +xtables-nft TITLE:=IP firewall administration tool nft PROVIDES:=ip6tables + DEFAULT_VARIANT:=1 ALTERNATIVES:=\ 300:/usr/sbin/ip6tables:xtables-nft-multi \ 300:/usr/sbin/ip6tables-restore:xtables-nft-multi \ From df45ed2da0afb3c2c4dce567338eaa3ef099217a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 16 Mar 2026 19:07:36 +0100 Subject: [PATCH 85/88] odhcpd: update to Git HEAD (2026-03-16) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 160e5fa3957c odhcpd: ensure zero padding on DNSSL 2a316dbfd798 odhcpd: ignore NULL in dhcpv4_free_lease() stub b960d4cbe27b ubus: fix truncated field in DHCPv6 lease query 4e26e1361335 dhcpv4: fix avl_delete on leases not in avl tree ea5af5bffa2d dhcpv4: fix segfault when disabling interface https://github.com/openwrt/odhcpd/compare/13cec018c0d9...160e5fa3957c Signed-off-by: Álvaro Fernández Rojas Link: https://github.com/openwrt/openwrt/pull/22454 Signed-off-by: Hauke Mehrtens --- package/network/services/odhcpd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/services/odhcpd/Makefile b/package/network/services/odhcpd/Makefile index bf40208fc3..c2164076c3 100644 --- a/package/network/services/odhcpd/Makefile +++ b/package/network/services/odhcpd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git -PKG_MIRROR_HASH:=389d840185dabe2d872dc9751da3cee0a4a3570c8dc6f89c71c9b6a456ba6d90 -PKG_SOURCE_DATE:=2026-03-12 -PKG_SOURCE_VERSION:=13cec018c0d9bd452f4cb5e583c52fdf206cdc31 +PKG_MIRROR_HASH:=1d0008c049d98c7e663d59fe7285e9d4a47552df3806494fe0fdba4658829904 +PKG_SOURCE_DATE:=2026-03-16 +PKG_SOURCE_VERSION:=160e5fa3957cfd9d89f8ff7493f28a8baaf6ced7 PKG_MAINTAINER:=Álvaro Fernández Rojas PKG_LICENSE:=GPL-2.0 From 74d120c22d7724da7da8913032579eefa6716ca4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Thu, 22 Jan 2026 12:44:55 +0100 Subject: [PATCH 86/88] linux-firmware: ath11k: add IPQ5018, IPQ8074, QCN9074 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use linux-firmware repository for IPQ5018, IPQ8074 and QCN9074. All officially released firmware versions are available there. Signed-off-by: Paweł Owoc Link: https://github.com/openwrt/openwrt/pull/21833 Signed-off-by: Robert Marko --- package/firmware/ath11k-firmware/Makefile | 41 ------------------- package/firmware/linux-firmware/qca_ath11k.mk | 24 +++++++++++ 2 files changed, 24 insertions(+), 41 deletions(-) diff --git a/package/firmware/ath11k-firmware/Makefile b/package/firmware/ath11k-firmware/Makefile index 0ef80b3719..63562f7718 100644 --- a/package/firmware/ath11k-firmware/Makefile +++ b/package/firmware/ath11k-firmware/Makefile @@ -47,11 +47,6 @@ define Package/ath11k-firmware-default DEPENDS:= endef -define Package/ath11k-firmware-ipq5018 -$(Package/ath11k-firmware-default) - TITLE:=IPQ5018 ath11k firmware -endef - define Package/ath11k-firmware-ipq5018-qcn6122 $(Package/ath11k-firmware-default) TITLE:=IPQ5018/QCN6122 ath11k firmware @@ -62,16 +57,6 @@ $(Package/ath11k-firmware-default) TITLE:=IPQ6018 ath11k firmware endef -define Package/ath11k-firmware-ipq8074 -$(Package/ath11k-firmware-default) - TITLE:=IPQ8074 ath11k firmware -endef - -define Package/ath11k-firmware-qcn9074 -$(Package/ath11k-firmware-default) - TITLE:=QCN9074 ath11k firmware -endef - define Build/Clean $(call Build/Clean/Default,) @@ -91,13 +76,6 @@ define Build/Compile endef -define Package/ath11k-firmware-ipq5018/install - $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0 - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ5018/hw1.0/2.6.0.1/WLAN.HK.2.6.0.1-01291-QCAHKSWPL_SILICONZ-1/* \ - $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/ -endef - define Package/ath11k-firmware-ipq5018-qcn6122/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0 $(INSTALL_DATA) \ @@ -116,24 +94,5 @@ define Package/ath11k-firmware-ipq6018/install $(1)/lib/firmware/IPQ6018/ endef -define Package/ath11k-firmware-ipq8074/install - $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ8074/hw2.0/2.9.0.1/WLAN.HK.2.9.0.1-02146-QCAHKSWPL_SILICONZ-1/* \ - $(1)/lib/firmware/IPQ8074/ -endef - -define Package/ath11k-firmware-qcn9074/install - $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0 - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/QCN9074/hw1.0/2.9.0.1/WLAN.HK.2.9.0.1-02146-QCAHKSWPL_SILICONZ-1/* \ - $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ - $(INSTALL_BIN) \ - $(PKG_BUILD_DIR)/QCN9074/hw1.0/board-2.bin $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin -endef - -$(eval $(call BuildPackage,ath11k-firmware-ipq5018)) $(eval $(call BuildPackage,ath11k-firmware-ipq5018-qcn6122)) $(eval $(call BuildPackage,ath11k-firmware-ipq6018)) -$(eval $(call BuildPackage,ath11k-firmware-ipq8074)) -$(eval $(call BuildPackage,ath11k-firmware-qcn9074)) diff --git a/package/firmware/linux-firmware/qca_ath11k.mk b/package/firmware/linux-firmware/qca_ath11k.mk index a700383610..a373cf5774 100644 --- a/package/firmware/linux-firmware/qca_ath11k.mk +++ b/package/firmware/linux-firmware/qca_ath11k.mk @@ -1,3 +1,19 @@ +Package/ath11k-firmware-ipq5018 = $(call Package/firmware-default,IPQ5018 ath11k firmware,,LICENCE.atheros_firmware) +define Package/ath11k-firmware-ipq5018/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ath11k/IPQ5018/hw1.0/* $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/ +endef +$(eval $(call BuildPackage,ath11k-firmware-ipq5018)) + +Package/ath11k-firmware-ipq8074 = $(call Package/firmware-default,IPQ8074 ath11k firmware,,LICENCE.atheros_firmware) +define Package/ath11k-firmware-ipq8074/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ath11k/IPQ8074/hw2.0/* $(1)/lib/firmware/IPQ8074/ +endef +$(eval $(call BuildPackage,ath11k-firmware-ipq8074)) + Package/ath11k-firmware-qca2066 = $(call Package/firmware-default,QCA2066 ath11k firmware,,LICENCE.atheros_firmware) define Package/ath11k-firmware-qca2066/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCA2066/hw2.1 @@ -14,6 +30,14 @@ define Package/ath11k-firmware-qca6390/install endef $(eval $(call BuildPackage,ath11k-firmware-qca6390)) +Package/ath11k-firmware-qcn9074 = $(call Package/firmware-default,QCN9074 ath11k firmware,,LICENCE.atheros_firmware) +define Package/ath11k-firmware-qcn9074/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ath11k/QCN9074/hw1.0/* $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ +endef +$(eval $(call BuildPackage,ath11k-firmware-qcn9074)) + Package/ath11k-firmware-wcn6750 = $(call Package/firmware-default,WCN6750 ath11k firmware,,LICENCE.atheros_firmware) define Package/ath11k-firmware-wcn6750/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/WCN6750/hw1.0 From 103e9aec15593fe872a882eae0a32a78eb145f6f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 5 Feb 2026 19:59:47 +0100 Subject: [PATCH 87/88] uboot-airoha: Add support for Nokia Valyrian Add support for Nokia Valyrian device that implement similar spec of an Airoha AN7581 RFB board. Link: https://github.com/openwrt/openwrt/pull/21761 Signed-off-by: Christian Marangi --- package/boot/uboot-airoha/Makefile | 13 +- .../patches/400-add-nokia-valyrian.patch | 242 ++++++++++++++++++ 2 files changed, 254 insertions(+), 1 deletion(-) create mode 100644 package/boot/uboot-airoha/patches/400-add-nokia-valyrian.patch diff --git a/package/boot/uboot-airoha/Makefile b/package/boot/uboot-airoha/Makefile index 1230e879da..52b95c68ed 100644 --- a/package/boot/uboot-airoha/Makefile +++ b/package/boot/uboot-airoha/Makefile @@ -54,11 +54,22 @@ define U-Boot/an7581_gemtek_w1700k UBOOT_IMAGE:=u-boot.bin endef +define U-Boot/an7581_nokia_valyrian + NAME:=Nokia Valyrian + UBOOT_CONFIG:=an7581_nokia_valyrian + BUILD_DEVICES:=nokia_valyrian + BUILD_SUBTARGET:=an7581 + UBOOT_IMAGE:=u-boot.fip + BL2_IMAGE:=an7581-bl2.bin + BL31_IMAGE:=an7581-bl31.bin +endef + UBOOT_TARGETS := \ en7523_rfb \ an7581_rfb \ an7583_rfb \ - an7581_gemtek_w1700k + an7581_gemtek_w1700k \ + an7581_nokia_valyrian UBOOT_CUSTOMIZE_CONFIG := \ --disable TOOLS_KWBIMAGE \ diff --git a/package/boot/uboot-airoha/patches/400-add-nokia-valyrian.patch b/package/boot/uboot-airoha/patches/400-add-nokia-valyrian.patch new file mode 100644 index 0000000000..51e467da51 --- /dev/null +++ b/package/boot/uboot-airoha/patches/400-add-nokia-valyrian.patch @@ -0,0 +1,242 @@ +--- /dev/null ++++ b/arch/arm/dts/an7581-nokia-valyrian-u-boot.dtsi +@@ -0,0 +1,104 @@ ++// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++ ++/ { ++ /* When running as a first-stage bootloader this isn't filled in automatically */ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x0 0x40000000>; ++ }; ++}; ++ ++#include "an7581-u-boot.dtsi" ++ ++&mmc0 { ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bl@800 { ++ label = "bl2"; ++ reg = <0x00000800 0x0001f800>; ++ }; ++ ++ bootloader@20000 { ++ label = "bootloader"; ++ reg = <0x00020000 0x000e0000>; ++ }; ++ ++ bootloader-inactive@100000 { ++ label = "bootloader-inactive"; ++ reg = <0x00100000 0x000e0000>; ++ }; ++ ++ u-boot-env@1e0000 { ++ label = "u-boot-env"; ++ reg = <0x001e0000 0x00020000>; ++ ++ u-boot,mmc-env-partition; ++ }; ++ ++ factory@200000 { ++ label = "factory"; ++ reg = <0x00200000 0x00800000>; ++ }; ++ ++ mfgdata@a00000 { ++ label = "mfgdata"; ++ reg = <0x00a00000 0x00100000>; ++ }; ++ ++ kernel-active@b00000 { ++ label = "kernel-active"; ++ reg = <0x00b00000 0x00800000>; ++ }; ++ ++ kernel-inactive@1300000 { ++ label = "kernel-inactive"; ++ reg = <0x01300000 0x00800000>; ++ }; ++ ++ rootfs-active@1b00000 { ++ label = "rootfs-active"; ++ reg = <0x01b00000 0x06400000>; ++ }; ++ ++ rootfs-inactive@7f00000 { ++ label = "rootfs-inactive"; ++ reg = <0x07f00000 0x06400000>; ++ }; ++ ++ rootfs-data@e300000 { ++ label = "rootfs_data"; ++ reg = <0x0e300000 0x02000000>; ++ }; ++ ++ securestore@10300000 { ++ label = "securestore"; ++ reg = <0x10300000 0x1000000>; ++ }; ++ ++ lcm-data@11300000 { ++ label = "lcm_data"; ++ reg = <0x11300000 0x40000000>; ++ }; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&gdm1 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/an7581_nokia_valyrian_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_AIROHA=y ++CONFIG_AUTOBOOT_USE_MENUKEY=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_TARGET_AN7581=y ++CONFIG_TEXT_BASE=0x81e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_ENV_OFFSET=0x1e0000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="airoha/an7581-nokia-valyrian" ++CONFIG_SYS_LOAD_ADDR=0x81800000 ++CONFIG_BUILD_TARGET="u-boot.bin" ++# CONFIG_EFI_LOADER is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_BOOTDELAY=3 ++CONFIG_DEFAULT_FDT_FILE="airoha/an7581-nokia-valyrian.dtb" ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_SYS_CONSOLE_IS_IN_ENV=y ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="AN7581> " ++CONFIG_SYS_MAXARGS=8 ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_XIMG is not set ++CONFIG_CMD_BIND=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_SPI=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PING=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_CMD_LOG=y ++CONFIG_OF_UPSTREAM=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SYS_RX_ETH_BUFFER=8 ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DMA=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_AIROHA_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_MDIO=y ++CONFIG_PCS_AIROHA_AN7581=y ++CONFIG_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_SYS_NS16550=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_AIROHA_SNFI_SPI=y ++CONFIG_SHA512=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/an7581_nokia_valyrian_env" ++CONFIG_FIP_LOADER=y ++CONFIG_PCS_AIROHA_AN7581=y ++CONFIG_PHY_AIROHA_EN8811=y ++CONFIG_PHY_ANEG_TIMEOUT=10000 ++CONFIG_PHY_ETHERNET_ID=y ++CONFIG_PHY_AS21XXX=y +--- /dev/null ++++ b/defenvs/an7581_nokia_valyrian_env +@@ -0,0 +1,25 @@ ++loadaddr=0x90000000 ++ipaddr=192.168.1.1 ++serverip=192.168.1.10 ++emmc_bootfile_bl2=openwrt-airoha-an7581-nokia_valyrian-preloader.bin ++emmc_bootfile_fip=openwrt-airoha-an7581-nokia_valyrian-bl31-uboot.fip ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [EMMC] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run emmc_boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_2=Load BL2 preloader via TFTP then write to eMMC.=run emmc_boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_3=Reboot.=reset ++bootmenu_4=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_default=bootm ++reset_factory=eraseenv && reset ++emmc_boot_tftp_write_fip=tftpboot $loadaddr $emmc_bootfile_fip && run emmc_write_fip ++emmc_boot_tftp_write_bl2=tftpboot $loadaddr $emmc_bootfile_bl2 && run emmc_write_bl2 ++emmc_write_bl2=mmc erase 0x4 0xfc && mmc write $fileaddr 0x4 0xfc ++emmc_write_fip=mmc erase 0x100 0x700 && mmc write $fileaddr 0x100 0x700 ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/dts/upstream/src/arm64/airoha/an7581-nokia-valyrian.dts +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "en7581.dtsi" ++ ++/ { ++ model = "Nokia Valyrian"; ++ compatible = "nokia,valyrian", "airoha,an7581", "airoha,en7581"; ++ ++ chosen { ++ stdout-path = &uart1; ++ }; ++}; From e210d994faa58d033c13147f16157a80aa266bf1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 28 Jan 2026 20:56:53 +0100 Subject: [PATCH 88/88] airoha: an7581: add Nokia Valyrian support Add support for Nokia Valyrian based on Airoha AN7581 SoC. Device specification -------------------- SoC Type: Airoha AN7581 RAM: 2x DDR4 Nanya NT5AD256M16E4-JR (1GB) Flash: eMMC Macronix MX52LM08A11XVW (1GB) Ethernet: 3x gigabit via AN7581, 1x 10g via AS21x1x, 1x SFP cage Wi-Fi: MT7996 - BE19000 LEDs: 11 LED via 2x 74HC595 shift register Button: Reset, WPS, WiFi USB ports: 1x 2.0 Miscellaneous: 1x Power Monitor via RTQ6059, 2x FXS port Device is unfused and is originally flashed with Airoha SDK bootloader that require signed images. Bootloader is username/password protected and use the leaked auth combo that can be found online. From the bootloadet instruction on how to flash custom bootloader are: 1. mmc erase 0 0x800 2. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-preloader.bin 3. mmc write $loadaddr 0x4 0xfc 4. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-bl31-uboot.fip 5. mmc write $loadaddr 0x100 0x700 It's also possible to use the Emergency Recovery procedure: From powered OFF device: 1. Keep the reset button pressed (middle button) 2. Power on the device 3. Notice the "Press x" prompt 4. Press x 5. Notice the "C" char waiting for XMODEM load 6. Load the preloader binary with XMODEM protocol 7. Notice the "Press x to load BL31 + U-Boot FIP" 8. Press x 9. Notice the "C" char waiting for XMODEM load 10. Load the fip binary with XMODEM protocol 11. You are now in U-Boot loaded from serial 12. Follow normal procedure to flash bootloader Due to BOOTROM limitation. the device can't have a standard GPT table implementation. Because of this fixed-partitions are used to handle this. U-Boot still doesn't have support for this (it's planned) and currently to flash and load and image it's needed to write and read from static address in eMMC. The GPT partition table follow Prpl guidelines with dual partition table with kernel and rootfs split. The address for kernel is 0xb00000 and the address for rootfs is 0x1b00000. Link: https://github.com/openwrt/openwrt/pull/21761 Signed-off-by: Christian Marangi --- .../an7581/base-files/etc/board.d/02_network | 2 + .../airoha/dts/an7581-nokia-valyrian.dts | 539 ++++++++++++++++++ target/linux/airoha/image/an7581.mk | 14 + 3 files changed, 555 insertions(+) create mode 100644 target/linux/airoha/dts/an7581-nokia-valyrian.dts diff --git a/target/linux/airoha/an7581/base-files/etc/board.d/02_network b/target/linux/airoha/an7581/base-files/etc/board.d/02_network index 734808cb3d..b6293658d9 100644 --- a/target/linux/airoha/an7581/base-files/etc/board.d/02_network +++ b/target/linux/airoha/an7581/base-files/etc/board.d/02_network @@ -17,6 +17,8 @@ an7581_setup_interfaces() gemtek,w1700k-ubi) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" "wan" ;; + nokia,valyrian) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 10g" "wan" *) echo "Unsupported hardware. Network interfaces not initialized" ;; diff --git a/target/linux/airoha/dts/an7581-nokia-valyrian.dts b/target/linux/airoha/dts/an7581-nokia-valyrian.dts new file mode 100644 index 0000000000..ae24d075e7 --- /dev/null +++ b/target/linux/airoha/dts/an7581-nokia-valyrian.dts @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include +#include +#include +#include "an7581.dtsi" + +/ { + model = "Nokia Valyrian"; + compatible = "nokia,valyrian", "airoha,an7581", "airoha,en7581"; + + aliases { + serial0 = &uart1; + led-boot = &led_status_white; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_blue; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + btn-0 { + label = "reset"; + linux,code = ; + gpios = <&en7581_pinctrl 0 GPIO_ACTIVE_LOW>; + }; + + btn-1 { + label = "wps"; + linux,code = ; + gpios = <&en7581_pinctrl 13 GPIO_ACTIVE_LOW>; + }; + + btn-2 { + label = "wifi"; + linux,code = ; + gpios = <&en7581_pinctrl 16 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&leds_shift_reg 0 GPIO_ACTIVE_LOW>; + }; + + led_status_green: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&leds_shift_reg 1 GPIO_ACTIVE_LOW>; + }; + + led_status_blue: led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&leds_shift_reg 2 GPIO_ACTIVE_LOW>; + }; + + led_status_white: led-3 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&leds_shift_reg 3 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&leds_shift_reg 4 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&leds_shift_reg 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-6 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&leds_shift_reg 6 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_MOBILE; + color = ; + gpios = <&leds_shift_reg 7 GPIO_ACTIVE_LOW>; + }; + + led-8 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&leds_shift_reg 8 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&leds_shift_reg 9 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_USB; + color = ; + gpios = <&leds_shift_reg 10 GPIO_ACTIVE_LOW>; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + + i2c-bus = <&i2c0>; + + mod-def0-gpios = <&en7581_pinctrl 33 GPIO_ACTIVE_LOW>; + los-gpios = <&en7581_pinctrl 36 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&en7581_pinctrl 41 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&en7581_pinctrl 40 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + i2c-1 { + compatible = "i2c-gpio"; + + sda-gpios = <&en7581_pinctrl 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&en7581_pinctrl 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + + #address-cells = <1>; + #size-cells = <0>; + + adc@40 { + compatible = "richtek,rtq6059"; + reg = <0x40>; + + #io-channel-cells = <1>; + }; + }; + + spi-0 { + compatible = "spi-gpio"; + + sck-gpios = <&en7581_pinctrl 4 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&en7581_pinctrl 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&en7581_pinctrl 30 GPIO_ACTIVE_LOW>; + + num-chipselects = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + leds_shift_reg: gpio-expander@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + + enable-gpios = <&en7581_pinctrl 14 GPIO_ACTIVE_LOW>; + + gpio-controller; + + registers-number = <2>; + spi-max-frequency = <100000>; + + #gpio-cells = <2>; + }; + }; +}; + +&en7581_pinctrl { + gpio-ranges = <&en7581_pinctrl 0 13 47>; + + pcie1_rst_pins: pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pcie2_rst_pins: pcie2-rst-pins { + conf { + pins = "pcie_reset2"; + drive-open-drain = <1>; + }; + }; + + gswp1_led0_pins: gswp1-led1-pins { + mux { + function = "phy1_led0"; + pins = "gpio43"; + }; + }; + + gswp2_led0_pins: gswp2-led1-pins { + mux { + function = "phy2_led0"; + pins = "gpio44"; + }; + }; + + gswp3_led0_pins: gswp3-led1-pins { + mux { + function = "phy3_led0"; + pins = "gpio45"; + }; + }; + + mmc_pins: mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bl@800 { + label = "bl2"; + reg = <0x00000800 0x0001f800>; + }; + + bootloader@20000 { + label = "bootloader"; + reg = <0x00020000 0x000e0000>; + }; + + bootloader-inactive@100000 { + label = "bootloader-inactive"; + reg = <0x00100000 0x000e0000>; + }; + + u-boot-env@1e0000 { + label = "u-boot-env"; + reg = <0x001e0000 0x00020000>; + + nvmem-layout { + compatible = "u-boot,env-layout"; + }; + }; + + factory@200000 { + label = "factory"; + reg = <0x00200000 0x00800000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x40000 0x1e00>; + }; + + mac_factory_2c0000: mac@2c0000 { + compatible = "mac-base"; + reg = <0x2c0000 0x6>; + + #nvmem-cell-cells = <1>; + }; + + onu_type_factory_2e0000: onu_type@2e0000 { + reg = <0x2e0000 0x10>; + }; + + board_config_factory_2e0010: board_config@2e0010 { + reg = <0x2e0010 0x8>; + }; + }; + }; + + mfgdata@a00000 { + label = "mfgdata"; + reg = <0x00a00000 0x00100000>; + }; + + kernel-active@b00000 { + label = "kernel-active"; + reg = <0x00b00000 0x00800000>; + }; + + kernel-inactive@1300000 { + label = "kernel-inactive"; + reg = <0x01300000 0x00800000>; + }; + + rootfs-active@1b00000 { + label = "rootfs-active"; + reg = <0x01b00000 0x06400000>; + }; + + rootfs-inactive@7f00000 { + label = "rootfs-inactive"; + reg = <0x07f00000 0x06400000>; + }; + + rootfs-data@e300000 { + label = "rootfs_data"; + reg = <0x0e300000 0x02000000>; + }; + + securestore@10300000 { + label = "securestore"; + reg = <0x10300000 0x1000000>; + }; + + lcm-data@11300000 { + label = "lcm_data"; + reg = <0x11300000 0x40000000>; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + + mediatek,u3p-dis-msk = <0x1>; + phys = <&usb0_phy PHY_TYPE_USB2>; +}; + +&i2c0 { + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_rst_pins>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + + airoha,npu = <&npu>; + airoha,eth = <ð>; + + band@0 { + /* 2.4 GHz */ + reg = <0>; + nvmem-cells = <&mac_factory_2c0000 6>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + /* 5 GHz */ + reg = <1>; + nvmem-cells = <&mac_factory_2c0000 7>; + nvmem-cell-names = "mac-address"; + }; + + band@2 { + /* 6 GHz */ + reg = <2>; + nvmem-cells =<&mac_factory_2c0000 8>; + nvmem-cell-names = "mac-address"; + }; + }; + }; +}; + +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_rst_pins>; + status = "okay"; +}; + +ð { + status = "okay"; +}; + +&gdm1 { + status = "okay"; + + nvmem-cells = <&mac_factory_2c0000 3>; + nvmem-cell-names = "mac-address"; +}; + +&mdio { + as21xx: ethernet-phy@1c { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1c>; + + firmware-name = "as21x1x_fw.bin"; + + reset-deassert-us = <1000000>; + reset-assert-us = <1000000>; + reset-gpios = <&en7581_pinctrl 31 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&switch { + status = "okay"; +}; + +&pon_pcs { + status = "okay"; +}; + +&gdm2 { + status = "okay"; + + sfp = <&sfp>; + + managed = "in-band-status"; + phy-mode = "usxgmii"; + + nvmem-cells = <&mac_factory_2c0000 4>; + nvmem-cell-names = "mac-address"; + + openwrt,netdev-name = "wan"; +}; + +ð_pcs { + status = "okay"; +}; + +&gdm4 { + status = "okay"; + + managed = "in-band-status"; + phy-handle = <&as21xx>; + phy-mode = "usxgmii"; + + nvmem-cells = <&mac_factory_2c0000 5>; + nvmem-cell-names = "mac-address"; + + openwrt,netdev-name = "10g"; +}; + +&gsw_port1 { + label = "lan1"; + + status = "okay"; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gswp1_led0_pins>; + + status = "okay"; +}; + +&gsw_phy1_led0 { + function = LED_FUNCTION_LAN; + active-low; + + status = "okay"; +}; + +&gsw_port2 { + label = "lan2"; + + status = "okay"; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gswp2_led0_pins>; + + status = "okay"; +}; + +&gsw_phy2_led0 { + function = LED_FUNCTION_LAN; + active-low; + + status = "okay"; +}; + +&gsw_port3 { + label = "lan3"; + + status = "okay"; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gswp3_led0_pins>; + + status = "okay"; +}; + +&gsw_phy3_led0 { + function = LED_FUNCTION_LAN; + active-low; + + status = "okay"; +}; diff --git a/target/linux/airoha/image/an7581.mk b/target/linux/airoha/image/an7581.mk index e52eff03a9..5e001cb816 100644 --- a/target/linux/airoha/image/an7581.mk +++ b/target/linux/airoha/image/an7581.mk @@ -104,3 +104,17 @@ define Device/gemtek_w1700k-ubi SOC := an7581 endef TARGET_DEVICES += gemtek_w1700k-ubi + +define Device/nokia_valyrian + DEVICE_VENDOR := Nokia + DEVICE_MODEL := Valyrian + DEVICE_DTS := an7581-nokia-valyrian + DEVICE_PACKAGES := kmod-spi-gpio kmod-gpio-nxp-74hc164 kmod-leds-gpio \ + kmod-i2c-an7581 kmod-i2c-gpio kmod-iio-richtek-rtq6056 \ + kmod-sfp kmod-phy-aeonsemi-as21xxx \ + kmod-mt7996-firmware + ARTIFACT/preloader.bin := an7581-preloader nokia_valyrian + ARTIFACT/bl31-uboot.fip := an7581-bl31-uboot nokia_valyrian + ARTIFACTS := preloader.bin bl31-uboot.fip +endef +TARGET_DEVICES += nokia_valyrian