175 lines
5.1 KiB
Diff
175 lines
5.1 KiB
Diff
From git@z Thu Jan 1 00:00:00 1970
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Subject: [PATCH v13 11/35] phy: rockchip: usbdp: Support single-lane DP
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From: Zhang Yubing <yubing.zhang@rock-chips.com>
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Date: Tue, 14 Jul 2026 21:26:12 +0200
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Message-Id: <20260714-rockchip-usbdp-cleanup-v13-11-6cb3e769d4c5@collabora.com>
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Implement support for using just a single DisplayPort line.
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Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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drivers/phy/rockchip/phy-rockchip-usbdp.c | 64 +++++++++++++------------------
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1 file changed, 27 insertions(+), 37 deletions(-)
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--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
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+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
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@@ -193,6 +193,7 @@ struct rk_udphy {
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int id;
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bool dp_in_use;
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+ int dp_lanes;
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/* PHY const config */
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const struct rk_udphy_cfg *cfgs;
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@@ -535,6 +536,13 @@ static void rk_udphy_usb_bvalid_enable(s
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* <0 1> dpln0 dpln1 usbrx usbtx
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* <2 3> usbrx usbtx dpln0 dpln1
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* ---------------------------------------------------------------------------
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+ * if 1 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x>;
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+ * sample as follow:
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+ * ---------------------------------------------------------------------------
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+ * B11-B10 A2-A3 A11-A10 B2-B3
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+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
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+ * <0> dpln0 \ usbrx usbtx
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+ * ---------------------------------------------------------------------------
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*/
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static void rk_udphy_dplane_select(struct rk_udphy *udphy)
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@@ -542,18 +550,18 @@ static void rk_udphy_dplane_select(struc
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const struct rk_udphy_cfg *cfg = udphy->cfgs;
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u32 value = 0;
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- switch (udphy->mode) {
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- case UDPHY_MODE_DP:
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- value |= 2 << udphy->dp_lane_sel[2] * 2;
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+ switch (udphy->dp_lanes) {
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+ case 4:
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value |= 3 << udphy->dp_lane_sel[3] * 2;
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+ value |= 2 << udphy->dp_lane_sel[2] * 2;
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fallthrough;
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- case UDPHY_MODE_DP_USB:
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- value |= 0 << udphy->dp_lane_sel[0] * 2;
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+ case 2:
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value |= 1 << udphy->dp_lane_sel[1] * 2;
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- break;
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+ fallthrough;
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- case UDPHY_MODE_USB:
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+ case 1:
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+ value |= 0 << udphy->dp_lane_sel[0] * 2;
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break;
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default:
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@@ -566,28 +574,6 @@ static void rk_udphy_dplane_select(struc
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FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
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}
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-static int rk_udphy_dplane_get(struct rk_udphy *udphy)
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-{
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- int dp_lanes;
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-
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- switch (udphy->mode) {
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- case UDPHY_MODE_DP:
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- dp_lanes = 4;
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- break;
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-
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- case UDPHY_MODE_DP_USB:
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- dp_lanes = 2;
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- break;
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-
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- case UDPHY_MODE_USB:
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- default:
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- dp_lanes = 0;
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- break;
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- }
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-
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- return dp_lanes;
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-}
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-
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static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
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{
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u32 val = 0;
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@@ -657,6 +643,7 @@ static void rk_udphy_set_typec_default_m
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}
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rk_udphy_mode_set(udphy, UDPHY_MODE_DP_USB);
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+ udphy->dp_lanes = 2;
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}
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static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
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@@ -895,7 +882,7 @@ static int rk_udphy_parse_lane_mux_data(
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return 0;
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}
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- if (num_lanes != 2 && num_lanes != 4)
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+ if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4)
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return dev_err_probe(udphy->dev, -EINVAL,
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"invalid number of lane mux\n");
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@@ -921,9 +908,11 @@ static int rk_udphy_parse_lane_mux_data(
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}
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udphy->mode = UDPHY_MODE_DP;
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- if (num_lanes == 2) {
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+ udphy->dp_lanes = num_lanes;
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+ if (num_lanes == 1 || num_lanes == 2) {
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udphy->mode |= UDPHY_MODE_USB;
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- udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP);
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+ udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP) ||
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+ (udphy->lane_mux_sel[1] == PHY_LANE_MUX_DP);
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}
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return 0;
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@@ -1050,18 +1039,17 @@ static int rk_udphy_dp_phy_exit(struct p
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static int rk_udphy_dp_phy_power_on(struct phy *phy)
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{
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struct rk_udphy *udphy = phy_get_drvdata(phy);
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- int ret, dp_lanes;
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+ int ret;
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mutex_lock(&udphy->mutex);
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- dp_lanes = rk_udphy_dplane_get(udphy);
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- phy_set_bus_width(phy, dp_lanes);
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+ phy_set_bus_width(phy, udphy->dp_lanes);
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ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
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if (ret)
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goto unlock;
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- rk_udphy_dplane_enable(udphy, dp_lanes);
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+ rk_udphy_dplane_enable(udphy, udphy->dp_lanes);
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rk_udphy_dplane_select(udphy);
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@@ -1341,6 +1329,7 @@ static int rk_udphy_typec_mux_set(struct
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udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
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udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
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mode = UDPHY_MODE_DP;
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+ udphy->dp_lanes = 4;
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break;
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case TYPEC_DP_STATE_D:
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@@ -1357,6 +1346,7 @@ static int rk_udphy_typec_mux_set(struct
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udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
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}
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mode = UDPHY_MODE_DP_USB;
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+ udphy->dp_lanes = 2;
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break;
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}
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@@ -1501,7 +1491,7 @@ static int rk_udphy_probe(struct platfor
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ret = PTR_ERR(udphy->phy_dp);
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return dev_err_probe(dev, ret, "failed to create DP phy\n");
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}
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- phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
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+ phy_set_bus_width(udphy->phy_dp, udphy->dp_lanes);
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udphy->phy_dp->attrs.max_link_rate = 8100;
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phy_set_drvdata(udphy->phy_dp, udphy);
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