Aleksander Jan BajkowskiandRobert Marko
21704379e0
Backport upstream patch that adds node for thermal driver. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Link: https://github.com/openwrt/openwrt/pull/22646 Signed-off-by: Robert Marko <robimarko@gmail.com>
54 lines
2.1 KiB
Diff
54 lines
2.1 KiB
Diff
From 0c74ae06ed6b6c9627712a74ecee4e61bbd4092d Mon Sep 17 00:00:00 2001
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From: developer <developer@mediatek.com>
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Date: Mon, 19 Jan 2026 21:42:29 +0800
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Subject: [PATCH] arm64: dts: mediatek: fix mt7981 spim clock
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1) Add spi0/1/2 clock parent setting
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2) Fix spi1 clock_sel to CLK_TOP_SPIM_MST_SEL
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Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/836034ca0baad57e4c287a62ccc5677c60be0e18
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 14 +++++++++++++-
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1 file changed, 13 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
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@@ -223,6 +223,10 @@
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI2_CK>,
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<&infracfg CLK_INFRA_SPI2_HCK_CK>;
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+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_SPI2_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -237,6 +241,10 @@
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI0_CK>,
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<&infracfg CLK_INFRA_SPI0_HCK_CK>;
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+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_SPI0_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -248,9 +256,13 @@
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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- <&topckgen CLK_TOP_SPI_SEL>,
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+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
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<&infracfg CLK_INFRA_SPI1_CK>,
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<&infracfg CLK_INFRA_SPI1_HCK_CK>;
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+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
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+ <&infracfg CLK_INFRA_SPI1_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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