Markus StockhausenandRobert Marko
316f41e310
The Realtek target currently uses two phy macros to simplify the device dts. - EXTERNAL_PHY() to denote a phy attached to the SoC - INTERNAL_PHY() to denote an internal PHY (inside the SoC) There is no benefit doing this. The topology around a port/phy is well defined by the port macros. They link port, phy, pcs and even leds. The only consumer of the attribute "phy-is-integrated" is inside the dsa driver and that is being refactored. As a first step define a new more meaningful PHY_C22() macro that describes a c22 capable phy. This does not need to care about the external/internal relation. To make it even more useful for the RTL93xx targets with multiple mdio busses give it two parameters PHY_C22(port_number, bus_address) where - port_number is the absolute overall unique phy number - bus_address is the location of the phy on the bus For RTL83xx these two parameters will usually be the same. Instead of three steps (inventing the macro, converting the consumers and removeing the old macor) do a one-step conversion for the existing EXTERNAL_PHY() macro. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22698 Signed-off-by: Robert Marko <robimarko@gmail.com>
152 lines
2.6 KiB
Devicetree
152 lines
2.6 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
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model = "INABA Abaniact AML2-17GP";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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keys {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x10000>;
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read-only;
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x90000 0x10000>;
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};
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partition@a0000 {
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label = "jffs2_cfg";
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reg = <0xa0000 0x400000>;
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read-only;
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};
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partition@4a0000 {
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label = "jffs2_log";
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reg = <0x4a0000 0x100000>;
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read-only;
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};
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partition@5a0000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x5a0000 0xd30000>;
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openwrt,ih-magic = <0x83800000>;
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};
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partition@12d0000 {
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label = "runtime2";
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reg = <0x12d0000 0xd30000>;
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};
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};
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};
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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PHY_C22(24, 24)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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SWITCH_PORT_SDS(16, 9, 2, qsgmii)
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SWITCH_PORT_SDS(17, 10, 2, qsgmii)
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SWITCH_PORT_SDS(18, 11, 2, qsgmii)
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SWITCH_PORT_SDS(19, 12, 2, qsgmii)
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SWITCH_PORT_SDS(20, 13, 3, qsgmii)
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SWITCH_PORT_SDS(21, 14, 3, qsgmii)
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SWITCH_PORT_SDS(22, 15, 3, qsgmii)
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SWITCH_PORT_SDS(23, 16, 3, qsgmii)
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port@24 {
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reg = <24>;
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label = "wan";
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phy-handle = <&phy24>;
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phy-mode = "qsgmii";
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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