Markus StockhausenandRobert Marko
316f41e310
The Realtek target currently uses two phy macros to simplify the device dts. - EXTERNAL_PHY() to denote a phy attached to the SoC - INTERNAL_PHY() to denote an internal PHY (inside the SoC) There is no benefit doing this. The topology around a port/phy is well defined by the port macros. They link port, phy, pcs and even leds. The only consumer of the attribute "phy-is-integrated" is inside the dsa driver and that is being refactored. As a first step define a new more meaningful PHY_C22() macro that describes a c22 capable phy. This does not need to care about the external/internal relation. To make it even more useful for the RTL93xx targets with multiple mdio busses give it two parameters PHY_C22(port_number, bus_address) where - port_number is the absolute overall unique phy number - bus_address is the location of the phy on the bus For RTL83xx these two parameters will usually be the same. Instead of three steps (inventing the macro, converting the consumers and removeing the old macor) do a one-step conversion for the existing EXTERNAL_PHY() macro. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22698 Signed-off-by: Robert Marko <robimarko@gmail.com>
164 lines
3.7 KiB
Devicetree
164 lines
3.7 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc";
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model = "Panasonic Switch-M16eG PN28160K";
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aliases {
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led-boot = &led_status_eco_green;
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led-failsafe = &led_status_eco_amber;
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led-running = &led_status_eco_green;
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led-upgrade = &led_status_eco_green;
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};
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/*
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* sfp0/1 are "combo" port with each TP port (23/24), and they are
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* connected to the RTL8218FB. Currently, there is no support for
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* the chip and only TP ports work by the RTL8218D support.
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*/
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sfp0: sfp-p23 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p24 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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};
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&leds {
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led_status_eco_amber: led-5 {
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gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <1>;
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};
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led_status_eco_green: led-6 {
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gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <2>;
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};
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};
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&i2c_gpio_0 {
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scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c_gpio_1 {
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scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&gpio2 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio0>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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/*
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* GPIO12 (IO1_4): RTL8218FB
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*
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* This GPIO pin should be specified as "reset-gpio" in mdio node, but
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* RTL8218FB phy won't be configured on RTL8218D support in the current
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* phy driver. So, ethernet ports on the phy will be broken after hard-
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* resetting.
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* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
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* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
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* by resetting.
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*/
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ext_switch_reset {
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "ext-switch-reset";
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};
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};
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&i2c_switch {
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i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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/* RTL8218FB */
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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SWITCH_PORT_SDS(16, 9, 2, qsgmii)
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SWITCH_PORT_SDS(17, 10, 2, qsgmii)
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SWITCH_PORT_SDS(18, 11, 2, qsgmii)
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SWITCH_PORT_SDS(19, 12, 2, qsgmii)
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SWITCH_PORT_SDS(20, 13, 3, qsgmii)
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SWITCH_PORT_SDS(21, 14, 3, qsgmii)
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SWITCH_PORT_SDS(22, 15, 3, qsgmii)
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SWITCH_PORT_SDS(23, 16, 3, qsgmii)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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