Markus StockhausenandRobert Marko
316f41e310
The Realtek target currently uses two phy macros to simplify the device dts. - EXTERNAL_PHY() to denote a phy attached to the SoC - INTERNAL_PHY() to denote an internal PHY (inside the SoC) There is no benefit doing this. The topology around a port/phy is well defined by the port macros. They link port, phy, pcs and even leds. The only consumer of the attribute "phy-is-integrated" is inside the dsa driver and that is being refactored. As a first step define a new more meaningful PHY_C22() macro that describes a c22 capable phy. This does not need to care about the external/internal relation. To make it even more useful for the RTL93xx targets with multiple mdio busses give it two parameters PHY_C22(port_number, bus_address) where - port_number is the absolute overall unique phy number - bus_address is the location of the phy on the bus For RTL83xx these two parameters will usually be the same. Instead of three steps (inventing the macro, converting the consumers and removeing the old macor) do a one-step conversion for the existing EXTERNAL_PHY() macro. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22698 Signed-off-by: Robert Marko <robimarko@gmail.com>
123 lines
2.7 KiB
Devicetree
123 lines
2.7 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl8380_zyxel_gs1900.dtsi"
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#include "rtl8380_zyxel_gs1900_gpio.dtsi"
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/ {
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/* i2c of the left SFP cage: port 25 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of the right SFP cage: port 26 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT_SDS(16, 17, 2, qsgmii)
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SWITCH_PORT_SDS(17, 18, 2, qsgmii)
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SWITCH_PORT_SDS(18, 19, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 2, qsgmii)
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SWITCH_PORT_SDS(20, 21, 3, qsgmii)
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SWITCH_PORT_SDS(21, 22, 3, qsgmii)
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SWITCH_PORT_SDS(22, 23, 3, qsgmii)
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SWITCH_PORT_SDS(23, 24, 3, qsgmii)
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port@24 {
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reg = <24>;
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label = "lan25";
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pcs-handle = <&serdes4>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan26";
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pcs-handle = <&serdes5>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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};
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};
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&gpio1 {
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/delete-node/ poe_enable;
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};
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