Markus StockhausenandRobert Marko
316f41e310
The Realtek target currently uses two phy macros to simplify the device dts. - EXTERNAL_PHY() to denote a phy attached to the SoC - INTERNAL_PHY() to denote an internal PHY (inside the SoC) There is no benefit doing this. The topology around a port/phy is well defined by the port macros. They link port, phy, pcs and even leds. The only consumer of the attribute "phy-is-integrated" is inside the dsa driver and that is being refactored. As a first step define a new more meaningful PHY_C22() macro that describes a c22 capable phy. This does not need to care about the external/internal relation. To make it even more useful for the RTL93xx targets with multiple mdio busses give it two parameters PHY_C22(port_number, bus_address) where - port_number is the absolute overall unique phy number - bus_address is the location of the phy on the bus For RTL83xx these two parameters will usually be the same. Instead of three steps (inventing the macro, converting the consumers and removeing the old macor) do a one-step conversion for the existing EXTERNAL_PHY() macro. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22698 Signed-off-by: Robert Marko <robimarko@gmail.com>
373 lines
8.1 KiB
Devicetree
373 lines
8.1 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl839x.dtsi"
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#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc";
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model = "Panasonic Switch-M48eG PN28480K";
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aliases {
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led-boot = &led_status_eco_green;
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led-failsafe = &led_status_eco_amber;
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led-running = &led_status_eco_green;
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led-upgrade = &led_status_eco_green;
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};
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fan: gpio-fan {
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compatible = "gpio-fan";
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gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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/* the actual speeds (rpm) are unknown, just use dummy values */
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gpio-fan,speed-map = <1 0>, <2 1>;
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#cooling-cells = <2>;
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};
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/*
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* sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48),
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* and they are connected to the RTL8218FB. Currently, there is
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* no support for the chip and only TP ports work by the RTL8218B
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* support.
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*/
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sfp0: sfp-p45 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p46 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp-p47 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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sfp3: sfp-p48 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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};
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thermal-zones {
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/*
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* Zone for SoC temperature
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*
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* Fan speed:
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*
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* - 0-44 celsius: Low
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* - 45-54 celsius: High
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*/
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cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens_soc>;
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trips {
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cpu_alert: trip-point {
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temperature = <45000>;
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hysteresis = <4000>;
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type = "active";
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};
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cpu_crit {
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temperature = <55000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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cooling-maps {
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map {
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trip = <&cpu_alert>;
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cooling-device = <&fan 0 1>;
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};
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};
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};
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/*
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* Zone for system temperature
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*
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* Fan speed:
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*
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* - 0-39 celsius: Low
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* - 40-49 celsius: High
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*
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* Note: official recommended ranges of temperature on each
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* fan speed setting:
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*
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* - Low speed : 0-40 celsius
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* - High speed: 0-50 celsius
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*
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* (stock firmware doesn't support auto-selection of
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* speed and need to be selected manually by user)
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*/
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sys-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens_sys>;
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trips {
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sys_alert: trip-point {
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temperature = <40000>;
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hysteresis = <4000>;
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type = "active";
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};
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sys_crit {
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temperature = <50000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map {
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trip = <&sys_alert>;
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cooling-device = <&fan 0 1>;
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};
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};
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};
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};
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};
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&leds {
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led_status_eco_amber: led-5 {
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gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <1>;
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};
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led_status_eco_green: led-6 {
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gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <2>;
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};
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};
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&i2c_gpio_0 {
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scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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/* Microchip TCN75A (for SoC) */
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tsens_soc: sensor@48 {
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compatible = "microchip,tcn75";
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reg = <0x48>;
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#thermal-sensor-cells = <0>;
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};
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/* Microchip TCN75A (for System) */
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tsens_sys: sensor@49 {
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compatible = "microchip,tcn75";
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reg = <0x49>;
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#thermal-sensor-cells = <0>;
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};
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};
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&i2c_gpio_1 {
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scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&gpio2 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio0>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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/*
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* GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB
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*
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* This GPIO pin should be specified as "reset-gpio" in mdio node,
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* but the current configuration of RTL8218B phy in the phy driver
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* seems to be incomplete and RTL8218FB phy won't be configured on
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* RTL8218D support. So, ethernet ports on these phys will be broken
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* after hard-resetting.
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* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
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* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
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* by resetting.
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*/
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ext_switch_reset {
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "ext-switch-reset";
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};
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};
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&i2c_switch {
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i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c2: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c3: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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PHY_C22(24, 24)
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PHY_C22(25, 25)
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PHY_C22(26, 26)
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PHY_C22(27, 27)
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PHY_C22(28, 28)
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PHY_C22(29, 29)
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PHY_C22(30, 30)
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PHY_C22(31, 31)
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PHY_C22(32, 32)
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PHY_C22(33, 33)
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PHY_C22(34, 34)
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PHY_C22(35, 35)
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PHY_C22(36, 36)
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PHY_C22(37, 37)
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PHY_C22(38, 38)
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PHY_C22(39, 39)
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/* RTL8218FB */
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PHY_C22(40, 40)
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PHY_C22(41, 41)
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PHY_C22(42, 42)
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PHY_C22(43, 43)
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PHY_C22(44, 44)
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PHY_C22(45, 45)
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PHY_C22(46, 46)
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PHY_C22(47, 47)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT_SDS(8, 9, 2, qsgmii)
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SWITCH_PORT_SDS(9, 10, 2, qsgmii)
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SWITCH_PORT_SDS(10, 11, 2, qsgmii)
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SWITCH_PORT_SDS(11, 12, 2, qsgmii)
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SWITCH_PORT_SDS(12, 13, 3, qsgmii)
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SWITCH_PORT_SDS(13, 14, 3, qsgmii)
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SWITCH_PORT_SDS(14, 15, 3, qsgmii)
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SWITCH_PORT_SDS(15, 16, 3, qsgmii)
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SWITCH_PORT_SDS(16, 17, 4, qsgmii)
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SWITCH_PORT_SDS(17, 18, 4, qsgmii)
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SWITCH_PORT_SDS(18, 19, 4, qsgmii)
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SWITCH_PORT_SDS(19, 20, 4, qsgmii)
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SWITCH_PORT_SDS(20, 21, 5, qsgmii)
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SWITCH_PORT_SDS(21, 22, 5, qsgmii)
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SWITCH_PORT_SDS(22, 23, 5, qsgmii)
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SWITCH_PORT_SDS(23, 24, 5, qsgmii)
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SWITCH_PORT_SDS(24, 25, 6, qsgmii)
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SWITCH_PORT_SDS(25, 26, 6, qsgmii)
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SWITCH_PORT_SDS(26, 27, 6, qsgmii)
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SWITCH_PORT_SDS(27, 28, 6, qsgmii)
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SWITCH_PORT_SDS(28, 29, 7, qsgmii)
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SWITCH_PORT_SDS(29, 30, 7, qsgmii)
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SWITCH_PORT_SDS(30, 31, 7, qsgmii)
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SWITCH_PORT_SDS(31, 32, 7, qsgmii)
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SWITCH_PORT_SDS(32, 33, 8, qsgmii)
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SWITCH_PORT_SDS(33, 34, 8, qsgmii)
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SWITCH_PORT_SDS(34, 35, 8, qsgmii)
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SWITCH_PORT_SDS(35, 36, 8, qsgmii)
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SWITCH_PORT_SDS(36, 37, 9, qsgmii)
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SWITCH_PORT_SDS(37, 38, 9, qsgmii)
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SWITCH_PORT_SDS(38, 39, 9, qsgmii)
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SWITCH_PORT_SDS(39, 40, 9, qsgmii)
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SWITCH_PORT_SDS(40, 41, 10, qsgmii)
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SWITCH_PORT_SDS(41, 42, 10, qsgmii)
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SWITCH_PORT_SDS(42, 43, 10, qsgmii)
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SWITCH_PORT_SDS(43, 44, 10, qsgmii)
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SWITCH_PORT_SDS(44, 45, 11, qsgmii)
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SWITCH_PORT_SDS(45, 46, 11, qsgmii)
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SWITCH_PORT_SDS(46, 47, 11, qsgmii)
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SWITCH_PORT_SDS(47, 48, 11, qsgmii)
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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