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eternalwrt-mt798x/target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
T
Markus StockhausenandRobert Marko 316f41e310 realtek: dts: convert EXTERNAL_PHY() to PHY_C22() 
The Realtek target currently uses two phy macros to simplify the
device dts.

- EXTERNAL_PHY() to denote a phy attached to the SoC
- INTERNAL_PHY() to denote an internal PHY (inside the SoC)

There is no benefit doing this. The topology around a port/phy is
well defined by the port macros. They link port, phy, pcs and even
leds. The only consumer of the attribute "phy-is-integrated" is
inside the dsa driver and that is being refactored.

As a first step define a new more meaningful PHY_C22() macro that
describes a c22 capable phy. This does not need to care about the
external/internal relation. To make it even more useful for the
RTL93xx targets with multiple mdio busses give it two parameters
PHY_C22(port_number, bus_address) where

- port_number is the absolute overall unique phy number
- bus_address is the location of the phy on the bus

For RTL83xx these two parameters will usually be the same. Instead
of three steps (inventing the macro, converting the consumers and
removeing the old macor) do a one-step conversion for the existing
EXTERNAL_PHY() macro.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22698
Signed-off-by: Robert Marko <robimarko@gmail.com>
2026-03-31 12:56:24 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rtl839x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
model = "TP-Link SG2452P v4";
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
label-mac-device = &ethernet0;
};
chosen {
stdout-path = "serial0:38400n8";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
speed {
label = "speed";
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
};
gpio_fan_sys {
compatible = "gpio-fan";
alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
gpio_fan_psu_1 {
pinctrl-names = "default";
pinctrl-0 = <&disable_jtag>;
compatible = "gpio-fan";
alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
/* the actual speeds (rpm) are unknown, just use dummy values */
gpio-fan,speed-map = <1 0>, <2 1>;
#cooling-cells = <2>;
};
gpio_fan_psu_2 {
/* This fan runs in parallel to PSU1 fan, but has a separate
* alarm GPIO. This is not (yet) supported by the gpio-fan driver,
* so a separate instance is added
*/
compatible = "gpio-fan";
alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
leds {
pinctrl-names = "default";
compatible = "gpio-leds";
led-0 {
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
};
led-1 {
gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
};
led_sys: led-2 {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led-3 {
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led-4 {
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
function = "fault-fan";
};
led-5 {
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = "alarm-poe";
};
};
i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* LAN9 - LAN12 */
tps23861@5 {
compatible = "ti,tps23861";
reg = <0x05>;
};
/* LAN17 - LAN20 */
tps23861@6 {
compatible = "ti,tps23861";
reg = <0x06>;
};
/* LAN45 - LAN48 */
tps23861@9 {
compatible = "ti,tps23861";
reg = <0x09>;
};
/* LAN37 - LAN40 */
tps23861@a {
compatible = "ti,tps23861";
reg = <0x0a>;
};
/* LAN1 - LAN4 */
tps23861@14 {
compatible = "ti,tps23861";
reg = <0x14>;
};
/* LAN25 - LAN28 */
tps23861@24 {
compatible = "ti,tps23861";
reg = <0x24>;
};
/* LAN33 - LAN 36 */
tps23861@25 {
compatible = "ti,tps23861";
reg = <0x25>;
};
/* LAN41 - LAN44 */
tps23861@26 {
compatible = "ti,tps23861";
reg = <0x26>;
};
/* LAN13 - LAN16 */
tps23861@29 {
compatible = "ti,tps23861";
reg = <0x29>;
};
/* LAN29 - LAN32 */
tps23861@2c {
compatible = "ti,tps23861";
reg = <0x2c>;
};
/* LAN5 - LAN8 */
tps23861@48 {
compatible = "ti,tps23861";
reg = <0x48>;
};
/* LAN21 - LAN24 */
tps23861@49 {
compatible = "ti,tps23861";
reg = <0x49>;
};
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
};
};
&gpio0 {
poe-enable {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-enable";
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0xe0000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0xe0000 0x20000>;
};
/* We use the "sys", "usrimg1" and "usrimg2" partitions
* as firmware since the kernel needs to be in "sys", but the
* partition is too small to hold the "rootfs" as well.
* The original partition map contains:
*
* partition@100000 {
* label = "sys";
* reg = <0x100000 0x600000>;
* };
* partition@700000 {
* label = "usrimg1";
* reg = <0x700000 0xa00000>;
* };
* partition@1100000 {
* label = "usrimg2";
* reg = <0x1100000 0xa00000>;
* };
*/
partition@100000 {
label = "firmware";
reg = <0x100000 0x1a00000>;
};
partition@1b00000 {
label = "usrappfs";
reg = <0x1b00000 0x400000>;
};
partition@1f00000 {
label = "para";
reg = <0x1f00000 0x100000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
factory_macaddr: macaddr@fdff4 {
reg = <0xfdff4 0x6>;
};
};
};
};
};
};
&ethernet0 {
nvmem-cells = <&factory_macaddr>;
nvmem-cell-names = "mac-address";
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
#address-cells = <1>;
#size-cells = <0>;
/* External phy RTL8218B #1 */
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
/* CPU-Port */
port@52 {
ethernet = <&ethernet0>;
reg = <52>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
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