Markus StockhausenandRobert Marko
d7de7cae1a
Make the remaining devices use the new PHY_C45() macro. At least those that have no extra attributes in the phy definitions. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22715 Signed-off-by: Robert Marko <robimarko@gmail.com>
341 lines
6.3 KiB
Devicetree
341 lines
6.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "xikestor,sks8300-12e2t2x", "realtek,rtl9302-soc";
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model = "XikeStor SKS8300-12E2T2X";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* first 256 MiB */
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<0x20000000 0x10000000>; /* remaining 256 MiB */
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/*
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* 2,5G Ports LED0 (orange): 10M/100M/1G/LINK/ACT
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* 2,5G Ports LED1 (green): 2.5G/LINK/ACT
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*/
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led_set0 = <(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/*
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* 10G Ports LED0 (orange): 10M/100M/1G/2.5G/5G/LINK/ACT
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* 10G Ports LED1 (green): 10G/LINK/ACT
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*/
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led_set1 = <(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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};
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sfp0: sfp-p15 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp0>;
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maximum-power-milliwatt = <1500>;
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mod-def0-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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los-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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#thermal-sensor-cells = <0>;
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};
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sfp1: sfp-p16 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp1>;
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maximum-power-milliwatt = <1500>;
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mod-def0-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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los-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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#thermal-sensor-cells = <0>;
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};
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aliases {
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label-mac-device = ðernet0;
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c_sfp0: i2c@0 {
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reg = <0>;
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};
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i2c_sfp1: i2c@1 {
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reg = <1>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x1c0000>;
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read-only;
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};
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partition@1c0000 {
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label = "u-boot-env";
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reg = <0x1c0000 0x10000>;
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};
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partition@1d0000 {
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label = "sysinfo";
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reg = <0x1d0000 0x10000>;
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read-only;
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};
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partition@1e0000 {
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label = "factory";
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reg = <0x1e0000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_macaddr: macaddr@80 {
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reg = <0x80 0x6>;
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};
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};
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};
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partition@1f0000 {
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label = "sysdata";
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reg = <0x1f0000 0x10000>;
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};
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partition@200000 {
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label = "jffs2_filesystem";
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reg = <0x200000 0xa00000>;
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};
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partition@c00000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0xc00000 0x1400000>;
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openwrt,ih-magic = <0x93000000>;
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openwrt,offset = <0x10>;
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_bus0 {
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PHY_C45(0, 0)
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PHY_C45(1, 1)
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PHY_C45(2, 2)
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PHY_C45(3, 3)
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};
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&mdio_bus1 {
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PHY_C45(8, 0)
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PHY_C45(9, 1)
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PHY_C45(10, 2)
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PHY_C45(11, 3)
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};
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&mdio_bus2 {
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PHY_C45(16, 0)
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PHY_C45(17, 1)
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PHY_C45(18, 2)
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PHY_C45(19, 3)
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};
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&mdio_bus3 {
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PHY_C45(24, 0)
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PHY_C45(25, 1)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan2";
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led-set = <0>;
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pcs-handle = <&serdes2>;
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phy-handle = <&phy0>;
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phy-mode = "10g-qxgmii";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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led-set = <0>;
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pcs-handle = <&serdes2>;
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phy-handle = <&phy1>;
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phy-mode = "10g-qxgmii";
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};
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port@2 {
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reg = <2>;
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label = "lan4";
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led-set = <0>;
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pcs-handle = <&serdes2>;
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phy-handle = <&phy2>;
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phy-mode = "10g-qxgmii";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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led-set = <0>;
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pcs-handle = <&serdes2>;
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phy-handle = <&phy3>;
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phy-mode = "10g-qxgmii";
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};
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port@8 {
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reg = <8>;
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label = "lan6";
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led-set = <0>;
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pcs-handle = <&serdes3>;
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phy-handle = <&phy8>;
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phy-mode = "10g-qxgmii";
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};
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port@9 {
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reg = <9>;
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label = "lan5";
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led-set = <0>;
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pcs-handle = <&serdes3>;
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phy-handle = <&phy9>;
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phy-mode = "10g-qxgmii";
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};
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port@10 {
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reg = <10>;
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label = "lan8";
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led-set = <0>;
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pcs-handle = <&serdes3>;
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phy-handle = <&phy10>;
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phy-mode = "10g-qxgmii";
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};
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port@11 {
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reg = <11>;
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label = "lan7";
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led-set = <0>;
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pcs-handle = <&serdes3>;
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phy-handle = <&phy11>;
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phy-mode = "10g-qxgmii";
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};
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port@16 {
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reg = <16>;
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label = "lan10";
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led-set = <0>;
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pcs-handle = <&serdes4>;
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phy-handle = <&phy16>;
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phy-mode = "10g-qxgmii";
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};
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port@17 {
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reg = <17>;
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label = "lan9";
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led-set = <0>;
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pcs-handle = <&serdes4>;
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phy-handle = <&phy17>;
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phy-mode = "10g-qxgmii";
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};
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port@18 {
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reg = <18>;
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label = "lan12";
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led-set = <0>;
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pcs-handle = <&serdes4>;
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phy-handle = <&phy18>;
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phy-mode = "10g-qxgmii";
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};
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port@19 {
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reg = <19>;
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label = "lan11";
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led-set = <0>;
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pcs-handle = <&serdes4>;
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phy-handle = <&phy19>;
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phy-mode = "10g-qxgmii";
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};
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port@24 {
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reg = <24>;
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label = "lan13";
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led-set = <1>;
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pcs-handle = <&serdes6>;
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phy-handle = <&phy24>;
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phy-mode = "usxgmii";
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};
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port@25 {
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reg = <25>;
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label = "lan14";
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led-set = <1>;
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pcs-handle = <&serdes7>;
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phy-handle = <&phy25>;
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phy-mode = "usxgmii";
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};
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port@26 {
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reg = <26>;
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label = "lan15";
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led-set = <1>;
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pcs-handle = <&serdes8>;
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phy-mode = "1000base-x";
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sfp = <&sfp0>;
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managed = "in-band-status";
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};
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port@27 {
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reg = <27>;
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label = "lan16";
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led-set = <1>;
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pcs-handle = <&serdes9>;
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phy-mode = "1000base-x";
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sfp = <&sfp1>;
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managed = "in-band-status";
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};
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port@28 {
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reg = <28>;
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ethernet = <ðernet0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&thermal_zones {
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sfp-thermal {
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polling-delay-passive = <10000>;
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polling-delay = <10000>;
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thermal-sensors = <&sfp0>, <&sfp1>;
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trips {
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sfp-crit {
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temperature = <110000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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};
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