Chukun PanandHauke Mehrtens
ba7aa2a971
Currently, the DesignWare PCIe driver cannot configure interrupts on SoC that do not support MSIX. All MSI interrupts are handled by CPU0. Backport MSI affinity support for the PCI dwc driver from linux-next, so now we can adjust MSI interrupts to other CPU cores. Tested on HINLINK H28K (RK3528) and OrangePi R2S (Ky X1). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/21770 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
145 lines
4.5 KiB
Diff
145 lines
4.5 KiB
Diff
From a60d92f6d941bd77bf3aaec724a7c95857c0165b Mon Sep 17 00:00:00 2001
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From: Mayank Rana <mayank.rana@oss.qualcomm.com>
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Date: Mon, 16 Jun 2025 15:42:56 -0700
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Subject: [PATCH] PCI: dwc: Export DWC MSI controller related APIs
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Export dw_pcie_msi_host_init(), dw_pcie_msi_init(), and dw_pcie_free_msi()
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APIs to allow them to be reused by the upcoming DWC based ECAM driver
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implementation. Also, move MSI IRQ related initialization code to
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dw_pcie_msi_init(), as this code must be executed before dw_pcie_msi_init()
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API can be used with ECAM driver.
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Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
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[mani: commit message rewording]
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Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
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Link: https://patch.msgid.link/20250616224259.3549811-2-mayank.rana@oss.qualcomm.com
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---
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.../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++---------
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drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++
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2 files changed, 34 insertions(+), 18 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-designware-host.c
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+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
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@@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_p
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return 0;
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}
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-static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
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+void dw_pcie_free_msi(struct dw_pcie_rp *pp)
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{
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u32 ctrl;
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@@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_p
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irq_domain_remove(pp->msi_domain);
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irq_domain_remove(pp->irq_domain);
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}
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+EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
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-static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
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+void dw_pcie_msi_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u64 msi_target = (u64)pp->msi_data;
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+ u32 ctrl, num_ctrls;
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if (!pci_msi_enabled() || !pp->has_msi_ctrl)
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return;
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+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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+
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+ /* Initialize IRQ Status array */
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+ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
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+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
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+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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+ pp->irq_mask[ctrl]);
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+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
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+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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+ ~0);
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+ }
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+
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/* Program the msi_data */
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dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
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dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
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}
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+EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
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static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
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{
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@@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(s
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return 0;
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}
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-static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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@@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct
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return 0;
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}
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+EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init);
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static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
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{
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@@ -809,7 +825,7 @@ static int dw_pcie_iatu_setup(struct dw_
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int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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- u32 val, ctrl, num_ctrls;
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+ u32 val;
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int ret;
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/*
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@@ -820,20 +836,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *
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dw_pcie_setup(pci);
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- if (pp->has_msi_ctrl) {
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- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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-
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- /* Initialize IRQ Status array */
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- for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
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- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
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- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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- pp->irq_mask[ctrl]);
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- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
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- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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- ~0);
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- }
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- }
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-
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dw_pcie_msi_init(pp);
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/* Setup RC BARs */
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--- a/drivers/pci/controller/dwc/pcie-designware.h
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+++ b/drivers/pci/controller/dwc/pcie-designware.h
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@@ -678,6 +678,9 @@ static inline enum dw_pcie_ltssm dw_pcie
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int dw_pcie_suspend_noirq(struct dw_pcie *pci);
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int dw_pcie_resume_noirq(struct dw_pcie *pci);
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irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
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+void dw_pcie_msi_init(struct dw_pcie_rp *pp);
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+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
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+void dw_pcie_free_msi(struct dw_pcie_rp *pp);
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int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
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int dw_pcie_host_init(struct dw_pcie_rp *pp);
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void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
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@@ -700,6 +703,17 @@ static inline irqreturn_t dw_handle_msi_
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return IRQ_NONE;
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}
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+static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
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+{ }
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+
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+static inline int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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+{
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+ return -ENODEV;
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+}
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+
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+static inline void dw_pcie_free_msi(struct dw_pcie_rp *pp)
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+{ }
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+
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static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
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{
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return 0;
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