Chukun PanandHauke Mehrtens
ba7aa2a971
Currently, the DesignWare PCIe driver cannot configure interrupts on SoC that do not support MSIX. All MSI interrupts are handled by CPU0. Backport MSI affinity support for the PCI dwc driver from linux-next, so now we can adjust MSI interrupts to other CPU cores. Tested on HINLINK H28K (RK3528) and OrangePi R2S (Ky X1). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/21770 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
93 lines
3.3 KiB
Diff
93 lines
3.3 KiB
Diff
From eaf290c404f7c39f23292e9ce83b8b5b51ab598a Mon Sep 17 00:00:00 2001
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From: Radu Rendec <rrendec@redhat.com>
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Date: Fri, 28 Nov 2025 16:20:55 -0500
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Subject: [PATCH] PCI: dwc: Enable MSI affinity support
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Leverage the interrupt redirection infrastructure to enable CPU affinity
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support for MSI interrupts. Since the parent interrupt affinity cannot
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be changed, affinity control for the child interrupt (MSI) is achieved
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by redirecting the handler to run in IRQ work context on the target CPU.
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This patch was originally prepared by Thomas Gleixner (see Link tag below)
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in a patch series that was never submitted as is, and only parts of that
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series have made it upstream so far.
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Originally-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Radu Rendec <rrendec@redhat.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
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Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redhat.com
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---
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.../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++---
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1 file changed, 28 insertions(+), 5 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-designware-host.c
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+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
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@@ -26,9 +26,27 @@ static struct pci_ops dw_pcie_ops;
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static struct pci_ops dw_pcie_ecam_ops;
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static struct pci_ops dw_child_pcie_ops;
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+#ifdef CONFIG_SMP
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+static void dw_irq_noop(struct irq_data *d) { }
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+#endif
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+
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+static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
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+ struct irq_domain *real_parent, struct msi_domain_info *info)
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+{
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+ if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
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+ return false;
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+
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+#ifdef CONFIG_SMP
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+ info->chip->irq_ack = dw_irq_noop;
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+ info->chip->irq_pre_redirect = irq_chip_pre_redirect_parent;
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+#else
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+ info->chip->irq_ack = irq_chip_ack_parent;
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+#endif
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+ return true;
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+}
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+
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#define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
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MSI_FLAG_USE_DEF_CHIP_OPS | \
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- MSI_FLAG_NO_AFFINITY | \
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MSI_FLAG_PCI_MSI_MASK_PARENT)
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#define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
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MSI_FLAG_PCI_MSIX | \
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@@ -40,9 +58,8 @@ static const struct msi_parent_ops dw_pc
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.required_flags = DW_PCIE_MSI_FLAGS_REQUIRED,
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.supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED,
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.bus_select_token = DOMAIN_BUS_PCI_MSI,
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- .chip_flags = MSI_CHIP_FLAG_SET_ACK,
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.prefix = "DW-",
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- .init_dev_msi_info = msi_lib_init_dev_msi_info,
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+ .init_dev_msi_info = dw_pcie_init_dev_msi_info,
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};
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/* MSI int handler */
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@@ -63,7 +80,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp
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continue;
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for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL)
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- generic_handle_domain_irq(pp->irq_domain, irq_off + pos);
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+ generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos);
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}
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}
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@@ -140,10 +157,16 @@ static void dw_pci_bottom_ack(struct irq
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static struct irq_chip dw_pci_msi_bottom_irq_chip = {
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.name = "DWPCI-MSI",
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- .irq_ack = dw_pci_bottom_ack,
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.irq_compose_msi_msg = dw_pci_setup_msi_msg,
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.irq_mask = dw_pci_bottom_mask,
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.irq_unmask = dw_pci_bottom_unmask,
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+#ifdef CONFIG_SMP
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+ .irq_ack = dw_irq_noop,
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+ .irq_pre_redirect = dw_pci_bottom_ack,
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+ .irq_set_affinity = irq_chip_redirect_set_affinity,
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+#else
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+ .irq_ack = dw_pci_bottom_ack,
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+#endif
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};
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static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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