Caleb James DeLisleandHauke Mehrtens
c6bec81528
Extend the EN7528 PCIe driver to EN751221 with a specific PHY tuning ritual. Also enable wifi drivers on SmartFiber XP8421-B, TpLink Archer VR1200V v2 and Zyxel PMG5617GA. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Link: https://github.com/openwrt/openwrt/pull/22208 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
309 lines
6.4 KiB
Devicetree
309 lines
6.4 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/reset/econet,en751221-scu.h>
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#include <dt-bindings/clock/econet,en751221-scu.h>
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/dts-v1/;
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/ {
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compatible = "econet,en751221";
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#address-cells = <1>;
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#size-cells = <1>;
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hpt_clock: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>; /* 200 MHz */
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips34Kc";
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reg = <0>;
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};
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};
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cpuintc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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spi_ctrl: spi_controller@1fa10000 {
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compatible = "airoha,en7523-spi";
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reg = <0x1fa10000 0x140>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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nand: nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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nand-ecc-engine = <&nand>;
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};
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};
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chip_scu: syscon@1fa20000 {
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compatible = "econet,en751221-chip-scu", "syscon";
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reg = <0x1fa20000 0x388>;
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};
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pcie_phy1: pcie-phy@1fac0000 {
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compatible = "econet,en751221-pcie-phy1";
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reg = <0x1fac0000 0x1000>;
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#phy-cells = <0>;
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};
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pcie_phy0: pcie-phy@1faf2000 {
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compatible = "econet,en751221-pcie-phy0";
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reg = <0x1faf2000 0x1000>;
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#phy-cells = <0>;
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};
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intc: interrupt-controller@1fb40000 {
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compatible = "econet,en751221-intc";
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reg = <0x1fb40000 0x100>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
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};
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scuclk: clock-controller@1fb00000 {
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compatible = "econet,en751221-scu", "syscon";
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reg = <0x1fb00000 0x970>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ethernet: ethernet@1fb50000 {
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compatible = "econet,en751221-eth";
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reg = <0x1fb50000 0x10000>;
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resets = <&scuclk EN751221_FE_RST>,
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<&scuclk EN751221_FE_QDMA1_RST>,
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<&scuclk EN751221_FE_QDMA2_RST>,
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<&scuclk EN751221_GSW_RST>,
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<&scuclk EN751221_XPON_MAC_RST>,
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<&scuclk EN751221_XPON_PHY_RST>;
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reset-names = "fe", "qdma0", "qdma1", "gsw",
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"xpon-mac", "xpon-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <21>, <22>;
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gmac0: mac@0 {
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compatible = "econet,eth-mac";
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reg = <0>;
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phy-mode = "trgmii";
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status = "disabled";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "econet,eth-mac";
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reg = <1>;
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status = "disabled";
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phy-mode = "rgmii-rxid";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch@1f {
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compatible = "mediatek,mt7530";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f>;
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mediatek,mcm;
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reset-names = "mcm";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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status = "disabled";
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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status = "disabled";
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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status = "disabled";
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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status = "disabled";
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reg = <3>;
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label = "lan3";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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};
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pciecfg: pciecfg@1fb80000 {
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compatible = "mediatek,generic-pciecfg", "syscon";
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reg = <0x1fb80000 0x1000>;
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};
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pcie0: pcie@1fb81000 {
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compatible = "econet,en7528-pcie";
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device_type = "pci";
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reg = <0x1fb81000 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <23>;
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interrupt-names = "pcie_irq";
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clocks = <&scuclk EN751221_CLK_PCIE>;
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clock-names = "sys_ck0";
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy0";
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bus-range = <0x00 0xff>;
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ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>,
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<0x82000000 0 0x20000000 0x20000000 0 0x08000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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slot0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie1: pcie@1fb83000 {
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compatible = "econet,en7528-pcie";
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device_type = "pci";
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reg = <0x1fb83000 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <24>;
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interrupt-names = "pcie_irq";
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clocks = <&scuclk EN751221_CLK_PCIE>;
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clock-names = "sys_ck1";
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phys = <&pcie_phy1>;
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phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>,
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<0x82000000 0 0x28000000 0x28000000 0 0x08000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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usb: usb@1fb90000 {
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compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
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reg = <0x1fb90000 0x4000>,
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<0x1fa80700 0x100>;
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reg-names = "mac", "ippc";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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usb3-lpm-capable;
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};
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uart: serial@1fbf0000 {
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compatible = "ns16550";
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reg = <0x1fbf0000 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <0>;
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/*
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* Conversion of baud rate to clock frequency requires a
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* computation that is not in the ns16550 driver, so this
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* uart is fixed at 115200 baud.
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*/
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clock-frequency = <1843200>;
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};
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timer_hpt: timer@1fbf0400 {
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compatible = "econet,en751221-timer";
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reg = <0x1fbf0400 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <30>;
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clocks = <&hpt_clock>;
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};
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};
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