136 lines
3.7 KiB
Diff
136 lines
3.7 KiB
Diff
From 1bec3bd1f839f269dfdec3c635dd2afe15e30995 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@kernel.org>
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Date: Sun, 21 Dec 2025 19:05:10 +0800
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Subject: [PATCH] arm64: dts: allwinner: sun55i: Add SPI controllers
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The A523 family SoCs have four SPI controllers. One of them also
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supports DBI mode.
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Add device nodes for all of them. Also add pinmux nodes for spi0 on the
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PC pins, which is commonly used for SPI-NOR boot flash.
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Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Link: https://patch.msgid.link/20251221110513.1850535-4-wens@kernel.org
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Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
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---
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.../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++
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1 file changed, 94 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
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@@ -214,6 +214,43 @@
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allwinner,pinmux = <2>;
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};
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+ /omit-if-no-ref/
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+ spi0_pc_pins: spi0-pc-pins {
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+ pins = "PC2", "PC4", "PC12";
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+ function = "spi0";
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+ allwinner,pinmux = <4>;
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+ };
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+
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+ /omit-if-no-ref/
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+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
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+ pins = "PC3";
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+ function = "spi0";
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+ allwinner,pinmux = <4>;
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+ };
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+
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+ /omit-if-no-ref/
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+ spi0_cs1_pc_pin: spi0-cs1-pc-pin {
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+ pins = "PC7";
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+ function = "spi0";
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+ allwinner,pinmux = <4>;
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+ };
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+
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+ /omit-if-no-ref/
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+ spi0_hold_pc_pin: spi0-hold-pc-pin {
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+ /* conflicts with eMMC D7 */
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+ pins = "PC16";
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+ function = "spi0";
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+ allwinner,pinmux = <4>;
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+ };
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+
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+ /omit-if-no-ref/
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+ spi0_wp_pc_pin: spi0-wp-pc-pin {
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+ /* conflicts with eMMC D2 */
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+ pins = "PC15";
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+ function = "spi0";
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+ allwinner,pinmux = <4>;
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+ };
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+
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB9", "PB10";
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allwinner,pinmux = <2>;
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@@ -563,6 +600,49 @@
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#size-cells = <0>;
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};
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+ spi0: spi@4025000 {
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+ compatible = "allwinner,sun55i-a523-spi";
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+ reg = <0x04025000 0x1000>;
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+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 22>, <&dma 22>;
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+ dma-names = "rx", "tx";
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+ resets = <&ccu RST_BUS_SPI0>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@4026000 {
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+ compatible = "allwinner,sun55i-a523-spi-dbi",
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+ "allwinner,sun55i-a523-spi";
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+ reg = <0x04026000 0x1000>;
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+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 23>, <&dma 23>;
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+ dma-names = "rx", "tx";
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+ resets = <&ccu RST_BUS_SPI1>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi2: spi@4027000 {
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+ compatible = "allwinner,sun55i-a523-spi";
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+ reg = <0x04027000 0x1000>;
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+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 24>, <&dma 24>;
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+ dma-names = "rx", "tx";
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+ resets = <&ccu RST_BUS_SPI2>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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usb_otg: usb@4100000 {
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compatible = "allwinner,sun55i-a523-musb",
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"allwinner,sun8i-a33-musb";
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@@ -815,6 +895,20 @@
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#clock-cells = <1>;
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};
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+ r_spi0: spi@7092000 {
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+ compatible = "allwinner,sun55i-a523-spi";
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+ reg = <0x07092000 0x1000>;
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+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 53>, <&dma 53>;
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+ dma-names = "rx", "tx";
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+ resets = <&r_ccu RST_BUS_R_SPI>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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mcu_ccu: clock-controller@7102000 {
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compatible = "allwinner,sun55i-a523-mcu-ccu";
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reg = <0x7102000 0x200>;
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