265 lines
5.9 KiB
Diff
265 lines
5.9 KiB
Diff
--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523-cpu-opp.dtsi
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@@ -0,0 +1,173 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/ {
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+ cpu0_opp_table: opp-table-cluster0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-408000000 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-672000000 {
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+ opp-hz = /bits/ 64 <672000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-792000000 {
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+ opp-hz = /bits/ 64 <792000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-936000000 {
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+ opp-hz = /bits/ 64 <936000000>;
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+ opp-microvolt = <920000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <920000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <960000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1224000000 {
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+ opp-hz = /bits/ 64 <1224000000>;
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+ opp-microvolt = <1000000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1320000000 {
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+ opp-hz = /bits/ 64 <1320000000>;
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+ opp-microvolt = <1050000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+
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+ cpu1_opp_table: opp-table-cluster1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-408000000 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-672000000 {
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+ opp-hz = /bits/ 64 <672000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-840000000 {
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+ opp-hz = /bits/ 64 <840000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <920000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1344000000 {
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+ opp-hz = /bits/ 64 <1344000000>;
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+ opp-microvolt = <960000>; //fixme
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1488000000 {
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+ opp-hz = /bits/ 64 <1488000000>;
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+ opp-microvolt = <1000000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1584000000 {
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+ opp-hz = /bits/ 64 <1584000000>;
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+ opp-microvolt = <1050000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1680000000 {
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+ opp-hz = /bits/ 64 <1680000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <1150000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1992000000 {
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+ opp-hz = /bits/ 64 <1992000000>;
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+ opp-microvolt = <1220000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ capacity-dmips-mhz = <5>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+};
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+
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+&cpu1 {
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+ capacity-dmips-mhz = <5>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+};
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+
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+&cpu2 {
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+ capacity-dmips-mhz = <5>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+};
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+
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+&cpu3 {
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+ capacity-dmips-mhz = <5>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+};
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+
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+&cpu4 {
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+ capacity-dmips-mhz = <9>;
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+ operating-points-v2 = <&cpu1_opp_table>;
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+};
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+
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+&cpu5 {
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+ capacity-dmips-mhz = <9>;
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+ operating-points-v2 = <&cpu1_opp_table>;
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+};
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+
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+&cpu6 {
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+ capacity-dmips-mhz = <9>;
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+ operating-points-v2 = <&cpu1_opp_table>;
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+};
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+
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+&cpu7 {
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+ capacity-dmips-mhz = <9>;
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+ operating-points-v2 = <&cpu1_opp_table>;
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+};
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--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
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@@ -4,6 +4,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/clock/sun55i-a523-ccu.h>
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+#include <dt-bindings/clock/sun55i-a523-ccu-cpu.h>
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#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
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#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-ccu.h>
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@@ -27,6 +28,7 @@
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device_type = "cpu";
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reg = <0x000>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUL>;
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#cooling-cells = <2>;
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};
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@@ -35,6 +37,7 @@
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device_type = "cpu";
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reg = <0x100>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUL>;
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#cooling-cells = <2>;
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};
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@@ -43,6 +46,7 @@
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device_type = "cpu";
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reg = <0x200>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUL>;
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#cooling-cells = <2>;
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};
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@@ -51,6 +55,7 @@
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device_type = "cpu";
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reg = <0x300>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUL>;
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#cooling-cells = <2>;
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};
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@@ -59,6 +64,7 @@
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device_type = "cpu";
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reg = <0x400>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUB>;
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#cooling-cells = <2>;
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};
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@@ -67,6 +73,7 @@
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device_type = "cpu";
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reg = <0x500>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUB>;
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#cooling-cells = <2>;
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};
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@@ -75,6 +82,7 @@
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device_type = "cpu";
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reg = <0x600>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUB>;
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#cooling-cells = <2>;
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};
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@@ -83,6 +91,7 @@
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device_type = "cpu";
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reg = <0x700>;
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enable-method = "psci";
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+ clocks = <&ccu_cpu CLK_CPUB>;
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#cooling-cells = <2>;
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};
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};
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@@ -622,6 +631,13 @@
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#size-cells = <0>;
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};
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+ ccu_cpu: clock@8817000 {
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+ compatible = "allwinner,sun55i-a523-ccu-cpu";
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+ reg = <0x08817000 0x4000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun55i-a523-mmc",
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"allwinner,sun20i-d1-mmc";
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