Tianling ShenandHauke Mehrtens
5917c67af9
Motorcomm YT6801 is a PCIe ethernet controller based on DWMAC4 IP. It integrates an GbE phy, supporting WOL, VLAN tagging and various types of offloading. It ships an on-chip eFuse for storing various vendor configuration, including MAC address. The PM and plat_data functions were slightly modified to build with current kernel. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/22923 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
86 lines
3.5 KiB
Diff
86 lines
3.5 KiB
Diff
From 63161fb6353493c648a260244f6ac7eca65fd48e Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jakub=20Van=C4=9Bk?= <linuxtardis@gmail.com>
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Date: Mon, 2 Mar 2026 20:31:37 +0100
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Subject: [PATCH] net: phy: Work around MDIO collisions in the YT8821 driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Cudy M3000 router suffers from a MDIO bus collision:
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- The MT7981B internal gigabit PHY listens on address 0.
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- The Motorcomm YT8821 is strapped to listen on address 1,
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but it initially also listens on address 0 (Motorcomm
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incorrectly considers that address a broadcast address).
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Without this patch, the YT8821 reacts to MDIO commands intended
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for the internal gigabit PHY and that makes it work unreliably.
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The YT8821 state somehow gets corrupted by the commands for the MT7981
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(e.g. we get 100Mbps speeds on gigabit links).
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This dirty workaround resets the PHY to cancel out any earlier
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YT8821 register corruption and then it disables the address 0
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as soon as possible. This should make the YT8821 work reliably.
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BEWARE though: the PHY will be reset only if the device tree
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node that defines the PHY carries the reset-gpios attribute.
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The PHY will not be reset if the reset GPIO is either on the MDIO
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bus node or is not defined at all. This might not always be a problem --
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some routers do not require the PHY to be reset (e.g. Cudy WR3000H,
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where there likely is less communication with the MT7981B PHY,
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and so the YT8821 PHY works reasonably well there even without this patch).
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This patch also does not address the possible MDIO bus collisions
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when the MT7981B PHY driver initially configures that PHY and invokes
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some read transactions on the bus. I am hoping that the MT7981B MDIO
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bus controller gives priority to the internal PHY and so it would
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not be affected by these collisions. However, I don't have anything
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to base this on apart from it "seeming to be working okay".
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This patch is unlikely to be mergeable into the mainline kernel.
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Upstream has strongly indicated that they would prefer this problem
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to be resolved by the platform bootloader (e.g. U-Boot), see
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- https://lore.kernel.org/all/d3bb9c36-5a0e-4339-901d-2dd21bdba395@gmail.com/
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- https://lore.kernel.org/all/20260228232241.1274236-1-linuxtardis@gmail.com/
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Signed-off-by: Jakub Vaněk <linuxtardis@gmail.com>
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---
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drivers/net/phy/motorcomm.c | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -228,6 +228,9 @@
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#define YT8521_LED_100_ON_EN BIT(5)
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#define YT8521_LED_10_ON_EN BIT(4)
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+#define YTPHY_MDIO_ADDRESS_CONTROL_REG 0xA005
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+#define YTPHY_MACR_EN_PHY_ADDR_0 BIT(6)
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+
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#define YTPHY_MISC_CONFIG_REG 0xA006
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#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
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#define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
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@@ -2777,6 +2780,23 @@ static int yt8821_config_init(struct phy
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int ret;
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u16 set;
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+ /* Hard-reset the PHY to clear out any register corruption
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+ * from preceding MDIO bus conflicts.
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+ */
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+ phy_device_reset(phydev, 1);
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+
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+ /* Deassert the reset GPIO under the MDIO bus lock to make
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+ * sure that nothing will communicate on the bus until we
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+ * disable the broadcast address in the YT8821.
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+ */
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+ phy_lock_mdio_bus(phydev);
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+ phy_device_reset(phydev, 0);
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+ ret = ytphy_modify_ext(phydev,
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+ YTPHY_MDIO_ADDRESS_CONTROL_REG,
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+ YTPHY_MACR_EN_PHY_ADDR_0,
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+ 0);
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+ phy_unlock_mdio_bus(phydev);
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+
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if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX)
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mode = YT8821_CHIP_MODE_FORCE_BX2500;
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