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eternalwrt-mt798x/target/linux/mediatek/patches-6.18/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch
T
Daniel Golle dbd8eab75d generic: 6.18: mtk_eth_soc: improve non-MTK tag_8021q DSA 
Add patches to improve support for using 3rd-party DSA switches
like MaxLinear MxL862xx with MediaTek's mtk_eth_soc being the
conduit. This involves reorganizing hardware queues to avoid
overlap (currently dp->index is used -- if there is more than one
DSA switch this is problematic), and correctly programming flows
of the non-MTK DSA users ports in the PPE offloading engine.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2026-04-27 13:12:03 +01:00

327 lines
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From 56973433cbea9f91f5f7eddebbc361ffc2bd6156 Mon Sep 17 00:00:00 2001
From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Date: Mon, 26 May 2025 13:20:42 +0800
Subject: [PATCH] net: ethernet: mtk_eth_soc: add mt7987 support
Without this patch, users are unable to bring up ETH driver on the
mt7987.
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_path.c | 9 +-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 138 ++++++++++++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 70 ++++++++--
3 files changed, 179 insertions(+), 38 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -106,13 +106,14 @@ static int set_mux_gmac2_gmac0_to_gephy(
return 0;
}
-static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
+static int set_mux_u3_gmac23_to_qphy(struct mtk_eth *eth, u64 path)
{
unsigned int val = 0, mask = 0, reg = 0;
bool updated = true;
switch (path) {
case MTK_ETH_PATH_GMAC2_SGMII:
+ case MTK_ETH_PATH_GMAC3_SGMII:
if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
reg = USB_PHY_SWITCH_REG;
val = SGMII_QPHY_SEL;
@@ -283,9 +284,9 @@ static const struct mtk_eth_muxc mtk_eth
.cap_bit = MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY,
.set_path = set_mux_gmac2_gmac0_to_gephy,
}, {
- .name = "mux_u3_gmac2_to_qphy",
- .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
- .set_path = set_mux_u3_gmac2_to_qphy,
+ .name = "mux_u3_gmac23_to_qphy",
+ .cap_bit = MTK_ETH_MUX_U3_GMAC23_TO_QPHY,
+ .set_path = set_mux_u3_gmac23_to_qphy,
}, {
.name = "mux_gmac2_to_2p5gphy",
.cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -794,10 +794,16 @@ static void mtk_set_queue_speed(struct m
return;
val = MTK_QTX_SCH_MIN_RATE_EN |
- /* minimum: 10 Mbps */
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+ /* minimum: 10 Mbps */
+ if (mtk_is_netsys_v3_or_greater(eth) &&
+ (eth->soc->caps != MT7988_CAPS)) {
+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
+ } else {
+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
+ }
if (mtk_is_netsys_v1(eth))
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
@@ -824,6 +830,30 @@ static void mtk_set_queue_speed(struct m
default:
break;
}
+ } else if (mtk_is_netsys_v3_or_greater(eth) &&
+ (eth->soc->caps != MT7988_CAPS)) {
+ switch (speed) {
+ case SPEED_10:
+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 4) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
+ break;
+ case SPEED_100:
+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 5) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
+ break;
+ case SPEED_1000:
+ val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 6) |
+ FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 10);
+ break;
+ default:
+ break;
+ }
} else {
switch (speed) {
case SPEED_10:
@@ -905,7 +935,7 @@ static void mtk_xgdm_mac_link_up(struct
return;
/* Eliminate the interference(before link-up) caused by PHY noise */
- mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
+ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->hw, mac->id));
mdelay(20);
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
MTK_XMAC_CNT_CTRL(mac->id));
@@ -2942,10 +2972,16 @@ static int mtk_tx_alloc(struct mtk_eth *
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
val = MTK_QTX_SCH_MIN_RATE_EN |
- /* minimum: 10 Mbps */
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+ /* minimum: 10 Mbps */
+ if (mtk_is_netsys_v3_or_greater(eth) &&
+ (eth->soc->caps != MT7988_CAPS)) {
+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
+ } else {
+ val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
+ }
if (mtk_is_netsys_v1(eth))
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
@@ -5993,6 +6029,37 @@ static const struct mtk_soc_data mt7986_
},
};
+static const struct mtk_soc_data mt7987_data = {
+ .reg_map = &mt7988_reg_map,
+ .ana_rgc3 = 0x128,
+ .caps = MT7987_CAPS,
+ .hw_features = MTK_HW_FEATURES,
+ .required_clks = MT7987_CLKS_BITMAP,
+ .required_pctl = false,
+ .version = 3,
+ .offload_version = 2,
+ .ppe_num = 2,
+ .hash_offset = 4,
+ .has_accounting = true,
+ .num_tx_queues = 32,
+ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ .tx = {
+ DESC_SIZE(struct mtk_tx_dma_v2),
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ .dma_size = MTK_DMA_SIZE(2K),
+ .fq_dma_size = MTK_DMA_SIZE(4K),
+ },
+ .rx = {
+ DESC_SIZE(struct mtk_rx_dma_v2),
+ .irq_done_mask = MTK_RX_DONE_INT_V2,
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ .dma_size = MTK_DMA_SIZE(2K),
+ },
+};
+
static const struct mtk_soc_data mt7988_data = {
.reg_map = &mt7988_reg_map,
.ana_rgc3 = 0x128,
@@ -6055,6 +6122,7 @@ const struct of_device_id of_mtk_match[]
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
+ { .compatible = "mediatek,mt7987-eth", .data = &mt7987_data },
{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
{},
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -271,6 +271,13 @@
#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
+#define MTK_QTX_SCH_MAX_RATE_EN_V3 BIT(26)
+#define MTK_QTX_SCH_MIN_RATE_MAN_V3 GENMASK(25, 19)
+#define MTK_QTX_SCH_MIN_RATE_EXP_V3 GENMASK(18, 16)
+#define MTK_QTX_SCH_MAX_RATE_WEIGHT_V3 GENMASK(15, 10)
+#define MTK_QTX_SCH_MAX_RATE_MAN_V3 GENMASK(9, 3)
+#define MTK_QTX_SCH_MAX_RATE_EXP_V3 GENMASK(2, 0)
+
/* QDMA TX Scheduler Rate Control Register */
#define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
@@ -546,9 +553,23 @@
#define XMAC_MCR_FORCE_RX_FC BIT(4)
/* XFI Mac logic reset registers */
-#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
+#define MTK_XMAC_LOGIC_RST(eth, x) (MTK_XMAC_BASE(x) + \
+ (MTK_HAS_CAPS((eth)->soc->caps, MTK_XGMAC_V2) ? \
+ 0x820 : 0x10))
#define XMAC_LOGIC_RST BIT(0)
+/* XFI Mac status force registers */
+#define MTK_XMAC_STS(x) (MTK_XMAC_MCR(x) + 0x14)
+
+/* XFI Mac status force registers */
+#define MTK_XMAC_STS_FRC(x) (MTK_XMAC_MCR(x) + 0x18)
+#define XMAC_FORCE_RX_FC_MODE BIT(13)
+#define XMAC_FORCE_TX_FC_MODE BIT(12)
+#define XMAC_FORCE_LINK_MODE BIT(8)
+#define XMAC_FORCE_RX_FC BIT(5)
+#define XMAC_FORCE_TX_FC BIT(4)
+#define XMAC_FORCE_LINK BIT(0)
+
/* XFI Mac count global control */
#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
#define XMAC_GLB_CNTCLR BIT(0)
@@ -849,6 +870,17 @@ enum mtk_clks_map {
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
+#define MT7987_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP1) | \
+ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP3) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL))
#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
@@ -1005,12 +1037,14 @@ enum mkt_eth_capabilities {
MTK_RSTCTRL_PPE2_BIT,
MTK_U3_COPHY_V2_BIT,
MTK_SRAM_BIT,
+ MTK_XGMAC_BIT,
+ MTK_XGMAC_V2_BIT,
MTK_36BIT_DMA_BIT,
/* MUX BITS*/
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
- MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
+ MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT,
MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
@@ -1052,14 +1086,16 @@ enum mkt_eth_capabilities {
#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
+#define MTK_XGMAC BIT_ULL(MTK_XGMAC_BIT)
+#define MTK_XGMAC_V2 BIT_ULL(MTK_XGMAC_V2_BIT)
#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
-#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
- BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
+#define MTK_ETH_MUX_U3_GMAC23_TO_QPHY \
+ BIT_ULL(MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT)
#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1091,12 +1127,13 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
-#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC)
+#define MTK_GMAC2_2P5GPHY_V2 (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC_V2)
#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
-#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
-#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
-#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII | MTK_XGMAC)
+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII | MTK_XGMAC)
+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII | MTK_XGMAC)
/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1106,9 +1143,9 @@ enum mkt_eth_capabilities {
#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
-/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
-#define MTK_MUX_U3_GMAC2_TO_QPHY \
- (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
+/* 0: U3 -> QPHY, 1: GMACx -> QPHY where x is 2 or 3 */
+#define MTK_MUX_U3_GMAC23_TO_QPHY \
+ (MTK_ETH_MUX_U3_GMAC23_TO_QPHY | MTK_MUX | MTK_INFRA)
/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1148,18 +1185,24 @@ enum mkt_eth_capabilities {
#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
- MTK_MUX_U3_GMAC2_TO_QPHY | \
+ MTK_MUX_U3_GMAC23_TO_QPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+ MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)
+#define MT7987_CAPS (MTK_36BIT_DMA | MTK_GMAC1_SGMII | \
+ MTK_GMAC2_2P5GPHY_V2 | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
+ MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
+ MTK_QDMA | MTK_RSTCTRL_PPE1)
+
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
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