Daniel Golle
dbd8eab75d
Add patches to improve support for using 3rd-party DSA switches like MaxLinear MxL862xx with MediaTek's mtk_eth_soc being the conduit. This involves reorganizing hardware queues to avoid overlap (currently dp->index is used -- if there is more than one DSA switch this is problematic), and correctly programming flows of the non-MTK DSA users ports in the PPE offloading engine. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
80 lines
2.7 KiB
Diff
80 lines
2.7 KiB
Diff
From 5ef0b04d30efff8f171e30bfbe876c00e3b9036a Mon Sep 17 00:00:00 2001
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From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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Date: Fri, 9 May 2025 09:49:04 +0800
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Subject: [PATCH] net: ethernet: mtk_eth_soc: revise hardware configuration for
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mt7987
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Change hardware configuration for the MT7987.
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- Enable PSE drop mechanism when the WDMA Rx ring full
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- Enable PSE no-drop mechanism for packets from the WDMA Tx
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Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 +++++++++++++--------
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1 file changed, 31 insertions(+), 18 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -4570,27 +4570,40 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
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PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
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- /* PSE free buffer drop threshold */
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- mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
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-
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- /* PSE should not drop port8, port9 and port13 packets from
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- * WDMA Tx
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- */
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- mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
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-
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- /* PSE should drop packets to port8, port9 and port13 on WDMA Rx
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- * ring full
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- */
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- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
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- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
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- mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
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-
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- /* GDM and CDM Threshold */
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- mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
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- mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
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-
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- /* Disable GDM1 RX CRC stripping */
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- mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
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+ if (eth->soc->caps == MT7988_CAPS) {
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+ /* PSE free buffer drop threshold */
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+ mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
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+
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+ /* PSE should not drop port8, port9 and port13 packets
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+ * from WDMA Tx
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+ */
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+ mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
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+
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+ /* PSE should drop packets to port8, port9 and port13
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+ * on WDMA Rx ring full
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+ */
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+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
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+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
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+ mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
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+
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+ /* GDM and CDM Threshold */
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+ mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
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+ mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
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+ } else if (eth->soc->caps == MT7987_CAPS) {
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+ /* PSE should not drop port8 packets from WDMA Tx */
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+ mtk_w32(eth, 0x00000100, PSE_DROP_CFG);
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+
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+ /* PSE should drop packets to port8 on WDMA Rx ring
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+ * full
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+ */
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+ mtk_w32(eth, 0x00000100, PSE_PPE_DROP(0));
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+ mtk_w32(eth, 0x00000100, PSE_PPE_DROP(1));
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+ }
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+
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_ESW)) {
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+ /* Disable GDM1 RX CRC stripping */
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+ mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
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+ }
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/* PSE GDM3 MIB counter has incorrect hw default values,
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* so the driver ought to read clear the values beforehand
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