Tianling ShenandNick Hainke
86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
57 lines
1.5 KiB
Diff
57 lines
1.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Date: Tue, 26 Aug 2025 10:08:36 +0200
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Subject: arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
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The Radxa ROCK 5T has two M.2 slots, much like the Radxa Rock 5B+. As it
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stands, the board won't be able to use PCIe3 if the second M.2 slot is
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in use.
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Fix this by adding the necessary node enablement and data-lanes property
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to the ROCK 5T device tree, mirroring what's in the ROCK 5B+ device
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tree.
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Reported-by: FUKAUMI Naoki <naoki@radxa.com>
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Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38610630;
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Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree")
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Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
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@@ -68,6 +68,22 @@
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status = "okay";
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};
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+&pcie30phy {
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+ data-lanes = <1 1 2 2>;
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+};
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+
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+&pcie3x2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie3x2_rst>;
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+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie30>;
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+ status = "okay";
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+};
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+
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+&pcie3x4 {
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+ num-lanes = <2>;
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+};
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+
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&pinctrl {
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hdmirx {
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hdmirx_hpd: hdmirx-5v-detection {
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@@ -90,6 +106,12 @@
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};
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};
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+ pcie3 {
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+ pcie3x2_rst: pcie3x2-rst {
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+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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sound {
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hp_detect: hp-detect {
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rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
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