Tianling ShenandNick Hainke
2c9986eedd
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
239 lines
7.1 KiB
Diff
239 lines
7.1 KiB
Diff
From a5e4cde647851ed67f19a5cb54a99282f32aae99 Mon Sep 17 00:00:00 2001
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From: Steven Liu <steven.liu@rock-chips.com>
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Date: Fri, 28 Feb 2025 06:40:09 +0000
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Subject: [PATCH] pinctrl: rockchip: Add support for RK3528
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Add gpio and pinctrl support for the 5 GPIO banks on RK3528.
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Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/20250228064024.3200000-4-jonas@kwiboo.se
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-rockchip.c | 160 ++++++++++++++++++++++++++++-
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drivers/pinctrl/pinctrl-rockchip.h | 1 +
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2 files changed, 160 insertions(+), 1 deletion(-)
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--- a/drivers/pinctrl/pinctrl-rockchip.c
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+++ b/drivers/pinctrl/pinctrl-rockchip.c
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@@ -2003,6 +2003,115 @@ static int rk3399_calc_drv_reg_and_bit(s
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return 0;
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}
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+#define RK3528_DRV_BITS_PER_PIN 8
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+#define RK3528_DRV_PINS_PER_REG 2
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+#define RK3528_DRV_GPIO0_OFFSET 0x100
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+#define RK3528_DRV_GPIO1_OFFSET 0x20120
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+#define RK3528_DRV_GPIO2_OFFSET 0x30160
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+#define RK3528_DRV_GPIO3_OFFSET 0x20190
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+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
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+
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+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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+ int pin_num, struct regmap **regmap,
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+ int *reg, u8 *bit)
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+{
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+ struct rockchip_pinctrl *info = bank->drvdata;
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+
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+ *regmap = info->regmap_base;
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+
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+ if (bank->bank_num == 0)
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+ *reg = RK3528_DRV_GPIO0_OFFSET;
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+ else if (bank->bank_num == 1)
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+ *reg = RK3528_DRV_GPIO1_OFFSET;
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+ else if (bank->bank_num == 2)
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+ *reg = RK3528_DRV_GPIO2_OFFSET;
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+ else if (bank->bank_num == 3)
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+ *reg = RK3528_DRV_GPIO3_OFFSET;
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+ else if (bank->bank_num == 4)
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+ *reg = RK3528_DRV_GPIO4_OFFSET;
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+ else
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+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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+
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+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
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+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
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+ *bit *= RK3528_DRV_BITS_PER_PIN;
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+
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+ return 0;
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+}
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+
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+#define RK3528_PULL_BITS_PER_PIN 2
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+#define RK3528_PULL_PINS_PER_REG 8
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+#define RK3528_PULL_GPIO0_OFFSET 0x200
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+#define RK3528_PULL_GPIO1_OFFSET 0x20210
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+#define RK3528_PULL_GPIO2_OFFSET 0x30220
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+#define RK3528_PULL_GPIO3_OFFSET 0x20230
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+#define RK3528_PULL_GPIO4_OFFSET 0x10240
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+
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+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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+ int pin_num, struct regmap **regmap,
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+ int *reg, u8 *bit)
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+{
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+ struct rockchip_pinctrl *info = bank->drvdata;
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+
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+ *regmap = info->regmap_base;
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+
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+ if (bank->bank_num == 0)
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+ *reg = RK3528_PULL_GPIO0_OFFSET;
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+ else if (bank->bank_num == 1)
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+ *reg = RK3528_PULL_GPIO1_OFFSET;
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+ else if (bank->bank_num == 2)
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+ *reg = RK3528_PULL_GPIO2_OFFSET;
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+ else if (bank->bank_num == 3)
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+ *reg = RK3528_PULL_GPIO3_OFFSET;
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+ else if (bank->bank_num == 4)
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+ *reg = RK3528_PULL_GPIO4_OFFSET;
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+ else
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+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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+
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+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
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+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
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+ *bit *= RK3528_PULL_BITS_PER_PIN;
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+
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+ return 0;
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+}
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+
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+#define RK3528_SMT_BITS_PER_PIN 1
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+#define RK3528_SMT_PINS_PER_REG 8
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+#define RK3528_SMT_GPIO0_OFFSET 0x400
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+#define RK3528_SMT_GPIO1_OFFSET 0x20410
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+#define RK3528_SMT_GPIO2_OFFSET 0x30420
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+#define RK3528_SMT_GPIO3_OFFSET 0x20430
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+#define RK3528_SMT_GPIO4_OFFSET 0x10440
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+
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+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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+ int pin_num,
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+ struct regmap **regmap,
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+ int *reg, u8 *bit)
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+{
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+ struct rockchip_pinctrl *info = bank->drvdata;
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+
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+ *regmap = info->regmap_base;
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+
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+ if (bank->bank_num == 0)
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+ *reg = RK3528_SMT_GPIO0_OFFSET;
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+ else if (bank->bank_num == 1)
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+ *reg = RK3528_SMT_GPIO1_OFFSET;
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+ else if (bank->bank_num == 2)
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+ *reg = RK3528_SMT_GPIO2_OFFSET;
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+ else if (bank->bank_num == 3)
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+ *reg = RK3528_SMT_GPIO3_OFFSET;
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+ else if (bank->bank_num == 4)
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+ *reg = RK3528_SMT_GPIO4_OFFSET;
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+ else
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+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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+
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+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
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+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
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+ *bit *= RK3528_SMT_BITS_PER_PIN;
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+
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+ return 0;
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+}
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+
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#define RK3568_PULL_PMU_OFFSET 0x20
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#define RK3568_PULL_GRF_OFFSET 0x80
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#define RK3568_PULL_BITS_PER_PIN 2
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@@ -2495,7 +2604,8 @@ static int rockchip_set_drive_perpin(str
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rmask_bits = RK3588_DRV_BITS_PER_PIN;
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ret = strength;
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goto config;
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- } else if (ctrl->type == RK3568) {
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+ } else if (ctrl->type == RK3528 ||
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+ ctrl->type == RK3568) {
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rmask_bits = RK3568_DRV_BITS_PER_PIN;
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ret = (1 << (strength + 1)) - 1;
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goto config;
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@@ -2639,6 +2749,7 @@ static int rockchip_get_pull(struct rock
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case RK3328:
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case RK3368:
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case RK3399:
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+ case RK3528:
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case RK3568:
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case RK3576:
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case RK3588:
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@@ -2699,6 +2810,7 @@ static int rockchip_set_pull(struct rock
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case RK3328:
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case RK3368:
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case RK3399:
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+ case RK3528:
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case RK3568:
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case RK3576:
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case RK3588:
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@@ -2964,6 +3076,7 @@ static bool rockchip_pinconf_pull_valid(
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case RK3328:
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case RK3368:
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case RK3399:
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+ case RK3528:
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case RK3568:
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case RK3576:
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case RK3588:
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@@ -4083,6 +4196,49 @@ static struct rockchip_pin_ctrl rk3399_p
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.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
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};
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+static struct rockchip_pin_bank rk3528_pin_banks[] = {
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+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ 0, 0, 0, 0),
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+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ 0x20020, 0x20028, 0x20030, 0x20038),
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+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ 0x30040, 0, 0, 0),
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+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ 0x20060, 0x20068, 0x20070, 0),
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+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ IOMUX_WIDTH_4BIT,
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+ 0x10080, 0x10088, 0x10090, 0x10098),
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+};
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+
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+static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
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+ .pin_banks = rk3528_pin_banks,
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+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
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+ .label = "RK3528-GPIO",
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+ .type = RK3528,
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+ .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
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+ .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
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+ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
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+};
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+
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static struct rockchip_pin_bank rk3568_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
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IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
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@@ -4207,6 +4363,8 @@ static const struct of_device_id rockchi
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.data = &rk3368_pin_ctrl },
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{ .compatible = "rockchip,rk3399-pinctrl",
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.data = &rk3399_pin_ctrl },
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+ { .compatible = "rockchip,rk3528-pinctrl",
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+ .data = &rk3528_pin_ctrl },
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{ .compatible = "rockchip,rk3568-pinctrl",
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.data = &rk3568_pin_ctrl },
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{ .compatible = "rockchip,rk3576-pinctrl",
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--- a/drivers/pinctrl/pinctrl-rockchip.h
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+++ b/drivers/pinctrl/pinctrl-rockchip.h
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@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
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RK3328,
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RK3368,
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RK3399,
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+ RK3528,
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RK3568,
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RK3576,
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RK3588,
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