Tianling ShenandNick Hainke
86e3c31bcc
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/23139 Signed-off-by: Nick Hainke <vincent@systemli.org>
26 lines
1.0 KiB
Diff
26 lines
1.0 KiB
Diff
From 831a8ac72264426ccd0ee5d2b0d74491ea7d2bfb Mon Sep 17 00:00:00 2001
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From: Alexander Shiyan <eagle.alexander923@gmail.com>
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Date: Tue, 8 Apr 2025 09:46:12 +0300
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Subject: [PATCH] clk: rockchip: rk3588: Add PLL rate for 1500 MHz
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At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
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that frequency to the PLL table.
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Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
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Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk
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RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
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RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
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RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
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+ RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
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RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
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RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
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RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
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