Daniel Golle
f0f6fa2e28
Swap pending with accepted patches, rebase remaining pending patches on top of new upstream. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
81 lines
3.3 KiB
Diff
81 lines
3.3 KiB
Diff
From b723f7484006aadbaa51e16b870f3c98390605b1 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 1 Apr 2026 13:43:12 +0100
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Subject: [PATCH 16/19] net: dsa: mxl862xx: support BR_HAIRPIN_MODE bridge flag
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Implement hairpin mode by including the port's own bridge port ID in
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its forwarding portmap. When hairpin is enabled, bridged frames whose
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destination resolves to the ingress port are allowed to egress there
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instead of being dropped.
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For LAG ports, the LAG's dedicated bridge port is added to the
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master's portmap, which naturally propagates to the LAG bridge port
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via the second loop in sync_bridge_members.
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The port_bridge_flags handler toggles the bit directly on the cached
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portmap and pushes the update via set_bridge_port, avoiding a full
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bridge member rebuild since only the calling port is affected.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/dsa/mxl862xx/mxl862xx.c | 12 ++++++++++--
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drivers/net/dsa/mxl862xx/mxl862xx.h | 5 +++++
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2 files changed, 15 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/mxl862xx/mxl862xx.c
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+++ b/drivers/net/dsa/mxl862xx/mxl862xx.c
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@@ -759,6 +759,10 @@ static int __mxl862xx_set_bridge_port(st
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}
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mxl862xx_fw_portmap_set_bit(br_port_cfg.bridge_port_map,
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mxl862xx_cpu_bridge_port_id(ds, port));
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+ if (p->hairpin)
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+ mxl862xx_fw_portmap_set_bit(br_port_cfg.bridge_port_map,
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+ mxl862xx_lag_bridge_port(priv,
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+ port));
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} else {
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mxl862xx_fw_portmap_set_bit(br_port_cfg.bridge_port_map,
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mxl862xx_cpu_bridge_port_id(ds, port));
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@@ -3895,7 +3899,7 @@ static int mxl862xx_port_pre_bridge_flag
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struct netlink_ext_ack *extack)
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{
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if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD |
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- BR_LEARNING))
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+ BR_LEARNING | BR_HAIRPIN_MODE))
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return -EINVAL;
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return 0;
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@@ -3937,7 +3941,11 @@ static int mxl862xx_port_bridge_flags(st
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if (flags.mask & BR_LEARNING)
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priv->ports[port].learning = !!(flags.val & BR_LEARNING);
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- if (block != old_block || (flags.mask & BR_LEARNING)) {
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+ if (flags.mask & BR_HAIRPIN_MODE)
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+ priv->ports[port].hairpin = !!(flags.val & BR_HAIRPIN_MODE);
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+
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+ if ((block != old_block) ||
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+ (flags.mask & (BR_LEARNING | BR_HAIRPIN_MODE))) {
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priv->ports[port].flood_block = block;
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ret = mxl862xx_set_bridge_port(ds, port);
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if (ret)
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--- a/drivers/net/dsa/mxl862xx/mxl862xx.h
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+++ b/drivers/net/dsa/mxl862xx/mxl862xx.h
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@@ -240,6 +240,10 @@ struct mxl862xx_port_stats {
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* @stats_lock: protects accumulator reads in .get_stats64 against
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* concurrent updates from the polling work
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* @tag_8021q_vid: currently assigned tag_8021q management VID
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+ * @hairpin: true when hairpin mode is active (BR_HAIRPIN_MODE);
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+ * the port's own bridge port is included in its
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+ * portmap so bridged frames can egress the ingress
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+ * port
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* @ingress_mirror: true when ingress mirroring is active on this port
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* @egress_mirror: true when egress mirroring is active on this port
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* @lag: non-NULL when port is member of a LAG group;
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@@ -269,6 +273,7 @@ struct mxl862xx_port {
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struct work_struct host_flood_work;
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u16 tag_8021q_vid;
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struct mxl862xx_evlan_block cpu_egress_evlan;
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+ bool hairpin;
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bool ingress_mirror;
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bool egress_mirror;
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struct dsa_lag *lag;
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