Robert MarkoandRobert Marko
ce81558d33
NVMEM OTP support was upstreamed, so backport those patches instead of our downstream ones. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
From a03ebe904b22e0c3f80498fe0dbfc66090552f67 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Thu, 25 Sep 2025 22:26:13 +0200
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Subject: [PATCH 122/124] arm64: dts: microchip: lan969x: add QSPI nodes
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Add the required DT nodes for both QSPI controllers.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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arch/arm64/boot/dts/microchip/lan9691.dtsi | 30 ++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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--- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
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+++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
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@@ -396,6 +396,36 @@
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clock-names = "cpu", "ddr", "sys";
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};
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+ qspi0: spi@e0804000 {
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+ compatible = "microchip,lan9691-qspi";
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+ reg = <0xe0804000 0x00000100>,
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+ <0x20000000 0x08000000>;
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+ reg-names = "qspi_base", "qspi_mmap";
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+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
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+ clock-names = "pclk", "gclk";
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+ assigned-clocks = <&clks GCK_ID_QSPI0>;
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+ assigned-clock-rates = <100000000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ qspi2: spi@e0834000 {
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+ compatible = "microchip,lan9691-qspi";
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+ reg = <0xe0834000 0x00000100>,
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+ <0x30000000 0x04000000>;
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+ reg-names = "qspi_base", "qspi_mmap";
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+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
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+ clock-names = "pclk", "gclk";
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+ assigned-clocks = <&clks GCK_ID_QSPI2>;
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+ assigned-clock-rates = <100000000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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reset: reset-controller@e201000c {
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compatible = "microchip,lan9691-switch-reset",
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"microchip,lan966x-switch-reset";
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