Chukun PanandChuanhong Guo
348f716408
- Update network port names based on the shell
- Fix boot log errors:
OF: /soc/pcie@11280000/pcie@0,0: Missing device_type
- Match vendor firmware Ethernet and wireless MAC addresses
LAN MAC 50:xx:xx:xx:xx:60
WAN MAC 50:xx:xx:xx:xx:61
2G MAC 50:xx:xx:xx:xx:63
5G MAC 50:xx:xx:xx:xx:65
Fixes: 7d79346581 ("mediatek: filogic: add support for Tenda BE12 Pro")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/22060
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
389 lines
7.1 KiB
Devicetree
389 lines
7.1 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Author: Developer X <dev@x-wrt.com>
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*/
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/dts-v1/;
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#include "mt7987a.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Tenda BE12 Pro";
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compatible = "tenda,be12-pro", "mediatek,mt7987a", "mediatek,mt7987";
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aliases {
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label-mac-device = &gmac0;
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led-boot = &led_status_green;
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led-failsafe = &led_status_red;
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led-running = &led_status_green;
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led-upgrade = &led_status_red;
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};
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chosen {
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bootargs-override = "console=ttyS0,115200n1 earlycon=uart8250,mmio32,0x11000000 pci=pcie_bus_perf";
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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debounce-interval = <10>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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debounce-interval = <10>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_status_green: status_green {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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};
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led_status_red: status_red {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&pio 7 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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mediatek,nmbm;
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mediatek,bmt-max-ratio = <1>;
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mediatek,bmt-max-reserved-blocks = <64>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x000000 0x0300000>;
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read-only;
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};
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partition@300000 {
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label = "u-boot-env";
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reg = <0x300000 0x0080000>;
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};
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partition@380000 {
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label = "Factory";
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reg = <0x380000 0x0400000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1e00>;
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};
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macaddr_factory_4: macaddr@4 {
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compatible = "mac-base";
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reg = <0x4 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@780000 {
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label = "kernel";
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reg = <0x780000 0x0600000>;
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};
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partition@d80000 {
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label = "ubi";
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reg = <0xd80000 0x5a00000>;
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};
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partition@6780000 {
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label = "CFG";
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reg = <0x6780000 0x400000>;
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read-only;
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};
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partition@6b80000 {
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label = "MISC2";
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reg = <0x6b80000 0x400000>;
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read-only;
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};
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};
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};
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};
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&gmac0 {
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phy-mode = "2500base-x";
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status = "okay";
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nvmem-cells = <&macaddr_factory_4 (-2)>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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&gmac1 {
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phy-mode = "internal";
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phy-handle = <&phy15>;
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status = "okay";
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nvmem-cells = <&macaddr_factory_4 (-2)>;
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nvmem-cell-names = "mac-address";
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};
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&gmac2 {
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phy-mode = "2500base-x";
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phy-handle = <&phy11>;
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status = "okay";
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nvmem-cells = <&macaddr_factory_4 (-1)>;
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nvmem-cell-names = "mac-address";
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};
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&mdio {
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phy11: phy@11 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <11>;
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reset-assert-us = <10000>;
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reset-deassert-us = <20000>;
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reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>;
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};
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phy15: phy@15 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <15>;
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};
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mfd@1 {
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compatible = "airoha,an8855-mfd";
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reg = <1>;
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efuse {
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compatible = "airoha,an8855-efuse";
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#nvmem-cell-cells = <0>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
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reg = <0xc 0x4>;
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};
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shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
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reg = <0x10 0x4>;
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};
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shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
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reg = <0x14 0x4>;
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};
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shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
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reg = <0x18 0x4>;
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};
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shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
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reg = <0x1c 0x4>;
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};
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shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
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reg = <0x20 0x4>;
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};
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shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
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reg = <0x24 0x4>;
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};
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shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
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reg = <0x28 0x4>;
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};
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shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
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reg = <0x2c 0x4>;
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};
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shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
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reg = <0x30 0x4>;
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};
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shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
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reg = <0x34 0x4>;
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};
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shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
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reg = <0x38 0x4>;
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};
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shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
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reg = <0x4c 0x4>;
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};
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shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
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reg = <0x50 0x4>;
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};
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shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
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reg = <0x54 0x4>;
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};
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shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
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reg = <0x58 0x4>;
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};
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};
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};
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ethernet-switch {
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compatible = "airoha,an8855-switch";
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reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
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airoha,ext-surge;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan5";
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phy-mode = "internal";
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phy-handle = <&internal_phy1>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&internal_phy2>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&internal_phy3>;
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};
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port@5 {
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reg = <5>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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mdio {
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compatible = "airoha,an8855-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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internal_phy1: phy@1 {
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reg = <1>;
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nvmem-cells = <&shift_sel_port0_tx_a>,
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<&shift_sel_port0_tx_b>,
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<&shift_sel_port0_tx_c>,
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<&shift_sel_port0_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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internal_phy2: phy@2 {
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reg = <2>;
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nvmem-cells = <&shift_sel_port1_tx_a>,
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<&shift_sel_port1_tx_b>,
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<&shift_sel_port1_tx_c>,
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<&shift_sel_port1_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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internal_phy3: phy@3 {
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reg = <3>;
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nvmem-cells = <&shift_sel_port2_tx_a>,
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<&shift_sel_port2_tx_b>,
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<&shift_sel_port2_tx_c>,
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<&shift_sel_port2_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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mt7992@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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#address-cells = <1>;
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#size-cells = <0>;
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ieee80211-freq-limit = <2400000 2500000>,
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<5170000 5835000>;
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band@0 {
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reg = <0>;
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nvmem-cells = <&macaddr_factory_4 1>;
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nvmem-cell-names = "mac-address";
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};
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band@1 {
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reg = <1>;
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nvmem-cells = <&macaddr_factory_4 3>;
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nvmem-cell-names = "mac-address";
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};
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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