Files
eternalwrt-mt798x/target/linux/bcm27xx/patches-6.18/0541-PCI-quirks-work-around-VL805-firmware-ASPM-meddling.patch
T
John AudiaandJonas Jelonek 276214fc06 kernel: bump 6.18 to 6.18.39
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.18.39

Removed upstreamed:
  backport-6.18/704-v7.2-netfilter-flowtable-fix-offloaded-ct-timeout-never-b.patch[1]

All other patches automatically rebased via update_kernel.sh

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.18.39&id=81a5971cbe18b474b49c651e32f2194b2fb171fe

Build system: x86/64
Build-tested: x86/64-glibc
Run-tested: x86/64-glibc

Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/24282
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-07-20 20:05:54 +02:00

44 lines
1.7 KiB
Diff

From 4f15a23089da8690bce75c0ed785a4158cb48d49 Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Tue, 15 Apr 2025 14:19:31 +0100
Subject: [PATCH] PCI: quirks: work around VL805 firmware ASPM meddling
Certain versions of the VL805 firmware manipulate the endpoint Link
Control register to toggle ASPM on/off based on workload, but these
versions also report 0 in the Device Capability Acceptable Latency field
leaving the RC with ASPM disabled.
As it turns out, this EP has a broken L0s implementation so a) override
L1 latency to a sensible value and b) mask L0s.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
---
drivers/pci/quirks.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6278,6 +6278,22 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
+
+/*
+ * VL805 firmware can report 0 in the L0s/L1 Acceptable Latency fields.
+ * This is shorter than its own exit latency so ASPM for the link partner
+ * never gets enabled (but firmware toggles EP L1/L0s enable internally).
+ * However, L0s is flaky so explicitly disable it.
+ */
+static void vl805_aspm_fixup(struct pci_dev *dev)
+{
+ dev->devcap &= ~PCI_EXP_DEVCAP_L1;
+ /* Set to own exit latency + 1 */
+ dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 5);
+ pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
+ pci_info(dev, "ASPM: VL805 fixup applied\n");
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, 0x3483, vl805_aspm_fixup);
#endif
#ifdef CONFIG_PCIE_DPC