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Daniel Golle
df0b899123
Update WPEWebKit to the 2.52 stable major release branch. Includes a pending patchset to get WASM BBQJIT working on RISCV64, upstream PR https://github.com/WebKit/WebKit/pull/65621 Alltogether this brings acceptable performance (even with LLVMPipe Mesa software renderer) on RISCV64. Link: https://wpewebkit.org/release/wpewebkit-2.52.0.html Link: https://wpewebkit.org/release/wpewebkit-2.52.1.html Link: https://wpewebkit.org/release/wpewebkit-2.52.2.html Link: https://wpewebkit.org/release/wpewebkit-2.52.3.html Signed-off-by: Daniel Golle <daniel@makrotopia.org>
66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From: Daniel Golle <daniel@makrotopia.org>
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Subject: [PATCH] JavaScriptCore: add RISCV64 support to GdbJIT
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GdbJIT emits a tiny in-memory ELF object for the debugger to pick up,
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and three places in the file hard-coded the supported architecture
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list to X86_64/ARM64 (with ARMv7/Thumb for the 32-bit case). Each of
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them refuses to compile on RISCV64.
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Add the missing CPU(RISCV64) branches:
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* ELF e_ident: ELFCLASS64 / ELFDATA2LSB, the same as X86_64 / ARM64.
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* ELF e_machine: EM_RISCV (243) from the RISC-V ELF psABI.
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* ELFSymbol::SerializedLayout: the 64-bit layout shared with the
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X86_64 / ARM64 branch, since RISCV64 has the same uintptr_t width
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and packed-symbol layout.
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* RegisterMapping (DWARF unwinding): RegisterFP = 8 (s0/x8) and
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RegisterLR = 1 (ra/x1), matching the RISC-V psABI's DWARF register
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numbering.
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This is a debug-only path; it has no effect on generated JIT code,
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it just makes GdbJIT.cpp compile on RISCV64.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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--- a/Source/JavaScriptCore/jit/GdbJIT.cpp
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+++ b/Source/JavaScriptCore/jit/GdbJIT.cpp
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@@ -873,7 +873,7 @@ private:
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0x7F, 'E', 'L', 'F', 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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-#elif CPU(X86_64) || CPU(ARM64)
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+#elif CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
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const uint8_t ident[16] = {
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0x7F, 'E', 'L', 'F', 2, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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@@ -895,6 +895,9 @@ private:
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#elif CPU(ARM64)
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// AARCH64
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header->machine = 0xB7;
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+#elif CPU(RISCV64)
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+ // EM_RISCV from the RISC-V ELF psABI specification.
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+ header->machine = 243;
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#else
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#error Unsupported target architecture.
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#endif
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@@ -996,7 +999,7 @@ public:
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uint8_t m_other;
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uint16_t m_section;
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} __attribute__((packed,aligned(1)));
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-#elif CPU(X86_64) || CPU(ARM64)
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+#elif CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
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struct SerializedLayout {
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SerializedLayout(uint32_t name, uintptr_t value, uintptr_t size, Binding binding, Type type, uint16_t section)
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: m_name(name)
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@@ -1166,6 +1169,11 @@ private:
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#elif CPU(ARM64)
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RegisterFP = 29,
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RegisterLR = 30,
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+#elif CPU(RISCV64)
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+ // RISC-V psABI: DWARF register numbers match x0..x31, so the frame
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+ // pointer s0/x8 is 8 and the return-address register ra/x1 is 1.
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+ RegisterFP = 8,
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+ RegisterLR = 1,
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#else
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RegisterFP = 7,
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RegisterLR = 14,
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