uboot: renew glinet gl-mt2500 support

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2024-10-16 18:43:22 +08:00
committed by hanwckf
parent d2772cc419
commit 58370a2264
6 changed files with 390 additions and 214 deletions

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@@ -1,177 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7981-rfb";
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
config {
bootcmd = "mtkboardboot";
blink_led = "blue:run";
system_led = "white:system";
gpio_power_clr = <12>;
environment {
lu = "mtkupgrade fip uboot-gl-mt2500.bin";
lf = "mtkupgrade fw openwrt-gl-mt2500.bin";
};
};
gpio-keys-polled {
compatible = "gpio-keys";
power-button {
label = "reset";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led@0 {
label = "white:system";
gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
};
led@1 {
label = "blue:run";
gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <1>;
phy-mode = "gmii";
phy-handle = <&phy0>;
mdio {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9461";
reg = <0x0>;
phy-mode = "gmii";
};
};
};
&pinctrl {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_1";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
/* pin15 as pwm0 */
one_pwm_pins: one-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1";
};
};
/* pin15 as pwm0 and pin14 as pwm1 */
two_pwm_pins: two-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0";
};
};
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
three_pwm_pins: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM0";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&two_pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <8>;
max-frequency = <52000000>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};

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@@ -0,0 +1,122 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7981-glinet_gl-mt2500";
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
config {
bootcmd = "mtkboardboot";
blink_led = "blue:run";
system_led = "white:system";
gpio_power_clr = <12>;
};
gpio-keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
label = "white:system";
gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
};
led-1 {
label = "blue:run";
gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&eth {
status = "okay";
mediatek,gmac-id = <1>;
phy-mode = "gmii";
phy-handle = <&phy0>;
mdio {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9461";
reg = <0x0>;
phy-mode = "gmii";
};
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <8>;
max-frequency = <52000000>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&pinctrl {
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM0";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "disabled";
};

View File

@@ -6,46 +6,70 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DEFAULT_DEVICE_TREE="gl-mt2500"
CONFIG_DEFAULT_DEVICE_TREE="mt7981-glinet-gl-mt2500"
CONFIG_TARGET_MT7981=y
CONFIG_MEDIATEK_BOOTMENU=y
CONFIG_MEDIATEK_BOOTMENU_DELAY=3
CONFIG_MEDIATEK_LOAD_FROM_RAM=y
# CONFIG_MTK_UPGRADE_IMAGE_VERIFY is not set
CONFIG_MT7981_BOOTMENU_EMMC=y
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
# CONFIG_AUTOBOOT_MENU_SHOW is not set
# CONFIG_AUTOBOOT_MENU_MTK_SHOW is not set
CONFIG_DEFAULT_FDT_FILE="gl-mt2500"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_MENU_SHOW=y
CONFIG_AUTOBOOT_MENU_MTK_SHOW=y
CONFIG_DEFAULT_FDT_FILE="mt7981-glinet-gl-mt2500"
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_POLLER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MT7981> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_LED_BLINK=y
CONFIG_CMD_SMC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_GL_BTN=y
# CONFIG_DOS_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_ARP_TIMEOUT=1000
CONFIG_NET_RETRY_COUNT=3
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_SYS_I2C_MTK=y
# CONFIG_INPUT is not set
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
@@ -70,36 +94,9 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_WEBUI_FAILSAFE=y
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_BLINK=y
# CMD_CONSOLE is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_BOOTEFI is not set
# CONFIG_CMD_FDT is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_NAND_EXT is not set
# CONFIG_CMD_SF is not set
# CONFIG_CMD_NFS is not set
# CONFIG_INPUT is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter \"gl\" to stop autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR="gl"
CONFIG_POLLER=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_ENV_IMPORT_FDT=y
CONFIG_CMD_GL_BTN=y
CONFIG_CMD_LED_BLINK=y
CONFIG_HUSH_PARSER=y
CONFIG_ARP_TIMEOUT=1000
CONFIG_NET_RETRY_COUNT=3
CONFIG_WEBUI_FAILSAFE_ON_AUTOBOOT_FAIL=y