8f5285bfba
* atf-20240117-bacca82a8: import new atf Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: remove Werror * atf-20240117-bacca82a8: call bromimage-x86_64 for aarch64 host * atf-20240117-bacca82a8: export ram boot uart option Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: apply openwrt patches Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: port board configs Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: switch to use atf-20240117-bacca82a8 Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: support new menuconfig Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: pass u-boot path by variable Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20231013-0ea67d76a: drop Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> --------- Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Co-authored-by: hanwckf <hanwckf@vip.qq.com>
52 lines
1.1 KiB
Plaintext
52 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
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*/
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#include <common/tbbr/tbbr_img_def.h>
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#include <dt-bindings/soc/stm32mp13-tzc400.h>
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#include <platform_def.h>
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#ifndef DDR_SIZE
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#error "DDR_SIZE is not defined"
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#endif
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#define DDR_NS_BASE STM32MP_DDR_BASE
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#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE
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#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE))
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#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE)
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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hw-config {
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load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
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max-size = <STM32MP_HW_CONFIG_MAX_SIZE>;
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id = <HW_CONFIG_ID>;
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};
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nt_fw {
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load-address = <0x0 STM32MP_BL33_BASE>;
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max-size = <STM32MP_BL33_MAX_SIZE>;
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id = <BL33_IMAGE_ID>;
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};
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tos_fw {
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load-address = <0x0 DDR_SEC_BASE>;
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max-size = <DDR_SEC_SIZE>;
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id = <BL32_IMAGE_ID>;
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};
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};
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st-mem-firewall {
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compatible = "st,mem-firewall";
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memory-ranges = <
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DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
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DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>;
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};
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};
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