8f5285bfba
* atf-20240117-bacca82a8: import new atf Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: remove Werror * atf-20240117-bacca82a8: call bromimage-x86_64 for aarch64 host * atf-20240117-bacca82a8: export ram boot uart option Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: apply openwrt patches Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20240117-bacca82a8: port board configs Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: switch to use atf-20240117-bacca82a8 Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: support new menuconfig Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * build.sh: pass u-boot path by variable Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> * atf-20231013-0ea67d76a: drop Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> --------- Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Co-authored-by: hanwckf <hanwckf@vip.qq.com>
113 lines
1.5 KiB
Plaintext
113 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
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*/
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&ddr {
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st,mem-name = DDR_MEM_NAME;
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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DDR_MRCTRL1
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DDR_DERATEEN
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DDR_DERATEINT
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DDR_PWRCTL
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DDR_PWRTMG
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DDR_HWLPCTL
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DDR_RFSHCTL0
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DDR_RFSHCTL3
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DDR_CRCPARCTL0
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DDR_ZQCTL0
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DDR_DFITMG0
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DDR_DFITMG1
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DDR_DFILPCFG0
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DDR_DFIUPD0
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DDR_DFIUPD1
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DDR_DFIUPD2
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DDR_DFIPHYMSTR
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DDR_ODTMAP
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DDR_DBG0
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DDR_DBG1
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DDR_DBGCMD
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DDR_POISONCFG
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DDR_PCCFG
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>;
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st,ctl-timing = <
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DDR_RFSHTMG
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DDR_DRAMTMG0
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DDR_DRAMTMG1
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DDR_DRAMTMG2
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DDR_DRAMTMG3
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DDR_DRAMTMG4
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DDR_DRAMTMG5
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DDR_DRAMTMG6
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DDR_DRAMTMG7
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DDR_DRAMTMG8
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DDR_DRAMTMG14
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DDR_ODTCFG
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>;
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st,ctl-map = <
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DDR_ADDRMAP1
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DDR_ADDRMAP2
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DDR_ADDRMAP3
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DDR_ADDRMAP4
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DDR_ADDRMAP5
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DDR_ADDRMAP6
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DDR_ADDRMAP9
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DDR_ADDRMAP10
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DDR_ADDRMAP11
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>;
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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DDR_PCFGR_1
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DDR_PCFGW_1
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DDR_PCFGQOS0_1
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DDR_PCFGQOS1_1
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DDR_PCFGWQOS0_1
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DDR_PCFGWQOS1_1
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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DDR_DX2GCR
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DDR_DX3GCR
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>;
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st,phy-timing = <
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DDR_PTR0
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DDR_PTR1
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DDR_PTR2
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DDR_DTPR0
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DDR_DTPR1
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DDR_DTPR2
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DDR_MR0
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DDR_MR1
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DDR_MR2
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DDR_MR3
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>;
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};
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