From cb8d930879726d51161e612d48b5c3dba7aa494a Mon Sep 17 00:00:00 2001 From: developer Date: Fri, 1 Jul 2022 17:25:10 +0800 Subject: [PATCH] [Description] Add configurations to enable WDMA Rx ring full drop for solving Panther AX7800/AX8400 5G(MT7915) WA CPU bound issue. If without this patch, system might run into WiFi Tx/Rx deadlock issue or WiFi Tx small packet low throughput issue. [Release-log] N/A Change-Id: I57cd4a8e3ae19bdcb34d7d042989b7c1327ea08e Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6193220 --- .../files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +++++-- .../files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c index a3059345b2..bef3da98f8 100644 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -2941,8 +2941,11 @@ static int mtk_hw_init(struct mtk_eth *eth, u32 type) /* PSE Free Queue Flow Control */ mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); - /* PSE should not drop port8 and port9 packets */ - mtk_w32(eth, 0x00000300, PSE_DROP_CFG); + /* PSE should not drop port8 and port9 packets from WDMA Tx */ + mtk_w32(eth, 0x00000300, PSE_NO_DROP_CFG); + + /* PSE should drop p8 and p9 packets when WDMA Rx ring full*/ + mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); /* PSE config input queue threshold */ mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 1b55ed447e..14e507709e 100644 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -124,7 +124,8 @@ /* PSE Free Queue Flow Control */ #define PSE_FQFC_CFG1 0x100 #define PSE_FQFC_CFG2 0x104 -#define PSE_DROP_CFG 0x108 +#define PSE_NO_DROP_CFG 0x108 +#define PSE_PPE0_DROP 0x110 /* PSE Input Queue Reservation Register*/ #define PSE_IQ_REV(x) (0x140 + ((x - 1) * 0x4))