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package_boot_uboot-rockchip / Update package_boot_uboot-rockchip (openwrt-25.12) (push) Successful in 8s
52 lines
1.5 KiB
Diff
52 lines
1.5 KiB
Diff
From 193563a005edc4e54426458ee6e097c8e4b38874 Mon Sep 17 00:00:00 2001
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From: Jon Lin <jon.lin@rock-chips.com>
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Date: Sun, 19 Oct 2025 15:47:15 +0000
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Subject: [PATCH] spi: rockchip_sfc: Support sclk_x2 version
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SFC after version 8 supports dtr mode, so the IO is the binary output of
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the controller clock.
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Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
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1 file changed, 12 insertions(+), 1 deletion(-)
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--- a/drivers/spi/rockchip_sfc.c
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+++ b/drivers/spi/rockchip_sfc.c
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@@ -108,6 +108,7 @@
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#define SFC_VER_3 0x3
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#define SFC_VER_4 0x4
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#define SFC_VER_5 0x5
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+#define SFC_VER_8 0x8
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/* Delay line controller resiter */
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#define SFC_DLL_CTRL0 0x3C
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@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s
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return 0;
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}
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+#if CONFIG_IS_ENABLED(CLK)
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+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
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+{
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+ if (sfc->version >= SFC_VER_8)
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+ return clk_set_rate(&sfc->clk, speed * 2);
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+ else
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+ return clk_set_rate(&sfc->clk, speed);
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+}
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+#endif
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+
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static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
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{
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struct rockchip_sfc *sfc = dev_get_plat(bus);
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@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct
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return 0;
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#if CONFIG_IS_ENABLED(CLK)
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- int ret = clk_set_rate(&sfc->clk, speed);
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+ int ret = rockchip_sfc_clk_set_rate(sfc, speed);
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if (ret < 0) {
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dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
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