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32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From f820034864dd463cdcd2bebe7940f2eca0eb4223 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Wed, 23 Jul 2025 10:06:43 +0200
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Subject: spi: spi-qpic-snand: don't hardcode ECC steps
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NAND devices with different page sizes requires different number
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of ECC steps, yet the qcom_spi_ecc_init_ctx_pipelined() function
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sets 4 steps in 'ecc_cfg' unconditionally.
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The correct number of the steps is calculated earlier in the
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function already, so use that instead of the hardcoded value.
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Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Link: https://patch.msgid.link/20250723-qpic-snand-fix-steps-v1-1-d800695dde4c@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/spi-qpic-snand.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -308,7 +308,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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ecc_cfg->bch_enabled = true;
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ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
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- ecc_cfg->steps = 4;
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+ ecc_cfg->steps = cwperpage;
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ecc_cfg->cw_data = 516;
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ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
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bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
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