29 lines
1.2 KiB
Diff
29 lines
1.2 KiB
Diff
From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Tue, 4 Feb 2025 14:40:07 +0200
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Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
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Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
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provider support"), the HDMI PHY PLL can be used as an alternative and
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more accurate pixel clock source for VOP2 to improve display modes
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handling on RK3588 SoC.
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Add the missing #clock-cells property to allow using the clock provider
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functionality of HDMI0 PHY.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Tested-by: FUKAUMI Naoki <naoki@radxa.com>
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Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -2813,6 +2813,7 @@
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reg = <0x0 0xfed60000 0x0 0x2000>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
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clock-names = "ref", "apb";
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+ #clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
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<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
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