53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Wed, 11 Dec 2024 01:06:15 +0200
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Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
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In preparation to enable the second HDMI output port found on RK3588
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SoC, add the related PHY node. This requires a GRF, hence add the
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dependent node as well.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
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Tested-by: Alexandre ARNOUD <aarnoud@me.com>
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Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@@ -67,6 +67,11 @@
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};
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};
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+ hdptxphy1_grf: syscon@fd5e4000 {
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+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
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+ reg = <0x0 0xfd5e4000 0x0 0x100>;
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+ };
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+
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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@@ -395,6 +400,22 @@
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};
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};
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+ hdptxphy1: phy@fed70000 {
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+ compatible = "rockchip,rk3588-hdptx-phy";
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+ reg = <0x0 0xfed70000 0x0 0x2000>;
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
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+ clock-names = "ref", "apb";
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+ #phy-cells = <0>;
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+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
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+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
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+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
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+ <&cru SRST_HDPTX1_LCPLL>;
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+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
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+ "lcpll";
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+ rockchip,grf = <&hdptxphy1_grf>;
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+ status = "disabled";
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+ };
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+
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usbdp_phy1: phy@fed90000 {
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compatible = "rockchip,rk3588-usbdp-phy";
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reg = <0x0 0xfed90000 0x0 0x10000>;
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