150 lines
3.9 KiB
Diff
150 lines
3.9 KiB
Diff
From 376cb9696298df2028afb620a9dc6c4b10a18605 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Thu, 8 May 2025 19:48:53 +0200
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Subject: arm64: dts: rockchip: add Rock 5B+
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Add ROCK 5B+, which is an improved version of the ROCK 5B with the
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following changes:
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* Memory LPDDR4X -> LPDDR5
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* HDMI input connector size
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* eMMC socket -> onboard
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* M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT
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* M.2 M-Key 1x4 lanes is replaced by 2x2 lanes
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* Added M.2 B-Key for USB connected WWAN modules (untested)
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* Add second camera port (not yet supported in upstream Linux)
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* Add dedicated USB-C port for device power (no impact in DT;
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the existing port has not been changed and the new port is
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handled by CH224D standalone chip)
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
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@@ -0,0 +1,113 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+
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+#include "rk3588-rock-5b.dtsi"
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+
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+/ {
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+ model = "Radxa ROCK 5B+";
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+ compatible = "radxa,rock-5b-plus", "rockchip,rk3588";
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+
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+ rfkill-wwan {
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+ compatible = "rfkill-gpio";
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+ label = "rfkill-m2-wwan";
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+ radio-type = "wwan";
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+ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ vcc3v3_4g: regulator-vcc3v3-4g {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
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+ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */
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+ regulator-name = "vcc3v3_4g";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <50000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wwan_power_en>;
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+ regulator-name = "vcc3v3_wwan_pwr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc3v3_4g>;
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+ };
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+};
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+
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+&gpio0 {
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+ wwan-disable2-n-hog {
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+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
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+ output-low;
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+ line-name = "M.2 B-key W_DISABLE2#";
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+ gpio-hog;
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+ };
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+};
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+
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+&gpio2 {
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+ wwan-reset-n-hog {
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+ gpios = <RK_PB3 GPIO_ACTIVE_LOW>;
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+ output-low;
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+ line-name = "M.2 B-key RESET#";
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+ gpio-hog;
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+ };
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+
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+ wwan-wake-n-hog {
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+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
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+ input;
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+ line-name = "M.2 B-key WoWWAN#";
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+ gpio-hog;
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+ };
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+};
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+
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+&pcie30phy {
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+ data-lanes = <1 1 2 2>;
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+};
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+
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+&pcie3x2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie3x2_rst>;
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+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie30>;
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+ status = "okay";
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+};
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+
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+&pcie3x4 {
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+ num-lanes = <2>;
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+};
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+
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+&pinctrl {
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+ wwan {
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+ wwan_power_en: wwan-pwr-en {
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+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pcie3 {
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+ pcie3x2_rst: pcie3x2-rst {
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+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ usb {
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+ vcc5v0_host_en: vcc5v0-host-en {
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+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+};
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+
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+&vcc5v0_host {
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+ enable-active-high;
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+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_host_en>;
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+};
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