28 lines
1.2 KiB
Diff
28 lines
1.2 KiB
Diff
From d934a93bbcccd551c142206b8129903d18126261 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko@sntech.de>
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Date: Mon, 10 Feb 2025 23:45:05 +0100
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Subject: [PATCH] clk: rockchip: rk3576: define clk_otp_phy_g
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The phy clock of the OTP block is also present, but was not defined
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so far. Though its clk-id already existed, so just define its location.
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Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20250210224510.1194963-2-heiko@sntech.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3576.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/clk/rockchip/clk-rk3576.c
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+++ b/drivers/clk/rockchip/clk-rk3576.c
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@@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576
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RK3576_CLKGATE_CON(5), 14, GFLAGS),
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GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
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RK3576_CLKGATE_CON(5), 15, GFLAGS),
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+ GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
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+ RK3576_CLKGATE_CON(6), 0, GFLAGS),
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COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,
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RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK3576_CLKGATE_CON(6), 3, GFLAGS),
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