91 lines
3.2 KiB
Diff
91 lines
3.2 KiB
Diff
From 9199ec29f0977efee223791c9ee3eb402d23f8ba Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Date: Fri, 2 May 2025 13:03:10 +0200
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Subject: [PATCH] clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
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The Rockchip RK3576 gates the SAI MCLKOUT clocks behind some IOC GRF
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writes.
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Add these clock branches, and add the IOC GRF to the auxiliary GRF
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hashtable.
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Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-4-376cef19dd7c@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3576.c | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/drivers/clk/rockchip/clk-rk3576.c
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+++ b/drivers/clk/rockchip/clk-rk3576.c
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@@ -15,6 +15,7 @@
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#define RK3576_GRF_SOC_STATUS0 0x600
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#define RK3576_PMU0_GRF_OSC_CON6 0x18
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+#define RK3576_VCCIO_IOC_MISC_CON0 0x6400
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enum rk3576_plls {
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bpll, lpll, vpll, aupll, cpll, gpll, ppll,
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@@ -1481,6 +1482,14 @@ static struct rockchip_clk_branch rk3576
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RK3576_CLKGATE_CON(10), 0, GFLAGS),
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GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0,
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RK3576_CLKGATE_CON(10), 1, GFLAGS),
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+ GATE_GRF(CLK_SAI0_MCLKOUT_TO_IO, "mclk_sai0_to_io", "clk_sai0_mclkout",
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+ 0, RK3576_VCCIO_IOC_MISC_CON0, 0, GFLAGS, grf_type_ioc),
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+ GATE_GRF(CLK_SAI1_MCLKOUT_TO_IO, "mclk_sai1_to_io", "clk_sai1_mclkout",
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+ 0, RK3576_VCCIO_IOC_MISC_CON0, 1, GFLAGS, grf_type_ioc),
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+ GATE_GRF(CLK_SAI2_MCLKOUT_TO_IO, "mclk_sai2_to_io", "clk_sai2_mclkout",
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+ 0, RK3576_VCCIO_IOC_MISC_CON0, 2, GFLAGS, grf_type_ioc),
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+ GATE_GRF(CLK_SAI3_MCLKOUT_TO_IO, "mclk_sai3_to_io", "clk_sai3_mclkout",
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+ 0, RK3576_VCCIO_IOC_MISC_CON0, 3, GFLAGS, grf_type_ioc),
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/* sdgmac */
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COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0,
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@@ -1727,7 +1736,9 @@ static void __init rk3576_clk_init(struc
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struct rockchip_clk_provider *ctx;
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unsigned long clk_nr_clks;
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void __iomem *reg_base;
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+ struct rockchip_aux_grf *ioc_grf_e;
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struct rockchip_aux_grf *pmu0_grf_e;
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+ struct regmap *ioc_grf;
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struct regmap *pmu0_grf;
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clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,
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@@ -1739,6 +1750,12 @@ static void __init rk3576_clk_init(struc
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return;
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}
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+ ioc_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-ioc-grf");
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+ if (IS_ERR(ioc_grf)) {
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+ pr_err("%s: could not get IOC GRF syscon\n", __func__);
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+ return;
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+ }
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+
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: could not map cru region\n", __func__);
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@@ -1759,6 +1776,14 @@ static void __init rk3576_clk_init(struc
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pmu0_grf_e->type = grf_type_pmu0;
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hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0);
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+ ioc_grf_e = kzalloc(sizeof(*ioc_grf_e), GFP_KERNEL);
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+ if (!ioc_grf_e)
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+ goto err_free_pmu0;
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+
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+ ioc_grf_e->grf = ioc_grf;
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+ ioc_grf_e->type = grf_type_ioc;
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+ hash_add(ctx->aux_grf_table, &ioc_grf_e->node, grf_type_ioc);
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+
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rockchip_clk_register_plls(ctx, rk3576_pll_clks,
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ARRAY_SIZE(rk3576_pll_clks),
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RK3576_GRF_SOC_STATUS0);
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@@ -1783,6 +1808,8 @@ static void __init rk3576_clk_init(struc
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return;
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+err_free_pmu0:
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+ kfree(pmu0_grf_e);
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err_unmap:
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iounmap(reg_base);
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return;
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