43 lines
1.9 KiB
Diff
43 lines
1.9 KiB
Diff
From a2a18e5da64f8da306fa97c397b4c739ea776f37 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Tue, 18 Nov 2025 17:52:05 +0800
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Subject: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
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When PCIe link enters L1 PM substates, the PHY will turn off its
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PLL for power-saving. However, it turns off the PLL too fast which
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leads the PHY to be broken. According to the PHY document, we need
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to delay PLL turnoff time.
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Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -21,6 +21,9 @@
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#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
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/* RK3528 COMBO PHY REG */
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+#define RK3528_PHYREG5 0x14
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+#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
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+#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
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#define RK3528_PHYREG6 0x18
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#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
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#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
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@@ -504,6 +507,10 @@ static int rk3528_combphy_cfg(struct roc
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case REF_CLOCK_100MHz:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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if (priv->type == PHY_TYPE_PCIE) {
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+ /* Gate_tx_pck_sel length select for L1ss support */
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+ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
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+ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
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+
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/* PLL KVCO tuning fine */
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val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
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rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
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