zhao
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target_linux_rockchip / Update target_linux_rockchip (openwrt-25.12) (push) Successful in 8s
196 lines
6.6 KiB
Diff
196 lines
6.6 KiB
Diff
From fda1e0af7c28f96d4f33e57cf51565b0e9c14e63 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 31 Oct 2025 16:58:23 +0100
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: Add command queue support for rockchip
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SOCs
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This adds CQE support for the Rockchip RK3588 and RK3576 platform. To
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be functional, the eMMC device-tree node must have a 'supports-cqe;'
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flag property.
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As the RK3576 device-tree has been upstreamed with the 'supports-cqe;'
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property set by default, the kernel already tried to use CQE, which
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results in system hang during suspend. This fixes the issue.
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Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Acked-by: Adrian Hunter <adrian.hunter@intel.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-of-dwcmshc.c | 93 ++++++++++++++++++++++++++++-
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1 file changed, 90 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -24,6 +24,7 @@
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#include "sdhci-pltfm.h"
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#include "cqhci.h"
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+#include "sdhci-cqhci.h"
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#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
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@@ -82,6 +83,8 @@
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#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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#define DECMSHC_EMMC_DLL_CMDOUT 0x810
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+#define DECMSHC_EMMC_MISC_CON 0x81C
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+#define MISC_INTCLK_EN BIT(1)
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#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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#define DWCMSHC_EMMC_DLL_START BIT(0)
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#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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@@ -234,6 +237,7 @@ struct dwcmshc_priv {
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struct dwcmshc_pltfm_data {
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const struct sdhci_pltfm_data pdata;
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+ const struct cqhci_host_ops *cqhci_host_ops;
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int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
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void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
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};
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@@ -616,6 +620,68 @@ static void dwcmshc_cqhci_dumpregs(struc
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sdhci_dumpregs(mmc_priv(mmc));
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}
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+static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
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+{
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+ struct sdhci_host *host = mmc_priv(mmc);
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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+ u32 reg;
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+
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+ reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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+ reg |= CQHCI_ENABLE;
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+ sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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+}
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+
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+static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
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+{
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+ struct sdhci_host *host = mmc_priv(mmc);
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+ u32 reg;
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+
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+ reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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+ while (reg & SDHCI_DATA_AVAILABLE) {
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+ sdhci_readl(host, SDHCI_BUFFER);
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+ reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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+ }
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+
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+ sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
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+
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+ sdhci_cqe_enable(mmc);
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+}
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+
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+static void rk35xx_sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
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+{
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+ struct sdhci_host *host = mmc_priv(mmc);
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+ unsigned long flags;
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+ u32 ctrl;
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+
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+ /*
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+ * During CQE command transfers, command complete bit gets latched.
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+ * So s/w should clear command complete interrupt status when CQE is
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+ * either halted or disabled. Otherwise unexpected SDCHI legacy
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+ * interrupt gets triggered when CQE is halted/disabled.
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+ */
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+ spin_lock_irqsave(&host->lock, flags);
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+ ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
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+ ctrl |= SDHCI_INT_RESPONSE;
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+ sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
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+ sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
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+ spin_unlock_irqrestore(&host->lock, flags);
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+
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+ sdhci_cqe_disable(mmc, recovery);
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+}
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+
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+static void rk35xx_sdhci_cqe_post_disable(struct mmc_host *mmc)
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+{
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+ struct sdhci_host *host = mmc_priv(mmc);
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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+ u32 ctrl;
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+
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+ ctrl = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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+ ctrl &= ~CQHCI_ENABLE;
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+ sdhci_writel(host, ctrl, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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+}
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+
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static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@@ -741,6 +807,10 @@ static void rk35xx_sdhci_reset(struct sd
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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struct rk35xx_priv *priv = dwc_priv->priv;
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+ u32 extra = sdhci_readl(host, DECMSHC_EMMC_MISC_CON);
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+
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+ if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
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+ cqhci_deactivate(host->mmc);
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if (mask & SDHCI_RESET_ALL && priv->reset) {
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reset_control_assert(priv->reset);
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@@ -749,6 +819,9 @@ static void rk35xx_sdhci_reset(struct sd
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}
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sdhci_reset(host, mask);
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+
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+ /* Enable INTERNAL CLOCK */
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+ sdhci_writel(host, MISC_INTCLK_EN | extra, DECMSHC_EMMC_MISC_CON);
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}
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static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host,
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@@ -1242,6 +1315,15 @@ static const struct dwcmshc_pltfm_data s
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};
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#endif
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+static const struct cqhci_host_ops rk35xx_cqhci_ops = {
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+ .pre_enable = rk35xx_sdhci_cqe_pre_enable,
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+ .enable = rk35xx_sdhci_cqe_enable,
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+ .disable = rk35xx_sdhci_cqe_disable,
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+ .post_disable = rk35xx_sdhci_cqe_post_disable,
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+ .dumpregs = dwcmshc_cqhci_dumpregs,
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+ .set_tran_desc = dwcmshc_set_tran_desc,
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+};
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+
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static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
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.pdata = {
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.ops = &sdhci_dwcmshc_rk35xx_ops,
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@@ -1250,6 +1332,7 @@ static const struct dwcmshc_pltfm_data s
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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},
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+ .cqhci_host_ops = &rk35xx_cqhci_ops,
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.init = dwcmshc_rk35xx_init,
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.postinit = dwcmshc_rk35xx_postinit,
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};
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@@ -1299,7 +1382,8 @@ static const struct cqhci_host_ops dwcms
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.set_tran_desc = dwcmshc_set_tran_desc,
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};
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-static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)
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+static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev,
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+ const struct dwcmshc_pltfm_data *pltfm_data)
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{
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struct cqhci_host *cq_host;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@@ -1329,7 +1413,10 @@ static void dwcmshc_cqhci_init(struct sd
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}
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cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;
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- cq_host->ops = &dwcmshc_cqhci_ops;
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+ if (pltfm_data->cqhci_host_ops)
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+ cq_host->ops = pltfm_data->cqhci_host_ops;
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+ else
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+ cq_host->ops = &dwcmshc_cqhci_ops;
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/* Enable using of 128-bit task descriptors */
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dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
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@@ -1498,7 +1585,7 @@ static int dwcmshc_probe(struct platform
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priv->vendor_specific_area2 =
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sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
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- dwcmshc_cqhci_init(host, pdev);
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+ dwcmshc_cqhci_init(host, pdev, pltfm_data);
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}
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if (pltfm_data->postinit)
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