167 lines
5.8 KiB
Diff
167 lines
5.8 KiB
Diff
From 1725f0eb37d621ce48303ccc14748fb66d618c9e Mon Sep 17 00:00:00 2001
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From: David Wu <david.wu@rock-chips.com>
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Date: Wed, 19 Mar 2025 21:44:06 +0000
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Subject: [PATCH] net: stmmac: dwmac-rk: Add GMAC support for RK3528
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Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
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Ethernet QoS IP.
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Add initial support for the RK3528 GMAC variant.
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Signed-off-by: David Wu <david.wu@rock-chips.com>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Link: https://patch.msgid.link/20250319214415.3086027-3-jonas@kwiboo.se
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 132 ++++++++++++++++++
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1 file changed, 132 insertions(+)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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@@ -1014,6 +1014,137 @@ static const struct rk_gmac_ops rk3399_o
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.set_rmii_speed = rk3399_set_rmii_speed,
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};
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+#define RK3528_VO_GRF_GMAC_CON 0x0018
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+#define RK3528_VO_GRF_MACPHY_CON0 0x001c
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+#define RK3528_VO_GRF_MACPHY_CON1 0x0020
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+#define RK3528_VPU_GRF_GMAC_CON5 0x0018
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+#define RK3528_VPU_GRF_GMAC_CON6 0x001c
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+
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+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
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+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
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+
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+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
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+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
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+
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+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
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+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
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+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
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+
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+#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
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+#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
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+
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+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
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+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
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+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
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+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
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+
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+#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
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+#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
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+#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
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+
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+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
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+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
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+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
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+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
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+
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+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
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+ int tx_delay, int rx_delay)
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+{
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ DELAY_ENABLE(RK3528, tx_delay, rx_delay));
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
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+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
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+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
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+}
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+
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+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
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+{
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+ if (bsp_priv->id == 1)
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
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+ else
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+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
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+ RK3528_GMAC0_PHY_INTF_SEL_RMII |
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+ RK3528_GMAC0_CLK_RMII_DIV2);
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+}
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+
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+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+
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+ if (speed == 10)
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_CLK_RGMII_DIV50);
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+ else if (speed == 100)
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_CLK_RGMII_DIV5);
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+ else if (speed == 1000)
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_CLK_RGMII_DIV1);
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+ else
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+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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+}
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+
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+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+ unsigned int reg, val;
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+
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+ if (speed == 10)
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+ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
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+ RK3528_GMAC0_CLK_RMII_DIV20;
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+ else if (speed == 100)
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+ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
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+ RK3528_GMAC0_CLK_RMII_DIV2;
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+ else {
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+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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+ return;
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+ }
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+
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+ reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
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+ RK3528_VO_GRF_GMAC_CON;
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+
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+ regmap_write(bsp_priv->grf, reg, val);
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+}
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+
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+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
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+ bool input, bool enable)
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+{
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+ unsigned int val;
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+
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+ if (bsp_priv->id == 1) {
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+ val = input ? RK3528_GMAC1_CLK_SELECT_IO :
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+ RK3528_GMAC1_CLK_SELECT_CRU;
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+ val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
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+ RK3528_GMAC1_CLK_RMII_GATE;
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
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+ } else {
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+ val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
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+ RK3528_GMAC0_CLK_RMII_GATE;
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+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
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+ }
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+}
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+
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+static const struct rk_gmac_ops rk3528_ops = {
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+ .set_to_rgmii = rk3528_set_to_rgmii,
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+ .set_to_rmii = rk3528_set_to_rmii,
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+ .set_rgmii_speed = rk3528_set_rgmii_speed,
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+ .set_rmii_speed = rk3528_set_rmii_speed,
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+ .set_clock_selection = rk3528_set_clock_selection,
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+ .regs_valid = true,
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+ .regs = {
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+ 0xffbd0000, /* gmac0 */
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+ 0xffbe0000, /* gmac1 */
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+ 0x0, /* sentinel */
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+ },
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+};
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+
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#define RK3568_GRF_GMAC0_CON0 0x0380
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#define RK3568_GRF_GMAC0_CON1 0x0384
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#define RK3568_GRF_GMAC1_CON0 0x0388
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@@ -2080,6 +2211,7 @@ static const struct of_device_id rk_gmac
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{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
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{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
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{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
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+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
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{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
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{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
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{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
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