127 lines
4.5 KiB
Diff
127 lines
4.5 KiB
Diff
From 0bed91f2b183bc38c216299ce035b44210148785 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 19 Mar 2025 21:44:07 +0000
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Subject: [PATCH] net: stmmac: dwmac-rk: Move integrated_phy_powerup/down
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functions
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Rockchip RK3528 (and RV1106) has a different integrated PHY compared to
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the integrated PHY on RK3228/RK3328. Current powerup/down operation is
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not compatible with the integrated PHY found in these SoCs.
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Move the rk_gmac_integrated_phy_powerup/down functions to top of the
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file to prepare for them to be called directly by a GMAC variant
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specific powerup/down operation.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/20250319214415.3086027-4-jonas@kwiboo.se
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 88 +++++++++----------
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1 file changed, 44 insertions(+), 44 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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@@ -92,6 +92,50 @@ struct rk_priv_data {
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(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
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((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
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+#define RK_GRF_MACPHY_CON0 0xb00
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+#define RK_GRF_MACPHY_CON1 0xb04
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+#define RK_GRF_MACPHY_CON2 0xb08
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+#define RK_GRF_MACPHY_CON3 0xb0c
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+
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+#define RK_MACPHY_ENABLE GRF_BIT(0)
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+#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
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+#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
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+#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
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+#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
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+#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
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+
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+static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
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+{
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+ if (priv->ops->integrated_phy_powerup)
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+ priv->ops->integrated_phy_powerup(priv);
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+
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
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+
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
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+
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+ if (priv->phy_reset) {
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+ /* PHY needs to be disabled before trying to reset it */
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
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+ if (priv->phy_reset)
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+ reset_control_assert(priv->phy_reset);
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+ usleep_range(10, 20);
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+ if (priv->phy_reset)
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+ reset_control_deassert(priv->phy_reset);
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+ usleep_range(10, 20);
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
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+ msleep(30);
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+ }
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+}
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+
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+static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
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+{
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+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
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+ if (priv->phy_reset)
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+ reset_control_assert(priv->phy_reset);
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+}
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+
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#define PX30_GRF_GMAC_CON1 0x0904
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/* PX30_GRF_GMAC_CON1 */
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@@ -1730,50 +1774,6 @@ static const struct rk_gmac_ops rv1126_o
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.set_rmii_speed = rv1126_set_rmii_speed,
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};
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-#define RK_GRF_MACPHY_CON0 0xb00
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-#define RK_GRF_MACPHY_CON1 0xb04
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-#define RK_GRF_MACPHY_CON2 0xb08
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-#define RK_GRF_MACPHY_CON3 0xb0c
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-
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-#define RK_MACPHY_ENABLE GRF_BIT(0)
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-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
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-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
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-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
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-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
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-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
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-
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-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
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-{
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- if (priv->ops->integrated_phy_powerup)
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- priv->ops->integrated_phy_powerup(priv);
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-
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
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-
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
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-
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- if (priv->phy_reset) {
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- /* PHY needs to be disabled before trying to reset it */
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
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- if (priv->phy_reset)
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- reset_control_assert(priv->phy_reset);
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- usleep_range(10, 20);
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- if (priv->phy_reset)
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- reset_control_deassert(priv->phy_reset);
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- usleep_range(10, 20);
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
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- msleep(30);
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- }
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-}
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-
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-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
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-{
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- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
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- if (priv->phy_reset)
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- reset_control_assert(priv->phy_reset);
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-}
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-
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static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
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{
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struct rk_priv_data *bsp_priv = plat->bsp_priv;
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