49 lines
1.9 KiB
Diff
49 lines
1.9 KiB
Diff
From c75e5e010fef2a62e6f2fe00ee8584e7b3ec82a6 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Wed, 5 Feb 2025 14:15:56 +0800
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Subject: [PATCH] scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC
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Add ufshc node to rk3576.dtsi, so the board using UFS could enable it.
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Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Link: https://lore.kernel.org/r/1738736156-119203-8-git-send-email-shawn.lin@rock-chips.com
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Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 24 ++++++++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1221,6 +1221,30 @@
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};
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};
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+ ufshc: ufshc@2a2d0000 {
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+ compatible = "rockchip,rk3576-ufshc";
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+ reg = <0x0 0x2a2d0000 0x0 0x10000>,
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+ <0x0 0x2b040000 0x0 0x10000>,
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+ <0x0 0x2601f000 0x0 0x1000>,
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+ <0x0 0x2603c000 0x0 0x1000>,
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+ <0x0 0x2a2e0000 0x0 0x10000>;
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+ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
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+ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
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+ <&cru CLK_REF_UFS_CLKOUT>;
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+ clock-names = "core", "pclk", "pclk_mphy", "ref_out";
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+ assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
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+ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
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+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_USB>;
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+ pinctrl-0 = <&ufs_refclk>;
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+ pinctrl-names = "default";
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+ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
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+ <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
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+ reset-names = "biu", "sys", "ufs", "grf";
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+ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
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+ status = "disabled";
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+ };
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+
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sdmmc: mmc@2a310000 {
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compatible = "rockchip,rk3576-dw-mshc";
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reg = <0x0 0x2a310000 0x0 0x4000>;
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