61 lines
2.0 KiB
Diff
61 lines
2.0 KiB
Diff
From 24d8127d801560c8fa811d554e8ab5db7e51511c Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Date: Thu, 24 Apr 2025 20:52:23 +0200
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Subject: [PATCH] arm64: dts: rockchip: add SATA nodes to RK3576
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The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind
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combphy0, which muxes between pcie0 and sata0.
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The second, sata1, is behind combphy1, which muxes between pcie1, sata1
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and usb_drd1_dwc3.
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I've only been able to test sata0 on my board, but it appears to work
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just fine.
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Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Link: https://lore.kernel.org/r/20250424-rk3576-sata-v1-2-23ee89c939fe@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 30 ++++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1442,6 +1442,36 @@
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};
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};
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+ sata0: sata@2a240000 {
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+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
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+ reg = <0x0 0x2a240000 0x0 0x1000>;
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+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
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+ <&cru CLK_RXOOB0>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_SUBPHP>;
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+ phys = <&combphy0_ps PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ dma-coherent;
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+ status = "disabled";
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+ };
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+
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+ sata1: sata@2a250000 {
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+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
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+ reg = <0x0 0x2a250000 0x0 0x1000>;
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+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
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+ <&cru CLK_RXOOB1>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_SUBPHP>;
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+ phys = <&combphy1_psu PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ dma-coherent;
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+ status = "disabled";
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+ };
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+
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ufshc: ufshc@2a2d0000 {
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compatible = "rockchip,rk3576-ufshc";
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reg = <0x0 0x2a2d0000 0x0 0x10000>,
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