92 lines
2.5 KiB
Diff
92 lines
2.5 KiB
Diff
From a4053badacf3699023527392c947314b074f5e0e Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Date: Tue, 10 Jun 2025 14:32:43 +0200
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Subject: [PATCH] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes
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Thanks to Heiko's work getting OTP working on the RK3576, we can specify
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the thermal sensor trim values which are stored there now, and with my
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driver addition to rockchip_thermal, we can make use of these.
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Add them to the devicetree for the SoC.
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Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++
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1 file changed, 57 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1937,6 +1937,30 @@
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log_leakage: log-leakage@22 {
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reg = <0x22 0x1>;
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};
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+ bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
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+ reg = <0x24 0x2>;
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+ bits = <0 10>;
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+ };
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+ litcore_tsadc_trim: litcore-tsadc-trim@26 {
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+ reg = <0x26 0x2>;
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+ bits = <0 10>;
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+ };
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+ ddr_tsadc_trim: ddr-tsadc-trim@28 {
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+ reg = <0x28 0x2>;
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+ bits = <0 10>;
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+ };
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+ npu_tsadc_trim: npu-tsadc-trim@2a {
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+ reg = <0x2a 0x2>;
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+ bits = <0 10>;
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+ };
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+ gpu_tsadc_trim: gpu-tsadc-trim@2c {
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+ reg = <0x2c 0x2>;
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+ bits = <0 10>;
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+ };
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+ soc_tsadc_trim: soc-tsadc-trim@64 {
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+ reg = <0x64 0x2>;
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+ bits = <0 10>;
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+ };
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};
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sai0: sai@2a600000 {
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@@ -2461,6 +2485,39 @@
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rockchip,hw-tshut-temp = <120000>;
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rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
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rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ sensor@0 {
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+ reg = <0>;
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+ nvmem-cells = <&soc_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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+ sensor@1 {
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+ reg = <1>;
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+ nvmem-cells = <&bigcore_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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+ sensor@2 {
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+ reg = <2>;
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+ nvmem-cells = <&litcore_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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+ sensor@3 {
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+ reg = <3>;
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+ nvmem-cells = <&ddr_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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+ sensor@4 {
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+ reg = <4>;
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+ nvmem-cells = <&npu_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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+ sensor@5 {
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+ reg = <5>;
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+ nvmem-cells = <&gpu_tsadc_trim>;
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+ nvmem-cell-names = "trim";
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+ };
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};
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i2c9: i2c@2ae80000 {
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