90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
From b9454434d0349223418f74fbfa7b902104da9bc5 Mon Sep 17 00:00:00 2001
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From: Yao Zi <ziyao@disroot.org>
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Date: Mon, 17 Feb 2025 06:11:46 +0000
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Subject: [PATCH] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
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Add missing clocks in UART nodes for RK3528 SoC.
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Signed-off-by: Yao Zi <ziyao@disroot.org>
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Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
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1 file changed, 16 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -168,7 +168,8 @@
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uart0: serial@ff9f0000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff9f0000 0x0 0x100>;
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- clock-frequency = <24000000>;
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+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -178,6 +179,8 @@
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uart1: serial@ff9f8000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff9f8000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -187,6 +190,8 @@
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uart2: serial@ffa00000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xffa00000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -195,6 +200,8 @@
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uart3: serial@ffa08000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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+ clock-names = "baudclk", "apb_pclk";
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reg = <0x0 0xffa08000 0x0 0x100>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -204,6 +211,8 @@
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uart4: serial@ffa10000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xffa10000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -213,6 +222,8 @@
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uart5: serial@ffa18000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xffa18000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -222,6 +233,8 @@
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uart6: serial@ffa20000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xffa20000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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@@ -231,6 +244,8 @@
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uart7: serial@ffa28000 {
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compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
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reg = <0x0 0xffa28000 0x0 0x100>;
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+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
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+ clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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