144 lines
4.1 KiB
Diff
144 lines
4.1 KiB
Diff
From d3a05f490d048808968df1e0d3240ab01fe82211 Mon Sep 17 00:00:00 2001
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From: Yao Zi <ziyao@disroot.org>
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Date: Thu, 17 Apr 2025 12:01:18 +0000
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Subject: [PATCH] arm64: dts: rockchip: Add I2C controllers for RK3528
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Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
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I2C-4 and I2C-7 which come with only a set of possible pins, a default
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pin configuration is included.
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Signed-off-by: Yao Zi <ziyao@disroot.org>
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Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
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Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
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1 file changed, 110 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -24,6 +24,14 @@
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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+ i2c0 = &i2c0;
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+ i2c1 = &i2c1;
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+ i2c2 = &i2c2;
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+ i2c3 = &i2c3;
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+ i2c4 = &i2c4;
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+ i2c5 = &i2c5;
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+ i2c6 = &i2c6;
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+ i2c7 = &i2c7;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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@@ -465,6 +473,108 @@
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status = "disabled";
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};
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+ i2c0: i2c@ffa50000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa50000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@ffa58000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa58000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@ffa60000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa60000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c2m1_xfer>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c3: i2c@ffa68000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa68000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c4: i2c@ffa70000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa70000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c4_xfer>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c5: i2c@ffa78000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa78000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c6: i2c@ffa80000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa80000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c7: i2c@ffa88000 {
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+ compatible = "rockchip,rk3528-i2c",
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+ "rockchip,rk3399-i2c";
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+ reg = <0x0 0xffa88000 0x0 0x1000>;
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+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
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+ clock-names = "i2c", "pclk";
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+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c7_xfer>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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saradc: adc@ffae0000 {
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compatible = "rockchip,rk3528-saradc";
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reg = <0x0 0xffae0000 0x0 0x10000>;
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